SPI_DEVICE/1R1W Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.361m	238.576ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	47.321us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.020s	472.322us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.970s	363.650us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.360s	610.315us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.910s	674.741us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.020s	472.322us	20	20	100.00
		spi_device_csr_aliasing	16.360s	610.315us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	10.246us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.150s	61.318us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	119.304us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	2.940us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	18.683us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.510s	172.081us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.510s	172.081us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.310s	8.931ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	316.962us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	41.950s	8.745ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.310s	122.792ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.750s	8.701ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.750s	8.701ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.900s	11.799ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.900s	11.799ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.900s	11.799ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.900s	11.799ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.900s	11.799ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	24.970s	13.203ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.129m	7.031ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.129m	7.031ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.129m	7.031ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	55.730s	3.637ms	50	50	100.00
		spi_device_read_buffer_direct	21.130s	1.558ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.129m	7.031ms	50	50	100.00
		spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.074m	91.071ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.670s	2.272ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.670s	2.272ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.361m	238.576ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.688m	64.837ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.016m	191.376ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	21.397us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	28.014us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.650s	952.463us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.650s	952.463us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	47.321us	5	5	100.00
		spi_device_csr_rw	3.020s	472.322us	20	20	100.00
		spi_device_csr_aliasing	16.360s	610.315us	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	155.625us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	47.321us	5	5	100.00
		spi_device_csr_rw	3.020s	472.322us	20	20	100.00
		spi_device_csr_aliasing	16.360s	610.315us	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	155.625us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.150s	319.220us	5	5	100.00
		spi_device_tl_intg_err	22.880s	3.625ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.880s	3.625ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.040m	292.405ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.74439245837596745986272027246435349275443222824541964781087756597561718599370
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1870178 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[26])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1870178 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1870178 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[922])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.10712982820561811314306199889628887032220187015465889928150960508888248284944
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    690182 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[64])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    690182 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    690182 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[960])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 38.spi_device_flash_mode_ignore_cmds.25266882834728141420882691032259565876721641384440387304316340334940249879388
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:657ff30d-34b6-4f72-a1c7-54c313a0905d
```