SPI_DEVICE/1R1W Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.816m	150.374ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.610s	227.842us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.680s	176.715us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	46.530s	11.212ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.920s	627.500us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.430s	60.923us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.680s	176.715us	20	20	100.00
		spi_device_csr_aliasing	21.920s	627.500us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	12.177us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.680s	262.149us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.890s	37.907us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	6.744us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	33.237us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.670s	166.449us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.670s	166.449us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.730s	27.995ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	267.395us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.410s	32.537ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.280s	12.974ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.500s	19.207ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.500s	19.207ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	43.760s	4.687ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	43.760s	4.687ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	43.760s	4.687ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	43.760s	4.687ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	43.760s	4.687ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.370s	49.954ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.803m	71.885ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.803m	71.885ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.803m	71.885ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	35.820s	3.026ms	50	50	100.00
		spi_device_read_buffer_direct	25.360s	3.393ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.803m	71.885ms	50	50	100.00
		spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.220m	81.528ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.210s	2.747ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.210s	2.747ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.816m	150.374ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.717m	363.675ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.297m	273.028ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.850s	17.134us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	167.526us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.940s	207.619us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.940s	207.619us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.610s	227.842us	5	5	100.00
		spi_device_csr_rw	2.680s	176.715us	20	20	100.00
		spi_device_csr_aliasing	21.920s	627.500us	5	5	100.00
		spi_device_same_csr_outstanding	4.630s	893.486us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.610s	227.842us	5	5	100.00
		spi_device_csr_rw	2.680s	176.715us	20	20	100.00
		spi_device_csr_aliasing	21.920s	627.500us	5	5	100.00
		spi_device_same_csr_outstanding	4.630s	893.486us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.100s	214.288us	5	5	100.00
		spi_device_tl_intg_err	24.540s	1.069ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.540s	1.069ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.547m	355.549ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	94.01	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.112466214008618427809338228020783871623224542731746881339973532726768051711553
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1805359 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[106])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1805359 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1805359 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1002])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.100169437162577629278587601013260326822211678029056751058038199045603234332444
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1380579 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[17])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1380579 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1380579 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[913])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.