SPI_DEVICE/1R1W Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.048m	153.587ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	170.693us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.900s	91.715us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.540s	1.851ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.030s	4.531ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.950s	131.258us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.900s	91.715us	20	20	100.00
		spi_device_csr_aliasing	22.030s	4.531ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	10.254us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.110s	356.340us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.940s	55.689us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	2.422us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	17.126us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.470s	253.394us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.470s	253.394us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.480s	8.716ms	50	50	100.00
		spi_device_tpm_sts_read	1.140s	159.500us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.160s	64.294ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	44.530s	31.449ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.640s	95.698ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.640s	95.698ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.200s	7.158ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.200s	7.158ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.200s	7.158ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.200s	7.158ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.200s	7.158ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.630s	9.567ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.583m	42.861ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.583m	42.861ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.583m	42.861ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.218m	7.371ms	50	50	100.00
		spi_device_read_buffer_direct	18.880s	6.135ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.583m	42.861ms	50	50	100.00
		spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.604m	41.912ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.720s	11.424ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.720s	11.424ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.048m	153.587ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.440m	80.918ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.107m	368.719ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.850s	41.385us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	16.538us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.280s	319.505us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.280s	319.505us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	170.693us	5	5	100.00
		spi_device_csr_rw	2.900s	91.715us	20	20	100.00
		spi_device_csr_aliasing	22.030s	4.531ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	163.397us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	170.693us	5	5	100.00
		spi_device_csr_rw	2.900s	91.715us	20	20	100.00
		spi_device_csr_aliasing	22.030s	4.531ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	163.397us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.350s	972.252us	5	5	100.00
		spi_device_tl_intg_err	23.050s	1.219ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.050s	1.219ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	32.990m	1.500s	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.75295044093289098857135623149424450188939510031886707509174573075006805881957
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2352840 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[85])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2352840 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2352840 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[981])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.113675447807789095439499305242593603455385164686641678220321019852505218521831
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1023036 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[92])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1023036 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1023036 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[988])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 40.spi_device_flash_mode_ignore_cmds.25411803007785157310025720379752114123885743389650942260664969421326820530352
    Line 274, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```