SPI_DEVICE/1R1W Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	16.037m	104.526ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.520s	40.354us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.580s	80.533us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.440s	1.886ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.530s	1.241ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.270s	184.827us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.580s	80.533us	20	20	100.00
		spi_device_csr_aliasing	24.530s	1.241ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	11.225us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.560s	44.471us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	46.283us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	1.776us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	18.919us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.600s	154.358us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.600s	154.358us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.780s	29.529ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	116.473us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.060s	33.408ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.630s	18.329ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.930s	37.343ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.930s	37.343ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.330s	8.169ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.330s	8.169ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.330s	8.169ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.330s	8.169ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.330s	8.169ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	40.790s	48.478ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.506m	23.514ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.506m	23.514ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.506m	23.514ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.312m	4.964ms	50	50	100.00
		spi_device_read_buffer_direct	19.490s	8.624ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.506m	23.514ms	50	50	100.00
		spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.675m	267.240ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.390s	8.113ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.390s	8.113ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	16.037m	104.526ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.094m	237.436ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.646m	120.296ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.870s	13.710us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	94.805us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.510s	283.879us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.510s	283.879us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.520s	40.354us	5	5	100.00
		spi_device_csr_rw	2.580s	80.533us	20	20	100.00
		spi_device_csr_aliasing	24.530s	1.241ms	5	5	100.00
		spi_device_same_csr_outstanding	4.030s	57.307us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.520s	40.354us	5	5	100.00
		spi_device_csr_rw	2.580s	80.533us	20	20	100.00
		spi_device_csr_aliasing	24.530s	1.241ms	5	5	100.00
		spi_device_same_csr_outstanding	4.030s	57.307us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.360s	433.874us	5	5	100.00
		spi_device_tl_intg_err	22.400s	859.790us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.400s	859.790us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.470m	271.498ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.77289309235725676684587961569074141159816309454274896175092351855117511762552
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1906233 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[35])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1906233 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1906233 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[931])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.6443761686146651410522639036726356663998771705650025763690892234530661881455
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    810711 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[21])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    810711 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    810711 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[917])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.