SPI_DEVICE/1R1W Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.606m	157.558ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.490s	49.201us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.730s	115.693us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.340s	7.207ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.730s	3.639ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.890s	56.324us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.730s	115.693us	20	20	100.00
		spi_device_csr_aliasing	23.730s	3.639ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	22.611us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	68.994us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	19.611us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	5.216us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	18.258us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.970s	150.737us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.970s	150.737us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.200s	36.560ms	50	50	100.00
		spi_device_tpm_sts_read	1.020s	161.995us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	40.330s	17.690ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.510s	38.278ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.140s	16.356ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.140s	16.356ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	40.710s	8.401ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	40.710s	8.401ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	40.710s	8.401ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	40.710s	8.401ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	40.710s	8.401ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.920s	14.479ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.944m	50.857ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.944m	50.857ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.944m	50.857ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.296m	15.584ms	50	50	100.00
		spi_device_read_buffer_direct	28.250s	3.090ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.944m	50.857ms	50	50	100.00
		spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.364m	60.871ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.460s	7.239ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.460s	7.239ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.606m	157.558ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.511m	403.993ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.704m	476.369ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	13.655us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	34.811us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.690s	202.478us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.690s	202.478us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.490s	49.201us	5	5	100.00
		spi_device_csr_rw	2.730s	115.693us	20	20	100.00
		spi_device_csr_aliasing	23.730s	3.639ms	5	5	100.00
		spi_device_same_csr_outstanding	4.280s	441.716us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.490s	49.201us	5	5	100.00
		spi_device_csr_rw	2.730s	115.693us	20	20	100.00
		spi_device_csr_aliasing	23.730s	3.639ms	5	5	100.00
		spi_device_same_csr_outstanding	4.280s	441.716us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.450s	1.728ms	5	5	100.00
		spi_device_tl_intg_err	22.210s	3.202ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.210s	3.202ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.493m	44.957ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.108809152443091687599741111938671213419348841587474213524598809068847808887686
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1052131 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1052131 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1052131 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[897])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.46132519357010387786820302134224318204072527260603797627374210179124340747383
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1319353 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[108])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1319353 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1319353 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1004])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

34.spi_device_flash_mode_ignore_cmds.33987355607451908816743704882790540612408044984865043846319046180447795509483
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 928343068 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 1092483737 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/8
  UVM_INFO @ 1092483737 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/8
  tl_ul_fuzzy_flash_status_q[i] = 0xaaee3c
  tl_ul_fuzzy_flash_status_q[i] = 0xf29ebc