| T118 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3805260412 |
|
|
Feb 08 06:51:12 PM UTC 25 |
Feb 08 06:51:20 PM UTC 25 |
1747070420 ps |
| T468 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1683167288 |
|
|
Feb 08 06:50:54 PM UTC 25 |
Feb 08 06:51:22 PM UTC 25 |
1969670310 ps |
| T469 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.186785836 |
|
|
Feb 08 06:51:21 PM UTC 25 |
Feb 08 06:51:23 PM UTC 25 |
17721734 ps |
| T470 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1295757955 |
|
|
Feb 08 06:51:22 PM UTC 25 |
Feb 08 06:51:24 PM UTC 25 |
175688113 ps |
| T334 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1297142122 |
|
|
Feb 08 06:51:10 PM UTC 25 |
Feb 08 06:51:25 PM UTC 25 |
2012465812 ps |
| T284 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3359237082 |
|
|
Feb 08 06:51:24 PM UTC 25 |
Feb 08 06:51:31 PM UTC 25 |
2368964395 ps |
| T326 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.611878136 |
|
|
Feb 08 06:51:06 PM UTC 25 |
Feb 08 06:51:33 PM UTC 25 |
20347743264 ps |
| T303 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.4292367384 |
|
|
Feb 08 06:50:51 PM UTC 25 |
Feb 08 06:51:35 PM UTC 25 |
2781634069 ps |
| T374 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.3714326353 |
|
|
Feb 08 06:51:11 PM UTC 25 |
Feb 08 06:51:35 PM UTC 25 |
766562247 ps |
| T108 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2754001275 |
|
|
Feb 08 06:49:50 PM UTC 25 |
Feb 08 06:51:37 PM UTC 25 |
12906107926 ps |
| T104 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.451609898 |
|
|
Feb 08 06:48:44 PM UTC 25 |
Feb 08 06:51:39 PM UTC 25 |
10400872634 ps |
| T471 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.1112829521 |
|
|
Feb 08 06:51:35 PM UTC 25 |
Feb 08 06:51:40 PM UTC 25 |
483222634 ps |
| T202 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.2682429022 |
|
|
Feb 08 06:50:36 PM UTC 25 |
Feb 08 06:51:43 PM UTC 25 |
8011233971 ps |
| T317 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2758680889 |
|
|
Feb 08 06:51:34 PM UTC 25 |
Feb 08 06:51:43 PM UTC 25 |
491802386 ps |
| T237 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.887457458 |
|
|
Feb 08 06:51:23 PM UTC 25 |
Feb 08 06:51:44 PM UTC 25 |
12044712140 ps |
| T472 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.441197144 |
|
|
Feb 08 06:51:44 PM UTC 25 |
Feb 08 06:51:46 PM UTC 25 |
13602137 ps |
| T473 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3463559903 |
|
|
Feb 08 06:51:38 PM UTC 25 |
Feb 08 06:51:46 PM UTC 25 |
1085709073 ps |
| T474 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3173177494 |
|
|
Feb 08 06:51:45 PM UTC 25 |
Feb 08 06:51:47 PM UTC 25 |
27441689 ps |
| T201 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1827488420 |
|
|
Feb 08 06:50:58 PM UTC 25 |
Feb 08 06:51:49 PM UTC 25 |
2134931986 ps |
| T228 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.1153012713 |
|
|
Feb 08 06:51:25 PM UTC 25 |
Feb 08 06:51:49 PM UTC 25 |
13533869291 ps |
| T475 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2807647220 |
|
|
Feb 08 06:51:49 PM UTC 25 |
Feb 08 06:51:52 PM UTC 25 |
10992317 ps |
| T476 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2981461625 |
|
|
Feb 08 06:51:50 PM UTC 25 |
Feb 08 06:51:52 PM UTC 25 |
40239382 ps |
| T382 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.2027866821 |
|
|
Feb 08 06:51:20 PM UTC 25 |
Feb 08 06:51:53 PM UTC 25 |
13461041880 ps |
| T335 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.3238491502 |
|
|
Feb 08 06:51:09 PM UTC 25 |
Feb 08 06:51:54 PM UTC 25 |
6838476004 ps |
| T477 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.2414245068 |
|
|
Feb 08 06:51:54 PM UTC 25 |
Feb 08 06:51:58 PM UTC 25 |
30189179 ps |
| T478 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.2194853184 |
|
|
Feb 08 06:51:40 PM UTC 25 |
Feb 08 06:51:59 PM UTC 25 |
1436802176 ps |
| T479 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1198303949 |
|
|
Feb 08 06:51:26 PM UTC 25 |
Feb 08 06:51:59 PM UTC 25 |
14085258544 ps |
| T480 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.1018173655 |
|
|
Feb 08 06:51:20 PM UTC 25 |
Feb 08 06:52:01 PM UTC 25 |
11045590091 ps |
| T229 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3004319906 |
|
|
Feb 08 06:47:45 PM UTC 25 |
Feb 08 06:52:02 PM UTC 25 |
27658998416 ps |
| T336 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2861829276 |
|
|
Feb 08 06:51:59 PM UTC 25 |
Feb 08 06:52:03 PM UTC 25 |
99021979 ps |
| T40 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1114942183 |
|
|
Feb 08 06:48:48 PM UTC 25 |
Feb 08 06:52:04 PM UTC 25 |
310429706548 ps |
| T222 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4076247069 |
|
|
Feb 08 06:49:27 PM UTC 25 |
Feb 08 06:52:04 PM UTC 25 |
21410382881 ps |
| T239 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.3365130405 |
|
|
Feb 08 06:51:53 PM UTC 25 |
Feb 08 06:52:07 PM UTC 25 |
2624380342 ps |
| T481 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.4132989098 |
|
|
Feb 08 06:51:47 PM UTC 25 |
Feb 08 06:52:09 PM UTC 25 |
4292604656 ps |
| T482 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.4207276378 |
|
|
Feb 08 06:52:07 PM UTC 25 |
Feb 08 06:52:10 PM UTC 25 |
13381854 ps |
| T330 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.4236914749 |
|
|
Feb 08 06:51:53 PM UTC 25 |
Feb 08 06:52:11 PM UTC 25 |
2632857589 ps |
| T251 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3874913065 |
|
|
Feb 08 06:52:00 PM UTC 25 |
Feb 08 06:52:12 PM UTC 25 |
433505510 ps |
| T256 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.3124338704 |
|
|
Feb 08 06:51:55 PM UTC 25 |
Feb 08 06:52:12 PM UTC 25 |
9662095943 ps |
| T290 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2243081910 |
|
|
Feb 08 06:51:11 PM UTC 25 |
Feb 08 06:52:12 PM UTC 25 |
5346655455 ps |
| T294 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.4056960809 |
|
|
Feb 08 06:52:17 PM UTC 25 |
Feb 08 06:52:27 PM UTC 25 |
2426114898 ps |
| T483 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.4031095977 |
|
|
Feb 08 06:52:10 PM UTC 25 |
Feb 08 06:52:13 PM UTC 25 |
70424641 ps |
| T484 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1317895002 |
|
|
Feb 08 06:52:13 PM UTC 25 |
Feb 08 06:52:15 PM UTC 25 |
31232851 ps |
| T485 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.1009797903 |
|
|
Feb 08 06:52:13 PM UTC 25 |
Feb 08 06:52:15 PM UTC 25 |
129163862 ps |
| T308 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1020590117 |
|
|
Feb 08 06:50:55 PM UTC 25 |
Feb 08 06:52:16 PM UTC 25 |
14098994426 ps |
| T277 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.967216858 |
|
|
Feb 08 06:48:31 PM UTC 25 |
Feb 08 06:52:16 PM UTC 25 |
29362012114 ps |
| T486 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.4049676110 |
|
|
Feb 08 06:51:32 PM UTC 25 |
Feb 08 06:52:17 PM UTC 25 |
49338810559 ps |
| T487 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.1777522349 |
|
|
Feb 08 06:52:14 PM UTC 25 |
Feb 08 06:52:19 PM UTC 25 |
270768300 ps |
| T488 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.1714656381 |
|
|
Feb 08 06:52:15 PM UTC 25 |
Feb 08 06:52:20 PM UTC 25 |
186273876 ps |
| T383 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.2659273227 |
|
|
Feb 08 06:51:48 PM UTC 25 |
Feb 08 06:52:20 PM UTC 25 |
4128345151 ps |
| T489 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1099537262 |
|
|
Feb 08 06:52:14 PM UTC 25 |
Feb 08 06:52:21 PM UTC 25 |
2647592380 ps |
| T490 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2782259367 |
|
|
Feb 08 06:52:02 PM UTC 25 |
Feb 08 06:52:22 PM UTC 25 |
1464946142 ps |
| T491 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.2192735642 |
|
|
Feb 08 06:52:13 PM UTC 25 |
Feb 08 06:52:22 PM UTC 25 |
338636579 ps |
| T492 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.2815688515 |
|
|
Feb 08 06:50:54 PM UTC 25 |
Feb 08 06:52:23 PM UTC 25 |
17126219375 ps |
| T493 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.4020653409 |
|
|
Feb 08 06:52:17 PM UTC 25 |
Feb 08 06:52:24 PM UTC 25 |
433922767 ps |
| T494 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.1689114591 |
|
|
Feb 08 06:52:23 PM UTC 25 |
Feb 08 06:52:26 PM UTC 25 |
15377625 ps |
| T101 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.3918115283 |
|
|
Feb 08 06:47:50 PM UTC 25 |
Feb 08 06:52:28 PM UTC 25 |
17887693561 ps |
| T495 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2613490252 |
|
|
Feb 08 06:52:24 PM UTC 25 |
Feb 08 06:52:27 PM UTC 25 |
136737816 ps |
| T276 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1366138434 |
|
|
Feb 08 06:51:51 PM UTC 25 |
Feb 08 06:52:27 PM UTC 25 |
10970709003 ps |
| T496 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.2279980577 |
|
|
Feb 08 06:52:27 PM UTC 25 |
Feb 08 06:52:30 PM UTC 25 |
51824703 ps |
| T497 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1885328532 |
|
|
Feb 08 06:52:20 PM UTC 25 |
Feb 08 06:52:27 PM UTC 25 |
778553800 ps |
| T498 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3669712761 |
|
|
Feb 08 06:52:27 PM UTC 25 |
Feb 08 06:52:30 PM UTC 25 |
388930106 ps |
| T105 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1542857080 |
|
|
Feb 08 06:49:15 PM UTC 25 |
Feb 08 06:52:33 PM UTC 25 |
9100331429 ps |
| T250 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2482157512 |
|
|
Feb 08 06:52:04 PM UTC 25 |
Feb 08 06:52:33 PM UTC 25 |
3817814731 ps |
| T499 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2428121367 |
|
|
Feb 08 06:52:12 PM UTC 25 |
Feb 08 06:52:33 PM UTC 25 |
11518723857 ps |
| T500 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3799622632 |
|
|
Feb 08 06:52:26 PM UTC 25 |
Feb 08 06:52:35 PM UTC 25 |
1823955769 ps |
| T339 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.934453841 |
|
|
Feb 08 06:52:31 PM UTC 25 |
Feb 08 06:52:36 PM UTC 25 |
171082688 ps |
| T501 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2155246819 |
|
|
Feb 08 06:52:36 PM UTC 25 |
Feb 08 06:52:38 PM UTC 25 |
27426035 ps |
| T502 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3582407300 |
|
|
Feb 08 06:52:34 PM UTC 25 |
Feb 08 06:52:40 PM UTC 25 |
143550423 ps |
| T503 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.3075019040 |
|
|
Feb 08 06:52:41 PM UTC 25 |
Feb 08 06:52:43 PM UTC 25 |
15428765 ps |
| T504 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.210083136 |
|
|
Feb 08 06:52:44 PM UTC 25 |
Feb 08 06:52:46 PM UTC 25 |
19532667 ps |
| T258 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1542068354 |
|
|
Feb 08 06:52:18 PM UTC 25 |
Feb 08 06:52:48 PM UTC 25 |
1181217692 ps |
| T372 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.878085038 |
|
|
Feb 08 06:52:29 PM UTC 25 |
Feb 08 06:52:54 PM UTC 25 |
2471091422 ps |
| T505 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.489206513 |
|
|
Feb 08 06:49:50 PM UTC 25 |
Feb 08 06:52:55 PM UTC 25 |
20028098590 ps |
| T506 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.801876463 |
|
|
Feb 08 06:52:54 PM UTC 25 |
Feb 08 06:52:57 PM UTC 25 |
137158697 ps |
| T507 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.3834864202 |
|
|
Feb 08 06:52:56 PM UTC 25 |
Feb 08 06:52:59 PM UTC 25 |
215335290 ps |
| T508 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3235559423 |
|
|
Feb 08 06:48:20 PM UTC 25 |
Feb 08 06:53:00 PM UTC 25 |
123028712691 ps |
| T509 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2584766800 |
|
|
Feb 08 06:52:49 PM UTC 25 |
Feb 08 06:53:01 PM UTC 25 |
4919985084 ps |
| T378 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.4288060332 |
|
|
Feb 08 06:52:34 PM UTC 25 |
Feb 08 06:53:02 PM UTC 25 |
7461199947 ps |
| T223 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1493678142 |
|
|
Feb 08 06:47:56 PM UTC 25 |
Feb 08 06:53:05 PM UTC 25 |
42503681810 ps |
| T241 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2173399081 |
|
|
Feb 08 06:52:29 PM UTC 25 |
Feb 08 06:53:07 PM UTC 25 |
2260269374 ps |
| T298 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.1034666847 |
|
|
Feb 08 06:53:00 PM UTC 25 |
Feb 08 06:53:08 PM UTC 25 |
726170153 ps |
| T321 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3026398068 |
|
|
Feb 08 06:52:58 PM UTC 25 |
Feb 08 06:53:09 PM UTC 25 |
408620788 ps |
| T262 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.3325497971 |
|
|
Feb 08 06:52:29 PM UTC 25 |
Feb 08 06:53:09 PM UTC 25 |
5328889621 ps |
| T274 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.2865565874 |
|
|
Feb 08 06:52:31 PM UTC 25 |
Feb 08 06:53:10 PM UTC 25 |
18851496003 ps |
| T381 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2542138389 |
|
|
Feb 08 06:52:27 PM UTC 25 |
Feb 08 06:53:11 PM UTC 25 |
17560862831 ps |
| T325 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.2977850146 |
|
|
Feb 08 06:53:00 PM UTC 25 |
Feb 08 06:53:11 PM UTC 25 |
4672272451 ps |
| T269 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1072635645 |
|
|
Feb 08 06:53:08 PM UTC 25 |
Feb 08 06:53:13 PM UTC 25 |
102058412 ps |
| T384 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.346424902 |
|
|
Feb 08 06:52:50 PM UTC 25 |
Feb 08 06:53:14 PM UTC 25 |
1596278757 ps |
| T288 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1819633245 |
|
|
Feb 08 06:50:54 PM UTC 25 |
Feb 08 06:53:16 PM UTC 25 |
27428914137 ps |
| T102 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.2843552582 |
|
|
Feb 08 06:52:05 PM UTC 25 |
Feb 08 06:53:16 PM UTC 25 |
12378616467 ps |
| T510 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.458902607 |
|
|
Feb 08 06:53:02 PM UTC 25 |
Feb 08 06:53:16 PM UTC 25 |
4719307888 ps |
| T511 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1500936481 |
|
|
Feb 08 06:53:14 PM UTC 25 |
Feb 08 06:53:16 PM UTC 25 |
29253578 ps |
| T512 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.3580660480 |
|
|
Feb 08 06:53:10 PM UTC 25 |
Feb 08 06:53:17 PM UTC 25 |
791857830 ps |
| T513 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.3830839432 |
|
|
Feb 08 06:53:15 PM UTC 25 |
Feb 08 06:53:17 PM UTC 25 |
63840725 ps |
| T514 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1050140032 |
|
|
Feb 08 06:51:38 PM UTC 25 |
Feb 08 06:53:18 PM UTC 25 |
41461501351 ps |
| T379 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1813623529 |
|
|
Feb 08 06:52:00 PM UTC 25 |
Feb 08 06:53:18 PM UTC 25 |
12536897516 ps |
| T322 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2202018214 |
|
|
Feb 08 06:52:29 PM UTC 25 |
Feb 08 06:53:19 PM UTC 25 |
9114785247 ps |
| T282 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2517664417 |
|
|
Feb 08 06:52:14 PM UTC 25 |
Feb 08 06:53:19 PM UTC 25 |
11039553280 ps |
| T310 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1112368989 |
|
|
Feb 08 06:52:02 PM UTC 25 |
Feb 08 06:53:19 PM UTC 25 |
13441748511 ps |
| T387 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3187140122 |
|
|
Feb 08 06:52:21 PM UTC 25 |
Feb 08 06:53:19 PM UTC 25 |
2297202880 ps |
| T515 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.109322457 |
|
|
Feb 08 06:53:17 PM UTC 25 |
Feb 08 06:53:19 PM UTC 25 |
42991648 ps |
| T289 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3466752561 |
|
|
Feb 08 06:49:13 PM UTC 25 |
Feb 08 06:53:21 PM UTC 25 |
80498431013 ps |
| T516 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.2709543092 |
|
|
Feb 08 06:53:17 PM UTC 25 |
Feb 08 06:53:22 PM UTC 25 |
816193840 ps |
| T517 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.3205174813 |
|
|
Feb 08 06:53:18 PM UTC 25 |
Feb 08 06:53:22 PM UTC 25 |
76433753 ps |
| T248 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1181681753 |
|
|
Feb 08 06:53:01 PM UTC 25 |
Feb 08 06:53:23 PM UTC 25 |
5266263738 ps |
| T315 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2781236661 |
|
|
Feb 08 06:53:20 PM UTC 25 |
Feb 08 06:53:24 PM UTC 25 |
156392385 ps |
| T300 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2397202675 |
|
|
Feb 08 06:53:06 PM UTC 25 |
Feb 08 06:53:24 PM UTC 25 |
1213740649 ps |
| T518 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1816911273 |
|
|
Feb 08 06:53:16 PM UTC 25 |
Feb 08 06:53:24 PM UTC 25 |
495464373 ps |
| T519 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1627785345 |
|
|
Feb 08 06:53:24 PM UTC 25 |
Feb 08 06:53:26 PM UTC 25 |
31917898 ps |
| T520 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.3896119188 |
|
|
Feb 08 06:53:24 PM UTC 25 |
Feb 08 06:53:26 PM UTC 25 |
41165893 ps |
| T521 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1085696 |
|
|
Feb 08 06:53:17 PM UTC 25 |
Feb 08 06:53:27 PM UTC 25 |
1720416088 ps |
| T332 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.356369591 |
|
|
Feb 08 06:53:20 PM UTC 25 |
Feb 08 06:53:28 PM UTC 25 |
2527959457 ps |
| T263 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3305999356 |
|
|
Feb 08 06:48:34 PM UTC 25 |
Feb 08 06:53:28 PM UTC 25 |
92662241325 ps |
| T240 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.531122474 |
|
|
Feb 08 06:53:18 PM UTC 25 |
Feb 08 06:53:29 PM UTC 25 |
779413913 ps |
| T522 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.3984557120 |
|
|
Feb 08 06:53:17 PM UTC 25 |
Feb 08 06:53:30 PM UTC 25 |
6008012834 ps |
| T523 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3781598903 |
|
|
Feb 08 06:53:27 PM UTC 25 |
Feb 08 06:53:30 PM UTC 25 |
17020147 ps |
| T524 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.4205704804 |
|
|
Feb 08 06:53:20 PM UTC 25 |
Feb 08 06:53:30 PM UTC 25 |
948566849 ps |
| T525 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.1086349131 |
|
|
Feb 08 06:53:27 PM UTC 25 |
Feb 08 06:53:30 PM UTC 25 |
86316561 ps |
| T238 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1098807935 |
|
|
Feb 08 06:49:52 PM UTC 25 |
Feb 08 06:53:31 PM UTC 25 |
14573458393 ps |
| T375 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2394435086 |
|
|
Feb 08 06:53:20 PM UTC 25 |
Feb 08 06:53:32 PM UTC 25 |
488057830 ps |
| T526 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3692953844 |
|
|
Feb 08 06:53:21 PM UTC 25 |
Feb 08 06:53:34 PM UTC 25 |
2112938121 ps |
| T316 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2478515687 |
|
|
Feb 08 06:53:31 PM UTC 25 |
Feb 08 06:53:36 PM UTC 25 |
233600888 ps |
| T527 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.179276217 |
|
|
Feb 08 06:53:31 PM UTC 25 |
Feb 08 06:53:36 PM UTC 25 |
172787282 ps |
| T528 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.4214528622 |
|
|
Feb 08 06:52:35 PM UTC 25 |
Feb 08 06:53:40 PM UTC 25 |
14665011376 ps |
| T529 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3287935677 |
|
|
Feb 08 06:53:33 PM UTC 25 |
Feb 08 06:53:43 PM UTC 25 |
662083153 ps |
| T324 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3261901898 |
|
|
Feb 08 06:53:30 PM UTC 25 |
Feb 08 06:53:44 PM UTC 25 |
3128390684 ps |
| T530 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.3068638244 |
|
|
Feb 08 06:53:43 PM UTC 25 |
Feb 08 06:53:45 PM UTC 25 |
17661805 ps |
| T531 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.3824579879 |
|
|
Feb 08 06:53:45 PM UTC 25 |
Feb 08 06:53:48 PM UTC 25 |
12705447 ps |
| T532 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2487541803 |
|
|
Feb 08 06:53:27 PM UTC 25 |
Feb 08 06:53:50 PM UTC 25 |
2577770641 ps |
| T533 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.2081506589 |
|
|
Feb 08 06:53:49 PM UTC 25 |
Feb 08 06:53:51 PM UTC 25 |
21302799 ps |
| T534 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.4016378552 |
|
|
Feb 08 06:53:31 PM UTC 25 |
Feb 08 06:53:51 PM UTC 25 |
367530324 ps |
| T535 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1146988038 |
|
|
Feb 08 06:53:46 PM UTC 25 |
Feb 08 06:53:53 PM UTC 25 |
926643785 ps |
| T536 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.1114802086 |
|
|
Feb 08 06:53:52 PM UTC 25 |
Feb 08 06:53:54 PM UTC 25 |
25378067 ps |
| T537 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2949069343 |
|
|
Feb 08 06:53:52 PM UTC 25 |
Feb 08 06:53:54 PM UTC 25 |
90870757 ps |
| T538 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.398316291 |
|
|
Feb 08 06:53:52 PM UTC 25 |
Feb 08 06:53:58 PM UTC 25 |
649894481 ps |
| T539 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2543533391 |
|
|
Feb 08 06:53:55 PM UTC 25 |
Feb 08 06:53:59 PM UTC 25 |
35480583 ps |
| T264 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2935616463 |
|
|
Feb 08 06:53:54 PM UTC 25 |
Feb 08 06:53:59 PM UTC 25 |
338370678 ps |
| T357 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.4272489109 |
|
|
Feb 08 06:53:21 PM UTC 25 |
Feb 08 06:54:01 PM UTC 25 |
3827802710 ps |
| T540 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.61430874 |
|
|
Feb 08 06:53:10 PM UTC 25 |
Feb 08 06:54:02 PM UTC 25 |
4948009306 ps |
| T541 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1644929345 |
|
|
Feb 08 06:53:30 PM UTC 25 |
Feb 08 06:54:03 PM UTC 25 |
3349193573 ps |
| T542 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1788217462 |
|
|
Feb 08 06:48:46 PM UTC 25 |
Feb 08 06:54:03 PM UTC 25 |
144485993449 ps |
| T543 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.880995175 |
|
|
Feb 08 06:53:25 PM UTC 25 |
Feb 08 06:54:05 PM UTC 25 |
7610160695 ps |
| T544 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.1311665128 |
|
|
Feb 08 06:54:03 PM UTC 25 |
Feb 08 06:54:11 PM UTC 25 |
163996789 ps |
| T545 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.3025323694 |
|
|
Feb 08 06:54:00 PM UTC 25 |
Feb 08 06:54:11 PM UTC 25 |
412914277 ps |
| T247 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.1640798799 |
|
|
Feb 08 06:53:56 PM UTC 25 |
Feb 08 06:54:12 PM UTC 25 |
1595981636 ps |
| T243 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2423305752 |
|
|
Feb 08 06:48:21 PM UTC 25 |
Feb 08 06:54:12 PM UTC 25 |
56857392439 ps |
| T546 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.104362092 |
|
|
Feb 08 06:54:12 PM UTC 25 |
Feb 08 06:54:14 PM UTC 25 |
18679272 ps |
| T547 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.601009532 |
|
|
Feb 08 06:54:12 PM UTC 25 |
Feb 08 06:54:14 PM UTC 25 |
18557808 ps |
| T266 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.3243173220 |
|
|
Feb 08 06:50:19 PM UTC 25 |
Feb 08 06:54:14 PM UTC 25 |
242864870021 ps |
| T548 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.217549455 |
|
|
Feb 08 06:54:13 PM UTC 25 |
Feb 08 06:54:17 PM UTC 25 |
1555497353 ps |
| T549 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1853354268 |
|
|
Feb 08 06:54:15 PM UTC 25 |
Feb 08 06:54:17 PM UTC 25 |
33029640 ps |
| T550 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.497979972 |
|
|
Feb 08 06:53:59 PM UTC 25 |
Feb 08 06:54:18 PM UTC 25 |
5042259648 ps |
| T551 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1612971550 |
|
|
Feb 08 06:54:15 PM UTC 25 |
Feb 08 06:54:19 PM UTC 25 |
98706503 ps |
| T552 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1376238855 |
|
|
Feb 08 06:53:28 PM UTC 25 |
Feb 08 06:54:20 PM UTC 25 |
40807395668 ps |
| T252 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1290243349 |
|
|
Feb 08 06:53:09 PM UTC 25 |
Feb 08 06:54:20 PM UTC 25 |
39533864494 ps |
| T553 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3183124349 |
|
|
Feb 08 06:54:18 PM UTC 25 |
Feb 08 06:54:23 PM UTC 25 |
2422263181 ps |
| T301 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3540340459 |
|
|
Feb 08 06:53:31 PM UTC 25 |
Feb 08 06:54:24 PM UTC 25 |
104608309193 ps |
| T293 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.474322190 |
|
|
Feb 08 06:53:11 PM UTC 25 |
Feb 08 06:54:28 PM UTC 25 |
3680736450 ps |
| T376 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1862796871 |
|
|
Feb 08 06:54:21 PM UTC 25 |
Feb 08 06:54:28 PM UTC 25 |
118239402 ps |
| T178 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1709972371 |
|
|
Feb 08 06:53:41 PM UTC 25 |
Feb 08 06:54:29 PM UTC 25 |
2893962621 ps |
| T270 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.4174192582 |
|
|
Feb 08 06:54:18 PM UTC 25 |
Feb 08 06:54:30 PM UTC 25 |
599642746 ps |
| T554 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.2254862340 |
|
|
Feb 08 06:54:21 PM UTC 25 |
Feb 08 06:54:30 PM UTC 25 |
2143846382 ps |
| T555 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.2093093386 |
|
|
Feb 08 06:54:01 PM UTC 25 |
Feb 08 06:54:31 PM UTC 25 |
2292805803 ps |
| T556 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.4164992759 |
|
|
Feb 08 06:54:31 PM UTC 25 |
Feb 08 06:54:33 PM UTC 25 |
11336859 ps |
| T557 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.1121814984 |
|
|
Feb 08 06:54:32 PM UTC 25 |
Feb 08 06:54:34 PM UTC 25 |
30431008 ps |
| T558 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3384542204 |
|
|
Feb 08 06:54:25 PM UTC 25 |
Feb 08 06:54:34 PM UTC 25 |
1490746251 ps |
| T340 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1939317209 |
|
|
Feb 08 06:54:15 PM UTC 25 |
Feb 08 06:54:35 PM UTC 25 |
24700687061 ps |
| T559 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1086191720 |
|
|
Feb 08 06:54:35 PM UTC 25 |
Feb 08 06:54:37 PM UTC 25 |
68100775 ps |
| T560 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2175831700 |
|
|
Feb 08 06:53:12 PM UTC 25 |
Feb 08 06:54:38 PM UTC 25 |
11920317840 ps |
| T561 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.3964620806 |
|
|
Feb 08 06:54:35 PM UTC 25 |
Feb 08 06:54:38 PM UTC 25 |
115117691 ps |
| T280 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1452324848 |
|
|
Feb 08 06:47:42 PM UTC 25 |
Feb 08 06:54:39 PM UTC 25 |
71745845218 ps |
| T562 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.440700141 |
|
|
Feb 08 06:54:33 PM UTC 25 |
Feb 08 06:54:42 PM UTC 25 |
941090206 ps |
| T563 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3860542195 |
|
|
Feb 08 06:54:21 PM UTC 25 |
Feb 08 06:54:43 PM UTC 25 |
7407352730 ps |
| T564 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1888259672 |
|
|
Feb 08 06:54:38 PM UTC 25 |
Feb 08 06:54:45 PM UTC 25 |
1060670952 ps |
| T253 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.901971174 |
|
|
Feb 08 06:51:35 PM UTC 25 |
Feb 08 06:54:47 PM UTC 25 |
31370687216 ps |
| T565 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.1777690553 |
|
|
Feb 08 06:54:13 PM UTC 25 |
Feb 08 06:54:50 PM UTC 25 |
22580283394 ps |
| T230 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1758372641 |
|
|
Feb 08 06:53:36 PM UTC 25 |
Feb 08 06:54:51 PM UTC 25 |
21696765108 ps |
| T242 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.4248852307 |
|
|
Feb 08 06:54:39 PM UTC 25 |
Feb 08 06:54:51 PM UTC 25 |
25478735945 ps |
| T566 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2799270311 |
|
|
Feb 08 06:54:46 PM UTC 25 |
Feb 08 06:54:52 PM UTC 25 |
212003747 ps |
| T567 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1103402084 |
|
|
Feb 08 06:54:36 PM UTC 25 |
Feb 08 06:54:52 PM UTC 25 |
1361495273 ps |
| T568 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.1322115177 |
|
|
Feb 08 06:54:34 PM UTC 25 |
Feb 08 06:54:53 PM UTC 25 |
2656185995 ps |
| T106 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.495040955 |
|
|
Feb 08 06:53:34 PM UTC 25 |
Feb 08 06:54:53 PM UTC 25 |
2581003050 ps |
| T569 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.149661955 |
|
|
Feb 08 06:54:53 PM UTC 25 |
Feb 08 06:54:55 PM UTC 25 |
12748127 ps |
| T570 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1342843316 |
|
|
Feb 08 06:54:53 PM UTC 25 |
Feb 08 06:54:55 PM UTC 25 |
38432692 ps |
| T571 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3329211312 |
|
|
Feb 08 06:54:38 PM UTC 25 |
Feb 08 06:54:56 PM UTC 25 |
5086464530 ps |
| T572 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1531869592 |
|
|
Feb 08 06:54:42 PM UTC 25 |
Feb 08 06:54:58 PM UTC 25 |
2387721386 ps |
| T573 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3912479421 |
|
|
Feb 08 06:54:56 PM UTC 25 |
Feb 08 06:54:58 PM UTC 25 |
85066048 ps |
| T574 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.3442207728 |
|
|
Feb 08 06:54:54 PM UTC 25 |
Feb 08 06:55:00 PM UTC 25 |
2975840964 ps |
| T333 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.774669223 |
|
|
Feb 08 06:51:44 PM UTC 25 |
Feb 08 06:55:00 PM UTC 25 |
14648898286 ps |
| T331 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2412637984 |
|
|
Feb 08 06:49:48 PM UTC 25 |
Feb 08 06:55:03 PM UTC 25 |
42726916050 ps |
| T329 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1985278446 |
|
|
Feb 08 06:54:58 PM UTC 25 |
Feb 08 06:55:04 PM UTC 25 |
295292807 ps |
| T575 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.2849686741 |
|
|
Feb 08 06:54:59 PM UTC 25 |
Feb 08 06:55:05 PM UTC 25 |
379829688 ps |
| T576 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.2191900551 |
|
|
Feb 08 06:54:56 PM UTC 25 |
Feb 08 06:55:06 PM UTC 25 |
941566498 ps |
| T577 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.361619442 |
|
|
Feb 08 06:55:05 PM UTC 25 |
Feb 08 06:55:09 PM UTC 25 |
30562537 ps |
| T578 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2528872761 |
|
|
Feb 08 06:54:44 PM UTC 25 |
Feb 08 06:55:12 PM UTC 25 |
2026343659 ps |
| T107 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3577920082 |
|
|
Feb 08 06:49:31 PM UTC 25 |
Feb 08 06:55:15 PM UTC 25 |
138164509658 ps |
| T579 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1481022580 |
|
|
Feb 08 06:54:54 PM UTC 25 |
Feb 08 06:55:17 PM UTC 25 |
3235606010 ps |
| T580 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.930567915 |
|
|
Feb 08 06:52:04 PM UTC 25 |
Feb 08 06:55:22 PM UTC 25 |
14722126723 ps |
| T581 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2082166679 |
|
|
Feb 08 06:55:01 PM UTC 25 |
Feb 08 06:55:23 PM UTC 25 |
2889829730 ps |
| T320 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.702526253 |
|
|
Feb 08 06:54:38 PM UTC 25 |
Feb 08 06:55:23 PM UTC 25 |
14640829316 ps |
| T582 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2093795035 |
|
|
Feb 08 06:55:07 PM UTC 25 |
Feb 08 06:55:25 PM UTC 25 |
15550320858 ps |
| T583 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2667481943 |
|
|
Feb 08 06:54:57 PM UTC 25 |
Feb 08 06:55:25 PM UTC 25 |
8423940782 ps |
| T584 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.953156686 |
|
|
Feb 08 06:55:23 PM UTC 25 |
Feb 08 06:55:25 PM UTC 25 |
29313160 ps |
| T283 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3914227670 |
|
|
Feb 08 06:53:36 PM UTC 25 |
Feb 08 06:55:25 PM UTC 25 |
12975857888 ps |
| T585 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.2459775214 |
|
|
Feb 08 06:55:24 PM UTC 25 |
Feb 08 06:55:26 PM UTC 25 |
83146200 ps |
| T586 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.881603254 |
|
|
Feb 08 06:55:01 PM UTC 25 |
Feb 08 06:55:27 PM UTC 25 |
9843125570 ps |
| T587 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3365212103 |
|
|
Feb 08 06:55:25 PM UTC 25 |
Feb 08 06:55:28 PM UTC 25 |
188984523 ps |
| T588 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.136889488 |
|
|
Feb 08 06:55:26 PM UTC 25 |
Feb 08 06:55:29 PM UTC 25 |
110288169 ps |
| T589 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.3890341203 |
|
|
Feb 08 06:54:43 PM UTC 25 |
Feb 08 06:55:30 PM UTC 25 |
3112790540 ps |
| T590 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2188463369 |
|
|
Feb 08 06:54:19 PM UTC 25 |
Feb 08 06:55:31 PM UTC 25 |
22200373785 ps |
| T591 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2324920345 |
|
|
Feb 08 06:55:28 PM UTC 25 |
Feb 08 06:55:34 PM UTC 25 |
3677890453 ps |
| T592 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.3473327398 |
|
|
Feb 08 06:55:05 PM UTC 25 |
Feb 08 06:55:37 PM UTC 25 |
9216468246 ps |
| T593 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1247888008 |
|
|
Feb 08 06:55:32 PM UTC 25 |
Feb 08 06:55:38 PM UTC 25 |
108655290 ps |
| T594 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.635149177 |
|
|
Feb 08 06:55:26 PM UTC 25 |
Feb 08 06:55:38 PM UTC 25 |
4392128738 ps |
| T595 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2769261358 |
|
|
Feb 08 06:55:29 PM UTC 25 |
Feb 08 06:55:39 PM UTC 25 |
951327957 ps |
| T596 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.419309401 |
|
|
Feb 08 06:55:30 PM UTC 25 |
Feb 08 06:55:40 PM UTC 25 |
492247448 ps |
| T597 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.1958702571 |
|
|
Feb 08 06:53:55 PM UTC 25 |
Feb 08 06:55:40 PM UTC 25 |
20359391431 ps |
| T353 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1266466033 |
|
|
Feb 08 06:52:38 PM UTC 25 |
Feb 08 06:55:40 PM UTC 25 |
20005384733 ps |
| T598 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1846697758 |
|
|
Feb 08 06:54:28 PM UTC 25 |
Feb 08 06:55:40 PM UTC 25 |
4999602155 ps |
| T599 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.288435006 |
|
|
Feb 08 06:55:29 PM UTC 25 |
Feb 08 06:55:41 PM UTC 25 |
2678048396 ps |
| T226 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1086033392 |
|
|
Feb 08 06:55:31 PM UTC 25 |
Feb 08 06:55:42 PM UTC 25 |
1817293251 ps |
| T600 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.4269879003 |
|
|
Feb 08 06:55:41 PM UTC 25 |
Feb 08 06:55:44 PM UTC 25 |
15033723 ps |
| T601 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.862522097 |
|
|
Feb 08 06:55:41 PM UTC 25 |
Feb 08 06:55:44 PM UTC 25 |
32755425 ps |
| T602 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.2780400940 |
|
|
Feb 08 06:55:41 PM UTC 25 |
Feb 08 06:55:44 PM UTC 25 |
99355476 ps |
| T186 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.955996397 |
|
|
Feb 08 06:55:41 PM UTC 25 |
Feb 08 06:55:44 PM UTC 25 |
65481733 ps |
| T603 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2237270574 |
|
|
Feb 08 06:55:42 PM UTC 25 |
Feb 08 06:55:45 PM UTC 25 |
28496482 ps |
| T604 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2769057725 |
|
|
Feb 08 06:55:37 PM UTC 25 |
Feb 08 06:55:47 PM UTC 25 |
2580506682 ps |
| T605 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.1118145444 |
|
|
Feb 08 06:55:25 PM UTC 25 |
Feb 08 06:55:49 PM UTC 25 |
9807890914 ps |
| T388 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3644722850 |
|
|
Feb 08 06:53:23 PM UTC 25 |
Feb 08 06:55:50 PM UTC 25 |
14551351132 ps |
| T606 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.529361028 |
|
|
Feb 08 06:55:46 PM UTC 25 |
Feb 08 06:55:51 PM UTC 25 |
201744523 ps |
| T271 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2434252852 |
|
|
Feb 08 06:54:04 PM UTC 25 |
Feb 08 06:55:52 PM UTC 25 |
8745022759 ps |
| T607 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.3737598661 |
|
|
Feb 08 06:55:41 PM UTC 25 |
Feb 08 06:55:52 PM UTC 25 |
3048376940 ps |
| T608 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.711449651 |
|
|
Feb 08 06:55:45 PM UTC 25 |
Feb 08 06:55:53 PM UTC 25 |
776241173 ps |
| T227 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.686797248 |
|
|
Feb 08 06:55:49 PM UTC 25 |
Feb 08 06:55:53 PM UTC 25 |
77418011 ps |
| T609 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1677137494 |
|
|
Feb 08 06:55:45 PM UTC 25 |
Feb 08 06:55:53 PM UTC 25 |
1052593486 ps |
| T610 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.1674687034 |
|
|
Feb 08 06:55:45 PM UTC 25 |
Feb 08 06:55:55 PM UTC 25 |
1565796256 ps |
| T179 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.724062855 |
|
|
Feb 08 06:49:34 PM UTC 25 |
Feb 08 06:55:55 PM UTC 25 |
90625712208 ps |
| T323 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1415575632 |
|
|
Feb 08 06:50:31 PM UTC 25 |
Feb 08 06:55:55 PM UTC 25 |
41049871168 ps |
| T611 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3790543865 |
|
|
Feb 08 06:55:45 PM UTC 25 |
Feb 08 06:55:57 PM UTC 25 |
231957985 ps |
| T612 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3472262012 |
|
|
Feb 08 06:55:55 PM UTC 25 |
Feb 08 06:55:58 PM UTC 25 |
13807024 ps |
| T613 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.782296024 |
|
|
Feb 08 06:55:56 PM UTC 25 |
Feb 08 06:55:58 PM UTC 25 |
14026433 ps |
| T614 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.4043437753 |
|
|
Feb 08 06:55:53 PM UTC 25 |
Feb 08 06:56:00 PM UTC 25 |
96418897 ps |
| T615 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1240006318 |
|
|
Feb 08 06:55:24 PM UTC 25 |
Feb 08 06:56:01 PM UTC 25 |
29352149398 ps |
| T616 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1440142702 |
|
|
Feb 08 06:55:59 PM UTC 25 |
Feb 08 06:56:01 PM UTC 25 |
72787491 ps |
| T617 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.2092107174 |
|
|
Feb 08 06:55:59 PM UTC 25 |
Feb 08 06:56:02 PM UTC 25 |
150441413 ps |
| T618 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.849946627 |
|
|
Feb 08 06:55:57 PM UTC 25 |
Feb 08 06:56:03 PM UTC 25 |
10219159427 ps |
| T619 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.379013248 |
|
|
Feb 08 06:54:51 PM UTC 25 |
Feb 08 06:56:07 PM UTC 25 |
7991148501 ps |
| T620 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.1466086944 |
|
|
Feb 08 06:56:02 PM UTC 25 |
Feb 08 06:56:08 PM UTC 25 |
1212214263 ps |
| T621 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.849636007 |
|
|
Feb 08 06:52:34 PM UTC 25 |
Feb 08 06:56:09 PM UTC 25 |
73219744536 ps |
| T622 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.3441589680 |
|
|
Feb 08 06:55:48 PM UTC 25 |
Feb 08 06:56:10 PM UTC 25 |
12025736155 ps |