| T831 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.410534042 |
|
|
Feb 08 07:00:46 PM UTC 25 |
Feb 08 07:00:49 PM UTC 25 |
59672840 ps |
| T832 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1631362810 |
|
|
Feb 08 07:00:31 PM UTC 25 |
Feb 08 07:00:51 PM UTC 25 |
1533094439 ps |
| T833 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.3254212488 |
|
|
Feb 08 06:55:16 PM UTC 25 |
Feb 08 07:00:52 PM UTC 25 |
73117981915 ps |
| T834 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2882170450 |
|
|
Feb 08 07:00:50 PM UTC 25 |
Feb 08 07:00:52 PM UTC 25 |
54422598 ps |
| T835 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3176217682 |
|
|
Feb 08 07:00:50 PM UTC 25 |
Feb 08 07:00:53 PM UTC 25 |
1290364468 ps |
| T836 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.4168684723 |
|
|
Feb 08 07:00:44 PM UTC 25 |
Feb 08 07:00:53 PM UTC 25 |
482431429 ps |
| T837 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.1358330834 |
|
|
Feb 08 07:00:42 PM UTC 25 |
Feb 08 07:00:53 PM UTC 25 |
1502473411 ps |
| T838 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.4215750200 |
|
|
Feb 08 07:00:34 PM UTC 25 |
Feb 08 07:00:53 PM UTC 25 |
7129570700 ps |
| T839 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.2679944449 |
|
|
Feb 08 07:00:53 PM UTC 25 |
Feb 08 07:00:55 PM UTC 25 |
20555299 ps |
| T840 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.868912298 |
|
|
Feb 08 07:00:53 PM UTC 25 |
Feb 08 07:00:55 PM UTC 25 |
179381320 ps |
| T342 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3809556518 |
|
|
Feb 08 06:59:43 PM UTC 25 |
Feb 08 07:00:56 PM UTC 25 |
10360776058 ps |
| T841 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3471564264 |
|
|
Feb 08 07:00:42 PM UTC 25 |
Feb 08 07:00:57 PM UTC 25 |
3894847113 ps |
| T842 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1015757577 |
|
|
Feb 08 07:00:34 PM UTC 25 |
Feb 08 07:00:59 PM UTC 25 |
5979329397 ps |
| T843 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.2607345366 |
|
|
Feb 08 07:00:56 PM UTC 25 |
Feb 08 07:01:01 PM UTC 25 |
63778433 ps |
| T844 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.44257982 |
|
|
Feb 08 07:00:45 PM UTC 25 |
Feb 08 07:01:02 PM UTC 25 |
1372943256 ps |
| T845 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1506019356 |
|
|
Feb 08 07:00:54 PM UTC 25 |
Feb 08 07:01:04 PM UTC 25 |
588850678 ps |
| T846 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.236235483 |
|
|
Feb 08 07:00:57 PM UTC 25 |
Feb 08 07:01:06 PM UTC 25 |
149292737 ps |
| T847 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.1344287895 |
|
|
Feb 08 06:53:12 PM UTC 25 |
Feb 08 07:01:09 PM UTC 25 |
225344059597 ps |
| T848 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.4087828750 |
|
|
Feb 08 06:59:58 PM UTC 25 |
Feb 08 07:01:09 PM UTC 25 |
12054516428 ps |
| T352 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.23637219 |
|
|
Feb 08 06:55:54 PM UTC 25 |
Feb 08 07:01:09 PM UTC 25 |
47762217146 ps |
| T849 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1700574711 |
|
|
Feb 08 06:50:15 PM UTC 25 |
Feb 08 07:01:09 PM UTC 25 |
331647092592 ps |
| T850 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.3702811396 |
|
|
Feb 08 06:58:38 PM UTC 25 |
Feb 08 07:01:09 PM UTC 25 |
19604722144 ps |
| T396 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1680892504 |
|
|
Feb 08 06:58:39 PM UTC 25 |
Feb 08 07:01:10 PM UTC 25 |
11376794485 ps |
| T851 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.620445339 |
|
|
Feb 08 07:00:56 PM UTC 25 |
Feb 08 07:01:11 PM UTC 25 |
6856895701 ps |
| T852 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.970235277 |
|
|
Feb 08 07:01:10 PM UTC 25 |
Feb 08 07:01:12 PM UTC 25 |
38571180 ps |
| T853 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2601888504 |
|
|
Feb 08 07:01:10 PM UTC 25 |
Feb 08 07:01:12 PM UTC 25 |
19302705 ps |
| T854 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1483718164 |
|
|
Feb 08 07:01:10 PM UTC 25 |
Feb 08 07:01:12 PM UTC 25 |
83558473 ps |
| T855 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1248430823 |
|
|
Feb 08 07:00:46 PM UTC 25 |
Feb 08 07:01:13 PM UTC 25 |
944079076 ps |
| T856 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2978982462 |
|
|
Feb 08 07:00:21 PM UTC 25 |
Feb 08 07:01:14 PM UTC 25 |
10355734106 ps |
| T857 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.428318150 |
|
|
Feb 08 07:01:11 PM UTC 25 |
Feb 08 07:01:14 PM UTC 25 |
104159789 ps |
| T858 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.3468212541 |
|
|
Feb 08 06:57:42 PM UTC 25 |
Feb 08 07:01:15 PM UTC 25 |
206895356393 ps |
| T859 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.402170484 |
|
|
Feb 08 07:00:43 PM UTC 25 |
Feb 08 07:01:16 PM UTC 25 |
1359893556 ps |
| T860 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.290800568 |
|
|
Feb 08 07:01:00 PM UTC 25 |
Feb 08 07:01:16 PM UTC 25 |
2201501753 ps |
| T861 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.550936197 |
|
|
Feb 08 07:00:52 PM UTC 25 |
Feb 08 07:01:17 PM UTC 25 |
4767974761 ps |
| T862 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2412965400 |
|
|
Feb 08 07:01:14 PM UTC 25 |
Feb 08 07:01:19 PM UTC 25 |
41933365 ps |
| T863 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2302126640 |
|
|
Feb 08 07:01:17 PM UTC 25 |
Feb 08 07:01:23 PM UTC 25 |
89310659 ps |
| T370 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.265674111 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:01:24 PM UTC 25 |
2536394460 ps |
| T864 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3409152703 |
|
|
Feb 08 07:01:12 PM UTC 25 |
Feb 08 07:01:24 PM UTC 25 |
1499852828 ps |
| T184 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.2435958854 |
|
|
Feb 08 06:55:17 PM UTC 25 |
Feb 08 07:01:24 PM UTC 25 |
43816997420 ps |
| T865 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1605475966 |
|
|
Feb 08 07:00:54 PM UTC 25 |
Feb 08 07:01:25 PM UTC 25 |
19046816236 ps |
| T866 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2284160893 |
|
|
Feb 08 07:00:54 PM UTC 25 |
Feb 08 07:01:25 PM UTC 25 |
6979450911 ps |
| T231 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3149408503 |
|
|
Feb 08 07:00:40 PM UTC 25 |
Feb 08 07:01:25 PM UTC 25 |
18588479039 ps |
| T867 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.3784472028 |
|
|
Feb 08 07:01:15 PM UTC 25 |
Feb 08 07:01:26 PM UTC 25 |
329900182 ps |
| T868 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1589112846 |
|
|
Feb 08 07:01:13 PM UTC 25 |
Feb 08 07:01:27 PM UTC 25 |
2478988931 ps |
| T869 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.4007438254 |
|
|
Feb 08 07:01:25 PM UTC 25 |
Feb 08 07:01:27 PM UTC 25 |
70200224 ps |
| T870 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2631278851 |
|
|
Feb 08 07:01:25 PM UTC 25 |
Feb 08 07:01:27 PM UTC 25 |
17149960 ps |
| T871 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2561772288 |
|
|
Feb 08 07:01:25 PM UTC 25 |
Feb 08 07:01:27 PM UTC 25 |
33841986 ps |
| T872 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1744857907 |
|
|
Feb 08 07:01:26 PM UTC 25 |
Feb 08 07:01:29 PM UTC 25 |
49055713 ps |
| T873 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2894752374 |
|
|
Feb 08 07:01:10 PM UTC 25 |
Feb 08 07:01:29 PM UTC 25 |
1812522624 ps |
| T874 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1317765191 |
|
|
Feb 08 07:01:26 PM UTC 25 |
Feb 08 07:01:29 PM UTC 25 |
29361395 ps |
| T875 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1024433522 |
|
|
Feb 08 07:00:27 PM UTC 25 |
Feb 08 07:01:29 PM UTC 25 |
7946874596 ps |
| T876 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.3942454865 |
|
|
Feb 08 07:01:13 PM UTC 25 |
Feb 08 07:01:34 PM UTC 25 |
12774515945 ps |
| T877 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1504875919 |
|
|
Feb 08 07:00:31 PM UTC 25 |
Feb 08 07:01:35 PM UTC 25 |
14675201730 ps |
| T878 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.66229287 |
|
|
Feb 08 07:01:06 PM UTC 25 |
Feb 08 07:01:36 PM UTC 25 |
897358718 ps |
| T879 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2878188676 |
|
|
Feb 08 07:01:29 PM UTC 25 |
Feb 08 07:01:39 PM UTC 25 |
855746571 ps |
| T880 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.204119859 |
|
|
Feb 08 07:01:13 PM UTC 25 |
Feb 08 07:01:40 PM UTC 25 |
22064001405 ps |
| T881 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1038191835 |
|
|
Feb 08 06:59:16 PM UTC 25 |
Feb 08 07:01:40 PM UTC 25 |
257940586113 ps |
| T882 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.450689924 |
|
|
Feb 08 07:01:10 PM UTC 25 |
Feb 08 07:01:41 PM UTC 25 |
120229482551 ps |
| T883 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.4276038210 |
|
|
Feb 08 06:57:58 PM UTC 25 |
Feb 08 07:01:42 PM UTC 25 |
21165355774 ps |
| T884 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1626707183 |
|
|
Feb 08 07:01:31 PM UTC 25 |
Feb 08 07:01:43 PM UTC 25 |
715871328 ps |
| T885 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.1353701951 |
|
|
Feb 08 07:01:41 PM UTC 25 |
Feb 08 07:01:43 PM UTC 25 |
14066871 ps |
| T886 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.1395243428 |
|
|
Feb 08 07:01:41 PM UTC 25 |
Feb 08 07:01:43 PM UTC 25 |
41019327 ps |
| T366 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.4174885503 |
|
|
Feb 08 06:59:22 PM UTC 25 |
Feb 08 07:01:44 PM UTC 25 |
20149200493 ps |
| T887 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.4094117247 |
|
|
Feb 08 07:01:28 PM UTC 25 |
Feb 08 07:01:45 PM UTC 25 |
5002801666 ps |
| T888 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3091608343 |
|
|
Feb 08 07:01:41 PM UTC 25 |
Feb 08 07:01:45 PM UTC 25 |
160447724 ps |
| T889 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.602246530 |
|
|
Feb 08 07:01:25 PM UTC 25 |
Feb 08 07:01:45 PM UTC 25 |
1844530844 ps |
| T890 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3766426918 |
|
|
Feb 08 07:01:43 PM UTC 25 |
Feb 08 07:01:46 PM UTC 25 |
51300737 ps |
| T891 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.531894485 |
|
|
Feb 08 07:01:44 PM UTC 25 |
Feb 08 07:01:47 PM UTC 25 |
54638636 ps |
| T892 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2103813679 |
|
|
Feb 08 07:01:30 PM UTC 25 |
Feb 08 07:01:48 PM UTC 25 |
2279876730 ps |
| T893 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2988127200 |
|
|
Feb 08 06:52:39 PM UTC 25 |
Feb 08 07:01:49 PM UTC 25 |
250111455497 ps |
| T894 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.3729881980 |
|
|
Feb 08 07:01:27 PM UTC 25 |
Feb 08 07:01:50 PM UTC 25 |
13318069115 ps |
| T895 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2798805406 |
|
|
Feb 08 07:01:29 PM UTC 25 |
Feb 08 07:01:51 PM UTC 25 |
4286393674 ps |
| T896 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3732218515 |
|
|
Feb 08 07:01:47 PM UTC 25 |
Feb 08 07:01:51 PM UTC 25 |
68094616 ps |
| T897 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2743041706 |
|
|
Feb 08 07:01:45 PM UTC 25 |
Feb 08 07:01:53 PM UTC 25 |
4253813741 ps |
| T898 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1190232382 |
|
|
Feb 08 07:01:27 PM UTC 25 |
Feb 08 07:01:53 PM UTC 25 |
9897426798 ps |
| T899 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.2273326720 |
|
|
Feb 08 07:01:54 PM UTC 25 |
Feb 08 07:01:57 PM UTC 25 |
26907370 ps |
| T344 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3598144228 |
|
|
Feb 08 06:59:50 PM UTC 25 |
Feb 08 07:01:57 PM UTC 25 |
21909489090 ps |
| T900 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.578857346 |
|
|
Feb 08 07:01:46 PM UTC 25 |
Feb 08 07:01:58 PM UTC 25 |
1504251366 ps |
| T901 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.3936289304 |
|
|
Feb 08 07:01:57 PM UTC 25 |
Feb 08 07:02:00 PM UTC 25 |
14307679 ps |
| T902 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.4196507662 |
|
|
Feb 08 07:01:50 PM UTC 25 |
Feb 08 07:02:00 PM UTC 25 |
553070478 ps |
| T232 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.3375786725 |
|
|
Feb 08 07:01:02 PM UTC 25 |
Feb 08 07:02:00 PM UTC 25 |
3194428241 ps |
| T903 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3843763996 |
|
|
Feb 08 07:02:01 PM UTC 25 |
Feb 08 07:02:03 PM UTC 25 |
14006150 ps |
| T904 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2566979460 |
|
|
Feb 08 07:02:01 PM UTC 25 |
Feb 08 07:02:03 PM UTC 25 |
50733777 ps |
| T905 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2775432076 |
|
|
Feb 08 07:01:46 PM UTC 25 |
Feb 08 07:02:05 PM UTC 25 |
13701189033 ps |
| T906 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1241900006 |
|
|
Feb 08 07:00:46 PM UTC 25 |
Feb 08 07:02:05 PM UTC 25 |
10471511575 ps |
| T907 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.2178485385 |
|
|
Feb 08 07:01:43 PM UTC 25 |
Feb 08 07:02:05 PM UTC 25 |
2728981680 ps |
| T908 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1390755966 |
|
|
Feb 08 07:01:57 PM UTC 25 |
Feb 08 07:02:05 PM UTC 25 |
883291637 ps |
| T909 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.3741627258 |
|
|
Feb 08 07:01:48 PM UTC 25 |
Feb 08 07:02:07 PM UTC 25 |
1223156667 ps |
| T910 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3314895527 |
|
|
Feb 08 07:01:30 PM UTC 25 |
Feb 08 07:02:07 PM UTC 25 |
5254402762 ps |
| T911 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2994699796 |
|
|
Feb 08 07:01:13 PM UTC 25 |
Feb 08 07:02:09 PM UTC 25 |
27151730546 ps |
| T912 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1691869191 |
|
|
Feb 08 07:02:01 PM UTC 25 |
Feb 08 07:02:10 PM UTC 25 |
907162279 ps |
| T348 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2853802128 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:02:10 PM UTC 25 |
64083378640 ps |
| T913 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3820839762 |
|
|
Feb 08 07:02:06 PM UTC 25 |
Feb 08 07:02:11 PM UTC 25 |
174184474 ps |
| T914 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.844705823 |
|
|
Feb 08 07:00:58 PM UTC 25 |
Feb 08 07:02:11 PM UTC 25 |
3297968705 ps |
| T915 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1222311519 |
|
|
Feb 08 07:02:06 PM UTC 25 |
Feb 08 07:02:12 PM UTC 25 |
2002584568 ps |
| T916 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1800426869 |
|
|
Feb 08 07:02:11 PM UTC 25 |
Feb 08 07:02:14 PM UTC 25 |
49860038 ps |
| T917 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.3490100759 |
|
|
Feb 08 07:00:54 PM UTC 25 |
Feb 08 07:02:15 PM UTC 25 |
54772477921 ps |
| T918 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3458643839 |
|
|
Feb 08 07:02:13 PM UTC 25 |
Feb 08 07:02:15 PM UTC 25 |
12690027 ps |
| T919 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.153675239 |
|
|
Feb 08 07:02:13 PM UTC 25 |
Feb 08 07:02:15 PM UTC 25 |
29471983 ps |
| T920 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.321070224 |
|
|
Feb 08 07:02:08 PM UTC 25 |
Feb 08 07:02:15 PM UTC 25 |
390194272 ps |
| T921 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1753760657 |
|
|
Feb 08 07:02:16 PM UTC 25 |
Feb 08 07:02:18 PM UTC 25 |
29056477 ps |
| T922 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2902342541 |
|
|
Feb 08 07:02:04 PM UTC 25 |
Feb 08 07:02:19 PM UTC 25 |
2230801594 ps |
| T923 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.1151080000 |
|
|
Feb 08 07:02:16 PM UTC 25 |
Feb 08 07:02:20 PM UTC 25 |
604586310 ps |
| T924 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.2579147544 |
|
|
Feb 08 07:02:06 PM UTC 25 |
Feb 08 07:02:21 PM UTC 25 |
6288204402 ps |
| T925 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.556883625 |
|
|
Feb 08 07:02:06 PM UTC 25 |
Feb 08 07:02:21 PM UTC 25 |
429976611 ps |
| T926 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.4210405581 |
|
|
Feb 08 07:02:16 PM UTC 25 |
Feb 08 07:02:22 PM UTC 25 |
1636269501 ps |
| T927 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2547848412 |
|
|
Feb 08 07:02:15 PM UTC 25 |
Feb 08 07:02:23 PM UTC 25 |
847943467 ps |
| T928 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.300484626 |
|
|
Feb 08 06:59:22 PM UTC 25 |
Feb 08 07:02:23 PM UTC 25 |
105359712225 ps |
| T929 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3355637248 |
|
|
Feb 08 07:02:20 PM UTC 25 |
Feb 08 07:02:24 PM UTC 25 |
131330754 ps |
| T930 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2101596953 |
|
|
Feb 08 07:02:19 PM UTC 25 |
Feb 08 07:02:25 PM UTC 25 |
381800411 ps |
| T931 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.4033654653 |
|
|
Feb 08 07:01:59 PM UTC 25 |
Feb 08 07:02:26 PM UTC 25 |
9571286603 ps |
| T932 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1111722339 |
|
|
Feb 08 07:01:44 PM UTC 25 |
Feb 08 07:02:27 PM UTC 25 |
13096413020 ps |
| T933 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.425810417 |
|
|
Feb 08 07:02:21 PM UTC 25 |
Feb 08 07:02:27 PM UTC 25 |
487894362 ps |
| T934 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.629290594 |
|
|
Feb 08 07:02:28 PM UTC 25 |
Feb 08 07:02:30 PM UTC 25 |
27749523 ps |
| T935 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.3569631382 |
|
|
Feb 08 07:02:28 PM UTC 25 |
Feb 08 07:02:30 PM UTC 25 |
106217088 ps |
| T936 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.3673676150 |
|
|
Feb 08 06:58:18 PM UTC 25 |
Feb 08 07:02:30 PM UTC 25 |
51319364132 ps |
| T937 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.875382286 |
|
|
Feb 08 07:02:21 PM UTC 25 |
Feb 08 07:02:31 PM UTC 25 |
1279549768 ps |
| T938 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1123445912 |
|
|
Feb 08 07:02:24 PM UTC 25 |
Feb 08 07:02:32 PM UTC 25 |
819404385 ps |
| T939 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3381993455 |
|
|
Feb 08 07:02:31 PM UTC 25 |
Feb 08 07:02:33 PM UTC 25 |
11441858 ps |
| T940 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.733159055 |
|
|
Feb 08 07:02:31 PM UTC 25 |
Feb 08 07:02:33 PM UTC 25 |
48120665 ps |
| T941 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2116872857 |
|
|
Feb 08 06:54:04 PM UTC 25 |
Feb 08 07:02:34 PM UTC 25 |
44650165418 ps |
| T350 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.4007221583 |
|
|
Feb 08 07:01:20 PM UTC 25 |
Feb 08 07:02:34 PM UTC 25 |
18697890932 ps |
| T341 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1806234890 |
|
|
Feb 08 07:01:51 PM UTC 25 |
Feb 08 07:02:34 PM UTC 25 |
6324594926 ps |
| T942 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2926112487 |
|
|
Feb 08 07:02:32 PM UTC 25 |
Feb 08 07:02:35 PM UTC 25 |
77315844 ps |
| T943 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.1598875851 |
|
|
Feb 08 07:02:33 PM UTC 25 |
Feb 08 07:02:35 PM UTC 25 |
19149088 ps |
| T944 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1616839491 |
|
|
Feb 08 07:02:22 PM UTC 25 |
Feb 08 07:02:35 PM UTC 25 |
3830372590 ps |
| T364 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1485570304 |
|
|
Feb 08 07:02:04 PM UTC 25 |
Feb 08 07:02:37 PM UTC 25 |
4761010644 ps |
| T945 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1525218774 |
|
|
Feb 08 07:02:22 PM UTC 25 |
Feb 08 07:02:37 PM UTC 25 |
1096903641 ps |
| T946 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1310726185 |
|
|
Feb 08 07:02:34 PM UTC 25 |
Feb 08 07:02:39 PM UTC 25 |
71457467 ps |
| T947 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3505519685 |
|
|
Feb 08 07:02:35 PM UTC 25 |
Feb 08 07:02:41 PM UTC 25 |
445623330 ps |
| T948 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.2943931267 |
|
|
Feb 08 07:02:35 PM UTC 25 |
Feb 08 07:02:42 PM UTC 25 |
434504843 ps |
| T949 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3264851700 |
|
|
Feb 08 07:01:46 PM UTC 25 |
Feb 08 07:02:43 PM UTC 25 |
18293353126 ps |
| T359 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1082571103 |
|
|
Feb 08 07:01:07 PM UTC 25 |
Feb 08 07:02:44 PM UTC 25 |
3848022854 ps |
| T950 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.798350721 |
|
|
Feb 08 07:02:44 PM UTC 25 |
Feb 08 07:02:46 PM UTC 25 |
80798991 ps |
| T951 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.1541297855 |
|
|
Feb 08 07:02:44 PM UTC 25 |
Feb 08 07:02:46 PM UTC 25 |
31360320 ps |
| T952 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3713132300 |
|
|
Feb 08 07:02:34 PM UTC 25 |
Feb 08 07:02:47 PM UTC 25 |
736030597 ps |
| T953 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.969678213 |
|
|
Feb 08 07:02:35 PM UTC 25 |
Feb 08 07:02:50 PM UTC 25 |
916724301 ps |
| T954 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.860332448 |
|
|
Feb 08 07:02:48 PM UTC 25 |
Feb 08 07:02:51 PM UTC 25 |
27834066 ps |
| T955 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1117324647 |
|
|
Feb 08 07:02:34 PM UTC 25 |
Feb 08 07:02:53 PM UTC 25 |
2669497329 ps |
| T956 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2212794369 |
|
|
Feb 08 07:02:51 PM UTC 25 |
Feb 08 07:02:56 PM UTC 25 |
101212520 ps |
| T957 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.1552022327 |
|
|
Feb 08 07:02:51 PM UTC 25 |
Feb 08 07:02:56 PM UTC 25 |
59969666 ps |
| T958 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2537515527 |
|
|
Feb 08 07:02:38 PM UTC 25 |
Feb 08 07:03:01 PM UTC 25 |
1296265193 ps |
| T81 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.572614840 |
|
|
Feb 08 06:54:52 PM UTC 25 |
Feb 08 07:03:02 PM UTC 25 |
44704383341 ps |
| T959 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.960388968 |
|
|
Feb 08 07:02:37 PM UTC 25 |
Feb 08 07:03:04 PM UTC 25 |
1436712278 ps |
| T960 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3374708735 |
|
|
Feb 08 07:02:47 PM UTC 25 |
Feb 08 07:03:04 PM UTC 25 |
1495458384 ps |
| T961 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.441794386 |
|
|
Feb 08 07:02:56 PM UTC 25 |
Feb 08 07:03:04 PM UTC 25 |
107111230 ps |
| T962 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.1634217431 |
|
|
Feb 08 07:02:58 PM UTC 25 |
Feb 08 07:03:05 PM UTC 25 |
2007023406 ps |
| T963 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.523962476 |
|
|
Feb 08 07:02:16 PM UTC 25 |
Feb 08 07:03:05 PM UTC 25 |
21812848018 ps |
| T964 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3972318600 |
|
|
Feb 08 07:03:02 PM UTC 25 |
Feb 08 07:03:05 PM UTC 25 |
223348109 ps |
| T965 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3935638393 |
|
|
Feb 08 07:03:03 PM UTC 25 |
Feb 08 07:03:06 PM UTC 25 |
43848480 ps |
| T966 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2236602039 |
|
|
Feb 08 07:03:05 PM UTC 25 |
Feb 08 07:03:07 PM UTC 25 |
52788537 ps |
| T967 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.159431658 |
|
|
Feb 08 07:03:05 PM UTC 25 |
Feb 08 07:03:10 PM UTC 25 |
32270166 ps |
| T968 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.718262127 |
|
|
Feb 08 07:03:08 PM UTC 25 |
Feb 08 07:03:10 PM UTC 25 |
42633418 ps |
| T969 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.4250406985 |
|
|
Feb 08 07:02:31 PM UTC 25 |
Feb 08 07:03:12 PM UTC 25 |
8726864651 ps |
| T970 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.3220170958 |
|
|
Feb 08 07:02:09 PM UTC 25 |
Feb 08 07:03:12 PM UTC 25 |
11441486197 ps |
| T971 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.514458223 |
|
|
Feb 08 07:03:05 PM UTC 25 |
Feb 08 07:03:14 PM UTC 25 |
807330170 ps |
| T349 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.2982520861 |
|
|
Feb 08 07:01:24 PM UTC 25 |
Feb 08 07:03:14 PM UTC 25 |
4333218305 ps |
| T972 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.778018913 |
|
|
Feb 08 07:01:35 PM UTC 25 |
Feb 08 07:03:15 PM UTC 25 |
6585187575 ps |
| T356 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.2243523869 |
|
|
Feb 08 06:56:12 PM UTC 25 |
Feb 08 07:03:19 PM UTC 25 |
99533038591 ps |
| T973 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.1487632393 |
|
|
Feb 08 07:03:06 PM UTC 25 |
Feb 08 07:03:23 PM UTC 25 |
528857540 ps |
| T974 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1835584843 |
|
|
Feb 08 07:02:47 PM UTC 25 |
Feb 08 07:03:28 PM UTC 25 |
61878321731 ps |
| T975 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2244717716 |
|
|
Feb 08 07:02:23 PM UTC 25 |
Feb 08 07:03:30 PM UTC 25 |
21737307112 ps |
| T976 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4141297842 |
|
|
Feb 08 07:03:06 PM UTC 25 |
Feb 08 07:03:33 PM UTC 25 |
4455837576 ps |
| T977 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2747641531 |
|
|
Feb 08 06:53:24 PM UTC 25 |
Feb 08 07:03:35 PM UTC 25 |
247880164562 ps |
| T360 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3731086407 |
|
|
Feb 08 06:54:24 PM UTC 25 |
Feb 08 07:03:44 PM UTC 25 |
216106439287 ps |
| T978 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.870392355 |
|
|
Feb 08 07:02:38 PM UTC 25 |
Feb 08 07:03:44 PM UTC 25 |
8834663397 ps |
| T979 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.965750204 |
|
|
Feb 08 07:02:53 PM UTC 25 |
Feb 08 07:03:45 PM UTC 25 |
8359424489 ps |
| T980 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.2224547110 |
|
|
Feb 08 07:02:24 PM UTC 25 |
Feb 08 07:03:58 PM UTC 25 |
25223465020 ps |
| T343 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1014061502 |
|
|
Feb 08 07:01:17 PM UTC 25 |
Feb 08 07:04:02 PM UTC 25 |
28012575839 ps |
| T369 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2373064236 |
|
|
Feb 08 07:01:51 PM UTC 25 |
Feb 08 07:04:16 PM UTC 25 |
9703806854 ps |
| T981 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3170691134 |
|
|
Feb 08 07:01:30 PM UTC 25 |
Feb 08 07:04:20 PM UTC 25 |
233878494371 ps |
| T982 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.4097846385 |
|
|
Feb 08 07:01:03 PM UTC 25 |
Feb 08 07:04:23 PM UTC 25 |
80050256756 ps |
| T362 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1122660769 |
|
|
Feb 08 07:01:49 PM UTC 25 |
Feb 08 07:04:28 PM UTC 25 |
11607126312 ps |
| T983 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.3308233579 |
|
|
Feb 08 06:57:26 PM UTC 25 |
Feb 08 07:04:31 PM UTC 25 |
43671090948 ps |
| T984 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2877325100 |
|
|
Feb 08 07:02:11 PM UTC 25 |
Feb 08 07:04:33 PM UTC 25 |
7922962368 ps |
| T985 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.3797062297 |
|
|
Feb 08 06:51:15 PM UTC 25 |
Feb 08 07:04:36 PM UTC 25 |
278237416976 ps |
| T345 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3144810175 |
|
|
Feb 08 06:56:46 PM UTC 25 |
Feb 08 07:04:49 PM UTC 25 |
151132817790 ps |
| T986 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1374702402 |
|
|
Feb 08 07:00:46 PM UTC 25 |
Feb 08 07:05:05 PM UTC 25 |
36941807355 ps |
| T987 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2743148248 |
|
|
Feb 08 07:01:19 PM UTC 25 |
Feb 08 07:05:06 PM UTC 25 |
326108509959 ps |
| T988 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3408432944 |
|
|
Feb 08 06:58:33 PM UTC 25 |
Feb 08 07:05:15 PM UTC 25 |
158181871546 ps |
| T989 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.720320020 |
|
|
Feb 08 07:00:09 PM UTC 25 |
Feb 08 07:05:22 PM UTC 25 |
31565570874 ps |
| T990 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.848763300 |
|
|
Feb 08 07:01:37 PM UTC 25 |
Feb 08 07:05:24 PM UTC 25 |
27173135870 ps |
| T991 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.983882217 |
|
|
Feb 08 06:56:45 PM UTC 25 |
Feb 08 07:05:31 PM UTC 25 |
261235085415 ps |
| T164 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2470631207 |
|
|
Feb 08 07:01:52 PM UTC 25 |
Feb 08 07:05:33 PM UTC 25 |
108277015079 ps |
| T992 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1481630183 |
|
|
Feb 08 07:00:31 PM UTC 25 |
Feb 08 07:06:07 PM UTC 25 |
135805041727 ps |
| T361 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3793817288 |
|
|
Feb 08 07:00:43 PM UTC 25 |
Feb 08 07:06:13 PM UTC 25 |
193048983387 ps |
| T993 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3894776055 |
|
|
Feb 08 07:02:26 PM UTC 25 |
Feb 08 07:06:31 PM UTC 25 |
206819507908 ps |
| T82 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3538334775 |
|
|
Feb 08 07:02:11 PM UTC 25 |
Feb 08 07:06:34 PM UTC 25 |
22623038814 ps |
| T994 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1971912623 |
|
|
Feb 08 07:02:27 PM UTC 25 |
Feb 08 07:06:55 PM UTC 25 |
24472033426 ps |
| T363 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.627380370 |
|
|
Feb 08 06:54:06 PM UTC 25 |
Feb 08 07:07:11 PM UTC 25 |
182939653144 ps |
| T995 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1141923478 |
|
|
Feb 08 07:02:37 PM UTC 25 |
Feb 08 07:07:12 PM UTC 25 |
119786466148 ps |
| T996 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.396438825 |
|
|
Feb 08 07:02:42 PM UTC 25 |
Feb 08 07:07:20 PM UTC 25 |
30859852899 ps |
| T997 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.3638234989 |
|
|
Feb 08 06:59:23 PM UTC 25 |
Feb 08 07:07:30 PM UTC 25 |
136064575591 ps |
| T998 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1411300617 |
|
|
Feb 08 07:03:07 PM UTC 25 |
Feb 08 07:07:33 PM UTC 25 |
35158522969 ps |
| T83 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.369674277 |
|
|
Feb 08 07:02:40 PM UTC 25 |
Feb 08 07:07:46 PM UTC 25 |
19054650887 ps |
| T999 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1645021422 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:08:04 PM UTC 25 |
212264123450 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3623372335 |
|
|
Feb 08 07:03:06 PM UTC 25 |
Feb 08 07:08:21 PM UTC 25 |
187365018291 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1130699411 |
|
|
Feb 08 07:02:08 PM UTC 25 |
Feb 08 07:08:58 PM UTC 25 |
47695896813 ps |
| T165 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3389185855 |
|
|
Feb 08 06:59:10 PM UTC 25 |
Feb 08 07:09:08 PM UTC 25 |
52608417381 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.716320929 |
|
|
Feb 08 06:58:15 PM UTC 25 |
Feb 08 07:09:16 PM UTC 25 |
258144509359 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.2700167083 |
|
|
Feb 08 07:00:29 PM UTC 25 |
Feb 08 07:11:18 PM UTC 25 |
110113154075 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1666432351 |
|
|
Feb 08 07:01:53 PM UTC 25 |
Feb 08 07:11:23 PM UTC 25 |
120062909666 ps |
| T1005 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1900264581 |
|
|
Feb 08 07:01:36 PM UTC 25 |
Feb 08 07:11:43 PM UTC 25 |
459340616256 ps |
| T1006 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.4202395570 |
|
|
Feb 08 07:01:17 PM UTC 25 |
Feb 08 07:12:15 PM UTC 25 |
350652937066 ps |
| T1007 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.2953754312 |
|
|
Feb 08 07:02:43 PM UTC 25 |
Feb 08 07:12:22 PM UTC 25 |
119736062565 ps |
| T371 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.381752199 |
|
|
Feb 08 07:01:40 PM UTC 25 |
Feb 08 07:19:23 PM UTC 25 |
83841951501 ps |
| T1008 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1861341904 |
|
|
Feb 08 07:03:12 PM UTC 25 |
Feb 08 07:03:15 PM UTC 25 |
13999713 ps |
| T1009 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2690236997 |
|
|
Feb 08 07:03:12 PM UTC 25 |
Feb 08 07:03:15 PM UTC 25 |
45759314 ps |
| T146 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1863703653 |
|
|
Feb 08 07:03:14 PM UTC 25 |
Feb 08 07:03:18 PM UTC 25 |
39978385 ps |
| T98 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1747523892 |
|
|
Feb 08 07:03:10 PM UTC 25 |
Feb 08 07:03:18 PM UTC 25 |
814472086 ps |
| T109 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3823241394 |
|
|
Feb 08 07:03:16 PM UTC 25 |
Feb 08 07:03:19 PM UTC 25 |
51960656 ps |
| T147 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3442538648 |
|
|
Feb 08 07:03:16 PM UTC 25 |
Feb 08 07:03:20 PM UTC 25 |
88564478 ps |
| T166 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1832513532 |
|
|
Feb 08 07:03:19 PM UTC 25 |
Feb 08 07:03:23 PM UTC 25 |
52724292 ps |
| T1010 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3329973556 |
|
|
Feb 08 07:03:21 PM UTC 25 |
Feb 08 07:03:23 PM UTC 25 |
11661910 ps |
| T99 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2167032930 |
|
|
Feb 08 07:03:11 PM UTC 25 |
Feb 08 07:03:24 PM UTC 25 |
352068624 ps |
| T100 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2524841070 |
|
|
Feb 08 07:03:19 PM UTC 25 |
Feb 08 07:03:24 PM UTC 25 |
156650280 ps |
| T123 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1733480621 |
|
|
Feb 08 07:03:20 PM UTC 25 |
Feb 08 07:03:24 PM UTC 25 |
32391714 ps |
| T1011 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1330703449 |
|
|
Feb 08 07:03:23 PM UTC 25 |
Feb 08 07:03:25 PM UTC 25 |
17216371 ps |
| T1012 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.4104031312 |
|
|
Feb 08 07:03:17 PM UTC 25 |
Feb 08 07:03:26 PM UTC 25 |
221088648 ps |
| T110 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3916464131 |
|
|
Feb 08 07:03:24 PM UTC 25 |
Feb 08 07:03:27 PM UTC 25 |
51128408 ps |
| T167 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1966818447 |
|
|
Feb 08 07:03:24 PM UTC 25 |
Feb 08 07:03:27 PM UTC 25 |
158114380 ps |
| T148 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1305220891 |
|
|
Feb 08 07:03:24 PM UTC 25 |
Feb 08 07:03:28 PM UTC 25 |
45228920 ps |
| T168 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4272284334 |
|
|
Feb 08 07:03:27 PM UTC 25 |
Feb 08 07:03:30 PM UTC 25 |
62972247 ps |
| T1013 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.4239845377 |
|
|
Feb 08 07:03:29 PM UTC 25 |
Feb 08 07:03:31 PM UTC 25 |
16242014 ps |
| T1014 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1064674440 |
|
|
Feb 08 07:03:29 PM UTC 25 |
Feb 08 07:03:31 PM UTC 25 |
101665229 ps |
| T124 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3679426913 |
|
|
Feb 08 07:03:27 PM UTC 25 |
Feb 08 07:03:32 PM UTC 25 |
125922014 ps |
| T125 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3359870807 |
|
|
Feb 08 07:03:28 PM UTC 25 |
Feb 08 07:03:34 PM UTC 25 |
139736587 ps |
| T149 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2597239202 |
|
|
Feb 08 07:03:31 PM UTC 25 |
Feb 08 07:03:34 PM UTC 25 |
46452315 ps |
| T111 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.772748637 |
|
|
Feb 08 07:03:31 PM UTC 25 |
Feb 08 07:03:34 PM UTC 25 |
22261263 ps |
| T150 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1480333000 |
|
|
Feb 08 07:03:32 PM UTC 25 |
Feb 08 07:03:37 PM UTC 25 |
108457691 ps |
| T151 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3729395750 |
|
|
Feb 08 07:03:26 PM UTC 25 |
Feb 08 07:03:38 PM UTC 25 |
387979491 ps |
| T1015 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.3507191133 |
|
|
Feb 08 07:03:36 PM UTC 25 |
Feb 08 07:03:38 PM UTC 25 |
83263162 ps |
| T169 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3022781808 |
|
|
Feb 08 07:03:33 PM UTC 25 |
Feb 08 07:03:38 PM UTC 25 |
617113704 ps |
| T143 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3583816833 |
|
|
Feb 08 07:03:34 PM UTC 25 |
Feb 08 07:03:39 PM UTC 25 |
41224290 ps |
| T134 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2128899726 |
|
|
Feb 08 07:03:35 PM UTC 25 |
Feb 08 07:03:40 PM UTC 25 |
49791549 ps |
| T1016 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.456166739 |
|
|
Feb 08 07:03:38 PM UTC 25 |
Feb 08 07:03:40 PM UTC 25 |
164384519 ps |
| T153 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1395607230 |
|
|
Feb 08 07:03:25 PM UTC 25 |
Feb 08 07:03:41 PM UTC 25 |
7556700807 ps |
| T152 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1456385715 |
|
|
Feb 08 07:03:38 PM UTC 25 |
Feb 08 07:03:41 PM UTC 25 |
121723727 ps |
| T1017 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2588857724 |
|
|
Feb 08 07:03:39 PM UTC 25 |
Feb 08 07:03:42 PM UTC 25 |
30641523 ps |
| T154 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2122389638 |
|
|
Feb 08 07:03:39 PM UTC 25 |
Feb 08 07:03:44 PM UTC 25 |
35532660 ps |
| T175 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2125166455 |
|
|
Feb 08 07:03:41 PM UTC 25 |
Feb 08 07:03:45 PM UTC 25 |
70952142 ps |
| T155 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1486456043 |
|
|
Feb 08 07:03:33 PM UTC 25 |
Feb 08 07:03:46 PM UTC 25 |
111235306 ps |
| T126 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.4266412668 |
|
|
Feb 08 07:03:35 PM UTC 25 |
Feb 08 07:03:46 PM UTC 25 |
321531950 ps |
| T1018 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1109868785 |
|
|
Feb 08 07:03:43 PM UTC 25 |
Feb 08 07:03:46 PM UTC 25 |
13035580 ps |
| T144 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.383978079 |
|
|
Feb 08 07:03:41 PM UTC 25 |
Feb 08 07:03:46 PM UTC 25 |
81481003 ps |
| T127 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2997516306 |
|
|
Feb 08 07:03:20 PM UTC 25 |
Feb 08 07:03:47 PM UTC 25 |
1110857868 ps |
| T1019 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3092363732 |
|
|
Feb 08 07:03:44 PM UTC 25 |
Feb 08 07:03:47 PM UTC 25 |
16113489 ps |
| T137 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.49644082 |
|
|
Feb 08 07:03:42 PM UTC 25 |
Feb 08 07:03:48 PM UTC 25 |
2089389884 ps |
| T1020 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2440440167 |
|
|
Feb 08 07:03:44 PM UTC 25 |
Feb 08 07:03:48 PM UTC 25 |
144618485 ps |
| T1021 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.727059874 |
|
|
Feb 08 07:03:46 PM UTC 25 |
Feb 08 07:03:49 PM UTC 25 |
25660092 ps |