| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.04 | 98.38 | 93.99 | 98.62 | 89.36 | 97.19 | 95.45 | 99.26 |
| T176 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.556933122 | Feb 08 07:03:46 PM UTC 25 | Feb 08 07:03:50 PM UTC 25 | 188194467 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3338408661 | Feb 08 07:03:48 PM UTC 25 | Feb 08 07:03:50 PM UTC 25 | 44972352 ps | ||
| T140 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3073085535 | Feb 08 07:03:47 PM UTC 25 | Feb 08 07:03:52 PM UTC 25 | 171315149 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3733297622 | Feb 08 07:03:47 PM UTC 25 | Feb 08 07:03:52 PM UTC 25 | 163424564 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3387148284 | Feb 08 07:03:49 PM UTC 25 | Feb 08 07:03:53 PM UTC 25 | 39537714 ps | ||
| T177 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2124242326 | Feb 08 07:03:49 PM UTC 25 | Feb 08 07:03:54 PM UTC 25 | 176532119 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3279807354 | Feb 08 07:03:49 PM UTC 25 | Feb 08 07:03:54 PM UTC 25 | 831850263 ps | ||
| T138 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3752015530 | Feb 08 07:03:48 PM UTC 25 | Feb 08 07:03:55 PM UTC 25 | 257624193 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3774888815 | Feb 08 07:03:53 PM UTC 25 | Feb 08 07:03:56 PM UTC 25 | 43206022 ps | ||
| T210 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2368678054 | Feb 08 07:03:29 PM UTC 25 | Feb 08 07:03:56 PM UTC 25 | 311679139 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.570105846 | Feb 08 07:03:54 PM UTC 25 | Feb 08 07:03:57 PM UTC 25 | 58999034 ps | ||
| T135 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1149551435 | Feb 08 07:03:50 PM UTC 25 | Feb 08 07:03:58 PM UTC 25 | 660604581 ps | ||
| T136 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2709855427 | Feb 08 07:03:55 PM UTC 25 | Feb 08 07:03:59 PM UTC 25 | 80657766 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2635539792 | Feb 08 07:03:57 PM UTC 25 | Feb 08 07:03:59 PM UTC 25 | 31652053 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3859396938 | Feb 08 07:03:40 PM UTC 25 | Feb 08 07:03:59 PM UTC 25 | 613407602 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.212417483 | Feb 08 07:03:54 PM UTC 25 | Feb 08 07:04:00 PM UTC 25 | 61631378 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2038180892 | Feb 08 07:03:57 PM UTC 25 | Feb 08 07:04:01 PM UTC 25 | 145245443 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3093405715 | Feb 08 07:03:55 PM UTC 25 | Feb 08 07:04:01 PM UTC 25 | 75298676 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2939633391 | Feb 08 07:03:39 PM UTC 25 | Feb 08 07:04:01 PM UTC 25 | 1407435665 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.46912875 | Feb 08 07:03:58 PM UTC 25 | Feb 08 07:04:03 PM UTC 25 | 175364234 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1024155376 | Feb 08 07:04:00 PM UTC 25 | Feb 08 07:04:03 PM UTC 25 | 50942320 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.532489589 | Feb 08 07:03:16 PM UTC 25 | Feb 08 07:04:03 PM UTC 25 | 749839263 ps | ||
| T212 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.4044717420 | Feb 08 07:03:51 PM UTC 25 | Feb 08 07:04:03 PM UTC 25 | 569855033 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2137038948 | Feb 08 07:03:59 PM UTC 25 | Feb 08 07:04:04 PM UTC 25 | 245904305 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3239056150 | Feb 08 07:04:00 PM UTC 25 | Feb 08 07:04:04 PM UTC 25 | 93424700 ps | ||
| T219 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3019194886 | Feb 08 07:03:48 PM UTC 25 | Feb 08 07:04:04 PM UTC 25 | 1100578674 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3184013799 | Feb 08 07:04:03 PM UTC 25 | Feb 08 07:04:05 PM UTC 25 | 11718836 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.260662663 | Feb 08 07:03:56 PM UTC 25 | Feb 08 07:04:05 PM UTC 25 | 112018648 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3741427810 | Feb 08 07:03:47 PM UTC 25 | Feb 08 07:04:06 PM UTC 25 | 183031910 ps | ||
| T139 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3534014128 | Feb 08 07:03:59 PM UTC 25 | Feb 08 07:04:06 PM UTC 25 | 62859705 ps | ||
| T141 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2129790516 | Feb 08 07:04:01 PM UTC 25 | Feb 08 07:04:06 PM UTC 25 | 1068673766 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2448536035 | Feb 08 07:04:04 PM UTC 25 | Feb 08 07:04:07 PM UTC 25 | 37988713 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2249549991 | Feb 08 07:04:05 PM UTC 25 | Feb 08 07:04:08 PM UTC 25 | 112950245 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3811814343 | Feb 08 07:04:01 PM UTC 25 | Feb 08 07:04:07 PM UTC 25 | 1282897612 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1758505700 | Feb 08 07:04:04 PM UTC 25 | Feb 08 07:04:08 PM UTC 25 | 26392662 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.81171793 | Feb 08 07:04:01 PM UTC 25 | Feb 08 07:04:08 PM UTC 25 | 147676458 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3269048380 | Feb 08 07:04:04 PM UTC 25 | Feb 08 07:04:08 PM UTC 25 | 43136263 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2422508594 | Feb 08 07:03:47 PM UTC 25 | Feb 08 07:04:09 PM UTC 25 | 2508125134 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2939177179 | Feb 08 07:04:07 PM UTC 25 | Feb 08 07:04:10 PM UTC 25 | 41294026 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4063160627 | Feb 08 07:04:05 PM UTC 25 | Feb 08 07:04:10 PM UTC 25 | 153268930 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.201668473 | Feb 08 07:04:05 PM UTC 25 | Feb 08 07:04:10 PM UTC 25 | 188445169 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1902122902 | Feb 08 07:04:07 PM UTC 25 | Feb 08 07:04:11 PM UTC 25 | 78735071 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1765698075 | Feb 08 07:04:05 PM UTC 25 | Feb 08 07:04:11 PM UTC 25 | 245400697 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2256098505 | Feb 08 07:03:32 PM UTC 25 | Feb 08 07:04:11 PM UTC 25 | 3829862525 ps | ||
| T211 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1603932899 | Feb 08 07:03:42 PM UTC 25 | Feb 08 07:04:11 PM UTC 25 | 796896092 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3031115664 | Feb 08 07:04:08 PM UTC 25 | Feb 08 07:04:11 PM UTC 25 | 66498005 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2690096040 | Feb 08 07:04:09 PM UTC 25 | Feb 08 07:04:12 PM UTC 25 | 16098188 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4144650993 | Feb 08 07:04:08 PM UTC 25 | Feb 08 07:04:13 PM UTC 25 | 160744268 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3368151010 | Feb 08 07:04:07 PM UTC 25 | Feb 08 07:04:13 PM UTC 25 | 207927497 ps | ||
| T214 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2442923159 | Feb 08 07:04:03 PM UTC 25 | Feb 08 07:04:13 PM UTC 25 | 1387572235 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.795795849 | Feb 08 07:04:11 PM UTC 25 | Feb 08 07:04:14 PM UTC 25 | 276219939 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1067117469 | Feb 08 07:04:09 PM UTC 25 | Feb 08 07:04:15 PM UTC 25 | 370973870 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.931817044 | Feb 08 07:04:11 PM UTC 25 | Feb 08 07:04:15 PM UTC 25 | 55456267 ps | ||
| T142 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2718938507 | Feb 08 07:04:09 PM UTC 25 | Feb 08 07:04:15 PM UTC 25 | 109796978 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2030723163 | Feb 08 07:04:12 PM UTC 25 | Feb 08 07:04:15 PM UTC 25 | 15514753 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1082447930 | Feb 08 07:04:12 PM UTC 25 | Feb 08 07:04:15 PM UTC 25 | 61258673 ps | ||
| T216 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.513489337 | Feb 08 07:04:05 PM UTC 25 | Feb 08 07:04:16 PM UTC 25 | 471203356 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.543895274 | Feb 08 07:04:14 PM UTC 25 | Feb 08 07:04:16 PM UTC 25 | 14418808 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.110388874 | Feb 08 07:04:11 PM UTC 25 | Feb 08 07:04:17 PM UTC 25 | 294037766 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2424742490 | Feb 08 07:04:13 PM UTC 25 | Feb 08 07:04:17 PM UTC 25 | 438095301 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1335992175 | Feb 08 07:04:12 PM UTC 25 | Feb 08 07:04:17 PM UTC 25 | 858515652 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.167668923 | Feb 08 07:04:12 PM UTC 25 | Feb 08 07:04:18 PM UTC 25 | 151575187 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.580594278 | Feb 08 07:04:14 PM UTC 25 | Feb 08 07:04:18 PM UTC 25 | 72874165 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2471807127 | Feb 08 07:04:16 PM UTC 25 | Feb 08 07:04:18 PM UTC 25 | 36154926 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3272358626 | Feb 08 07:04:14 PM UTC 25 | Feb 08 07:04:19 PM UTC 25 | 104916212 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2830210795 | Feb 08 07:04:16 PM UTC 25 | Feb 08 07:04:21 PM UTC 25 | 112222691 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.685108516 | Feb 08 07:04:16 PM UTC 25 | Feb 08 07:04:21 PM UTC 25 | 96794120 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1640664799 | Feb 08 07:04:18 PM UTC 25 | Feb 08 07:04:21 PM UTC 25 | 326227397 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3195929364 | Feb 08 07:04:16 PM UTC 25 | Feb 08 07:04:21 PM UTC 25 | 473866829 ps | ||
| T213 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2386282924 | Feb 08 07:03:59 PM UTC 25 | Feb 08 07:04:21 PM UTC 25 | 317087983 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1349574565 | Feb 08 07:04:18 PM UTC 25 | Feb 08 07:04:22 PM UTC 25 | 1207387418 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.77070382 | Feb 08 07:04:19 PM UTC 25 | Feb 08 07:04:22 PM UTC 25 | 57021080 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1926801693 | Feb 08 07:04:18 PM UTC 25 | Feb 08 07:04:23 PM UTC 25 | 423373118 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.459429756 | Feb 08 07:04:19 PM UTC 25 | Feb 08 07:04:23 PM UTC 25 | 33650260 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.4262141039 | Feb 08 07:04:21 PM UTC 25 | Feb 08 07:04:23 PM UTC 25 | 62440458 ps | ||
| T220 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.3627276484 | Feb 08 07:04:16 PM UTC 25 | Feb 08 07:04:23 PM UTC 25 | 382555577 ps | ||
| T215 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1758789056 | Feb 08 07:04:07 PM UTC 25 | Feb 08 07:04:24 PM UTC 25 | 953719810 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3990646811 | Feb 08 07:04:20 PM UTC 25 | Feb 08 07:04:24 PM UTC 25 | 463465201 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.654246538 | Feb 08 07:04:20 PM UTC 25 | Feb 08 07:04:24 PM UTC 25 | 148926006 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.3508546512 | Feb 08 07:04:23 PM UTC 25 | Feb 08 07:04:26 PM UTC 25 | 15496316 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3392081576 | Feb 08 07:04:20 PM UTC 25 | Feb 08 07:04:26 PM UTC 25 | 217045383 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2430120426 | Feb 08 07:04:16 PM UTC 25 | Feb 08 07:04:26 PM UTC 25 | 1156003058 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3446457343 | Feb 08 07:04:23 PM UTC 25 | Feb 08 07:04:27 PM UTC 25 | 55451871 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2506300525 | Feb 08 07:04:23 PM UTC 25 | Feb 08 07:04:27 PM UTC 25 | 100120319 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2543385265 | Feb 08 07:04:23 PM UTC 25 | Feb 08 07:04:27 PM UTC 25 | 79260422 ps | ||
| T221 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4023409426 | Feb 08 07:04:09 PM UTC 25 | Feb 08 07:04:28 PM UTC 25 | 294332631 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1855740583 | Feb 08 07:04:23 PM UTC 25 | Feb 08 07:04:28 PM UTC 25 | 89631428 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1810404513 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:28 PM UTC 25 | 25816254 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2875085003 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:29 PM UTC 25 | 19409690 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2441131108 | Feb 08 07:04:23 PM UTC 25 | Feb 08 07:04:29 PM UTC 25 | 537458484 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.272059237 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:29 PM UTC 25 | 113852081 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1652794661 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 106361833 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3630061169 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 61825671 ps | ||
| T217 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.838981147 | Feb 08 07:04:12 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 713421618 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4155244747 | Feb 08 07:04:28 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 21079854 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.374416031 | Feb 08 07:04:28 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 43765067 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.406530653 | Feb 08 07:04:28 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 12983696 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.4044350659 | Feb 08 07:04:28 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 55484387 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.2002732827 | Feb 08 07:04:28 PM UTC 25 | Feb 08 07:04:30 PM UTC 25 | 15373772 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1952928666 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:31 PM UTC 25 | 51686621 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.1115649659 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:31 PM UTC 25 | 882004522 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3245659166 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:32 PM UTC 25 | 182881689 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.518470033 | Feb 08 07:04:30 PM UTC 25 | Feb 08 07:04:32 PM UTC 25 | 38962319 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.4023583838 | Feb 08 07:04:30 PM UTC 25 | Feb 08 07:04:32 PM UTC 25 | 22032245 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.461896255 | Feb 08 07:04:30 PM UTC 25 | Feb 08 07:04:32 PM UTC 25 | 11154471 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3474112585 | Feb 08 07:04:30 PM UTC 25 | Feb 08 07:04:32 PM UTC 25 | 55487065 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3531514474 | Feb 08 07:04:30 PM UTC 25 | Feb 08 07:04:32 PM UTC 25 | 45399101 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.243463469 | Feb 08 07:04:30 PM UTC 25 | Feb 08 07:04:32 PM UTC 25 | 47253450 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.325649087 | Feb 08 07:04:26 PM UTC 25 | Feb 08 07:04:34 PM UTC 25 | 443287980 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3894991568 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 50840620 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.4158803038 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 190291712 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2037352169 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 14251860 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1019386367 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 21940345 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.4199227215 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 17173516 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.123303765 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 13152084 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1445422887 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 68536912 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2450892105 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:35 PM UTC 25 | 85637253 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.387709477 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 12657634 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3611246605 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 33120296 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2246295802 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 17747959 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2947881139 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 12198107 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.542103495 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 31667985 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1904248121 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 40647253 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1462694882 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 17062927 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3283024486 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 47202227 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2655631546 | Feb 08 07:04:33 PM UTC 25 | Feb 08 07:04:36 PM UTC 25 | 13688832 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2955058547 | Feb 08 07:04:35 PM UTC 25 | Feb 08 07:04:37 PM UTC 25 | 15583381 ps | ||
| T218 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3760372052 | Feb 08 07:04:14 PM UTC 25 | Feb 08 07:04:37 PM UTC 25 | 3972535409 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1398463751 | Feb 08 07:04:18 PM UTC 25 | Feb 08 07:04:41 PM UTC 25 | 1048785974 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3214616479 | Feb 08 07:04:23 PM UTC 25 | Feb 08 07:04:42 PM UTC 25 | 1225066750 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1603071712 | Feb 08 07:04:21 PM UTC 25 | Feb 08 07:04:44 PM UTC 25 | 3154073855 ps |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.453428210 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 31242033 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:45 PM UTC 25 |
| Peak memory | 233940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453428210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.453428210 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3252637297 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 891428183 ps |
| CPU time | 10.66 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:55 PM UTC 25 |
| Peak memory | 231680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252637297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3252637297 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.1844001260 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3322159507 ps |
| CPU time | 29.45 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:48:15 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844001260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1844001260 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3837180774 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 41484664 ps |
| CPU time | 2.3 seconds |
| Started | Feb 08 06:47:48 PM UTC 25 |
| Finished | Feb 08 06:47:51 PM UTC 25 |
| Peak memory | 235112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837180774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3837180774 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.1629657708 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2791397087 ps |
| CPU time | 44.67 seconds |
| Started | Feb 08 06:48:07 PM UTC 25 |
| Finished | Feb 08 06:48:53 PM UTC 25 |
| Peak memory | 251700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629657708 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.1629657708 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1673767987 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 29125672025 ps |
| CPU time | 163.86 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:50:29 PM UTC 25 |
| Peak memory | 282464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673767987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1673767987 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2167032930 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 352068624 ps |
| CPU time | 11.21 seconds |
| Started | Feb 08 07:03:11 PM UTC 25 |
| Finished | Feb 08 07:03:24 PM UTC 25 |
| Peak memory | 227460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167032930 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.2167032930 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.2774335227 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4681584228 ps |
| CPU time | 7.82 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:53 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774335227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2774335227 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2016766801 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 6906535755 ps |
| CPU time | 79.49 seconds |
| Started | Feb 08 06:48:32 PM UTC 25 |
| Finished | Feb 08 06:49:53 PM UTC 25 |
| Peak memory | 261856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016766801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2016766801 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1366732885 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 11088243034 ps |
| CPU time | 180.92 seconds |
| Started | Feb 08 06:47:50 PM UTC 25 |
| Finished | Feb 08 06:50:54 PM UTC 25 |
| Peak memory | 284248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366732885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.1366732885 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.3905376779 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 34974414 ps |
| CPU time | 0.74 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:44 PM UTC 25 |
| Peak memory | 225648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905376779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3905376779 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3213895561 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5060844482 ps |
| CPU time | 95.82 seconds |
| Started | Feb 08 06:48:05 PM UTC 25 |
| Finished | Feb 08 06:49:43 PM UTC 25 |
| Peak memory | 267948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213895561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3213895561 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.3918115283 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 17887693561 ps |
| CPU time | 273.44 seconds |
| Started | Feb 08 06:47:50 PM UTC 25 |
| Finished | Feb 08 06:52:28 PM UTC 25 |
| Peak memory | 282368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918115283 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.3918115283 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.724062855 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 90625712208 ps |
| CPU time | 376.76 seconds |
| Started | Feb 08 06:49:34 PM UTC 25 |
| Finished | Feb 08 06:55:55 PM UTC 25 |
| Peak memory | 300764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724062855 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.724062855 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3359870807 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 139736587 ps |
| CPU time | 5.06 seconds |
| Started | Feb 08 07:03:28 PM UTC 25 |
| Finished | Feb 08 07:03:34 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359870807 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3359870807 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3305999356 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 92662241325 ps |
| CPU time | 290.22 seconds |
| Started | Feb 08 06:48:34 PM UTC 25 |
| Finished | Feb 08 06:53:28 PM UTC 25 |
| Peak memory | 278388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305999356 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.3305999356 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.255382291 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 792297842 ps |
| CPU time | 15.56 seconds |
| Started | Feb 08 06:47:49 PM UTC 25 |
| Finished | Feb 08 06:48:06 PM UTC 25 |
| Peak memory | 245300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255382291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.255382291 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1801717000 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 111162998 ps |
| CPU time | 3.55 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:47 PM UTC 25 |
| Peak memory | 235136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801717000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1801717000 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1566593341 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 102092905 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:46 PM UTC 25 |
| Peak memory | 259936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566593341 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1566593341 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1542857080 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 9100331429 ps |
| CPU time | 194.67 seconds |
| Started | Feb 08 06:49:15 PM UTC 25 |
| Finished | Feb 08 06:52:33 PM UTC 25 |
| Peak memory | 284388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542857080 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.1542857080 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.429145169 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 6769209211 ps |
| CPU time | 88.67 seconds |
| Started | Feb 08 06:48:07 PM UTC 25 |
| Finished | Feb 08 06:49:38 PM UTC 25 |
| Peak memory | 261884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429145169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.429145169 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2372901693 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2140207901 ps |
| CPU time | 52.5 seconds |
| Started | Feb 08 06:49:33 PM UTC 25 |
| Finished | Feb 08 06:50:28 PM UTC 25 |
| Peak memory | 261800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372901693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2372901693 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3235193146 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 85350638720 ps |
| CPU time | 461.07 seconds |
| Started | Feb 08 06:49:54 PM UTC 25 |
| Finished | Feb 08 06:57:41 PM UTC 25 |
| Peak memory | 284408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235193146 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.3235193146 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3823241394 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 51960656 ps |
| CPU time | 2.2 seconds |
| Started | Feb 08 07:03:16 PM UTC 25 |
| Finished | Feb 08 07:03:19 PM UTC 25 |
| Peak memory | 227252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823241394 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3823241394 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.611473944 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 39769673587 ps |
| CPU time | 206.47 seconds |
| Started | Feb 08 06:53:23 PM UTC 25 |
| Finished | Feb 08 06:56:53 PM UTC 25 |
| Peak memory | 294628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611473944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.611473944 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2918604981 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 7275956260 ps |
| CPU time | 84.92 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:49:09 PM UTC 25 |
| Peak memory | 265912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918604981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.2918604981 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2176193409 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 47960606040 ps |
| CPU time | 414.69 seconds |
| Started | Feb 08 06:51:01 PM UTC 25 |
| Finished | Feb 08 06:58:01 PM UTC 25 |
| Peak memory | 278328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176193409 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.2176193409 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2434252852 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 8745022759 ps |
| CPU time | 106.39 seconds |
| Started | Feb 08 06:54:04 PM UTC 25 |
| Finished | Feb 08 06:55:52 PM UTC 25 |
| Peak memory | 267976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434252852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.2434252852 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1660286099 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10924617641 ps |
| CPU time | 149.79 seconds |
| Started | Feb 08 06:47:57 PM UTC 25 |
| Finished | Feb 08 06:50:29 PM UTC 25 |
| Peak memory | 267980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660286099 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1660286099 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.451609898 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 10400872634 ps |
| CPU time | 171.28 seconds |
| Started | Feb 08 06:48:44 PM UTC 25 |
| Finished | Feb 08 06:51:39 PM UTC 25 |
| Peak memory | 284336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451609898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.451609898 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1452324848 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 71745845218 ps |
| CPU time | 410.66 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:54:39 PM UTC 25 |
| Peak memory | 278244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452324848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.1452324848 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.4223948616 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 36941311 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:46 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223948616 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4223948616 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2219972501 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2413539429 ps |
| CPU time | 6.36 seconds |
| Started | Feb 08 06:47:44 PM UTC 25 |
| Finished | Feb 08 06:47:51 PM UTC 25 |
| Peak memory | 245512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219972501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2219972501 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3374544124 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 62634296148 ps |
| CPU time | 361.1 seconds |
| Started | Feb 08 06:54:28 PM UTC 25 |
| Finished | Feb 08 07:00:34 PM UTC 25 |
| Peak memory | 276204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374544124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.3374544124 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3752015530 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 257624193 ps |
| CPU time | 5.67 seconds |
| Started | Feb 08 07:03:48 PM UTC 25 |
| Finished | Feb 08 07:03:55 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752015530 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3752015530 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1603932899 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 796896092 ps |
| CPU time | 27.32 seconds |
| Started | Feb 08 07:03:42 PM UTC 25 |
| Finished | Feb 08 07:04:11 PM UTC 25 |
| Peak memory | 227476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603932899 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.1603932899 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.938798591 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 319398349341 ps |
| CPU time | 636.82 seconds |
| Started | Feb 08 06:47:45 PM UTC 25 |
| Finished | Feb 08 06:58:29 PM UTC 25 |
| Peak memory | 263928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938798591 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.938798591 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2352260357 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 17746001541 ps |
| CPU time | 72.43 seconds |
| Started | Feb 08 06:49:58 PM UTC 25 |
| Finished | Feb 08 06:51:12 PM UTC 25 |
| Peak memory | 231692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352260357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2352260357 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.2496764338 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1588214515 ps |
| CPU time | 16.62 seconds |
| Started | Feb 08 06:50:30 PM UTC 25 |
| Finished | Feb 08 06:50:47 PM UTC 25 |
| Peak memory | 245308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496764338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2496764338 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2542270994 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 291651845407 ps |
| CPU time | 288.18 seconds |
| Started | Feb 08 06:52:23 PM UTC 25 |
| Finished | Feb 08 06:57:15 PM UTC 25 |
| Peak memory | 300756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542270994 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.2542270994 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3449864698 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 450640415 ps |
| CPU time | 8.39 seconds |
| Started | Feb 08 06:47:44 PM UTC 25 |
| Finished | Feb 08 06:47:54 PM UTC 25 |
| Peak memory | 245336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449864698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3449864698 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2624029112 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 65282110299 ps |
| CPU time | 134.29 seconds |
| Started | Feb 08 06:47:49 PM UTC 25 |
| Finished | Feb 08 06:50:06 PM UTC 25 |
| Peak memory | 261800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624029112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2624029112 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4076247069 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 21410382881 ps |
| CPU time | 155.02 seconds |
| Started | Feb 08 06:49:27 PM UTC 25 |
| Finished | Feb 08 06:52:04 PM UTC 25 |
| Peak memory | 265900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076247069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.4076247069 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2997516306 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1110857868 ps |
| CPU time | 25.37 seconds |
| Started | Feb 08 07:03:20 PM UTC 25 |
| Finished | Feb 08 07:03:47 PM UTC 25 |
| Peak memory | 227528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997516306 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.2997516306 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1537817791 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 70314642274 ps |
| CPU time | 404.9 seconds |
| Started | Feb 08 06:52:22 PM UTC 25 |
| Finished | Feb 08 06:59:12 PM UTC 25 |
| Peak memory | 278248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537817791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.1537817791 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1266466033 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 20005384733 ps |
| CPU time | 179.8 seconds |
| Started | Feb 08 06:52:38 PM UTC 25 |
| Finished | Feb 08 06:55:40 PM UTC 25 |
| Peak memory | 261848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266466033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.1266466033 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1758372641 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 21696765108 ps |
| CPU time | 72.99 seconds |
| Started | Feb 08 06:53:36 PM UTC 25 |
| Finished | Feb 08 06:54:51 PM UTC 25 |
| Peak memory | 261804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758372641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1758372641 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.2982520861 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4333218305 ps |
| CPU time | 108.15 seconds |
| Started | Feb 08 07:01:24 PM UTC 25 |
| Finished | Feb 08 07:03:14 PM UTC 25 |
| Peak memory | 284416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982520861 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.2982520861 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1246032152 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 95109219 ps |
| CPU time | 3.12 seconds |
| Started | Feb 08 06:57:52 PM UTC 25 |
| Finished | Feb 08 06:57:57 PM UTC 25 |
| Peak memory | 245296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246032152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1246032152 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2718938507 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 109796978 ps |
| CPU time | 4.01 seconds |
| Started | Feb 08 07:04:09 PM UTC 25 |
| Finished | Feb 08 07:04:15 PM UTC 25 |
| Peak memory | 225612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718938507 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.2718938507 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.513489337 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 471203356 ps |
| CPU time | 9.13 seconds |
| Started | Feb 08 07:04:05 PM UTC 25 |
| Finished | Feb 08 07:04:16 PM UTC 25 |
| Peak memory | 227440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513489337 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.513489337 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.702906161 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 90094890 ps |
| CPU time | 4.45 seconds |
| Started | Feb 08 06:49:47 PM UTC 25 |
| Finished | Feb 08 06:49:53 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702906161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.702906161 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2542025872 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5441197279 ps |
| CPU time | 21.19 seconds |
| Started | Feb 08 06:50:39 PM UTC 25 |
| Finished | Feb 08 06:51:01 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542025872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.2542025872 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3731086407 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 216106439287 ps |
| CPU time | 553.42 seconds |
| Started | Feb 08 06:54:24 PM UTC 25 |
| Finished | Feb 08 07:03:44 PM UTC 25 |
| Peak memory | 278204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731086407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.3731086407 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.611055164 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 643773470653 ps |
| CPU time | 319.78 seconds |
| Started | Feb 08 06:55:06 PM UTC 25 |
| Finished | Feb 08 07:00:30 PM UTC 25 |
| Peak memory | 263856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611055164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.611055164 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1534303575 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 7631539542 ps |
| CPU time | 55.4 seconds |
| Started | Feb 08 06:55:54 PM UTC 25 |
| Finished | Feb 08 06:56:51 PM UTC 25 |
| Peak memory | 235268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534303575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.1534303575 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.265674111 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2536394460 ps |
| CPU time | 62.74 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:01:24 PM UTC 25 |
| Peak memory | 261788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265674111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.265674111 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.4007221583 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 18697890932 ps |
| CPU time | 72.3 seconds |
| Started | Feb 08 07:01:20 PM UTC 25 |
| Finished | Feb 08 07:02:34 PM UTC 25 |
| Peak memory | 251644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007221583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.4007221583 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.624059182 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2243113780 ps |
| CPU time | 14.19 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:58 PM UTC 25 |
| Peak memory | 229428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624059182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.624059182 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.4104031312 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 221088648 ps |
| CPU time | 7.63 seconds |
| Started | Feb 08 07:03:17 PM UTC 25 |
| Finished | Feb 08 07:03:26 PM UTC 25 |
| Peak memory | 215372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104031312 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.4104031312 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.532489589 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 749839263 ps |
| CPU time | 45.7 seconds |
| Started | Feb 08 07:03:16 PM UTC 25 |
| Finished | Feb 08 07:04:03 PM UTC 25 |
| Peak memory | 215236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532489589 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.532489589 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2524841070 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 156650280 ps |
| CPU time | 4.24 seconds |
| Started | Feb 08 07:03:19 PM UTC 25 |
| Finished | Feb 08 07:03:24 PM UTC 25 |
| Peak memory | 229864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2524841070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_ mem_rw_with_rand_reset.2524841070 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3442538648 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 88564478 ps |
| CPU time | 3.6 seconds |
| Started | Feb 08 07:03:16 PM UTC 25 |
| Finished | Feb 08 07:03:20 PM UTC 25 |
| Peak memory | 225588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442538648 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3442538648 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2690236997 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 45759314 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 07:03:12 PM UTC 25 |
| Finished | Feb 08 07:03:15 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690236997 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2690236997 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1863703653 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 39978385 ps |
| CPU time | 2 seconds |
| Started | Feb 08 07:03:14 PM UTC 25 |
| Finished | Feb 08 07:03:18 PM UTC 25 |
| Peak memory | 224240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863703653 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1863703653 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1861341904 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 13999713 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 07:03:12 PM UTC 25 |
| Finished | Feb 08 07:03:15 PM UTC 25 |
| Peak memory | 213004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861341904 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.1861341904 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1832513532 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 52724292 ps |
| CPU time | 2.64 seconds |
| Started | Feb 08 07:03:19 PM UTC 25 |
| Finished | Feb 08 07:03:23 PM UTC 25 |
| Peak memory | 225596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832513532 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.1832513532 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1747523892 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 814472086 ps |
| CPU time | 6.92 seconds |
| Started | Feb 08 07:03:10 PM UTC 25 |
| Finished | Feb 08 07:03:18 PM UTC 25 |
| Peak memory | 225728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747523892 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1747523892 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3729395750 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 387979491 ps |
| CPU time | 10.84 seconds |
| Started | Feb 08 07:03:26 PM UTC 25 |
| Finished | Feb 08 07:03:38 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729395750 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3729395750 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1395607230 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 7556700807 ps |
| CPU time | 13.94 seconds |
| Started | Feb 08 07:03:25 PM UTC 25 |
| Finished | Feb 08 07:03:41 PM UTC 25 |
| Peak memory | 215248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395607230 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.1395607230 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3916464131 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 51128408 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 07:03:24 PM UTC 25 |
| Finished | Feb 08 07:03:27 PM UTC 25 |
| Peak memory | 214260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916464131 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3916464131 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3679426913 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 125922014 ps |
| CPU time | 4.59 seconds |
| Started | Feb 08 07:03:27 PM UTC 25 |
| Finished | Feb 08 07:03:32 PM UTC 25 |
| Peak memory | 229580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3679426913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_ mem_rw_with_rand_reset.3679426913 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1966818447 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 158114380 ps |
| CPU time | 1.95 seconds |
| Started | Feb 08 07:03:24 PM UTC 25 |
| Finished | Feb 08 07:03:27 PM UTC 25 |
| Peak memory | 226244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966818447 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1966818447 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3329973556 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 11661910 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 07:03:21 PM UTC 25 |
| Finished | Feb 08 07:03:23 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329973556 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3329973556 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1305220891 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 45228920 ps |
| CPU time | 2.76 seconds |
| Started | Feb 08 07:03:24 PM UTC 25 |
| Finished | Feb 08 07:03:28 PM UTC 25 |
| Peak memory | 225368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305220891 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1305220891 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1330703449 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 17216371 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 07:03:23 PM UTC 25 |
| Finished | Feb 08 07:03:25 PM UTC 25 |
| Peak memory | 212224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330703449 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.1330703449 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4272284334 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 62972247 ps |
| CPU time | 2.55 seconds |
| Started | Feb 08 07:03:27 PM UTC 25 |
| Finished | Feb 08 07:03:30 PM UTC 25 |
| Peak memory | 225352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272284334 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.4272284334 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1733480621 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 32391714 ps |
| CPU time | 3.13 seconds |
| Started | Feb 08 07:03:20 PM UTC 25 |
| Finished | Feb 08 07:03:24 PM UTC 25 |
| Peak memory | 227640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733480621 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1733480621 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1902122902 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 78735071 ps |
| CPU time | 2.71 seconds |
| Started | Feb 08 07:04:07 PM UTC 25 |
| Finished | Feb 08 07:04:11 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1902122902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr _mem_rw_with_rand_reset.1902122902 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4063160627 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 153268930 ps |
| CPU time | 2.95 seconds |
| Started | Feb 08 07:04:05 PM UTC 25 |
| Finished | Feb 08 07:04:10 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063160627 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.4063160627 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2249549991 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 112950245 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 07:04:05 PM UTC 25 |
| Finished | Feb 08 07:04:08 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249549991 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.2249549991 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.201668473 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 188445169 ps |
| CPU time | 3.6 seconds |
| Started | Feb 08 07:04:05 PM UTC 25 |
| Finished | Feb 08 07:04:10 PM UTC 25 |
| Peak memory | 215288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201668473 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.201668473 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1765698075 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 245400697 ps |
| CPU time | 4.19 seconds |
| Started | Feb 08 07:04:05 PM UTC 25 |
| Finished | Feb 08 07:04:11 PM UTC 25 |
| Peak memory | 227716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765698075 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1765698075 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1067117469 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 370973870 ps |
| CPU time | 3.92 seconds |
| Started | Feb 08 07:04:09 PM UTC 25 |
| Finished | Feb 08 07:04:15 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1067117469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr _mem_rw_with_rand_reset.1067117469 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3031115664 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 66498005 ps |
| CPU time | 2.06 seconds |
| Started | Feb 08 07:04:08 PM UTC 25 |
| Finished | Feb 08 07:04:11 PM UTC 25 |
| Peak memory | 215424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031115664 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.3031115664 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2939177179 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 41294026 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 07:04:07 PM UTC 25 |
| Finished | Feb 08 07:04:10 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939177179 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.2939177179 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4144650993 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 160744268 ps |
| CPU time | 3.26 seconds |
| Started | Feb 08 07:04:08 PM UTC 25 |
| Finished | Feb 08 07:04:13 PM UTC 25 |
| Peak memory | 225420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144650993 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.4144650993 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3368151010 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 207927497 ps |
| CPU time | 4.73 seconds |
| Started | Feb 08 07:04:07 PM UTC 25 |
| Finished | Feb 08 07:04:13 PM UTC 25 |
| Peak memory | 225668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368151010 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3368151010 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1758789056 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 953719810 ps |
| CPU time | 15.27 seconds |
| Started | Feb 08 07:04:07 PM UTC 25 |
| Finished | Feb 08 07:04:24 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758789056 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.1758789056 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.931817044 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 55456267 ps |
| CPU time | 2.54 seconds |
| Started | Feb 08 07:04:11 PM UTC 25 |
| Finished | Feb 08 07:04:15 PM UTC 25 |
| Peak memory | 227728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=931817044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_ mem_rw_with_rand_reset.931817044 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.795795849 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 276219939 ps |
| CPU time | 2.16 seconds |
| Started | Feb 08 07:04:11 PM UTC 25 |
| Finished | Feb 08 07:04:14 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795795849 -assert nopostproc +UVM_TESTNAME=spi_devi ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi _device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.795795849 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2690096040 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 16098188 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 07:04:09 PM UTC 25 |
| Finished | Feb 08 07:04:12 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690096040 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2690096040 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.110388874 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 294037766 ps |
| CPU time | 5.1 seconds |
| Started | Feb 08 07:04:11 PM UTC 25 |
| Finished | Feb 08 07:04:17 PM UTC 25 |
| Peak memory | 225468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110388874 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.110388874 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4023409426 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 294332631 ps |
| CPU time | 16.99 seconds |
| Started | Feb 08 07:04:09 PM UTC 25 |
| Finished | Feb 08 07:04:28 PM UTC 25 |
| Peak memory | 225460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023409426 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.4023409426 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2424742490 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 438095301 ps |
| CPU time | 3.58 seconds |
| Started | Feb 08 07:04:13 PM UTC 25 |
| Finished | Feb 08 07:04:17 PM UTC 25 |
| Peak memory | 229712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2424742490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr _mem_rw_with_rand_reset.2424742490 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1082447930 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 61258673 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 07:04:12 PM UTC 25 |
| Finished | Feb 08 07:04:15 PM UTC 25 |
| Peak memory | 213960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082447930 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.1082447930 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2030723163 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15514753 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 07:04:12 PM UTC 25 |
| Finished | Feb 08 07:04:15 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030723163 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2030723163 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.167668923 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 151575187 ps |
| CPU time | 3.84 seconds |
| Started | Feb 08 07:04:12 PM UTC 25 |
| Finished | Feb 08 07:04:18 PM UTC 25 |
| Peak memory | 225576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167668923 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.167668923 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1335992175 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 858515652 ps |
| CPU time | 3.96 seconds |
| Started | Feb 08 07:04:12 PM UTC 25 |
| Finished | Feb 08 07:04:17 PM UTC 25 |
| Peak memory | 225392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335992175 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.1335992175 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.838981147 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 713421618 ps |
| CPU time | 16.37 seconds |
| Started | Feb 08 07:04:12 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 227376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838981147 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.838981147 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3195929364 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 473866829 ps |
| CPU time | 3.88 seconds |
| Started | Feb 08 07:04:16 PM UTC 25 |
| Finished | Feb 08 07:04:21 PM UTC 25 |
| Peak memory | 229444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3195929364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr _mem_rw_with_rand_reset.3195929364 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.580594278 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 72874165 ps |
| CPU time | 2.23 seconds |
| Started | Feb 08 07:04:14 PM UTC 25 |
| Finished | Feb 08 07:04:18 PM UTC 25 |
| Peak memory | 215168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580594278 -assert nopostproc +UVM_TESTNAME=spi_devi ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi _device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.580594278 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.543895274 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 14418808 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 07:04:14 PM UTC 25 |
| Finished | Feb 08 07:04:16 PM UTC 25 |
| Peak memory | 212300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543895274 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.543895274 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2830210795 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 112222691 ps |
| CPU time | 3.51 seconds |
| Started | Feb 08 07:04:16 PM UTC 25 |
| Finished | Feb 08 07:04:21 PM UTC 25 |
| Peak memory | 225320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830210795 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.2830210795 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3272358626 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 104916212 ps |
| CPU time | 3.9 seconds |
| Started | Feb 08 07:04:14 PM UTC 25 |
| Finished | Feb 08 07:04:19 PM UTC 25 |
| Peak memory | 225264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272358626 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3272358626 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3760372052 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3972535409 ps |
| CPU time | 21.9 seconds |
| Started | Feb 08 07:04:14 PM UTC 25 |
| Finished | Feb 08 07:04:37 PM UTC 25 |
| Peak memory | 227596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760372052 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.3760372052 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1926801693 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 423373118 ps |
| CPU time | 3.94 seconds |
| Started | Feb 08 07:04:18 PM UTC 25 |
| Finished | Feb 08 07:04:23 PM UTC 25 |
| Peak memory | 227728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1926801693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr _mem_rw_with_rand_reset.1926801693 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.685108516 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 96794120 ps |
| CPU time | 3.4 seconds |
| Started | Feb 08 07:04:16 PM UTC 25 |
| Finished | Feb 08 07:04:21 PM UTC 25 |
| Peak memory | 215232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685108516 -assert nopostproc +UVM_TESTNAME=spi_devi ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi _device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.685108516 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2471807127 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 36154926 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 07:04:16 PM UTC 25 |
| Finished | Feb 08 07:04:18 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471807127 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2471807127 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1640664799 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 326227397 ps |
| CPU time | 2.2 seconds |
| Started | Feb 08 07:04:18 PM UTC 25 |
| Finished | Feb 08 07:04:21 PM UTC 25 |
| Peak memory | 225412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640664799 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.1640664799 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2430120426 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 1156003058 ps |
| CPU time | 9.03 seconds |
| Started | Feb 08 07:04:16 PM UTC 25 |
| Finished | Feb 08 07:04:26 PM UTC 25 |
| Peak memory | 227868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430120426 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.2430120426 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.3627276484 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 382555577 ps |
| CPU time | 6.13 seconds |
| Started | Feb 08 07:04:16 PM UTC 25 |
| Finished | Feb 08 07:04:23 PM UTC 25 |
| Peak memory | 227456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627276484 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.3627276484 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.654246538 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 148926006 ps |
| CPU time | 3.19 seconds |
| Started | Feb 08 07:04:20 PM UTC 25 |
| Finished | Feb 08 07:04:24 PM UTC 25 |
| Peak memory | 227792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=654246538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_ mem_rw_with_rand_reset.654246538 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.459429756 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 33650260 ps |
| CPU time | 2.52 seconds |
| Started | Feb 08 07:04:19 PM UTC 25 |
| Finished | Feb 08 07:04:23 PM UTC 25 |
| Peak memory | 225412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459429756 -assert nopostproc +UVM_TESTNAME=spi_devi ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi _device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.459429756 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.77070382 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 57021080 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 07:04:19 PM UTC 25 |
| Finished | Feb 08 07:04:22 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77070382 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev ice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.77070382 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3990646811 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 463465201 ps |
| CPU time | 2.99 seconds |
| Started | Feb 08 07:04:20 PM UTC 25 |
| Finished | Feb 08 07:04:24 PM UTC 25 |
| Peak memory | 225564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990646811 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.3990646811 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1349574565 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 1207387418 ps |
| CPU time | 2.6 seconds |
| Started | Feb 08 07:04:18 PM UTC 25 |
| Finished | Feb 08 07:04:22 PM UTC 25 |
| Peak memory | 227780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349574565 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1349574565 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1398463751 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 1048785974 ps |
| CPU time | 21.37 seconds |
| Started | Feb 08 07:04:18 PM UTC 25 |
| Finished | Feb 08 07:04:41 PM UTC 25 |
| Peak memory | 227476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398463751 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.1398463751 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1855740583 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 89631428 ps |
| CPU time | 3.34 seconds |
| Started | Feb 08 07:04:23 PM UTC 25 |
| Finished | Feb 08 07:04:28 PM UTC 25 |
| Peak memory | 227460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1855740583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr _mem_rw_with_rand_reset.1855740583 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2506300525 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 100120319 ps |
| CPU time | 2.62 seconds |
| Started | Feb 08 07:04:23 PM UTC 25 |
| Finished | Feb 08 07:04:27 PM UTC 25 |
| Peak memory | 227716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506300525 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2506300525 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.4262141039 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 62440458 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 07:04:21 PM UTC 25 |
| Finished | Feb 08 07:04:23 PM UTC 25 |
| Peak memory | 211920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262141039 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.4262141039 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2441131108 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 537458484 ps |
| CPU time | 4.64 seconds |
| Started | Feb 08 07:04:23 PM UTC 25 |
| Finished | Feb 08 07:04:29 PM UTC 25 |
| Peak memory | 225432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441131108 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.2441131108 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3392081576 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 217045383 ps |
| CPU time | 5.38 seconds |
| Started | Feb 08 07:04:20 PM UTC 25 |
| Finished | Feb 08 07:04:26 PM UTC 25 |
| Peak memory | 225788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392081576 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.3392081576 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1603071712 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 3154073855 ps |
| CPU time | 21.23 seconds |
| Started | Feb 08 07:04:21 PM UTC 25 |
| Finished | Feb 08 07:04:44 PM UTC 25 |
| Peak memory | 229440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603071712 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.1603071712 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1952928666 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 51686621 ps |
| CPU time | 3.59 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:31 PM UTC 25 |
| Peak memory | 227260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1952928666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr _mem_rw_with_rand_reset.1952928666 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2543385265 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 79260422 ps |
| CPU time | 2.51 seconds |
| Started | Feb 08 07:04:23 PM UTC 25 |
| Finished | Feb 08 07:04:27 PM UTC 25 |
| Peak memory | 225604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543385265 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.2543385265 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.3508546512 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 15496316 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 07:04:23 PM UTC 25 |
| Finished | Feb 08 07:04:26 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508546512 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.3508546512 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.272059237 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 113852081 ps |
| CPU time | 2.19 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:29 PM UTC 25 |
| Peak memory | 215364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272059237 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.272059237 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3446457343 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 55451871 ps |
| CPU time | 2.31 seconds |
| Started | Feb 08 07:04:23 PM UTC 25 |
| Finished | Feb 08 07:04:27 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446457343 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3446457343 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3214616479 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 1225066750 ps |
| CPU time | 17.45 seconds |
| Started | Feb 08 07:04:23 PM UTC 25 |
| Finished | Feb 08 07:04:42 PM UTC 25 |
| Peak memory | 227456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214616479 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.3214616479 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3630061169 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 61825671 ps |
| CPU time | 2.52 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 227432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3630061169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr _mem_rw_with_rand_reset.3630061169 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1652794661 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 106361833 ps |
| CPU time | 2.23 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 225332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652794661 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.1652794661 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1810404513 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 25816254 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:28 PM UTC 25 |
| Peak memory | 212044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810404513 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.1810404513 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3245659166 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 182881689 ps |
| CPU time | 4.19 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:32 PM UTC 25 |
| Peak memory | 225476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245659166 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.3245659166 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.1115649659 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 882004522 ps |
| CPU time | 3.58 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:31 PM UTC 25 |
| Peak memory | 225420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115649659 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.1115649659 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.325649087 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 443287980 ps |
| CPU time | 6.43 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:34 PM UTC 25 |
| Peak memory | 225620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325649087 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.325649087 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1486456043 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 111235306 ps |
| CPU time | 11.06 seconds |
| Started | Feb 08 07:03:33 PM UTC 25 |
| Finished | Feb 08 07:03:46 PM UTC 25 |
| Peak memory | 214812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486456043 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.1486456043 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2256098505 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3829862525 ps |
| CPU time | 37.47 seconds |
| Started | Feb 08 07:03:32 PM UTC 25 |
| Finished | Feb 08 07:04:11 PM UTC 25 |
| Peak memory | 215308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256098505 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.2256098505 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.772748637 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 22261263 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 07:03:31 PM UTC 25 |
| Finished | Feb 08 07:03:34 PM UTC 25 |
| Peak memory | 214276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772748637 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.772748637 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3583816833 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 41224290 ps |
| CPU time | 3.7 seconds |
| Started | Feb 08 07:03:34 PM UTC 25 |
| Finished | Feb 08 07:03:39 PM UTC 25 |
| Peak memory | 227340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3583816833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_ mem_rw_with_rand_reset.3583816833 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1480333000 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 108457691 ps |
| CPU time | 3.62 seconds |
| Started | Feb 08 07:03:32 PM UTC 25 |
| Finished | Feb 08 07:03:37 PM UTC 25 |
| Peak memory | 225328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480333000 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1480333000 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1064674440 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 101665229 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 07:03:29 PM UTC 25 |
| Finished | Feb 08 07:03:31 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064674440 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1064674440 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2597239202 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 46452315 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 07:03:31 PM UTC 25 |
| Finished | Feb 08 07:03:34 PM UTC 25 |
| Peak memory | 224240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597239202 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.2597239202 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.4239845377 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 16242014 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 07:03:29 PM UTC 25 |
| Finished | Feb 08 07:03:31 PM UTC 25 |
| Peak memory | 212224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239845377 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.4239845377 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3022781808 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 617113704 ps |
| CPU time | 3.97 seconds |
| Started | Feb 08 07:03:33 PM UTC 25 |
| Finished | Feb 08 07:03:38 PM UTC 25 |
| Peak memory | 225364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022781808 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.3022781808 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2368678054 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 311679139 ps |
| CPU time | 25.77 seconds |
| Started | Feb 08 07:03:29 PM UTC 25 |
| Finished | Feb 08 07:03:56 PM UTC 25 |
| Peak memory | 227388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368678054 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.2368678054 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2875085003 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 19409690 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 07:04:26 PM UTC 25 |
| Finished | Feb 08 07:04:29 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875085003 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.2875085003 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.2002732827 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 15373772 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 07:04:28 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 212240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002732827 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.2002732827 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.406530653 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 12983696 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 07:04:28 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 212284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406530653 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.406530653 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.4044350659 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 55484387 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 07:04:28 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044350659 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.4044350659 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4155244747 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 21079854 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 07:04:28 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155244747 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.4155244747 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.374416031 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 43765067 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 07:04:28 PM UTC 25 |
| Finished | Feb 08 07:04:30 PM UTC 25 |
| Peak memory | 212300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374416031 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.374416031 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3531514474 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 45399101 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 07:04:30 PM UTC 25 |
| Finished | Feb 08 07:04:32 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531514474 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.3531514474 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.4023583838 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 22032245 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 07:04:30 PM UTC 25 |
| Finished | Feb 08 07:04:32 PM UTC 25 |
| Peak memory | 212208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023583838 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.4023583838 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.518470033 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 38962319 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 07:04:30 PM UTC 25 |
| Finished | Feb 08 07:04:32 PM UTC 25 |
| Peak memory | 212300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518470033 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.518470033 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.243463469 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 47253450 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 07:04:30 PM UTC 25 |
| Finished | Feb 08 07:04:32 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243463469 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.243463469 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3859396938 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 613407602 ps |
| CPU time | 17.76 seconds |
| Started | Feb 08 07:03:40 PM UTC 25 |
| Finished | Feb 08 07:03:59 PM UTC 25 |
| Peak memory | 225348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859396938 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.3859396938 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2939633391 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 1407435665 ps |
| CPU time | 21.01 seconds |
| Started | Feb 08 07:03:39 PM UTC 25 |
| Finished | Feb 08 07:04:01 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939633391 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.2939633391 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2588857724 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 30641523 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 07:03:39 PM UTC 25 |
| Finished | Feb 08 07:03:42 PM UTC 25 |
| Peak memory | 224372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588857724 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2588857724 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.383978079 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 81481003 ps |
| CPU time | 3.99 seconds |
| Started | Feb 08 07:03:41 PM UTC 25 |
| Finished | Feb 08 07:03:46 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=383978079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_m em_rw_with_rand_reset.383978079 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2122389638 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 35532660 ps |
| CPU time | 3.39 seconds |
| Started | Feb 08 07:03:39 PM UTC 25 |
| Finished | Feb 08 07:03:44 PM UTC 25 |
| Peak memory | 225312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122389638 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2122389638 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.3507191133 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 83263162 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 07:03:36 PM UTC 25 |
| Finished | Feb 08 07:03:38 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507191133 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3507191133 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1456385715 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 121723727 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 07:03:38 PM UTC 25 |
| Finished | Feb 08 07:03:41 PM UTC 25 |
| Peak memory | 224240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456385715 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.1456385715 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.456166739 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 164384519 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 07:03:38 PM UTC 25 |
| Finished | Feb 08 07:03:40 PM UTC 25 |
| Peak memory | 212224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456166739 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.456166739 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2125166455 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 70952142 ps |
| CPU time | 2.78 seconds |
| Started | Feb 08 07:03:41 PM UTC 25 |
| Finished | Feb 08 07:03:45 PM UTC 25 |
| Peak memory | 225340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125166455 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.2125166455 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2128899726 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 49791549 ps |
| CPU time | 4.25 seconds |
| Started | Feb 08 07:03:35 PM UTC 25 |
| Finished | Feb 08 07:03:40 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128899726 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2128899726 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.4266412668 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 321531950 ps |
| CPU time | 10.07 seconds |
| Started | Feb 08 07:03:35 PM UTC 25 |
| Finished | Feb 08 07:03:46 PM UTC 25 |
| Peak memory | 225672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266412668 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.4266412668 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.461896255 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 11154471 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 07:04:30 PM UTC 25 |
| Finished | Feb 08 07:04:32 PM UTC 25 |
| Peak memory | 212300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461896255 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.461896255 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3474112585 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 55487065 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 07:04:30 PM UTC 25 |
| Finished | Feb 08 07:04:32 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474112585 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3474112585 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3894991568 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 50840620 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894991568 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3894991568 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1019386367 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 21940345 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019386367 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.1019386367 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2037352169 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 14251860 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037352169 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.2037352169 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.4158803038 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 190291712 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158803038 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.4158803038 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.4199227215 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 17173516 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199227215 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.4199227215 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.123303765 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 13152084 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123303765 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.123303765 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2450892105 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 85637253 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450892105 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.2450892105 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2246295802 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 17747959 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246295802 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.2246295802 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2422508594 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 2508125134 ps |
| CPU time | 20.77 seconds |
| Started | Feb 08 07:03:47 PM UTC 25 |
| Finished | Feb 08 07:04:09 PM UTC 25 |
| Peak memory | 225292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422508594 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.2422508594 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3741427810 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 183031910 ps |
| CPU time | 17.08 seconds |
| Started | Feb 08 07:03:47 PM UTC 25 |
| Finished | Feb 08 07:04:06 PM UTC 25 |
| Peak memory | 214672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741427810 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3741427810 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.727059874 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 25660092 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 07:03:46 PM UTC 25 |
| Finished | Feb 08 07:03:49 PM UTC 25 |
| Peak memory | 214440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727059874 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.727059874 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3073085535 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 171315149 ps |
| CPU time | 3.83 seconds |
| Started | Feb 08 07:03:47 PM UTC 25 |
| Finished | Feb 08 07:03:52 PM UTC 25 |
| Peak memory | 227608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3073085535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_ mem_rw_with_rand_reset.3073085535 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.556933122 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 188194467 ps |
| CPU time | 2.17 seconds |
| Started | Feb 08 07:03:46 PM UTC 25 |
| Finished | Feb 08 07:03:50 PM UTC 25 |
| Peak memory | 215188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556933122 -assert nopostproc +UVM_TESTNAME=spi_devi ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi _device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.556933122 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1109868785 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 13035580 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 07:03:43 PM UTC 25 |
| Finished | Feb 08 07:03:46 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109868785 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1109868785 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2440440167 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 144618485 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 07:03:44 PM UTC 25 |
| Finished | Feb 08 07:03:48 PM UTC 25 |
| Peak memory | 224240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440440167 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2440440167 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3092363732 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 16113489 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 07:03:44 PM UTC 25 |
| Finished | Feb 08 07:03:47 PM UTC 25 |
| Peak memory | 212224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092363732 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.3092363732 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3733297622 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 163424564 ps |
| CPU time | 3.9 seconds |
| Started | Feb 08 07:03:47 PM UTC 25 |
| Finished | Feb 08 07:03:52 PM UTC 25 |
| Peak memory | 225468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733297622 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.3733297622 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.49644082 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2089389884 ps |
| CPU time | 4.51 seconds |
| Started | Feb 08 07:03:42 PM UTC 25 |
| Finished | Feb 08 07:03:48 PM UTC 25 |
| Peak memory | 225856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49644082 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev ice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.49644082 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.387709477 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 12657634 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387709477 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.387709477 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1445422887 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 68536912 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:35 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445422887 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.1445422887 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3611246605 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 33120296 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611246605 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3611246605 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.542103495 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 31667985 ps |
| CPU time | 1 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542103495 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de vice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.542103495 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1462694882 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 17062927 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462694882 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1462694882 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2947881139 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 12198107 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947881139 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.2947881139 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2655631546 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 13688832 ps |
| CPU time | 1 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655631546 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2655631546 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1904248121 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 40647253 ps |
| CPU time | 0.82 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904248121 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.1904248121 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3283024486 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 47202227 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 07:04:33 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283024486 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.3283024486 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2955058547 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 15583381 ps |
| CPU time | 0.8 seconds |
| Started | Feb 08 07:04:35 PM UTC 25 |
| Finished | Feb 08 07:04:37 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955058547 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2955058547 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3387148284 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 39537714 ps |
| CPU time | 2.55 seconds |
| Started | Feb 08 07:03:49 PM UTC 25 |
| Finished | Feb 08 07:03:53 PM UTC 25 |
| Peak memory | 227548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3387148284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_ mem_rw_with_rand_reset.3387148284 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2124242326 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 176532119 ps |
| CPU time | 3.26 seconds |
| Started | Feb 08 07:03:49 PM UTC 25 |
| Finished | Feb 08 07:03:54 PM UTC 25 |
| Peak memory | 225212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124242326 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2124242326 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3338408661 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 44972352 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 07:03:48 PM UTC 25 |
| Finished | Feb 08 07:03:50 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338408661 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3338408661 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3279807354 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 831850263 ps |
| CPU time | 3.53 seconds |
| Started | Feb 08 07:03:49 PM UTC 25 |
| Finished | Feb 08 07:03:54 PM UTC 25 |
| Peak memory | 225216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279807354 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.3279807354 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3019194886 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1100578674 ps |
| CPU time | 15.13 seconds |
| Started | Feb 08 07:03:48 PM UTC 25 |
| Finished | Feb 08 07:04:04 PM UTC 25 |
| Peak memory | 227396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019194886 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.3019194886 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3093405715 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 75298676 ps |
| CPU time | 5.12 seconds |
| Started | Feb 08 07:03:55 PM UTC 25 |
| Finished | Feb 08 07:04:01 PM UTC 25 |
| Peak memory | 229524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3093405715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_ mem_rw_with_rand_reset.3093405715 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.570105846 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 58999034 ps |
| CPU time | 2.15 seconds |
| Started | Feb 08 07:03:54 PM UTC 25 |
| Finished | Feb 08 07:03:57 PM UTC 25 |
| Peak memory | 215168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570105846 -assert nopostproc +UVM_TESTNAME=spi_devi ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi _device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.570105846 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3774888815 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 43206022 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 07:03:53 PM UTC 25 |
| Finished | Feb 08 07:03:56 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774888815 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3774888815 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.212417483 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 61631378 ps |
| CPU time | 5.25 seconds |
| Started | Feb 08 07:03:54 PM UTC 25 |
| Finished | Feb 08 07:04:00 PM UTC 25 |
| Peak memory | 225324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212417483 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.212417483 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1149551435 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 660604581 ps |
| CPU time | 6.48 seconds |
| Started | Feb 08 07:03:50 PM UTC 25 |
| Finished | Feb 08 07:03:58 PM UTC 25 |
| Peak memory | 225916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149551435 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1149551435 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.4044717420 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 569855033 ps |
| CPU time | 10.82 seconds |
| Started | Feb 08 07:03:51 PM UTC 25 |
| Finished | Feb 08 07:04:03 PM UTC 25 |
| Peak memory | 227380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044717420 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.4044717420 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2137038948 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 245904305 ps |
| CPU time | 3.83 seconds |
| Started | Feb 08 07:03:59 PM UTC 25 |
| Finished | Feb 08 07:04:04 PM UTC 25 |
| Peak memory | 229856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2137038948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_ mem_rw_with_rand_reset.2137038948 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2038180892 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 145245443 ps |
| CPU time | 2.66 seconds |
| Started | Feb 08 07:03:57 PM UTC 25 |
| Finished | Feb 08 07:04:01 PM UTC 25 |
| Peak memory | 225344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038180892 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2038180892 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2635539792 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 31652053 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 07:03:57 PM UTC 25 |
| Finished | Feb 08 07:03:59 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635539792 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2635539792 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.46912875 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 175364234 ps |
| CPU time | 3.33 seconds |
| Started | Feb 08 07:03:58 PM UTC 25 |
| Finished | Feb 08 07:04:03 PM UTC 25 |
| Peak memory | 225464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46912875 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.46912875 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2709855427 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 80657766 ps |
| CPU time | 2.7 seconds |
| Started | Feb 08 07:03:55 PM UTC 25 |
| Finished | Feb 08 07:03:59 PM UTC 25 |
| Peak memory | 225460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709855427 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2709855427 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.260662663 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 112018648 ps |
| CPU time | 7.64 seconds |
| Started | Feb 08 07:03:56 PM UTC 25 |
| Finished | Feb 08 07:04:05 PM UTC 25 |
| Peak memory | 225492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260662663 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.260662663 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3811814343 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 1282897612 ps |
| CPU time | 4.74 seconds |
| Started | Feb 08 07:04:01 PM UTC 25 |
| Finished | Feb 08 07:04:07 PM UTC 25 |
| Peak memory | 229252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3811814343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_ mem_rw_with_rand_reset.3811814343 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3239056150 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 93424700 ps |
| CPU time | 2.69 seconds |
| Started | Feb 08 07:04:00 PM UTC 25 |
| Finished | Feb 08 07:04:04 PM UTC 25 |
| Peak memory | 225460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239056150 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3239056150 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1024155376 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 50942320 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 07:04:00 PM UTC 25 |
| Finished | Feb 08 07:04:03 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024155376 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1024155376 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.81171793 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 147676458 ps |
| CPU time | 5.36 seconds |
| Started | Feb 08 07:04:01 PM UTC 25 |
| Finished | Feb 08 07:04:08 PM UTC 25 |
| Peak memory | 225476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81171793 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.81171793 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3534014128 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 62859705 ps |
| CPU time | 5.23 seconds |
| Started | Feb 08 07:03:59 PM UTC 25 |
| Finished | Feb 08 07:04:06 PM UTC 25 |
| Peak memory | 225592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534014128 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3534014128 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2386282924 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 317087983 ps |
| CPU time | 20.55 seconds |
| Started | Feb 08 07:03:59 PM UTC 25 |
| Finished | Feb 08 07:04:21 PM UTC 25 |
| Peak memory | 225420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386282924 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.2386282924 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1758505700 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 26392662 ps |
| CPU time | 2.43 seconds |
| Started | Feb 08 07:04:04 PM UTC 25 |
| Finished | Feb 08 07:04:08 PM UTC 25 |
| Peak memory | 227532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1758505700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_ mem_rw_with_rand_reset.1758505700 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2448536035 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 37988713 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 07:04:04 PM UTC 25 |
| Finished | Feb 08 07:04:07 PM UTC 25 |
| Peak memory | 224180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448536035 -assert nopostproc +UVM_TESTNAME=spi_dev ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp i_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2448536035 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3184013799 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 11718836 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 07:04:03 PM UTC 25 |
| Finished | Feb 08 07:04:05 PM UTC 25 |
| Peak memory | 212296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184013799 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3184013799 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3269048380 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 43136263 ps |
| CPU time | 2.84 seconds |
| Started | Feb 08 07:04:04 PM UTC 25 |
| Finished | Feb 08 07:04:08 PM UTC 25 |
| Peak memory | 225396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269048380 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.3269048380 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2129790516 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1068673766 ps |
| CPU time | 3.05 seconds |
| Started | Feb 08 07:04:01 PM UTC 25 |
| Finished | Feb 08 07:04:06 PM UTC 25 |
| Peak memory | 225216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129790516 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2129790516 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2442923159 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1387572235 ps |
| CPU time | 9.1 seconds |
| Started | Feb 08 07:04:03 PM UTC 25 |
| Finished | Feb 08 07:04:13 PM UTC 25 |
| Peak memory | 227388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442923159 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2442923159 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.4053147797 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 144319143 ps |
| CPU time | 2.48 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:46 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053147797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4053147797 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3329759668 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 54086085 ps |
| CPU time | 0.81 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:44 PM UTC 25 |
| Peak memory | 215908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329759668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3329759668 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2190646768 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 135707056 ps |
| CPU time | 2.56 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:46 PM UTC 25 |
| Peak memory | 245324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190646768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2190646768 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3972957460 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 409726286 ps |
| CPU time | 11.57 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:55 PM UTC 25 |
| Peak memory | 245328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972957460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3972957460 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2691502018 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1829511918 ps |
| CPU time | 10.35 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:54 PM UTC 25 |
| Peak memory | 249456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691502018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2691502018 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.759454261 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13944461401 ps |
| CPU time | 18.87 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:48:03 PM UTC 25 |
| Peak memory | 235252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759454261 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.759454261 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.3351090748 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 22960603 ps |
| CPU time | 0.73 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:44 PM UTC 25 |
| Peak memory | 215772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351090748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3351090748 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3195597042 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5522054562 ps |
| CPU time | 2.83 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:46 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195597042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3195597042 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.3660059199 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 262822623 ps |
| CPU time | 7.57 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:51 PM UTC 25 |
| Peak memory | 227500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660059199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3660059199 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.4054693933 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 280292789 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:47:44 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054693933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4054693933 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.3500014413 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 23270789615 ps |
| CPU time | 20.35 seconds |
| Started | Feb 08 06:47:42 PM UTC 25 |
| Finished | Feb 08 06:48:04 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500014413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3500014413 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2930932450 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 24691707 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 06:47:46 PM UTC 25 |
| Finished | Feb 08 06:47:48 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930932450 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2930932450 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3720063640 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 22386762 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:45 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720063640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3720063640 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2626094629 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 56611064309 ps |
| CPU time | 121.36 seconds |
| Started | Feb 08 06:47:45 PM UTC 25 |
| Finished | Feb 08 06:49:49 PM UTC 25 |
| Peak memory | 249536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626094629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2626094629 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1618355169 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 40221172143 ps |
| CPU time | 50.63 seconds |
| Started | Feb 08 06:47:45 PM UTC 25 |
| Finished | Feb 08 06:48:37 PM UTC 25 |
| Peak memory | 229660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618355169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1618355169 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1072338477 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 81480456233 ps |
| CPU time | 185.17 seconds |
| Started | Feb 08 06:47:45 PM UTC 25 |
| Finished | Feb 08 06:50:53 PM UTC 25 |
| Peak memory | 261952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072338477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1072338477 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.3128738687 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 119571123 ps |
| CPU time | 2.72 seconds |
| Started | Feb 08 06:47:44 PM UTC 25 |
| Finished | Feb 08 06:47:48 PM UTC 25 |
| Peak memory | 235116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128738687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3128738687 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3004319906 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 27658998416 ps |
| CPU time | 253.22 seconds |
| Started | Feb 08 06:47:45 PM UTC 25 |
| Finished | Feb 08 06:52:02 PM UTC 25 |
| Peak memory | 278208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004319906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.3004319906 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2866363598 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 36794642 ps |
| CPU time | 2.13 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:47 PM UTC 25 |
| Peak memory | 244996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866363598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2866363598 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3671374601 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 380976539 ps |
| CPU time | 10.69 seconds |
| Started | Feb 08 06:47:44 PM UTC 25 |
| Finished | Feb 08 06:47:56 PM UTC 25 |
| Peak memory | 245384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671374601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3671374601 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.154876742 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 893932809 ps |
| CPU time | 8.28 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:53 PM UTC 25 |
| Peak memory | 235252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154876742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.154876742 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2122224477 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 287674364 ps |
| CPU time | 2.97 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:48 PM UTC 25 |
| Peak memory | 245320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122224477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2122224477 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1794238213 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 205630866 ps |
| CPU time | 4.67 seconds |
| Started | Feb 08 06:47:45 PM UTC 25 |
| Finished | Feb 08 06:47:51 PM UTC 25 |
| Peak memory | 231408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794238213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.1794238213 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.2980818984 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 59122778 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:47:45 PM UTC 25 |
| Finished | Feb 08 06:47:47 PM UTC 25 |
| Peak memory | 257952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980818984 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2980818984 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.29934191 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 130568670 ps |
| CPU time | 3.14 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:48 PM UTC 25 |
| Peak memory | 227500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29934191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.29934191 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.854308231 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 64996157 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 06:47:43 PM UTC 25 |
| Finished | Feb 08 06:47:46 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854308231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.854308231 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.660584487 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 42642655 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:49:54 PM UTC 25 |
| Finished | Feb 08 06:49:56 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660584487 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.660584487 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1575507053 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2850548770 ps |
| CPU time | 37.55 seconds |
| Started | Feb 08 06:49:44 PM UTC 25 |
| Finished | Feb 08 06:50:24 PM UTC 25 |
| Peak memory | 245492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575507053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1575507053 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.4165690659 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 30354405 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:49:35 PM UTC 25 |
| Finished | Feb 08 06:49:37 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165690659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4165690659 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.489206513 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 20028098590 ps |
| CPU time | 182.56 seconds |
| Started | Feb 08 06:49:50 PM UTC 25 |
| Finished | Feb 08 06:52:55 PM UTC 25 |
| Peak memory | 263872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489206513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.489206513 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2754001275 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 12906107926 ps |
| CPU time | 105.44 seconds |
| Started | Feb 08 06:49:50 PM UTC 25 |
| Finished | Feb 08 06:51:37 PM UTC 25 |
| Peak memory | 265952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754001275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2754001275 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1098807935 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 14573458393 ps |
| CPU time | 216.01 seconds |
| Started | Feb 08 06:49:52 PM UTC 25 |
| Finished | Feb 08 06:53:31 PM UTC 25 |
| Peak memory | 276268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098807935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.1098807935 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2412637984 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 42726916050 ps |
| CPU time | 310.9 seconds |
| Started | Feb 08 06:49:48 PM UTC 25 |
| Finished | Feb 08 06:55:03 PM UTC 25 |
| Peak memory | 263844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412637984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2412637984 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.773937541 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 72948570 ps |
| CPU time | 3.34 seconds |
| Started | Feb 08 06:49:43 PM UTC 25 |
| Finished | Feb 08 06:49:48 PM UTC 25 |
| Peak memory | 245312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773937541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.773937541 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3789706437 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 23198289871 ps |
| CPU time | 77.58 seconds |
| Started | Feb 08 06:49:43 PM UTC 25 |
| Finished | Feb 08 06:51:03 PM UTC 25 |
| Peak memory | 235256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789706437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3789706437 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3227253053 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 9864366277 ps |
| CPU time | 21.31 seconds |
| Started | Feb 08 06:49:43 PM UTC 25 |
| Finished | Feb 08 06:50:06 PM UTC 25 |
| Peak memory | 251572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227253053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.3227253053 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2779383183 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1583455444 ps |
| CPU time | 5.07 seconds |
| Started | Feb 08 06:49:41 PM UTC 25 |
| Finished | Feb 08 06:49:47 PM UTC 25 |
| Peak memory | 234968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779383183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2779383183 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3021161558 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 623497288 ps |
| CPU time | 4.6 seconds |
| Started | Feb 08 06:49:48 PM UTC 25 |
| Finished | Feb 08 06:49:54 PM UTC 25 |
| Peak memory | 231416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021161558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.3021161558 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1963569209 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2497623536 ps |
| CPU time | 46.88 seconds |
| Started | Feb 08 06:49:38 PM UTC 25 |
| Finished | Feb 08 06:50:26 PM UTC 25 |
| Peak memory | 231676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963569209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1963569209 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.4202156765 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2791582848 ps |
| CPU time | 18.87 seconds |
| Started | Feb 08 06:49:38 PM UTC 25 |
| Finished | Feb 08 06:49:58 PM UTC 25 |
| Peak memory | 227604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202156765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4202156765 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1520201636 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 24253599 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:49:41 PM UTC 25 |
| Finished | Feb 08 06:49:43 PM UTC 25 |
| Peak memory | 215776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520201636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1520201636 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1599387234 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 134055832 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:49:39 PM UTC 25 |
| Finished | Feb 08 06:49:42 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599387234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1599387234 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.1609104192 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 7726157747 ps |
| CPU time | 47.93 seconds |
| Started | Feb 08 06:49:43 PM UTC 25 |
| Finished | Feb 08 06:50:33 PM UTC 25 |
| Peak memory | 247424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609104192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1609104192 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.1490134512 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 35470121 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:50:21 PM UTC 25 |
| Finished | Feb 08 06:50:23 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490134512 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.1490134512 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2653517171 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 162956945 ps |
| CPU time | 3.49 seconds |
| Started | Feb 08 06:50:09 PM UTC 25 |
| Finished | Feb 08 06:50:13 PM UTC 25 |
| Peak memory | 245296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653517171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2653517171 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.516585280 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 16214083 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:49:55 PM UTC 25 |
| Finished | Feb 08 06:49:57 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516585280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.516585280 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.3176282353 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1127144455 ps |
| CPU time | 27.78 seconds |
| Started | Feb 08 06:50:14 PM UTC 25 |
| Finished | Feb 08 06:50:43 PM UTC 25 |
| Peak memory | 249524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176282353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3176282353 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1700574711 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 331647092592 ps |
| CPU time | 646.05 seconds |
| Started | Feb 08 06:50:15 PM UTC 25 |
| Finished | Feb 08 07:01:09 PM UTC 25 |
| Peak memory | 278256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700574711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1700574711 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2954852230 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 12142070439 ps |
| CPU time | 42.01 seconds |
| Started | Feb 08 06:50:18 PM UTC 25 |
| Finished | Feb 08 06:51:01 PM UTC 25 |
| Peak memory | 261784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954852230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.2954852230 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.3887619144 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 888272291 ps |
| CPU time | 18.96 seconds |
| Started | Feb 08 06:50:09 PM UTC 25 |
| Finished | Feb 08 06:50:29 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887619144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3887619144 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.407388227 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4803274892 ps |
| CPU time | 44.67 seconds |
| Started | Feb 08 06:50:11 PM UTC 25 |
| Finished | Feb 08 06:50:57 PM UTC 25 |
| Peak memory | 249536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407388227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.407388227 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.4196395033 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 580052189 ps |
| CPU time | 12.85 seconds |
| Started | Feb 08 06:50:06 PM UTC 25 |
| Finished | Feb 08 06:50:20 PM UTC 25 |
| Peak memory | 235060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196395033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4196395033 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1925165198 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 112657742 ps |
| CPU time | 3.34 seconds |
| Started | Feb 08 06:50:06 PM UTC 25 |
| Finished | Feb 08 06:50:11 PM UTC 25 |
| Peak memory | 241932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925165198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1925165198 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1584473934 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 263376251 ps |
| CPU time | 4.38 seconds |
| Started | Feb 08 06:50:02 PM UTC 25 |
| Finished | Feb 08 06:50:08 PM UTC 25 |
| Peak memory | 235108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584473934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.1584473934 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2787429139 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1137798166 ps |
| CPU time | 4.29 seconds |
| Started | Feb 08 06:50:02 PM UTC 25 |
| Finished | Feb 08 06:50:08 PM UTC 25 |
| Peak memory | 235060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787429139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2787429139 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3634151216 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 323949714 ps |
| CPU time | 7.84 seconds |
| Started | Feb 08 06:50:12 PM UTC 25 |
| Finished | Feb 08 06:50:21 PM UTC 25 |
| Peak memory | 231476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634151216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.3634151216 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.3243173220 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 242864870021 ps |
| CPU time | 232.3 seconds |
| Started | Feb 08 06:50:19 PM UTC 25 |
| Finished | Feb 08 06:54:14 PM UTC 25 |
| Peak memory | 278268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243173220 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.3243173220 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3001909145 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 571505731 ps |
| CPU time | 3.59 seconds |
| Started | Feb 08 06:49:57 PM UTC 25 |
| Finished | Feb 08 06:50:02 PM UTC 25 |
| Peak memory | 227504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001909145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3001909145 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.553142567 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 374539264 ps |
| CPU time | 9.09 seconds |
| Started | Feb 08 06:49:59 PM UTC 25 |
| Finished | Feb 08 06:50:10 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553142567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.553142567 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.529514868 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 62821574 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:49:59 PM UTC 25 |
| Finished | Feb 08 06:50:01 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529514868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.529514868 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.91064915 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 7223077432 ps |
| CPU time | 53.23 seconds |
| Started | Feb 08 06:50:08 PM UTC 25 |
| Finished | Feb 08 06:51:02 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91064915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.91064915 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1142013179 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 17207968 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:50:42 PM UTC 25 |
| Finished | Feb 08 06:50:44 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142013179 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.1142013179 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.4136559574 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 345962975 ps |
| CPU time | 3.85 seconds |
| Started | Feb 08 06:50:30 PM UTC 25 |
| Finished | Feb 08 06:50:35 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136559574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4136559574 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3914818571 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 56852745 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:50:22 PM UTC 25 |
| Finished | Feb 08 06:50:24 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914818571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3914818571 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.2682429022 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 8011233971 ps |
| CPU time | 65.22 seconds |
| Started | Feb 08 06:50:36 PM UTC 25 |
| Finished | Feb 08 06:51:43 PM UTC 25 |
| Peak memory | 265900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682429022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2682429022 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2517775980 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1516278049 ps |
| CPU time | 32.82 seconds |
| Started | Feb 08 06:50:37 PM UTC 25 |
| Finished | Feb 08 06:51:11 PM UTC 25 |
| Peak memory | 249512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517775980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2517775980 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1415575632 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 41049871168 ps |
| CPU time | 320.47 seconds |
| Started | Feb 08 06:50:31 PM UTC 25 |
| Finished | Feb 08 06:55:55 PM UTC 25 |
| Peak memory | 267952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415575632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.1415575632 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.214567015 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1754815218 ps |
| CPU time | 8.25 seconds |
| Started | Feb 08 06:50:28 PM UTC 25 |
| Finished | Feb 08 06:50:38 PM UTC 25 |
| Peak memory | 234856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214567015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.214567015 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.272194924 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 8141572794 ps |
| CPU time | 19.38 seconds |
| Started | Feb 08 06:50:28 PM UTC 25 |
| Finished | Feb 08 06:50:49 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272194924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.272194924 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2688691989 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 11042065517 ps |
| CPU time | 21.59 seconds |
| Started | Feb 08 06:50:28 PM UTC 25 |
| Finished | Feb 08 06:50:51 PM UTC 25 |
| Peak memory | 251624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688691989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.2688691989 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1375033229 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1629455018 ps |
| CPU time | 7.89 seconds |
| Started | Feb 08 06:50:27 PM UTC 25 |
| Finished | Feb 08 06:50:36 PM UTC 25 |
| Peak memory | 235200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375033229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1375033229 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3250280186 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1537195003 ps |
| CPU time | 10.07 seconds |
| Started | Feb 08 06:50:34 PM UTC 25 |
| Finished | Feb 08 06:50:45 PM UTC 25 |
| Peak memory | 231604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250280186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.3250280186 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.3959153945 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 75525415 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:50:39 PM UTC 25 |
| Finished | Feb 08 06:50:41 PM UTC 25 |
| Peak memory | 215848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959153945 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.3959153945 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1243695559 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1834894043 ps |
| CPU time | 19.65 seconds |
| Started | Feb 08 06:50:24 PM UTC 25 |
| Finished | Feb 08 06:50:45 PM UTC 25 |
| Peak memory | 227576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243695559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1243695559 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3799027293 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 734377991 ps |
| CPU time | 3.52 seconds |
| Started | Feb 08 06:50:24 PM UTC 25 |
| Finished | Feb 08 06:50:29 PM UTC 25 |
| Peak memory | 227496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799027293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3799027293 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3681832218 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 22198393 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:50:25 PM UTC 25 |
| Finished | Feb 08 06:50:28 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681832218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3681832218 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2334317026 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 54566964 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:50:25 PM UTC 25 |
| Finished | Feb 08 06:50:27 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334317026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2334317026 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3798343318 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 230828799 ps |
| CPU time | 7.4 seconds |
| Started | Feb 08 06:50:30 PM UTC 25 |
| Finished | Feb 08 06:50:38 PM UTC 25 |
| Peak memory | 235048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798343318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3798343318 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3757918736 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 47921320 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:51:02 PM UTC 25 |
| Finished | Feb 08 06:51:05 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757918736 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.3757918736 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.4159885445 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 382000684 ps |
| CPU time | 10.43 seconds |
| Started | Feb 08 06:50:53 PM UTC 25 |
| Finished | Feb 08 06:51:04 PM UTC 25 |
| Peak memory | 245312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159885445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4159885445 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3026169096 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 129766987 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:50:44 PM UTC 25 |
| Finished | Feb 08 06:50:46 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026169096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3026169096 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.2815688515 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 17126219375 ps |
| CPU time | 87.04 seconds |
| Started | Feb 08 06:50:54 PM UTC 25 |
| Finished | Feb 08 06:52:23 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815688515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2815688515 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1020590117 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 14098994426 ps |
| CPU time | 78.6 seconds |
| Started | Feb 08 06:50:55 PM UTC 25 |
| Finished | Feb 08 06:52:16 PM UTC 25 |
| Peak memory | 267924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020590117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1020590117 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1827488420 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2134931986 ps |
| CPU time | 48.88 seconds |
| Started | Feb 08 06:50:58 PM UTC 25 |
| Finished | Feb 08 06:51:49 PM UTC 25 |
| Peak memory | 261804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827488420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.1827488420 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3124439725 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 276668654 ps |
| CPU time | 4.96 seconds |
| Started | Feb 08 06:50:54 PM UTC 25 |
| Finished | Feb 08 06:51:00 PM UTC 25 |
| Peak memory | 245416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124439725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3124439725 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1819633245 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 27428914137 ps |
| CPU time | 139.13 seconds |
| Started | Feb 08 06:50:54 PM UTC 25 |
| Finished | Feb 08 06:53:16 PM UTC 25 |
| Peak memory | 268072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819633245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.1819633245 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.3664510029 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 923573195 ps |
| CPU time | 10.34 seconds |
| Started | Feb 08 06:50:50 PM UTC 25 |
| Finished | Feb 08 06:51:01 PM UTC 25 |
| Peak memory | 245312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664510029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3664510029 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.4292367384 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2781634069 ps |
| CPU time | 42.49 seconds |
| Started | Feb 08 06:50:51 PM UTC 25 |
| Finished | Feb 08 06:51:35 PM UTC 25 |
| Peak memory | 235328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292367384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4292367384 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2403434159 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 82710661 ps |
| CPU time | 3.53 seconds |
| Started | Feb 08 06:50:49 PM UTC 25 |
| Finished | Feb 08 06:50:53 PM UTC 25 |
| Peak memory | 245352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403434159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2403434159 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.828626854 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 188577616 ps |
| CPU time | 4.12 seconds |
| Started | Feb 08 06:50:47 PM UTC 25 |
| Finished | Feb 08 06:50:53 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828626854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.828626854 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1683167288 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1969670310 ps |
| CPU time | 26.75 seconds |
| Started | Feb 08 06:50:54 PM UTC 25 |
| Finished | Feb 08 06:51:22 PM UTC 25 |
| Peak memory | 231476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683167288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.1683167288 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.1498344362 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2238025091 ps |
| CPU time | 22.67 seconds |
| Started | Feb 08 06:50:46 PM UTC 25 |
| Finished | Feb 08 06:51:10 PM UTC 25 |
| Peak memory | 231704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498344362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1498344362 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3153571246 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1810021135 ps |
| CPU time | 6.07 seconds |
| Started | Feb 08 06:50:45 PM UTC 25 |
| Finished | Feb 08 06:50:53 PM UTC 25 |
| Peak memory | 227704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153571246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3153571246 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.3707880056 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 677998852 ps |
| CPU time | 3.59 seconds |
| Started | Feb 08 06:50:47 PM UTC 25 |
| Finished | Feb 08 06:50:52 PM UTC 25 |
| Peak memory | 227504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707880056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3707880056 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.1290808521 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 417582411 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:50:46 PM UTC 25 |
| Finished | Feb 08 06:50:49 PM UTC 25 |
| Peak memory | 215888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290808521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1290808521 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.4095936790 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5666150733 ps |
| CPU time | 20.49 seconds |
| Started | Feb 08 06:50:53 PM UTC 25 |
| Finished | Feb 08 06:51:15 PM UTC 25 |
| Peak memory | 245336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095936790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4095936790 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.2479034209 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 14492268 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:51:16 PM UTC 25 |
| Finished | Feb 08 06:51:19 PM UTC 25 |
| Peak memory | 215832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479034209 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.2479034209 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3275890379 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 86226879 ps |
| CPU time | 3.7 seconds |
| Started | Feb 08 06:51:11 PM UTC 25 |
| Finished | Feb 08 06:51:16 PM UTC 25 |
| Peak memory | 245228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275890379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3275890379 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.3808607507 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 14910732 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:51:02 PM UTC 25 |
| Finished | Feb 08 06:51:05 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808607507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3808607507 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.3394048787 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 179641308009 ps |
| CPU time | 434.78 seconds |
| Started | Feb 08 06:51:12 PM UTC 25 |
| Finished | Feb 08 06:58:32 PM UTC 25 |
| Peak memory | 268036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394048787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3394048787 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.4272458746 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 548839552047 ps |
| CPU time | 370.7 seconds |
| Started | Feb 08 06:51:13 PM UTC 25 |
| Finished | Feb 08 06:57:29 PM UTC 25 |
| Peak memory | 284376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272458746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4272458746 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1840110694 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 44488778711 ps |
| CPU time | 408.57 seconds |
| Started | Feb 08 06:51:15 PM UTC 25 |
| Finished | Feb 08 06:58:10 PM UTC 25 |
| Peak memory | 268036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840110694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.1840110694 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.3714326353 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 766562247 ps |
| CPU time | 22.43 seconds |
| Started | Feb 08 06:51:11 PM UTC 25 |
| Finished | Feb 08 06:51:35 PM UTC 25 |
| Peak memory | 235012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714326353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3714326353 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2243081910 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5346655455 ps |
| CPU time | 59.39 seconds |
| Started | Feb 08 06:51:11 PM UTC 25 |
| Finished | Feb 08 06:52:12 PM UTC 25 |
| Peak memory | 267952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243081910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.2243081910 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.882374442 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 105861084 ps |
| CPU time | 6.02 seconds |
| Started | Feb 08 06:51:08 PM UTC 25 |
| Finished | Feb 08 06:51:15 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882374442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.882374442 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.3238491502 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6838476004 ps |
| CPU time | 43.41 seconds |
| Started | Feb 08 06:51:09 PM UTC 25 |
| Finished | Feb 08 06:51:54 PM UTC 25 |
| Peak memory | 235312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238491502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3238491502 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.611878136 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 20347743264 ps |
| CPU time | 26.38 seconds |
| Started | Feb 08 06:51:06 PM UTC 25 |
| Finished | Feb 08 06:51:33 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611878136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.611878136 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2774330503 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2392482105 ps |
| CPU time | 11.25 seconds |
| Started | Feb 08 06:51:06 PM UTC 25 |
| Finished | Feb 08 06:51:18 PM UTC 25 |
| Peak memory | 245548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774330503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2774330503 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3805260412 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1747070420 ps |
| CPU time | 6.29 seconds |
| Started | Feb 08 06:51:12 PM UTC 25 |
| Finished | Feb 08 06:51:20 PM UTC 25 |
| Peak memory | 231476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805260412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.3805260412 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.3797062297 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 278237416976 ps |
| CPU time | 791.37 seconds |
| Started | Feb 08 06:51:15 PM UTC 25 |
| Finished | Feb 08 07:04:36 PM UTC 25 |
| Peak memory | 311032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797062297 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.3797062297 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2859855530 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1219828296 ps |
| CPU time | 10.72 seconds |
| Started | Feb 08 06:51:03 PM UTC 25 |
| Finished | Feb 08 06:51:15 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859855530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2859855530 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2681013553 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 837091066 ps |
| CPU time | 7.06 seconds |
| Started | Feb 08 06:51:03 PM UTC 25 |
| Finished | Feb 08 06:51:12 PM UTC 25 |
| Peak memory | 227572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681013553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2681013553 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.645427108 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 195460140 ps |
| CPU time | 2.06 seconds |
| Started | Feb 08 06:51:06 PM UTC 25 |
| Finished | Feb 08 06:51:09 PM UTC 25 |
| Peak memory | 227432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645427108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.645427108 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3508207368 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 50078505 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:51:06 PM UTC 25 |
| Finished | Feb 08 06:51:08 PM UTC 25 |
| Peak memory | 215724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508207368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3508207368 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1297142122 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2012465812 ps |
| CPU time | 14.06 seconds |
| Started | Feb 08 06:51:10 PM UTC 25 |
| Finished | Feb 08 06:51:25 PM UTC 25 |
| Peak memory | 235116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297142122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1297142122 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.441197144 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 13602137 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:51:44 PM UTC 25 |
| Finished | Feb 08 06:51:46 PM UTC 25 |
| Peak memory | 215692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441197144 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.441197144 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2758680889 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 491802386 ps |
| CPU time | 7.54 seconds |
| Started | Feb 08 06:51:34 PM UTC 25 |
| Finished | Feb 08 06:51:43 PM UTC 25 |
| Peak memory | 245304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758680889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2758680889 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.1803624127 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 115689270 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:51:17 PM UTC 25 |
| Finished | Feb 08 06:51:19 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803624127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1803624127 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1050140032 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 41461501351 ps |
| CPU time | 97.61 seconds |
| Started | Feb 08 06:51:38 PM UTC 25 |
| Finished | Feb 08 06:53:18 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050140032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1050140032 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.2194853184 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1436802176 ps |
| CPU time | 17.44 seconds |
| Started | Feb 08 06:51:40 PM UTC 25 |
| Finished | Feb 08 06:51:59 PM UTC 25 |
| Peak memory | 251576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194853184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2194853184 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1160629195 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 48468138834 ps |
| CPU time | 465.11 seconds |
| Started | Feb 08 06:51:41 PM UTC 25 |
| Finished | Feb 08 06:59:32 PM UTC 25 |
| Peak memory | 268032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160629195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1160629195 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.1112829521 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 483222634 ps |
| CPU time | 3.52 seconds |
| Started | Feb 08 06:51:35 PM UTC 25 |
| Finished | Feb 08 06:51:40 PM UTC 25 |
| Peak memory | 244036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112829521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1112829521 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.901971174 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 31370687216 ps |
| CPU time | 188.56 seconds |
| Started | Feb 08 06:51:35 PM UTC 25 |
| Finished | Feb 08 06:54:47 PM UTC 25 |
| Peak memory | 267948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901971174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.901971174 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.1153012713 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 13533869291 ps |
| CPU time | 22.37 seconds |
| Started | Feb 08 06:51:25 PM UTC 25 |
| Finished | Feb 08 06:51:49 PM UTC 25 |
| Peak memory | 245380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153012713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1153012713 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1198303949 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 14085258544 ps |
| CPU time | 31.78 seconds |
| Started | Feb 08 06:51:26 PM UTC 25 |
| Finished | Feb 08 06:51:59 PM UTC 25 |
| Peak memory | 245448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198303949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1198303949 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3359237082 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2368964395 ps |
| CPU time | 5.83 seconds |
| Started | Feb 08 06:51:24 PM UTC 25 |
| Finished | Feb 08 06:51:31 PM UTC 25 |
| Peak memory | 235076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359237082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3359237082 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.887457458 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 12044712140 ps |
| CPU time | 20.01 seconds |
| Started | Feb 08 06:51:23 PM UTC 25 |
| Finished | Feb 08 06:51:44 PM UTC 25 |
| Peak memory | 247480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887457458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.887457458 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3463559903 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1085709073 ps |
| CPU time | 7.29 seconds |
| Started | Feb 08 06:51:38 PM UTC 25 |
| Finished | Feb 08 06:51:46 PM UTC 25 |
| Peak memory | 231604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463559903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.3463559903 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.774669223 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 14648898286 ps |
| CPU time | 193.19 seconds |
| Started | Feb 08 06:51:44 PM UTC 25 |
| Finished | Feb 08 06:55:00 PM UTC 25 |
| Peak memory | 267952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774669223 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.774669223 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.2027866821 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 13461041880 ps |
| CPU time | 31.61 seconds |
| Started | Feb 08 06:51:20 PM UTC 25 |
| Finished | Feb 08 06:51:53 PM UTC 25 |
| Peak memory | 227620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027866821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2027866821 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.1018173655 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 11045590091 ps |
| CPU time | 39.95 seconds |
| Started | Feb 08 06:51:20 PM UTC 25 |
| Finished | Feb 08 06:52:01 PM UTC 25 |
| Peak memory | 227532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018173655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1018173655 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1295757955 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 175688113 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:51:22 PM UTC 25 |
| Finished | Feb 08 06:51:24 PM UTC 25 |
| Peak memory | 215964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295757955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1295757955 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.186785836 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 17721734 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:51:21 PM UTC 25 |
| Finished | Feb 08 06:51:23 PM UTC 25 |
| Peak memory | 216076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186785836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.186785836 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.4049676110 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 49338810559 ps |
| CPU time | 42.78 seconds |
| Started | Feb 08 06:51:32 PM UTC 25 |
| Finished | Feb 08 06:52:17 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049676110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4049676110 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.4207276378 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 13381854 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:52:07 PM UTC 25 |
| Finished | Feb 08 06:52:10 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207276378 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.4207276378 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2861829276 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 99021979 ps |
| CPU time | 2.86 seconds |
| Started | Feb 08 06:51:59 PM UTC 25 |
| Finished | Feb 08 06:52:03 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861829276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2861829276 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3173177494 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 27441689 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:51:45 PM UTC 25 |
| Finished | Feb 08 06:51:47 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173177494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3173177494 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1112368989 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 13441748511 ps |
| CPU time | 74.29 seconds |
| Started | Feb 08 06:52:02 PM UTC 25 |
| Finished | Feb 08 06:53:19 PM UTC 25 |
| Peak memory | 251572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112368989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1112368989 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2482157512 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3817814731 ps |
| CPU time | 26.75 seconds |
| Started | Feb 08 06:52:04 PM UTC 25 |
| Finished | Feb 08 06:52:33 PM UTC 25 |
| Peak memory | 261792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482157512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2482157512 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.930567915 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 14722126723 ps |
| CPU time | 194.32 seconds |
| Started | Feb 08 06:52:04 PM UTC 25 |
| Finished | Feb 08 06:55:22 PM UTC 25 |
| Peak memory | 265968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930567915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.930567915 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1813623529 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 12536897516 ps |
| CPU time | 76.32 seconds |
| Started | Feb 08 06:52:00 PM UTC 25 |
| Finished | Feb 08 06:53:18 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813623529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1813623529 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3874913065 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 433505510 ps |
| CPU time | 10.64 seconds |
| Started | Feb 08 06:52:00 PM UTC 25 |
| Finished | Feb 08 06:52:12 PM UTC 25 |
| Peak memory | 233780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874913065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.3874913065 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.3365130405 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2624380342 ps |
| CPU time | 12.86 seconds |
| Started | Feb 08 06:51:53 PM UTC 25 |
| Finished | Feb 08 06:52:07 PM UTC 25 |
| Peak memory | 235180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365130405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3365130405 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.2414245068 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 30189179 ps |
| CPU time | 3 seconds |
| Started | Feb 08 06:51:54 PM UTC 25 |
| Finished | Feb 08 06:51:58 PM UTC 25 |
| Peak memory | 234720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414245068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2414245068 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.4236914749 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2632857589 ps |
| CPU time | 17.19 seconds |
| Started | Feb 08 06:51:53 PM UTC 25 |
| Finished | Feb 08 06:52:11 PM UTC 25 |
| Peak memory | 245552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236914749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.4236914749 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1366138434 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 10970709003 ps |
| CPU time | 34.75 seconds |
| Started | Feb 08 06:51:51 PM UTC 25 |
| Finished | Feb 08 06:52:27 PM UTC 25 |
| Peak memory | 245416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366138434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1366138434 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2782259367 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1464946142 ps |
| CPU time | 17.7 seconds |
| Started | Feb 08 06:52:02 PM UTC 25 |
| Finished | Feb 08 06:52:22 PM UTC 25 |
| Peak memory | 233768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782259367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.2782259367 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.2843552582 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 12378616467 ps |
| CPU time | 68.6 seconds |
| Started | Feb 08 06:52:05 PM UTC 25 |
| Finished | Feb 08 06:53:16 PM UTC 25 |
| Peak memory | 261880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843552582 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.2843552582 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.2659273227 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4128345151 ps |
| CPU time | 29.96 seconds |
| Started | Feb 08 06:51:48 PM UTC 25 |
| Finished | Feb 08 06:52:20 PM UTC 25 |
| Peak memory | 227644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659273227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2659273227 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.4132989098 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4292604656 ps |
| CPU time | 20.68 seconds |
| Started | Feb 08 06:51:47 PM UTC 25 |
| Finished | Feb 08 06:52:09 PM UTC 25 |
| Peak memory | 227772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132989098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4132989098 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2981461625 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 40239382 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:51:50 PM UTC 25 |
| Finished | Feb 08 06:51:52 PM UTC 25 |
| Peak memory | 216012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981461625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2981461625 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2807647220 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 10992317 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:51:49 PM UTC 25 |
| Finished | Feb 08 06:51:52 PM UTC 25 |
| Peak memory | 215996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807647220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2807647220 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.3124338704 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 9662095943 ps |
| CPU time | 16.08 seconds |
| Started | Feb 08 06:51:55 PM UTC 25 |
| Finished | Feb 08 06:52:12 PM UTC 25 |
| Peak memory | 249536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124338704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3124338704 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.1689114591 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 15377625 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:52:23 PM UTC 25 |
| Finished | Feb 08 06:52:26 PM UTC 25 |
| Peak memory | 215776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689114591 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.1689114591 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.4056960809 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2426114898 ps |
| CPU time | 9.63 seconds |
| Started | Feb 08 06:52:17 PM UTC 25 |
| Finished | Feb 08 06:52:27 PM UTC 25 |
| Peak memory | 235168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056960809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4056960809 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.4031095977 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 70424641 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:52:10 PM UTC 25 |
| Finished | Feb 08 06:52:13 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031095977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4031095977 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.2030625254 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 90746347796 ps |
| CPU time | 391.42 seconds |
| Started | Feb 08 06:52:21 PM UTC 25 |
| Finished | Feb 08 06:58:58 PM UTC 25 |
| Peak memory | 278272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030625254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2030625254 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3187140122 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2297202880 ps |
| CPU time | 56.35 seconds |
| Started | Feb 08 06:52:21 PM UTC 25 |
| Finished | Feb 08 06:53:19 PM UTC 25 |
| Peak memory | 263920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187140122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3187140122 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.3592484147 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1141916960 ps |
| CPU time | 8.47 seconds |
| Started | Feb 08 06:52:18 PM UTC 25 |
| Finished | Feb 08 06:52:27 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592484147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3592484147 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1542068354 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1181217692 ps |
| CPU time | 28.88 seconds |
| Started | Feb 08 06:52:18 PM UTC 25 |
| Finished | Feb 08 06:52:48 PM UTC 25 |
| Peak memory | 261820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542068354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.1542068354 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.1777522349 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 270768300 ps |
| CPU time | 3.46 seconds |
| Started | Feb 08 06:52:14 PM UTC 25 |
| Finished | Feb 08 06:52:19 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777522349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1777522349 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.1714656381 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 186273876 ps |
| CPU time | 2.97 seconds |
| Started | Feb 08 06:52:15 PM UTC 25 |
| Finished | Feb 08 06:52:20 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714656381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1714656381 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2517664417 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 11039553280 ps |
| CPU time | 62.86 seconds |
| Started | Feb 08 06:52:14 PM UTC 25 |
| Finished | Feb 08 06:53:19 PM UTC 25 |
| Peak memory | 261828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517664417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.2517664417 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1099537262 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2647592380 ps |
| CPU time | 5.8 seconds |
| Started | Feb 08 06:52:14 PM UTC 25 |
| Finished | Feb 08 06:52:21 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099537262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1099537262 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1885328532 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 778553800 ps |
| CPU time | 5.99 seconds |
| Started | Feb 08 06:52:20 PM UTC 25 |
| Finished | Feb 08 06:52:27 PM UTC 25 |
| Peak memory | 231416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885328532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.1885328532 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.2192735642 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 338636579 ps |
| CPU time | 8.08 seconds |
| Started | Feb 08 06:52:13 PM UTC 25 |
| Finished | Feb 08 06:52:22 PM UTC 25 |
| Peak memory | 227576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192735642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2192735642 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2428121367 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 11518723857 ps |
| CPU time | 19.86 seconds |
| Started | Feb 08 06:52:12 PM UTC 25 |
| Finished | Feb 08 06:52:33 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428121367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2428121367 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.1009797903 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 129163862 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:52:13 PM UTC 25 |
| Finished | Feb 08 06:52:15 PM UTC 25 |
| Peak memory | 215964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009797903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1009797903 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1317895002 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 31232851 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:52:13 PM UTC 25 |
| Finished | Feb 08 06:52:15 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317895002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1317895002 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.4020653409 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 433922767 ps |
| CPU time | 5.84 seconds |
| Started | Feb 08 06:52:17 PM UTC 25 |
| Finished | Feb 08 06:52:24 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020653409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4020653409 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.3075019040 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 15428765 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:52:41 PM UTC 25 |
| Finished | Feb 08 06:52:43 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075019040 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.3075019040 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.934453841 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 171082688 ps |
| CPU time | 4.61 seconds |
| Started | Feb 08 06:52:31 PM UTC 25 |
| Finished | Feb 08 06:52:36 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934453841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.934453841 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2613490252 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 136737816 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:52:24 PM UTC 25 |
| Finished | Feb 08 06:52:27 PM UTC 25 |
| Peak memory | 215492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613490252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2613490252 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.4214528622 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 14665011376 ps |
| CPU time | 63.33 seconds |
| Started | Feb 08 06:52:35 PM UTC 25 |
| Finished | Feb 08 06:53:40 PM UTC 25 |
| Peak memory | 261872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214528622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4214528622 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2155246819 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 27426035 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:52:36 PM UTC 25 |
| Finished | Feb 08 06:52:38 PM UTC 25 |
| Peak memory | 227876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155246819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2155246819 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.4288060332 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 7461199947 ps |
| CPU time | 26.45 seconds |
| Started | Feb 08 06:52:34 PM UTC 25 |
| Finished | Feb 08 06:53:02 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288060332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4288060332 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.849636007 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 73219744536 ps |
| CPU time | 211.31 seconds |
| Started | Feb 08 06:52:34 PM UTC 25 |
| Finished | Feb 08 06:56:09 PM UTC 25 |
| Peak memory | 261888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849636007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.849636007 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2173399081 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2260269374 ps |
| CPU time | 36.8 seconds |
| Started | Feb 08 06:52:29 PM UTC 25 |
| Finished | Feb 08 06:53:07 PM UTC 25 |
| Peak memory | 235200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173399081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2173399081 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.3325497971 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5328889621 ps |
| CPU time | 39.07 seconds |
| Started | Feb 08 06:52:29 PM UTC 25 |
| Finished | Feb 08 06:53:09 PM UTC 25 |
| Peak memory | 251596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325497971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3325497971 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.878085038 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2471091422 ps |
| CPU time | 23.41 seconds |
| Started | Feb 08 06:52:29 PM UTC 25 |
| Finished | Feb 08 06:52:54 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878085038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.878085038 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2202018214 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9114785247 ps |
| CPU time | 48.39 seconds |
| Started | Feb 08 06:52:29 PM UTC 25 |
| Finished | Feb 08 06:53:19 PM UTC 25 |
| Peak memory | 251508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202018214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2202018214 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3582407300 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 143550423 ps |
| CPU time | 5.23 seconds |
| Started | Feb 08 06:52:34 PM UTC 25 |
| Finished | Feb 08 06:52:40 PM UTC 25 |
| Peak memory | 231416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582407300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.3582407300 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2988127200 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 250111455497 ps |
| CPU time | 544.36 seconds |
| Started | Feb 08 06:52:39 PM UTC 25 |
| Finished | Feb 08 07:01:49 PM UTC 25 |
| Peak memory | 278308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988127200 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2988127200 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2542138389 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 17560862831 ps |
| CPU time | 41.9 seconds |
| Started | Feb 08 06:52:27 PM UTC 25 |
| Finished | Feb 08 06:53:11 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542138389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2542138389 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3799622632 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1823955769 ps |
| CPU time | 7 seconds |
| Started | Feb 08 06:52:26 PM UTC 25 |
| Finished | Feb 08 06:52:35 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799622632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3799622632 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.2279980577 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 51824703 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:52:27 PM UTC 25 |
| Finished | Feb 08 06:52:30 PM UTC 25 |
| Peak memory | 215964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279980577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2279980577 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3669712761 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 388930106 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:52:27 PM UTC 25 |
| Finished | Feb 08 06:52:30 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669712761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3669712761 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.2865565874 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 18851496003 ps |
| CPU time | 37.89 seconds |
| Started | Feb 08 06:52:31 PM UTC 25 |
| Finished | Feb 08 06:53:10 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865565874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2865565874 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1500936481 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 29253578 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:53:14 PM UTC 25 |
| Finished | Feb 08 06:53:16 PM UTC 25 |
| Peak memory | 215900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500936481 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1500936481 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2397202675 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1213740649 ps |
| CPU time | 16.92 seconds |
| Started | Feb 08 06:53:06 PM UTC 25 |
| Finished | Feb 08 06:53:24 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397202675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2397202675 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.210083136 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 19532667 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:52:44 PM UTC 25 |
| Finished | Feb 08 06:52:46 PM UTC 25 |
| Peak memory | 215492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210083136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.210083136 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.61430874 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 4948009306 ps |
| CPU time | 50.62 seconds |
| Started | Feb 08 06:53:10 PM UTC 25 |
| Finished | Feb 08 06:54:02 PM UTC 25 |
| Peak memory | 278192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61430874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.61430874 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.474322190 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3680736450 ps |
| CPU time | 74.99 seconds |
| Started | Feb 08 06:53:11 PM UTC 25 |
| Finished | Feb 08 06:54:28 PM UTC 25 |
| Peak memory | 267952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474322190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.474322190 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2175831700 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 11920317840 ps |
| CPU time | 83.72 seconds |
| Started | Feb 08 06:53:12 PM UTC 25 |
| Finished | Feb 08 06:54:38 PM UTC 25 |
| Peak memory | 278380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175831700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.2175831700 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1072635645 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 102058412 ps |
| CPU time | 4.26 seconds |
| Started | Feb 08 06:53:08 PM UTC 25 |
| Finished | Feb 08 06:53:13 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072635645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1072635645 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1290243349 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 39533864494 ps |
| CPU time | 69.47 seconds |
| Started | Feb 08 06:53:09 PM UTC 25 |
| Finished | Feb 08 06:54:20 PM UTC 25 |
| Peak memory | 263856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290243349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1290243349 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.1034666847 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 726170153 ps |
| CPU time | 6.25 seconds |
| Started | Feb 08 06:53:00 PM UTC 25 |
| Finished | Feb 08 06:53:08 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034666847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1034666847 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1181681753 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5266263738 ps |
| CPU time | 20.22 seconds |
| Started | Feb 08 06:53:01 PM UTC 25 |
| Finished | Feb 08 06:53:23 PM UTC 25 |
| Peak memory | 245432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181681753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1181681753 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.2977850146 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4672272451 ps |
| CPU time | 9.66 seconds |
| Started | Feb 08 06:53:00 PM UTC 25 |
| Finished | Feb 08 06:53:11 PM UTC 25 |
| Peak memory | 245544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977850146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.2977850146 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3026398068 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 408620788 ps |
| CPU time | 9.59 seconds |
| Started | Feb 08 06:52:58 PM UTC 25 |
| Finished | Feb 08 06:53:09 PM UTC 25 |
| Peak memory | 245276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026398068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3026398068 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.3580660480 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 791857830 ps |
| CPU time | 5.69 seconds |
| Started | Feb 08 06:53:10 PM UTC 25 |
| Finished | Feb 08 06:53:17 PM UTC 25 |
| Peak memory | 231472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580660480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.3580660480 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.1344287895 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 225344059597 ps |
| CPU time | 470.95 seconds |
| Started | Feb 08 06:53:12 PM UTC 25 |
| Finished | Feb 08 07:01:09 PM UTC 25 |
| Peak memory | 263928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344287895 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.1344287895 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.346424902 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1596278757 ps |
| CPU time | 22.56 seconds |
| Started | Feb 08 06:52:50 PM UTC 25 |
| Finished | Feb 08 06:53:14 PM UTC 25 |
| Peak memory | 227508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346424902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.346424902 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2584766800 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 4919985084 ps |
| CPU time | 10.66 seconds |
| Started | Feb 08 06:52:49 PM UTC 25 |
| Finished | Feb 08 06:53:01 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584766800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2584766800 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.3834864202 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 215335290 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:52:56 PM UTC 25 |
| Finished | Feb 08 06:52:59 PM UTC 25 |
| Peak memory | 216620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834864202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3834864202 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.801876463 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 137158697 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:52:54 PM UTC 25 |
| Finished | Feb 08 06:52:57 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801876463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.801876463 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.458902607 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 4719307888 ps |
| CPU time | 12.37 seconds |
| Started | Feb 08 06:53:02 PM UTC 25 |
| Finished | Feb 08 06:53:16 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458902607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.458902607 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.271414162 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 35790365 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:47:51 PM UTC 25 |
| Finished | Feb 08 06:47:53 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271414162 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.271414162 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2720872962 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 71454644 ps |
| CPU time | 4.39 seconds |
| Started | Feb 08 06:47:49 PM UTC 25 |
| Finished | Feb 08 06:47:54 PM UTC 25 |
| Peak memory | 245136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720872962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2720872962 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2453746490 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 50133390 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:47:46 PM UTC 25 |
| Finished | Feb 08 06:47:48 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453746490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2453746490 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3609573105 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4139143177 ps |
| CPU time | 14.22 seconds |
| Started | Feb 08 06:47:49 PM UTC 25 |
| Finished | Feb 08 06:48:04 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609573105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3609573105 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2875783290 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4062364754 ps |
| CPU time | 33.08 seconds |
| Started | Feb 08 06:47:49 PM UTC 25 |
| Finished | Feb 08 06:48:23 PM UTC 25 |
| Peak memory | 231568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875783290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.2875783290 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.228657188 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2435537350 ps |
| CPU time | 8.59 seconds |
| Started | Feb 08 06:47:48 PM UTC 25 |
| Finished | Feb 08 06:47:57 PM UTC 25 |
| Peak memory | 245380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228657188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.228657188 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.576501819 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 12418235920 ps |
| CPU time | 106.8 seconds |
| Started | Feb 08 06:47:48 PM UTC 25 |
| Finished | Feb 08 06:49:37 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576501819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.576501819 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3379126287 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 245716299 ps |
| CPU time | 6.68 seconds |
| Started | Feb 08 06:47:48 PM UTC 25 |
| Finished | Feb 08 06:47:56 PM UTC 25 |
| Peak memory | 245228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379126287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.3379126287 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3368158858 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3461274660 ps |
| CPU time | 12.84 seconds |
| Started | Feb 08 06:47:48 PM UTC 25 |
| Finished | Feb 08 06:48:02 PM UTC 25 |
| Peak memory | 251432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368158858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3368158858 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1879686750 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1003132163 ps |
| CPU time | 7.44 seconds |
| Started | Feb 08 06:47:49 PM UTC 25 |
| Finished | Feb 08 06:47:57 PM UTC 25 |
| Peak memory | 233924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879686750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.1879686750 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2288358211 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 216884567 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:47:50 PM UTC 25 |
| Finished | Feb 08 06:47:53 PM UTC 25 |
| Peak memory | 257892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288358211 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2288358211 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.2893323027 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 11030749611 ps |
| CPU time | 33.84 seconds |
| Started | Feb 08 06:47:46 PM UTC 25 |
| Finished | Feb 08 06:48:22 PM UTC 25 |
| Peak memory | 231740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893323027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2893323027 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3291276970 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 8173953570 ps |
| CPU time | 8.45 seconds |
| Started | Feb 08 06:47:46 PM UTC 25 |
| Finished | Feb 08 06:47:56 PM UTC 25 |
| Peak memory | 229696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291276970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3291276970 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.394766156 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 97050853 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:47:46 PM UTC 25 |
| Finished | Feb 08 06:47:49 PM UTC 25 |
| Peak memory | 216224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394766156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.394766156 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3860598004 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13138772 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:47:46 PM UTC 25 |
| Finished | Feb 08 06:47:49 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860598004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3860598004 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1627785345 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 31917898 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:53:24 PM UTC 25 |
| Finished | Feb 08 06:53:26 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627785345 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.1627785345 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2781236661 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 156392385 ps |
| CPU time | 2.8 seconds |
| Started | Feb 08 06:53:20 PM UTC 25 |
| Finished | Feb 08 06:53:24 PM UTC 25 |
| Peak memory | 245304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781236661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2781236661 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.3830839432 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 63840725 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:53:15 PM UTC 25 |
| Finished | Feb 08 06:53:17 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830839432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3830839432 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.1539902997 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 50620241539 ps |
| CPU time | 229.81 seconds |
| Started | Feb 08 06:53:22 PM UTC 25 |
| Finished | Feb 08 06:57:15 PM UTC 25 |
| Peak memory | 278188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539902997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1539902997 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3644722850 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 14551351132 ps |
| CPU time | 143.97 seconds |
| Started | Feb 08 06:53:23 PM UTC 25 |
| Finished | Feb 08 06:55:50 PM UTC 25 |
| Peak memory | 261868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644722850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.3644722850 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2394435086 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 488057830 ps |
| CPU time | 10.86 seconds |
| Started | Feb 08 06:53:20 PM UTC 25 |
| Finished | Feb 08 06:53:32 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394435086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2394435086 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.4272489109 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3827802710 ps |
| CPU time | 38.64 seconds |
| Started | Feb 08 06:53:21 PM UTC 25 |
| Finished | Feb 08 06:54:01 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272489109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.4272489109 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.3205174813 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 76433753 ps |
| CPU time | 2.68 seconds |
| Started | Feb 08 06:53:18 PM UTC 25 |
| Finished | Feb 08 06:53:22 PM UTC 25 |
| Peak memory | 233492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205174813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3205174813 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.356369591 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2527959457 ps |
| CPU time | 6.99 seconds |
| Started | Feb 08 06:53:20 PM UTC 25 |
| Finished | Feb 08 06:53:28 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356369591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.356369591 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.531122474 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 779413913 ps |
| CPU time | 8.94 seconds |
| Started | Feb 08 06:53:18 PM UTC 25 |
| Finished | Feb 08 06:53:29 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531122474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.531122474 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1085696 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1720416088 ps |
| CPU time | 8.2 seconds |
| Started | Feb 08 06:53:17 PM UTC 25 |
| Finished | Feb 08 06:53:27 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1085696 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3692953844 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2112938121 ps |
| CPU time | 11.51 seconds |
| Started | Feb 08 06:53:21 PM UTC 25 |
| Finished | Feb 08 06:53:34 PM UTC 25 |
| Peak memory | 231412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692953844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3692953844 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2747641531 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 247880164562 ps |
| CPU time | 603.26 seconds |
| Started | Feb 08 06:53:24 PM UTC 25 |
| Finished | Feb 08 07:03:35 PM UTC 25 |
| Peak memory | 278268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747641531 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.2747641531 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.3984557120 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 6008012834 ps |
| CPU time | 11.06 seconds |
| Started | Feb 08 06:53:17 PM UTC 25 |
| Finished | Feb 08 06:53:30 PM UTC 25 |
| Peak memory | 227764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984557120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3984557120 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1816911273 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 495464373 ps |
| CPU time | 6.87 seconds |
| Started | Feb 08 06:53:16 PM UTC 25 |
| Finished | Feb 08 06:53:24 PM UTC 25 |
| Peak memory | 227544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816911273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1816911273 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.2709543092 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 816193840 ps |
| CPU time | 3.2 seconds |
| Started | Feb 08 06:53:17 PM UTC 25 |
| Finished | Feb 08 06:53:22 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709543092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2709543092 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.109322457 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 42991648 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:53:17 PM UTC 25 |
| Finished | Feb 08 06:53:19 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109322457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.109322457 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.4205704804 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 948566849 ps |
| CPU time | 9.31 seconds |
| Started | Feb 08 06:53:20 PM UTC 25 |
| Finished | Feb 08 06:53:30 PM UTC 25 |
| Peak memory | 251512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205704804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4205704804 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.3068638244 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 17661805 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:53:43 PM UTC 25 |
| Finished | Feb 08 06:53:45 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068638244 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.3068638244 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2478515687 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 233600888 ps |
| CPU time | 3.66 seconds |
| Started | Feb 08 06:53:31 PM UTC 25 |
| Finished | Feb 08 06:53:36 PM UTC 25 |
| Peak memory | 235140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478515687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2478515687 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.3896119188 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 41165893 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:53:24 PM UTC 25 |
| Finished | Feb 08 06:53:26 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896119188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3896119188 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.495040955 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2581003050 ps |
| CPU time | 77.38 seconds |
| Started | Feb 08 06:53:34 PM UTC 25 |
| Finished | Feb 08 06:54:53 PM UTC 25 |
| Peak memory | 267944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495040955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.495040955 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3914227670 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 12975857888 ps |
| CPU time | 107.13 seconds |
| Started | Feb 08 06:53:36 PM UTC 25 |
| Finished | Feb 08 06:55:25 PM UTC 25 |
| Peak memory | 278248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914227670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3914227670 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.179276217 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 172787282 ps |
| CPU time | 3.79 seconds |
| Started | Feb 08 06:53:31 PM UTC 25 |
| Finished | Feb 08 06:53:36 PM UTC 25 |
| Peak memory | 245428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179276217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.179276217 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3012112962 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 85146315834 ps |
| CPU time | 180.34 seconds |
| Started | Feb 08 06:53:32 PM UTC 25 |
| Finished | Feb 08 06:56:35 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012112962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3012112962 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1644929345 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3349193573 ps |
| CPU time | 31.75 seconds |
| Started | Feb 08 06:53:30 PM UTC 25 |
| Finished | Feb 08 06:54:03 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644929345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1644929345 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.4016378552 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 367530324 ps |
| CPU time | 18.98 seconds |
| Started | Feb 08 06:53:31 PM UTC 25 |
| Finished | Feb 08 06:53:51 PM UTC 25 |
| Peak memory | 235144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016378552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4016378552 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3261901898 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3128390684 ps |
| CPU time | 13.56 seconds |
| Started | Feb 08 06:53:30 PM UTC 25 |
| Finished | Feb 08 06:53:44 PM UTC 25 |
| Peak memory | 235128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261901898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3261901898 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1376238855 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 40807395668 ps |
| CPU time | 49.28 seconds |
| Started | Feb 08 06:53:28 PM UTC 25 |
| Finished | Feb 08 06:54:20 PM UTC 25 |
| Peak memory | 261872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376238855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1376238855 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3287935677 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 662083153 ps |
| CPU time | 8.76 seconds |
| Started | Feb 08 06:53:33 PM UTC 25 |
| Finished | Feb 08 06:53:43 PM UTC 25 |
| Peak memory | 233524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287935677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.3287935677 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1709972371 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2893962621 ps |
| CPU time | 46.56 seconds |
| Started | Feb 08 06:53:41 PM UTC 25 |
| Finished | Feb 08 06:54:29 PM UTC 25 |
| Peak memory | 249584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709972371 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1709972371 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2487541803 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2577770641 ps |
| CPU time | 21.63 seconds |
| Started | Feb 08 06:53:27 PM UTC 25 |
| Finished | Feb 08 06:53:50 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487541803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2487541803 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.880995175 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 7610160695 ps |
| CPU time | 38.01 seconds |
| Started | Feb 08 06:53:25 PM UTC 25 |
| Finished | Feb 08 06:54:05 PM UTC 25 |
| Peak memory | 227760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880995175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.880995175 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.1086349131 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 86316561 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:53:27 PM UTC 25 |
| Finished | Feb 08 06:53:30 PM UTC 25 |
| Peak memory | 216620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086349131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1086349131 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3781598903 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 17020147 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:53:27 PM UTC 25 |
| Finished | Feb 08 06:53:30 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781598903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3781598903 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3540340459 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 104608309193 ps |
| CPU time | 51.47 seconds |
| Started | Feb 08 06:53:31 PM UTC 25 |
| Finished | Feb 08 06:54:24 PM UTC 25 |
| Peak memory | 261816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540340459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3540340459 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.104362092 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 18679272 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:54:12 PM UTC 25 |
| Finished | Feb 08 06:54:14 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104362092 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.104362092 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.497979972 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 5042259648 ps |
| CPU time | 17.61 seconds |
| Started | Feb 08 06:53:59 PM UTC 25 |
| Finished | Feb 08 06:54:18 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497979972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.497979972 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.3824579879 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 12705447 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:53:45 PM UTC 25 |
| Finished | Feb 08 06:53:48 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824579879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3824579879 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.1311665128 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 163996789 ps |
| CPU time | 6.92 seconds |
| Started | Feb 08 06:54:03 PM UTC 25 |
| Finished | Feb 08 06:54:11 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311665128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1311665128 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2116872857 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 44650165418 ps |
| CPU time | 503.51 seconds |
| Started | Feb 08 06:54:04 PM UTC 25 |
| Finished | Feb 08 07:02:34 PM UTC 25 |
| Peak memory | 268024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116872857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2116872857 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.3025323694 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 412914277 ps |
| CPU time | 9.2 seconds |
| Started | Feb 08 06:54:00 PM UTC 25 |
| Finished | Feb 08 06:54:11 PM UTC 25 |
| Peak memory | 261756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025323694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3025323694 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3273330920 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 43943016570 ps |
| CPU time | 264.4 seconds |
| Started | Feb 08 06:54:00 PM UTC 25 |
| Finished | Feb 08 06:58:29 PM UTC 25 |
| Peak memory | 268028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273330920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.3273330920 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2543533391 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 35480583 ps |
| CPU time | 3.23 seconds |
| Started | Feb 08 06:53:55 PM UTC 25 |
| Finished | Feb 08 06:53:59 PM UTC 25 |
| Peak memory | 244932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543533391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2543533391 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.1958702571 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 20359391431 ps |
| CPU time | 103.09 seconds |
| Started | Feb 08 06:53:55 PM UTC 25 |
| Finished | Feb 08 06:55:40 PM UTC 25 |
| Peak memory | 235200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958702571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1958702571 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2935616463 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 338370678 ps |
| CPU time | 4.6 seconds |
| Started | Feb 08 06:53:54 PM UTC 25 |
| Finished | Feb 08 06:53:59 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935616463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.2935616463 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.398316291 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 649894481 ps |
| CPU time | 5.22 seconds |
| Started | Feb 08 06:53:52 PM UTC 25 |
| Finished | Feb 08 06:53:58 PM UTC 25 |
| Peak memory | 235036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398316291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.398316291 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.2093093386 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2292805803 ps |
| CPU time | 28.49 seconds |
| Started | Feb 08 06:54:01 PM UTC 25 |
| Finished | Feb 08 06:54:31 PM UTC 25 |
| Peak memory | 231480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093093386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.2093093386 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.627380370 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 182939653144 ps |
| CPU time | 775.34 seconds |
| Started | Feb 08 06:54:06 PM UTC 25 |
| Finished | Feb 08 07:07:11 PM UTC 25 |
| Peak memory | 278300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627380370 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.627380370 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.2081506589 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 21302799 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:53:49 PM UTC 25 |
| Finished | Feb 08 06:53:51 PM UTC 25 |
| Peak memory | 215900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081506589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2081506589 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1146988038 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 926643785 ps |
| CPU time | 5.04 seconds |
| Started | Feb 08 06:53:46 PM UTC 25 |
| Finished | Feb 08 06:53:53 PM UTC 25 |
| Peak memory | 227500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146988038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1146988038 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.1114802086 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 25378067 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:53:52 PM UTC 25 |
| Finished | Feb 08 06:53:54 PM UTC 25 |
| Peak memory | 216012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114802086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1114802086 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2949069343 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 90870757 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:53:52 PM UTC 25 |
| Finished | Feb 08 06:53:54 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949069343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2949069343 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.1640798799 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1595981636 ps |
| CPU time | 14.31 seconds |
| Started | Feb 08 06:53:56 PM UTC 25 |
| Finished | Feb 08 06:54:12 PM UTC 25 |
| Peak memory | 245296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640798799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1640798799 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.4164992759 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 11336859 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:54:31 PM UTC 25 |
| Finished | Feb 08 06:54:33 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164992759 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.4164992759 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3860542195 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 7407352730 ps |
| CPU time | 21.24 seconds |
| Started | Feb 08 06:54:21 PM UTC 25 |
| Finished | Feb 08 06:54:43 PM UTC 25 |
| Peak memory | 245444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860542195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3860542195 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.601009532 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 18557808 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:54:12 PM UTC 25 |
| Finished | Feb 08 06:54:14 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601009532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.601009532 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2096938922 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 18064547322 ps |
| CPU time | 109.41 seconds |
| Started | Feb 08 06:54:28 PM UTC 25 |
| Finished | Feb 08 06:56:20 PM UTC 25 |
| Peak memory | 251564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096938922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2096938922 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1846697758 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4999602155 ps |
| CPU time | 70.06 seconds |
| Started | Feb 08 06:54:28 PM UTC 25 |
| Finished | Feb 08 06:55:40 PM UTC 25 |
| Peak memory | 261972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846697758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1846697758 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1862796871 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 118239402 ps |
| CPU time | 6.07 seconds |
| Started | Feb 08 06:54:21 PM UTC 25 |
| Finished | Feb 08 06:54:28 PM UTC 25 |
| Peak memory | 245484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862796871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1862796871 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.4174192582 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 599642746 ps |
| CPU time | 10.56 seconds |
| Started | Feb 08 06:54:18 PM UTC 25 |
| Finished | Feb 08 06:54:30 PM UTC 25 |
| Peak memory | 234960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174192582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4174192582 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2188463369 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 22200373785 ps |
| CPU time | 69.98 seconds |
| Started | Feb 08 06:54:19 PM UTC 25 |
| Finished | Feb 08 06:55:31 PM UTC 25 |
| Peak memory | 235192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188463369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2188463369 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3183124349 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2422263181 ps |
| CPU time | 3.89 seconds |
| Started | Feb 08 06:54:18 PM UTC 25 |
| Finished | Feb 08 06:54:23 PM UTC 25 |
| Peak memory | 245236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183124349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.3183124349 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1939317209 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 24700687061 ps |
| CPU time | 18.21 seconds |
| Started | Feb 08 06:54:15 PM UTC 25 |
| Finished | Feb 08 06:54:35 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939317209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1939317209 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3384542204 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1490746251 ps |
| CPU time | 8.33 seconds |
| Started | Feb 08 06:54:25 PM UTC 25 |
| Finished | Feb 08 06:54:34 PM UTC 25 |
| Peak memory | 233524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384542204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.3384542204 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.1210134869 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 7371360896 ps |
| CPU time | 128.49 seconds |
| Started | Feb 08 06:54:31 PM UTC 25 |
| Finished | Feb 08 06:56:41 PM UTC 25 |
| Peak memory | 280376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210134869 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.1210134869 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.1777690553 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 22580283394 ps |
| CPU time | 35.18 seconds |
| Started | Feb 08 06:54:13 PM UTC 25 |
| Finished | Feb 08 06:54:50 PM UTC 25 |
| Peak memory | 227424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777690553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1777690553 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.217549455 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1555497353 ps |
| CPU time | 3 seconds |
| Started | Feb 08 06:54:13 PM UTC 25 |
| Finished | Feb 08 06:54:17 PM UTC 25 |
| Peak memory | 227416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217549455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.217549455 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1612971550 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 98706503 ps |
| CPU time | 3.11 seconds |
| Started | Feb 08 06:54:15 PM UTC 25 |
| Finished | Feb 08 06:54:19 PM UTC 25 |
| Peak memory | 227560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612971550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1612971550 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1853354268 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 33029640 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:54:15 PM UTC 25 |
| Finished | Feb 08 06:54:17 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853354268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1853354268 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.2254862340 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2143846382 ps |
| CPU time | 8.6 seconds |
| Started | Feb 08 06:54:21 PM UTC 25 |
| Finished | Feb 08 06:54:30 PM UTC 25 |
| Peak memory | 245312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254862340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2254862340 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.149661955 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 12748127 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:54:53 PM UTC 25 |
| Finished | Feb 08 06:54:55 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149661955 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.149661955 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1531869592 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2387721386 ps |
| CPU time | 14.35 seconds |
| Started | Feb 08 06:54:42 PM UTC 25 |
| Finished | Feb 08 06:54:58 PM UTC 25 |
| Peak memory | 235204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531869592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1531869592 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.1121814984 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 30431008 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:54:32 PM UTC 25 |
| Finished | Feb 08 06:54:34 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121814984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1121814984 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.2080169931 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 27327455893 ps |
| CPU time | 130.35 seconds |
| Started | Feb 08 06:54:48 PM UTC 25 |
| Finished | Feb 08 06:57:00 PM UTC 25 |
| Peak memory | 261800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080169931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2080169931 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.379013248 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 7991148501 ps |
| CPU time | 74.69 seconds |
| Started | Feb 08 06:54:51 PM UTC 25 |
| Finished | Feb 08 06:56:07 PM UTC 25 |
| Peak memory | 261860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379013248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.379013248 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.107898105 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 60371078166 ps |
| CPU time | 131.42 seconds |
| Started | Feb 08 06:54:52 PM UTC 25 |
| Finished | Feb 08 06:57:06 PM UTC 25 |
| Peak memory | 263916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107898105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.107898105 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.3890341203 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 3112790540 ps |
| CPU time | 45.16 seconds |
| Started | Feb 08 06:54:43 PM UTC 25 |
| Finished | Feb 08 06:55:30 PM UTC 25 |
| Peak memory | 261884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890341203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3890341203 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2528872761 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2026343659 ps |
| CPU time | 26.36 seconds |
| Started | Feb 08 06:54:44 PM UTC 25 |
| Finished | Feb 08 06:55:12 PM UTC 25 |
| Peak memory | 251504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528872761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2528872761 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3329211312 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5086464530 ps |
| CPU time | 16.79 seconds |
| Started | Feb 08 06:54:38 PM UTC 25 |
| Finished | Feb 08 06:54:56 PM UTC 25 |
| Peak memory | 245444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329211312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3329211312 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.702526253 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 14640829316 ps |
| CPU time | 43.63 seconds |
| Started | Feb 08 06:54:38 PM UTC 25 |
| Finished | Feb 08 06:55:23 PM UTC 25 |
| Peak memory | 235188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702526253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.702526253 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1888259672 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1060670952 ps |
| CPU time | 5.34 seconds |
| Started | Feb 08 06:54:38 PM UTC 25 |
| Finished | Feb 08 06:54:45 PM UTC 25 |
| Peak memory | 235112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888259672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.1888259672 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1103402084 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1361495273 ps |
| CPU time | 14.97 seconds |
| Started | Feb 08 06:54:36 PM UTC 25 |
| Finished | Feb 08 06:54:52 PM UTC 25 |
| Peak memory | 261744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103402084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1103402084 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2799270311 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 212003747 ps |
| CPU time | 5.13 seconds |
| Started | Feb 08 06:54:46 PM UTC 25 |
| Finished | Feb 08 06:54:52 PM UTC 25 |
| Peak memory | 234148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799270311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2799270311 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.572614840 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 44704383341 ps |
| CPU time | 483.4 seconds |
| Started | Feb 08 06:54:52 PM UTC 25 |
| Finished | Feb 08 07:03:02 PM UTC 25 |
| Peak memory | 278252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572614840 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.572614840 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.1322115177 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2656185995 ps |
| CPU time | 17.71 seconds |
| Started | Feb 08 06:54:34 PM UTC 25 |
| Finished | Feb 08 06:54:53 PM UTC 25 |
| Peak memory | 227624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322115177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1322115177 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.440700141 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 941090206 ps |
| CPU time | 7.67 seconds |
| Started | Feb 08 06:54:33 PM UTC 25 |
| Finished | Feb 08 06:54:42 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440700141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.440700141 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.3964620806 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 115117691 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:54:35 PM UTC 25 |
| Finished | Feb 08 06:54:38 PM UTC 25 |
| Peak memory | 216452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964620806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3964620806 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1086191720 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 68100775 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:54:35 PM UTC 25 |
| Finished | Feb 08 06:54:37 PM UTC 25 |
| Peak memory | 215912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086191720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1086191720 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.4248852307 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 25478735945 ps |
| CPU time | 10.83 seconds |
| Started | Feb 08 06:54:39 PM UTC 25 |
| Finished | Feb 08 06:54:51 PM UTC 25 |
| Peak memory | 235136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248852307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4248852307 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.953156686 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 29313160 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:55:23 PM UTC 25 |
| Finished | Feb 08 06:55:25 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953156686 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.953156686 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.361619442 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 30562537 ps |
| CPU time | 3.12 seconds |
| Started | Feb 08 06:55:05 PM UTC 25 |
| Finished | Feb 08 06:55:09 PM UTC 25 |
| Peak memory | 244988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361619442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.361619442 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1342843316 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 38432692 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:54:53 PM UTC 25 |
| Finished | Feb 08 06:54:55 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342843316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1342843316 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.2871225984 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 9971278289 ps |
| CPU time | 90.01 seconds |
| Started | Feb 08 06:55:10 PM UTC 25 |
| Finished | Feb 08 06:56:42 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871225984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2871225984 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.2198434557 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 74917124675 ps |
| CPU time | 149.58 seconds |
| Started | Feb 08 06:55:13 PM UTC 25 |
| Finished | Feb 08 06:57:45 PM UTC 25 |
| Peak memory | 251616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198434557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2198434557 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.3254212488 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 73117981915 ps |
| CPU time | 331.57 seconds |
| Started | Feb 08 06:55:16 PM UTC 25 |
| Finished | Feb 08 07:00:52 PM UTC 25 |
| Peak memory | 251628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254212488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.3254212488 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.3473327398 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 9216468246 ps |
| CPU time | 30.57 seconds |
| Started | Feb 08 06:55:05 PM UTC 25 |
| Finished | Feb 08 06:55:37 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473327398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3473327398 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.2849686741 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 379829688 ps |
| CPU time | 4.78 seconds |
| Started | Feb 08 06:54:59 PM UTC 25 |
| Finished | Feb 08 06:55:05 PM UTC 25 |
| Peak memory | 235004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849686741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2849686741 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2082166679 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2889829730 ps |
| CPU time | 20.39 seconds |
| Started | Feb 08 06:55:01 PM UTC 25 |
| Finished | Feb 08 06:55:23 PM UTC 25 |
| Peak memory | 245384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082166679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2082166679 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1985278446 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 295292807 ps |
| CPU time | 4.52 seconds |
| Started | Feb 08 06:54:58 PM UTC 25 |
| Finished | Feb 08 06:55:04 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985278446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1985278446 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2667481943 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 8423940782 ps |
| CPU time | 26.13 seconds |
| Started | Feb 08 06:54:57 PM UTC 25 |
| Finished | Feb 08 06:55:25 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667481943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2667481943 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2093795035 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 15550320858 ps |
| CPU time | 16.62 seconds |
| Started | Feb 08 06:55:07 PM UTC 25 |
| Finished | Feb 08 06:55:25 PM UTC 25 |
| Peak memory | 231480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093795035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.2093795035 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.2435958854 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 43816997420 ps |
| CPU time | 362.52 seconds |
| Started | Feb 08 06:55:17 PM UTC 25 |
| Finished | Feb 08 07:01:24 PM UTC 25 |
| Peak memory | 278256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435958854 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.2435958854 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1481022580 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3235606010 ps |
| CPU time | 21.35 seconds |
| Started | Feb 08 06:54:54 PM UTC 25 |
| Finished | Feb 08 06:55:17 PM UTC 25 |
| Peak memory | 227644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481022580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1481022580 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.3442207728 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2975840964 ps |
| CPU time | 5.04 seconds |
| Started | Feb 08 06:54:54 PM UTC 25 |
| Finished | Feb 08 06:55:00 PM UTC 25 |
| Peak memory | 227420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442207728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3442207728 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.2191900551 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 941566498 ps |
| CPU time | 8.17 seconds |
| Started | Feb 08 06:54:56 PM UTC 25 |
| Finished | Feb 08 06:55:06 PM UTC 25 |
| Peak memory | 227400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191900551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2191900551 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3912479421 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 85066048 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:54:56 PM UTC 25 |
| Finished | Feb 08 06:54:58 PM UTC 25 |
| Peak memory | 215824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912479421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3912479421 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.881603254 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 9843125570 ps |
| CPU time | 24.44 seconds |
| Started | Feb 08 06:55:01 PM UTC 25 |
| Finished | Feb 08 06:55:27 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881603254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.881603254 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.4269879003 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 15033723 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:55:41 PM UTC 25 |
| Finished | Feb 08 06:55:44 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269879003 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.4269879003 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1086033392 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1817293251 ps |
| CPU time | 9.8 seconds |
| Started | Feb 08 06:55:31 PM UTC 25 |
| Finished | Feb 08 06:55:42 PM UTC 25 |
| Peak memory | 245304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086033392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1086033392 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.2459775214 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 83146200 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:55:24 PM UTC 25 |
| Finished | Feb 08 06:55:26 PM UTC 25 |
| Peak memory | 215492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459775214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2459775214 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.3504880440 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 29637840105 ps |
| CPU time | 228.23 seconds |
| Started | Feb 08 06:55:39 PM UTC 25 |
| Finished | Feb 08 06:59:31 PM UTC 25 |
| Peak memory | 267816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504880440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3504880440 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.1591830144 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 15015140244 ps |
| CPU time | 92.17 seconds |
| Started | Feb 08 06:55:39 PM UTC 25 |
| Finished | Feb 08 06:57:13 PM UTC 25 |
| Peak memory | 261872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591830144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1591830144 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.491501624 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 25609779212 ps |
| CPU time | 126.23 seconds |
| Started | Feb 08 06:55:40 PM UTC 25 |
| Finished | Feb 08 06:57:49 PM UTC 25 |
| Peak memory | 261912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491501624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.491501624 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1247888008 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 108655290 ps |
| CPU time | 4.91 seconds |
| Started | Feb 08 06:55:32 PM UTC 25 |
| Finished | Feb 08 06:55:38 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247888008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1247888008 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.4083370200 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 9784769416 ps |
| CPU time | 158.84 seconds |
| Started | Feb 08 06:55:35 PM UTC 25 |
| Finished | Feb 08 06:58:17 PM UTC 25 |
| Peak memory | 278320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083370200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.4083370200 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2769261358 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 951327957 ps |
| CPU time | 9.18 seconds |
| Started | Feb 08 06:55:29 PM UTC 25 |
| Finished | Feb 08 06:55:39 PM UTC 25 |
| Peak memory | 234992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769261358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2769261358 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.288435006 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2678048396 ps |
| CPU time | 10.83 seconds |
| Started | Feb 08 06:55:29 PM UTC 25 |
| Finished | Feb 08 06:55:41 PM UTC 25 |
| Peak memory | 235112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288435006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.288435006 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2324920345 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3677890453 ps |
| CPU time | 5.72 seconds |
| Started | Feb 08 06:55:28 PM UTC 25 |
| Finished | Feb 08 06:55:34 PM UTC 25 |
| Peak memory | 235188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324920345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.2324920345 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.635149177 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4392128738 ps |
| CPU time | 10.59 seconds |
| Started | Feb 08 06:55:26 PM UTC 25 |
| Finished | Feb 08 06:55:38 PM UTC 25 |
| Peak memory | 245432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635149177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.635149177 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2769057725 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2580506682 ps |
| CPU time | 8.26 seconds |
| Started | Feb 08 06:55:37 PM UTC 25 |
| Finished | Feb 08 06:55:47 PM UTC 25 |
| Peak memory | 234300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769057725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2769057725 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.955996397 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 65481733 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:55:41 PM UTC 25 |
| Finished | Feb 08 06:55:44 PM UTC 25 |
| Peak memory | 216248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955996397 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.955996397 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.1118145444 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 9807890914 ps |
| CPU time | 22 seconds |
| Started | Feb 08 06:55:25 PM UTC 25 |
| Finished | Feb 08 06:55:49 PM UTC 25 |
| Peak memory | 231676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118145444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1118145444 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1240006318 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 29352149398 ps |
| CPU time | 35 seconds |
| Started | Feb 08 06:55:24 PM UTC 25 |
| Finished | Feb 08 06:56:01 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240006318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1240006318 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.136889488 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 110288169 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:55:26 PM UTC 25 |
| Finished | Feb 08 06:55:29 PM UTC 25 |
| Peak memory | 216488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136889488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.136889488 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3365212103 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 188984523 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:55:25 PM UTC 25 |
| Finished | Feb 08 06:55:28 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365212103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3365212103 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.419309401 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 492247448 ps |
| CPU time | 9.09 seconds |
| Started | Feb 08 06:55:30 PM UTC 25 |
| Finished | Feb 08 06:55:40 PM UTC 25 |
| Peak memory | 245312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419309401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.419309401 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3472262012 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 13807024 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:55:55 PM UTC 25 |
| Finished | Feb 08 06:55:58 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472262012 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.3472262012 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.686797248 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 77418011 ps |
| CPU time | 3.11 seconds |
| Started | Feb 08 06:55:49 PM UTC 25 |
| Finished | Feb 08 06:55:53 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686797248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.686797248 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.2780400940 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 99355476 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:55:41 PM UTC 25 |
| Finished | Feb 08 06:55:44 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780400940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2780400940 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.2284604566 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 38431458361 ps |
| CPU time | 128.65 seconds |
| Started | Feb 08 06:55:53 PM UTC 25 |
| Finished | Feb 08 06:58:04 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284604566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2284604566 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.220218996 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 10371406845 ps |
| CPU time | 49.16 seconds |
| Started | Feb 08 06:55:53 PM UTC 25 |
| Finished | Feb 08 06:56:44 PM UTC 25 |
| Peak memory | 229740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220218996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.220218996 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3738979047 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2265680732 ps |
| CPU time | 44.6 seconds |
| Started | Feb 08 06:55:50 PM UTC 25 |
| Finished | Feb 08 06:56:36 PM UTC 25 |
| Peak memory | 261816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738979047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3738979047 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.124200922 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 8197017277 ps |
| CPU time | 57.86 seconds |
| Started | Feb 08 06:55:51 PM UTC 25 |
| Finished | Feb 08 06:56:51 PM UTC 25 |
| Peak memory | 247472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124200922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.124200922 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.711449651 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 776241173 ps |
| CPU time | 6.8 seconds |
| Started | Feb 08 06:55:45 PM UTC 25 |
| Finished | Feb 08 06:55:53 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711449651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.711449651 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.529361028 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 201744523 ps |
| CPU time | 3.73 seconds |
| Started | Feb 08 06:55:46 PM UTC 25 |
| Finished | Feb 08 06:55:51 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529361028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.529361028 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3790543865 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 231957985 ps |
| CPU time | 10.57 seconds |
| Started | Feb 08 06:55:45 PM UTC 25 |
| Finished | Feb 08 06:55:57 PM UTC 25 |
| Peak memory | 235192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790543865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3790543865 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.1674687034 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1565796256 ps |
| CPU time | 8.61 seconds |
| Started | Feb 08 06:55:45 PM UTC 25 |
| Finished | Feb 08 06:55:55 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674687034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1674687034 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.4043437753 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 96418897 ps |
| CPU time | 5.93 seconds |
| Started | Feb 08 06:55:53 PM UTC 25 |
| Finished | Feb 08 06:56:00 PM UTC 25 |
| Peak memory | 233804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043437753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.4043437753 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.23637219 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 47762217146 ps |
| CPU time | 310.66 seconds |
| Started | Feb 08 06:55:54 PM UTC 25 |
| Finished | Feb 08 07:01:09 PM UTC 25 |
| Peak memory | 278264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23637219 -assert nopostproc +UVM_TESTNAME=spi_ device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.23637219 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.862522097 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 32755425 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:55:41 PM UTC 25 |
| Finished | Feb 08 06:55:44 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862522097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.862522097 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.3737598661 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3048376940 ps |
| CPU time | 9.64 seconds |
| Started | Feb 08 06:55:41 PM UTC 25 |
| Finished | Feb 08 06:55:52 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737598661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3737598661 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1677137494 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1052593486 ps |
| CPU time | 7.34 seconds |
| Started | Feb 08 06:55:45 PM UTC 25 |
| Finished | Feb 08 06:55:53 PM UTC 25 |
| Peak memory | 227520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677137494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1677137494 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2237270574 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 28496482 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:55:42 PM UTC 25 |
| Finished | Feb 08 06:55:45 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237270574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2237270574 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.3441589680 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 12025736155 ps |
| CPU time | 21.02 seconds |
| Started | Feb 08 06:55:48 PM UTC 25 |
| Finished | Feb 08 06:56:10 PM UTC 25 |
| Peak memory | 245548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441589680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3441589680 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.1264806291 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 66113627 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:56:22 PM UTC 25 |
| Finished | Feb 08 06:56:24 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264806291 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.1264806291 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.2163894356 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 242334585 ps |
| CPU time | 3.78 seconds |
| Started | Feb 08 06:56:08 PM UTC 25 |
| Finished | Feb 08 06:56:13 PM UTC 25 |
| Peak memory | 245508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163894356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2163894356 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.782296024 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 14026433 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:55:56 PM UTC 25 |
| Finished | Feb 08 06:55:58 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782296024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.782296024 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.2243523869 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 99533038591 ps |
| CPU time | 421.05 seconds |
| Started | Feb 08 06:56:12 PM UTC 25 |
| Finished | Feb 08 07:03:19 PM UTC 25 |
| Peak memory | 267952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243523869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2243523869 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.3130641350 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 6080636628 ps |
| CPU time | 73.46 seconds |
| Started | Feb 08 06:56:13 PM UTC 25 |
| Finished | Feb 08 06:57:29 PM UTC 25 |
| Peak memory | 251652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130641350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3130641350 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.823085659 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 11235234829 ps |
| CPU time | 105.79 seconds |
| Started | Feb 08 06:56:20 PM UTC 25 |
| Finished | Feb 08 06:58:08 PM UTC 25 |
| Peak memory | 261884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823085659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.823085659 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.1821960793 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 4512740474 ps |
| CPU time | 17.44 seconds |
| Started | Feb 08 06:56:08 PM UTC 25 |
| Finished | Feb 08 06:56:27 PM UTC 25 |
| Peak memory | 249580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821960793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1821960793 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3693383191 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1021200342 ps |
| CPU time | 11.73 seconds |
| Started | Feb 08 06:56:09 PM UTC 25 |
| Finished | Feb 08 06:56:22 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693383191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.3693383191 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.1466086944 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1212214263 ps |
| CPU time | 4.45 seconds |
| Started | Feb 08 06:56:02 PM UTC 25 |
| Finished | Feb 08 06:56:08 PM UTC 25 |
| Peak memory | 235020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466086944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1466086944 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.1435846185 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3230525554 ps |
| CPU time | 20.54 seconds |
| Started | Feb 08 06:56:02 PM UTC 25 |
| Finished | Feb 08 06:56:24 PM UTC 25 |
| Peak memory | 251528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435846185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1435846185 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3672427997 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3057812517 ps |
| CPU time | 16.67 seconds |
| Started | Feb 08 06:56:02 PM UTC 25 |
| Finished | Feb 08 06:56:20 PM UTC 25 |
| Peak memory | 245556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672427997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3672427997 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.2494753298 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 5391265288 ps |
| CPU time | 30.11 seconds |
| Started | Feb 08 06:56:01 PM UTC 25 |
| Finished | Feb 08 06:56:32 PM UTC 25 |
| Peak memory | 245416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494753298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2494753298 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2410182719 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2120725953 ps |
| CPU time | 6.2 seconds |
| Started | Feb 08 06:56:11 PM UTC 25 |
| Finished | Feb 08 06:56:19 PM UTC 25 |
| Peak memory | 231540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410182719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.2410182719 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.2520007300 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 60868660813 ps |
| CPU time | 165.04 seconds |
| Started | Feb 08 06:56:21 PM UTC 25 |
| Finished | Feb 08 06:59:09 PM UTC 25 |
| Peak memory | 268008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520007300 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.2520007300 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2911765911 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 34915826120 ps |
| CPU time | 65.53 seconds |
| Started | Feb 08 06:55:58 PM UTC 25 |
| Finished | Feb 08 06:57:05 PM UTC 25 |
| Peak memory | 227704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911765911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2911765911 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.849946627 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 10219159427 ps |
| CPU time | 4.98 seconds |
| Started | Feb 08 06:55:57 PM UTC 25 |
| Finished | Feb 08 06:56:03 PM UTC 25 |
| Peak memory | 227616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849946627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.849946627 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.2092107174 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 150441413 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:55:59 PM UTC 25 |
| Finished | Feb 08 06:56:02 PM UTC 25 |
| Peak memory | 226712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092107174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2092107174 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1440142702 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 72787491 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:55:59 PM UTC 25 |
| Finished | Feb 08 06:56:01 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440142702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1440142702 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.1327540487 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2980164892 ps |
| CPU time | 6.94 seconds |
| Started | Feb 08 06:56:03 PM UTC 25 |
| Finished | Feb 08 06:56:11 PM UTC 25 |
| Peak memory | 251524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327540487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1327540487 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.259666112 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 21879951 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:56:49 PM UTC 25 |
| Finished | Feb 08 06:56:51 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259666112 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.259666112 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.690413240 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1210408889 ps |
| CPU time | 5.3 seconds |
| Started | Feb 08 06:56:36 PM UTC 25 |
| Finished | Feb 08 06:56:43 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690413240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.690413240 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.1185936890 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 16717201 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:56:23 PM UTC 25 |
| Finished | Feb 08 06:56:25 PM UTC 25 |
| Peak memory | 215552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185936890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1185936890 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.3102133398 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 61865870430 ps |
| CPU time | 86.73 seconds |
| Started | Feb 08 06:56:43 PM UTC 25 |
| Finished | Feb 08 06:58:12 PM UTC 25 |
| Peak memory | 261804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102133398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3102133398 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.603944600 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 47068195557 ps |
| CPU time | 214.77 seconds |
| Started | Feb 08 06:56:44 PM UTC 25 |
| Finished | Feb 08 07:00:22 PM UTC 25 |
| Peak memory | 278252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603944600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.603944600 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.983882217 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 261235085415 ps |
| CPU time | 519.87 seconds |
| Started | Feb 08 06:56:45 PM UTC 25 |
| Finished | Feb 08 07:05:31 PM UTC 25 |
| Peak memory | 265960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983882217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.983882217 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.2500191034 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 278818546 ps |
| CPU time | 8.86 seconds |
| Started | Feb 08 06:56:37 PM UTC 25 |
| Finished | Feb 08 06:56:48 PM UTC 25 |
| Peak memory | 235032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500191034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2500191034 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3196611213 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1733761288 ps |
| CPU time | 49.82 seconds |
| Started | Feb 08 06:56:40 PM UTC 25 |
| Finished | Feb 08 06:57:31 PM UTC 25 |
| Peak memory | 263788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196611213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3196611213 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.2199614671 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 312223043 ps |
| CPU time | 10.36 seconds |
| Started | Feb 08 06:56:33 PM UTC 25 |
| Finished | Feb 08 06:56:45 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199614671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2199614671 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.1421572310 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5055693595 ps |
| CPU time | 34.03 seconds |
| Started | Feb 08 06:56:33 PM UTC 25 |
| Finished | Feb 08 06:57:09 PM UTC 25 |
| Peak memory | 245384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421572310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1421572310 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2731926017 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 254160933 ps |
| CPU time | 5.2 seconds |
| Started | Feb 08 06:56:32 PM UTC 25 |
| Finished | Feb 08 06:56:38 PM UTC 25 |
| Peak memory | 249456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731926017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.2731926017 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2418953957 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 263484503 ps |
| CPU time | 3.8 seconds |
| Started | Feb 08 06:56:29 PM UTC 25 |
| Finished | Feb 08 06:56:34 PM UTC 25 |
| Peak memory | 245348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418953957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2418953957 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3414358528 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 3811904083 ps |
| CPU time | 11.59 seconds |
| Started | Feb 08 06:56:43 PM UTC 25 |
| Finished | Feb 08 06:56:56 PM UTC 25 |
| Peak memory | 231544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414358528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.3414358528 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3144810175 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 151132817790 ps |
| CPU time | 477.09 seconds |
| Started | Feb 08 06:56:46 PM UTC 25 |
| Finished | Feb 08 07:04:49 PM UTC 25 |
| Peak memory | 284440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144810175 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3144810175 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.3946119704 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 979123721 ps |
| CPU time | 25.52 seconds |
| Started | Feb 08 06:56:25 PM UTC 25 |
| Finished | Feb 08 06:56:52 PM UTC 25 |
| Peak memory | 227516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946119704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3946119704 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3381831307 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1910343977 ps |
| CPU time | 6.32 seconds |
| Started | Feb 08 06:56:25 PM UTC 25 |
| Finished | Feb 08 06:56:32 PM UTC 25 |
| Peak memory | 227552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381831307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3381831307 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.761351924 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 133974142 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:56:28 PM UTC 25 |
| Finished | Feb 08 06:56:31 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761351924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.761351924 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1463232354 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 111190095 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:56:26 PM UTC 25 |
| Finished | Feb 08 06:56:28 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463232354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1463232354 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.1110736320 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 3409077978 ps |
| CPU time | 16.34 seconds |
| Started | Feb 08 06:56:35 PM UTC 25 |
| Finished | Feb 08 06:56:53 PM UTC 25 |
| Peak memory | 245480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110736320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1110736320 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.735340369 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 49139068 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:47:58 PM UTC 25 |
| Finished | Feb 08 06:48:00 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735340369 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.735340369 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2275009975 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 471104317 ps |
| CPU time | 5.66 seconds |
| Started | Feb 08 06:47:55 PM UTC 25 |
| Finished | Feb 08 06:48:02 PM UTC 25 |
| Peak memory | 235068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275009975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2275009975 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1882432641 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 18832766 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:47:51 PM UTC 25 |
| Finished | Feb 08 06:47:54 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882432641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1882432641 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.1012599936 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 264071992 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:47:57 PM UTC 25 |
| Finished | Feb 08 06:47:59 PM UTC 25 |
| Peak memory | 225820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012599936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1012599936 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1694431861 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13857081565 ps |
| CPU time | 72.14 seconds |
| Started | Feb 08 06:47:57 PM UTC 25 |
| Finished | Feb 08 06:49:11 PM UTC 25 |
| Peak memory | 249628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694431861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1694431861 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2343527387 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27591078917 ps |
| CPU time | 141.84 seconds |
| Started | Feb 08 06:47:57 PM UTC 25 |
| Finished | Feb 08 06:50:21 PM UTC 25 |
| Peak memory | 268096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343527387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.2343527387 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.1904988611 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3809259877 ps |
| CPU time | 37.07 seconds |
| Started | Feb 08 06:47:55 PM UTC 25 |
| Finished | Feb 08 06:48:34 PM UTC 25 |
| Peak memory | 261868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904988611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1904988611 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1493678142 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 42503681810 ps |
| CPU time | 305.43 seconds |
| Started | Feb 08 06:47:56 PM UTC 25 |
| Finished | Feb 08 06:53:05 PM UTC 25 |
| Peak memory | 267952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493678142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.1493678142 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.3800785138 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 796721355 ps |
| CPU time | 5.7 seconds |
| Started | Feb 08 06:47:54 PM UTC 25 |
| Finished | Feb 08 06:48:01 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800785138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3800785138 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.1936724574 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1292642951 ps |
| CPU time | 21.51 seconds |
| Started | Feb 08 06:47:55 PM UTC 25 |
| Finished | Feb 08 06:48:18 PM UTC 25 |
| Peak memory | 245328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936724574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1936724574 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2572957515 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 606741114 ps |
| CPU time | 9.53 seconds |
| Started | Feb 08 06:47:54 PM UTC 25 |
| Finished | Feb 08 06:48:05 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572957515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.2572957515 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2545905170 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 35245059459 ps |
| CPU time | 25.78 seconds |
| Started | Feb 08 06:47:54 PM UTC 25 |
| Finished | Feb 08 06:48:21 PM UTC 25 |
| Peak memory | 245016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545905170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2545905170 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3292451201 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1214153218 ps |
| CPU time | 11.36 seconds |
| Started | Feb 08 06:47:56 PM UTC 25 |
| Finished | Feb 08 06:48:08 PM UTC 25 |
| Peak memory | 231468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292451201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.3292451201 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.4071255438 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 251292919 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:47:57 PM UTC 25 |
| Finished | Feb 08 06:48:00 PM UTC 25 |
| Peak memory | 257888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071255438 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4071255438 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2335423417 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 6028126448 ps |
| CPU time | 25.9 seconds |
| Started | Feb 08 06:47:54 PM UTC 25 |
| Finished | Feb 08 06:48:21 PM UTC 25 |
| Peak memory | 231740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335423417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2335423417 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2697894825 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2275843245 ps |
| CPU time | 13.15 seconds |
| Started | Feb 08 06:47:52 PM UTC 25 |
| Finished | Feb 08 06:48:07 PM UTC 25 |
| Peak memory | 227636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697894825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2697894825 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.855517974 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 62607301 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:47:54 PM UTC 25 |
| Finished | Feb 08 06:47:56 PM UTC 25 |
| Peak memory | 226476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855517974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.855517974 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2880484544 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 35245121 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:47:54 PM UTC 25 |
| Finished | Feb 08 06:47:56 PM UTC 25 |
| Peak memory | 214840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880484544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2880484544 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.2759413588 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 8454149993 ps |
| CPU time | 37.12 seconds |
| Started | Feb 08 06:47:55 PM UTC 25 |
| Finished | Feb 08 06:48:34 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759413588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2759413588 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.2815696405 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 28879865 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:57:10 PM UTC 25 |
| Finished | Feb 08 06:57:13 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815696405 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.2815696405 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.2867877879 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1042913487 ps |
| CPU time | 17.71 seconds |
| Started | Feb 08 06:57:00 PM UTC 25 |
| Finished | Feb 08 06:57:19 PM UTC 25 |
| Peak memory | 245384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867877879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2867877879 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.3087325461 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 22004811 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:56:51 PM UTC 25 |
| Finished | Feb 08 06:56:53 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087325461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3087325461 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1346306377 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 12632183 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:57:06 PM UTC 25 |
| Finished | Feb 08 06:57:08 PM UTC 25 |
| Peak memory | 225832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346306377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1346306377 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.483832839 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6839766778 ps |
| CPU time | 134.64 seconds |
| Started | Feb 08 06:57:07 PM UTC 25 |
| Finished | Feb 08 06:59:25 PM UTC 25 |
| Peak memory | 278220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483832839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.483832839 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1697782567 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 37693107740 ps |
| CPU time | 101.78 seconds |
| Started | Feb 08 06:57:07 PM UTC 25 |
| Finished | Feb 08 06:58:51 PM UTC 25 |
| Peak memory | 261836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697782567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.1697782567 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.1897570885 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4826050796 ps |
| CPU time | 13.52 seconds |
| Started | Feb 08 06:57:01 PM UTC 25 |
| Finished | Feb 08 06:57:16 PM UTC 25 |
| Peak memory | 235240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897570885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1897570885 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2392144354 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 860967608 ps |
| CPU time | 19.63 seconds |
| Started | Feb 08 06:57:04 PM UTC 25 |
| Finished | Feb 08 06:57:25 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392144354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2392144354 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.1683385438 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1775004103 ps |
| CPU time | 4.03 seconds |
| Started | Feb 08 06:56:56 PM UTC 25 |
| Finished | Feb 08 06:57:03 PM UTC 25 |
| Peak memory | 235076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683385438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1683385438 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2059289810 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 531323173 ps |
| CPU time | 19.23 seconds |
| Started | Feb 08 06:56:57 PM UTC 25 |
| Finished | Feb 08 06:57:17 PM UTC 25 |
| Peak memory | 251504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059289810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2059289810 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1036433659 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2340295781 ps |
| CPU time | 9 seconds |
| Started | Feb 08 06:56:54 PM UTC 25 |
| Finished | Feb 08 06:57:05 PM UTC 25 |
| Peak memory | 235128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036433659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1036433659 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.1654701266 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 13441782356 ps |
| CPU time | 66.83 seconds |
| Started | Feb 08 06:56:53 PM UTC 25 |
| Finished | Feb 08 06:58:02 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654701266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1654701266 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1763460290 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 14468957579 ps |
| CPU time | 16.07 seconds |
| Started | Feb 08 06:57:06 PM UTC 25 |
| Finished | Feb 08 06:57:24 PM UTC 25 |
| Peak memory | 233940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763460290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.1763460290 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.535475691 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 69598628 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:57:09 PM UTC 25 |
| Finished | Feb 08 06:57:12 PM UTC 25 |
| Peak memory | 215840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535475691 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.535475691 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3491622504 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2896666348 ps |
| CPU time | 12.57 seconds |
| Started | Feb 08 06:56:52 PM UTC 25 |
| Finished | Feb 08 06:57:06 PM UTC 25 |
| Peak memory | 227596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491622504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3491622504 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.2231465530 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 351789958 ps |
| CPU time | 5.22 seconds |
| Started | Feb 08 06:56:52 PM UTC 25 |
| Finished | Feb 08 06:56:59 PM UTC 25 |
| Peak memory | 227556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231465530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2231465530 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.4053375478 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 72119179 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:56:53 PM UTC 25 |
| Finished | Feb 08 06:56:56 PM UTC 25 |
| Peak memory | 215988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053375478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4053375478 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.3713320929 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 157464027 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:56:53 PM UTC 25 |
| Finished | Feb 08 06:56:56 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713320929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3713320929 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.1579021744 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 43985031565 ps |
| CPU time | 37.15 seconds |
| Started | Feb 08 06:56:58 PM UTC 25 |
| Finished | Feb 08 06:57:37 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579021744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1579021744 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.2696225838 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 12598482 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:57:27 PM UTC 25 |
| Finished | Feb 08 06:57:30 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696225838 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.2696225838 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4272987378 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2848281489 ps |
| CPU time | 8.57 seconds |
| Started | Feb 08 06:57:23 PM UTC 25 |
| Finished | Feb 08 06:57:33 PM UTC 25 |
| Peak memory | 235180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272987378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4272987378 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.43910005 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 42976724 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:57:13 PM UTC 25 |
| Finished | Feb 08 06:57:16 PM UTC 25 |
| Peak memory | 215488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43910005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.43910005 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.3386713354 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3968337321 ps |
| CPU time | 14.73 seconds |
| Started | Feb 08 06:57:25 PM UTC 25 |
| Finished | Feb 08 06:57:41 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386713354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3386713354 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.801707186 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2533051237 ps |
| CPU time | 51.93 seconds |
| Started | Feb 08 06:57:26 PM UTC 25 |
| Finished | Feb 08 06:58:20 PM UTC 25 |
| Peak memory | 261916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801707186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.801707186 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2085618381 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 199443355 ps |
| CPU time | 7.41 seconds |
| Started | Feb 08 06:57:26 PM UTC 25 |
| Finished | Feb 08 06:57:35 PM UTC 25 |
| Peak memory | 235172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085618381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.2085618381 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.1547385558 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 672812900 ps |
| CPU time | 12.08 seconds |
| Started | Feb 08 06:57:24 PM UTC 25 |
| Finished | Feb 08 06:57:37 PM UTC 25 |
| Peak memory | 245300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547385558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1547385558 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1905718438 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 10673781 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:57:25 PM UTC 25 |
| Finished | Feb 08 06:57:27 PM UTC 25 |
| Peak memory | 225832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905718438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.1905718438 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.2546975251 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1703168524 ps |
| CPU time | 5.3 seconds |
| Started | Feb 08 06:57:18 PM UTC 25 |
| Finished | Feb 08 06:57:24 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546975251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2546975251 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.4220744196 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 275874355 ps |
| CPU time | 4.82 seconds |
| Started | Feb 08 06:57:19 PM UTC 25 |
| Finished | Feb 08 06:57:25 PM UTC 25 |
| Peak memory | 245384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220744196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4220744196 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2213564979 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 156377038 ps |
| CPU time | 4.46 seconds |
| Started | Feb 08 06:57:17 PM UTC 25 |
| Finished | Feb 08 06:57:23 PM UTC 25 |
| Peak memory | 245300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213564979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.2213564979 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.843459243 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1963185641 ps |
| CPU time | 5.82 seconds |
| Started | Feb 08 06:57:17 PM UTC 25 |
| Finished | Feb 08 06:57:24 PM UTC 25 |
| Peak memory | 235256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843459243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.843459243 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1681683923 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 716051340 ps |
| CPU time | 10.54 seconds |
| Started | Feb 08 06:57:25 PM UTC 25 |
| Finished | Feb 08 06:57:37 PM UTC 25 |
| Peak memory | 233524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681683923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1681683923 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.3308233579 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 43671090948 ps |
| CPU time | 418.7 seconds |
| Started | Feb 08 06:57:26 PM UTC 25 |
| Finished | Feb 08 07:04:31 PM UTC 25 |
| Peak memory | 278252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308233579 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.3308233579 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2248465567 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1000540320 ps |
| CPU time | 16.53 seconds |
| Started | Feb 08 06:57:14 PM UTC 25 |
| Finished | Feb 08 06:57:33 PM UTC 25 |
| Peak memory | 227516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248465567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2248465567 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.3682740575 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 8117820086 ps |
| CPU time | 11.64 seconds |
| Started | Feb 08 06:57:13 PM UTC 25 |
| Finished | Feb 08 06:57:26 PM UTC 25 |
| Peak memory | 227624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682740575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3682740575 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.2609367307 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 624203468 ps |
| CPU time | 7.49 seconds |
| Started | Feb 08 06:57:17 PM UTC 25 |
| Finished | Feb 08 06:57:25 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609367307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2609367307 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.4231689445 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 76101631 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:57:15 PM UTC 25 |
| Finished | Feb 08 06:57:18 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231689445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4231689445 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.1355757777 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 314640323 ps |
| CPU time | 3.24 seconds |
| Started | Feb 08 06:57:20 PM UTC 25 |
| Finished | Feb 08 06:57:24 PM UTC 25 |
| Peak memory | 245512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355757777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1355757777 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.1601221473 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 14436401 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:57:43 PM UTC 25 |
| Finished | Feb 08 06:57:45 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601221473 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.1601221473 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.1180449910 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 31796482 ps |
| CPU time | 2.88 seconds |
| Started | Feb 08 06:57:36 PM UTC 25 |
| Finished | Feb 08 06:57:40 PM UTC 25 |
| Peak memory | 234472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180449910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1180449910 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.958975788 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 18984203 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:57:29 PM UTC 25 |
| Finished | Feb 08 06:57:31 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958975788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.958975788 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.2791322816 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2808362901 ps |
| CPU time | 21.85 seconds |
| Started | Feb 08 06:57:38 PM UTC 25 |
| Finished | Feb 08 06:58:02 PM UTC 25 |
| Peak memory | 247552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791322816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2791322816 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3360536944 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3420327266 ps |
| CPU time | 45.54 seconds |
| Started | Feb 08 06:57:40 PM UTC 25 |
| Finished | Feb 08 06:58:28 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360536944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3360536944 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1913029317 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 24764687183 ps |
| CPU time | 88.85 seconds |
| Started | Feb 08 06:57:42 PM UTC 25 |
| Finished | Feb 08 06:59:13 PM UTC 25 |
| Peak memory | 234876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913029317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1913029317 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.1108218128 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 171871065 ps |
| CPU time | 3.73 seconds |
| Started | Feb 08 06:57:37 PM UTC 25 |
| Finished | Feb 08 06:57:42 PM UTC 25 |
| Peak memory | 235116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108218128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1108218128 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.608187526 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1512391837 ps |
| CPU time | 59.28 seconds |
| Started | Feb 08 06:57:38 PM UTC 25 |
| Finished | Feb 08 06:58:39 PM UTC 25 |
| Peak memory | 251500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608187526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.608187526 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.779508417 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 860363620 ps |
| CPU time | 7.28 seconds |
| Started | Feb 08 06:57:34 PM UTC 25 |
| Finished | Feb 08 06:57:43 PM UTC 25 |
| Peak memory | 245440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779508417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.779508417 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.631454556 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 25028747433 ps |
| CPU time | 62.17 seconds |
| Started | Feb 08 06:57:34 PM UTC 25 |
| Finished | Feb 08 06:58:38 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631454556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.631454556 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1979909674 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 745451547 ps |
| CPU time | 9.08 seconds |
| Started | Feb 08 06:57:33 PM UTC 25 |
| Finished | Feb 08 06:57:43 PM UTC 25 |
| Peak memory | 235176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979909674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.1979909674 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.92672138 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2853452293 ps |
| CPU time | 12.9 seconds |
| Started | Feb 08 06:57:32 PM UTC 25 |
| Finished | Feb 08 06:57:46 PM UTC 25 |
| Peak memory | 245428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92672138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.92672138 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2152057477 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 81106128 ps |
| CPU time | 5.28 seconds |
| Started | Feb 08 06:57:38 PM UTC 25 |
| Finished | Feb 08 06:57:45 PM UTC 25 |
| Peak memory | 233948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152057477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.2152057477 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.3468212541 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 206895356393 ps |
| CPU time | 210.25 seconds |
| Started | Feb 08 06:57:42 PM UTC 25 |
| Finished | Feb 08 07:01:15 PM UTC 25 |
| Peak memory | 261500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468212541 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.3468212541 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.990475815 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1204252253 ps |
| CPU time | 23.46 seconds |
| Started | Feb 08 06:57:31 PM UTC 25 |
| Finished | Feb 08 06:57:55 PM UTC 25 |
| Peak memory | 227504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990475815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.990475815 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3029569625 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 15684998 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:57:30 PM UTC 25 |
| Finished | Feb 08 06:57:32 PM UTC 25 |
| Peak memory | 215952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029569625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3029569625 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.2560936459 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2326994305 ps |
| CPU time | 4.4 seconds |
| Started | Feb 08 06:57:32 PM UTC 25 |
| Finished | Feb 08 06:57:37 PM UTC 25 |
| Peak memory | 227572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560936459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2560936459 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2199538551 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 17412843 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:57:31 PM UTC 25 |
| Finished | Feb 08 06:57:33 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199538551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2199538551 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.2096946694 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 9301706884 ps |
| CPU time | 31.92 seconds |
| Started | Feb 08 06:57:34 PM UTC 25 |
| Finished | Feb 08 06:58:07 PM UTC 25 |
| Peak memory | 261816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096946694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2096946694 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.1814920885 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 16586395 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:58:03 PM UTC 25 |
| Finished | Feb 08 06:58:05 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814920885 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.1814920885 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.1070405856 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 14819567 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:57:44 PM UTC 25 |
| Finished | Feb 08 06:57:46 PM UTC 25 |
| Peak memory | 215552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070405856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1070405856 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.4276038210 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 21165355774 ps |
| CPU time | 221.08 seconds |
| Started | Feb 08 06:57:58 PM UTC 25 |
| Finished | Feb 08 07:01:42 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276038210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4276038210 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.321514708 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2936261108 ps |
| CPU time | 78.29 seconds |
| Started | Feb 08 06:57:58 PM UTC 25 |
| Finished | Feb 08 06:59:18 PM UTC 25 |
| Peak memory | 261852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321514708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.321514708 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1523817703 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 10696664348 ps |
| CPU time | 121.42 seconds |
| Started | Feb 08 06:58:00 PM UTC 25 |
| Finished | Feb 08 07:00:03 PM UTC 25 |
| Peak memory | 251604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523817703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.1523817703 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2321787112 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 14735959739 ps |
| CPU time | 53.33 seconds |
| Started | Feb 08 06:57:55 PM UTC 25 |
| Finished | Feb 08 06:58:50 PM UTC 25 |
| Peak memory | 251504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321787112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2321787112 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.401346262 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 41208315641 ps |
| CPU time | 117.71 seconds |
| Started | Feb 08 06:57:55 PM UTC 25 |
| Finished | Feb 08 06:59:56 PM UTC 25 |
| Peak memory | 265904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401346262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.401346262 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.2112167221 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 771211304 ps |
| CPU time | 8.72 seconds |
| Started | Feb 08 06:57:49 PM UTC 25 |
| Finished | Feb 08 06:57:59 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112167221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2112167221 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3630554929 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 7697395135 ps |
| CPU time | 65.06 seconds |
| Started | Feb 08 06:57:50 PM UTC 25 |
| Finished | Feb 08 06:58:57 PM UTC 25 |
| Peak memory | 245432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630554929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3630554929 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.359642851 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 205511691 ps |
| CPU time | 6.49 seconds |
| Started | Feb 08 06:57:47 PM UTC 25 |
| Finished | Feb 08 06:57:55 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359642851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.359642851 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3736292957 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 792699906 ps |
| CPU time | 6.49 seconds |
| Started | Feb 08 06:57:47 PM UTC 25 |
| Finished | Feb 08 06:57:55 PM UTC 25 |
| Peak memory | 235060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736292957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3736292957 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2189326688 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 104503143 ps |
| CPU time | 5.23 seconds |
| Started | Feb 08 06:57:56 PM UTC 25 |
| Finished | Feb 08 06:58:03 PM UTC 25 |
| Peak memory | 233676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189326688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.2189326688 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1949931240 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 68361685388 ps |
| CPU time | 118.54 seconds |
| Started | Feb 08 06:58:02 PM UTC 25 |
| Finished | Feb 08 07:00:03 PM UTC 25 |
| Peak memory | 268036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949931240 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1949931240 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.3584749046 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 4822813857 ps |
| CPU time | 25.54 seconds |
| Started | Feb 08 06:57:46 PM UTC 25 |
| Finished | Feb 08 06:58:13 PM UTC 25 |
| Peak memory | 227524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584749046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3584749046 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2959733012 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2139253811 ps |
| CPU time | 6.67 seconds |
| Started | Feb 08 06:57:44 PM UTC 25 |
| Finished | Feb 08 06:57:52 PM UTC 25 |
| Peak memory | 227564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959733012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2959733012 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.597531764 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 488813105 ps |
| CPU time | 2.71 seconds |
| Started | Feb 08 06:57:46 PM UTC 25 |
| Finished | Feb 08 06:57:50 PM UTC 25 |
| Peak memory | 227524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597531764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.597531764 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1367410482 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 23938473 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:57:46 PM UTC 25 |
| Finished | Feb 08 06:57:48 PM UTC 25 |
| Peak memory | 215908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367410482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1367410482 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.584244426 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 492558909 ps |
| CPU time | 5.01 seconds |
| Started | Feb 08 06:57:50 PM UTC 25 |
| Finished | Feb 08 06:57:56 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584244426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.584244426 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.3284769312 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 20089822 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:58:18 PM UTC 25 |
| Finished | Feb 08 06:58:20 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284769312 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.3284769312 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3430404273 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 637328129 ps |
| CPU time | 5.39 seconds |
| Started | Feb 08 06:58:10 PM UTC 25 |
| Finished | Feb 08 06:58:17 PM UTC 25 |
| Peak memory | 245428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430404273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3430404273 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.3048364811 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 44694171 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:58:03 PM UTC 25 |
| Finished | Feb 08 06:58:05 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048364811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3048364811 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.4294474764 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 130700424899 ps |
| CPU time | 91.78 seconds |
| Started | Feb 08 06:58:15 PM UTC 25 |
| Finished | Feb 08 06:59:49 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294474764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4294474764 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.716320929 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 258144509359 ps |
| CPU time | 653.93 seconds |
| Started | Feb 08 06:58:15 PM UTC 25 |
| Finished | Feb 08 07:09:16 PM UTC 25 |
| Peak memory | 278228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716320929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.716320929 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2908217881 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5038247283 ps |
| CPU time | 36.8 seconds |
| Started | Feb 08 06:58:16 PM UTC 25 |
| Finished | Feb 08 06:58:54 PM UTC 25 |
| Peak memory | 263796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908217881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.2908217881 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.898312245 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3959695576 ps |
| CPU time | 9.54 seconds |
| Started | Feb 08 06:58:13 PM UTC 25 |
| Finished | Feb 08 06:58:23 PM UTC 25 |
| Peak memory | 245428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898312245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.898312245 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.536980094 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 15886818309 ps |
| CPU time | 61.36 seconds |
| Started | Feb 08 06:58:14 PM UTC 25 |
| Finished | Feb 08 06:59:17 PM UTC 25 |
| Peak memory | 265920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536980094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.536980094 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.549071524 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 34036549 ps |
| CPU time | 3.28 seconds |
| Started | Feb 08 06:58:09 PM UTC 25 |
| Finished | Feb 08 06:58:14 PM UTC 25 |
| Peak memory | 244932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549071524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.549071524 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.1470716782 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 110864872 ps |
| CPU time | 2.72 seconds |
| Started | Feb 08 06:58:09 PM UTC 25 |
| Finished | Feb 08 06:58:13 PM UTC 25 |
| Peak memory | 245128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470716782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1470716782 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1346455933 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 208065614 ps |
| CPU time | 4.97 seconds |
| Started | Feb 08 06:58:08 PM UTC 25 |
| Finished | Feb 08 06:58:14 PM UTC 25 |
| Peak memory | 235108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346455933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.1346455933 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1030638803 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3141126771 ps |
| CPU time | 14.96 seconds |
| Started | Feb 08 06:58:08 PM UTC 25 |
| Finished | Feb 08 06:58:24 PM UTC 25 |
| Peak memory | 251560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030638803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1030638803 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.1976484562 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1956085488 ps |
| CPU time | 10.49 seconds |
| Started | Feb 08 06:58:14 PM UTC 25 |
| Finished | Feb 08 06:58:25 PM UTC 25 |
| Peak memory | 231416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976484562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.1976484562 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.3673676150 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 51319364132 ps |
| CPU time | 248.79 seconds |
| Started | Feb 08 06:58:18 PM UTC 25 |
| Finished | Feb 08 07:02:30 PM UTC 25 |
| Peak memory | 261844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673676150 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.3673676150 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.2049825994 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 7122828318 ps |
| CPU time | 44.14 seconds |
| Started | Feb 08 06:58:05 PM UTC 25 |
| Finished | Feb 08 06:58:51 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049825994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2049825994 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3093878662 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 145928845 ps |
| CPU time | 2.18 seconds |
| Started | Feb 08 06:58:04 PM UTC 25 |
| Finished | Feb 08 06:58:07 PM UTC 25 |
| Peak memory | 217108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093878662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3093878662 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.2228931768 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 110932073 ps |
| CPU time | 2.43 seconds |
| Started | Feb 08 06:58:06 PM UTC 25 |
| Finished | Feb 08 06:58:10 PM UTC 25 |
| Peak memory | 227564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228931768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2228931768 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1753556194 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 29078834 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:58:06 PM UTC 25 |
| Finished | Feb 08 06:58:08 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753556194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1753556194 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.4217266049 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 333350918 ps |
| CPU time | 3.33 seconds |
| Started | Feb 08 06:58:10 PM UTC 25 |
| Finished | Feb 08 06:58:15 PM UTC 25 |
| Peak memory | 235116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217266049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4217266049 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2568451564 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 20250257 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:58:42 PM UTC 25 |
| Finished | Feb 08 06:58:44 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568451564 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2568451564 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2841323633 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 189106267 ps |
| CPU time | 3.4 seconds |
| Started | Feb 08 06:58:32 PM UTC 25 |
| Finished | Feb 08 06:58:36 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841323633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2841323633 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.2414075803 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 19632632 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:58:21 PM UTC 25 |
| Finished | Feb 08 06:58:23 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414075803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2414075803 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.3702811396 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 19604722144 ps |
| CPU time | 148.67 seconds |
| Started | Feb 08 06:58:38 PM UTC 25 |
| Finished | Feb 08 07:01:09 PM UTC 25 |
| Peak memory | 268032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702811396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3702811396 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1680892504 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 11376794485 ps |
| CPU time | 148.35 seconds |
| Started | Feb 08 06:58:39 PM UTC 25 |
| Finished | Feb 08 07:01:10 PM UTC 25 |
| Peak memory | 278212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680892504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1680892504 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1308082674 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1836365664 ps |
| CPU time | 39.71 seconds |
| Started | Feb 08 06:58:40 PM UTC 25 |
| Finished | Feb 08 06:59:21 PM UTC 25 |
| Peak memory | 261792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308082674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1308082674 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2830970749 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 13584103623 ps |
| CPU time | 45.64 seconds |
| Started | Feb 08 06:58:33 PM UTC 25 |
| Finished | Feb 08 06:59:20 PM UTC 25 |
| Peak memory | 251532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830970749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2830970749 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3408432944 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 158181871546 ps |
| CPU time | 396.91 seconds |
| Started | Feb 08 06:58:33 PM UTC 25 |
| Finished | Feb 08 07:05:15 PM UTC 25 |
| Peak memory | 278168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408432944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.3408432944 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3528073749 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 543153338 ps |
| CPU time | 11.36 seconds |
| Started | Feb 08 06:58:28 PM UTC 25 |
| Finished | Feb 08 06:58:41 PM UTC 25 |
| Peak memory | 245380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528073749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3528073749 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.2753001695 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3078341359 ps |
| CPU time | 49.37 seconds |
| Started | Feb 08 06:58:30 PM UTC 25 |
| Finished | Feb 08 06:59:21 PM UTC 25 |
| Peak memory | 245448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753001695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2753001695 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.457297924 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1682176108 ps |
| CPU time | 18.44 seconds |
| Started | Feb 08 06:58:27 PM UTC 25 |
| Finished | Feb 08 06:58:47 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457297924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.457297924 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2692358348 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4483004980 ps |
| CPU time | 15.15 seconds |
| Started | Feb 08 06:58:26 PM UTC 25 |
| Finished | Feb 08 06:58:43 PM UTC 25 |
| Peak memory | 245496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692358348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2692358348 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1003099651 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 442177028 ps |
| CPU time | 5.04 seconds |
| Started | Feb 08 06:58:37 PM UTC 25 |
| Finished | Feb 08 06:58:43 PM UTC 25 |
| Peak memory | 233524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003099651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1003099651 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2947001964 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 25540380261 ps |
| CPU time | 124.78 seconds |
| Started | Feb 08 06:58:41 PM UTC 25 |
| Finished | Feb 08 07:00:49 PM UTC 25 |
| Peak memory | 268092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947001964 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2947001964 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.2833400224 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1999592905 ps |
| CPU time | 5.16 seconds |
| Started | Feb 08 06:58:24 PM UTC 25 |
| Finished | Feb 08 06:58:31 PM UTC 25 |
| Peak memory | 227476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833400224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2833400224 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3017244881 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2302658347 ps |
| CPU time | 14.61 seconds |
| Started | Feb 08 06:58:21 PM UTC 25 |
| Finished | Feb 08 06:58:37 PM UTC 25 |
| Peak memory | 227760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017244881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3017244881 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.3681174522 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 405429408 ps |
| CPU time | 5.39 seconds |
| Started | Feb 08 06:58:25 PM UTC 25 |
| Finished | Feb 08 06:58:32 PM UTC 25 |
| Peak memory | 227564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681174522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3681174522 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.1896525691 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 12944506 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:58:24 PM UTC 25 |
| Finished | Feb 08 06:58:26 PM UTC 25 |
| Peak memory | 216056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896525691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1896525691 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.1517577229 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1061789351 ps |
| CPU time | 8.39 seconds |
| Started | Feb 08 06:58:31 PM UTC 25 |
| Finished | Feb 08 06:58:40 PM UTC 25 |
| Peak memory | 235036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517577229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1517577229 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.300714335 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 22217952 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:59:10 PM UTC 25 |
| Finished | Feb 08 06:59:12 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300714335 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.300714335 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2854172487 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 15584975760 ps |
| CPU time | 17.29 seconds |
| Started | Feb 08 06:58:55 PM UTC 25 |
| Finished | Feb 08 06:59:13 PM UTC 25 |
| Peak memory | 245384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854172487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2854172487 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.1662236282 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 56032035 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:58:43 PM UTC 25 |
| Finished | Feb 08 06:58:46 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662236282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1662236282 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.81455273 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3250750544 ps |
| CPU time | 53.7 seconds |
| Started | Feb 08 06:59:07 PM UTC 25 |
| Finished | Feb 08 07:00:02 PM UTC 25 |
| Peak memory | 251584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81455273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.81455273 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.757158092 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4056348106 ps |
| CPU time | 77.75 seconds |
| Started | Feb 08 06:59:08 PM UTC 25 |
| Finished | Feb 08 07:00:27 PM UTC 25 |
| Peak memory | 265980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757158092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.757158092 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.1790132995 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5641942759 ps |
| CPU time | 40.86 seconds |
| Started | Feb 08 06:59:10 PM UTC 25 |
| Finished | Feb 08 06:59:52 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790132995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.1790132995 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.3216184256 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1975090233 ps |
| CPU time | 13.74 seconds |
| Started | Feb 08 06:58:58 PM UTC 25 |
| Finished | Feb 08 06:59:13 PM UTC 25 |
| Peak memory | 247424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216184256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3216184256 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2639569526 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 15432347516 ps |
| CPU time | 104.16 seconds |
| Started | Feb 08 06:58:58 PM UTC 25 |
| Finished | Feb 08 07:00:44 PM UTC 25 |
| Peak memory | 267948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639569526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.2639569526 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.298588486 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1124512349 ps |
| CPU time | 16.22 seconds |
| Started | Feb 08 06:58:52 PM UTC 25 |
| Finished | Feb 08 06:59:09 PM UTC 25 |
| Peak memory | 244540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298588486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.298588486 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.2501478944 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 13995383920 ps |
| CPU time | 31.71 seconds |
| Started | Feb 08 06:58:52 PM UTC 25 |
| Finished | Feb 08 06:59:25 PM UTC 25 |
| Peak memory | 241408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501478944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2501478944 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1760684935 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 11163002802 ps |
| CPU time | 49.71 seconds |
| Started | Feb 08 06:58:51 PM UTC 25 |
| Finished | Feb 08 06:59:42 PM UTC 25 |
| Peak memory | 245444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760684935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.1760684935 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.1184432643 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2228648101 ps |
| CPU time | 13.38 seconds |
| Started | Feb 08 06:58:50 PM UTC 25 |
| Finished | Feb 08 06:59:04 PM UTC 25 |
| Peak memory | 251568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184432643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1184432643 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1569890810 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 389395355 ps |
| CPU time | 4.71 seconds |
| Started | Feb 08 06:59:05 PM UTC 25 |
| Finished | Feb 08 06:59:11 PM UTC 25 |
| Peak memory | 229368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569890810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.1569890810 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3389185855 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 52608417381 ps |
| CPU time | 590.82 seconds |
| Started | Feb 08 06:59:10 PM UTC 25 |
| Finished | Feb 08 07:09:08 PM UTC 25 |
| Peak memory | 294644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389185855 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.3389185855 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.195437327 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 2644495473 ps |
| CPU time | 22.39 seconds |
| Started | Feb 08 06:58:45 PM UTC 25 |
| Finished | Feb 08 06:59:09 PM UTC 25 |
| Peak memory | 227572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195437327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.195437327 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.685436928 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 11430513832 ps |
| CPU time | 20.99 seconds |
| Started | Feb 08 06:58:44 PM UTC 25 |
| Finished | Feb 08 06:59:07 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685436928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.685436928 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.492973470 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 162353139 ps |
| CPU time | 2.41 seconds |
| Started | Feb 08 06:58:48 PM UTC 25 |
| Finished | Feb 08 06:58:51 PM UTC 25 |
| Peak memory | 227492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492973470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.492973470 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.1677592372 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 147328969 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:58:46 PM UTC 25 |
| Finished | Feb 08 06:58:49 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677592372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1677592372 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1335878817 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5342444235 ps |
| CPU time | 19.6 seconds |
| Started | Feb 08 06:58:52 PM UTC 25 |
| Finished | Feb 08 06:59:13 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335878817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1335878817 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.1157745835 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 57087259 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:59:25 PM UTC 25 |
| Finished | Feb 08 06:59:27 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157745835 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.1157745835 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3418262418 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 194812511 ps |
| CPU time | 2.99 seconds |
| Started | Feb 08 06:59:18 PM UTC 25 |
| Finished | Feb 08 06:59:22 PM UTC 25 |
| Peak memory | 244980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418262418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3418262418 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.4264849207 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 94069027 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:59:12 PM UTC 25 |
| Finished | Feb 08 06:59:14 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264849207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4264849207 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.4174885503 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 20149200493 ps |
| CPU time | 139.46 seconds |
| Started | Feb 08 06:59:22 PM UTC 25 |
| Finished | Feb 08 07:01:44 PM UTC 25 |
| Peak memory | 278260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174885503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4174885503 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3190236711 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 8009926887 ps |
| CPU time | 54.66 seconds |
| Started | Feb 08 06:59:22 PM UTC 25 |
| Finished | Feb 08 07:00:18 PM UTC 25 |
| Peak memory | 261856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190236711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3190236711 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.300484626 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 105359712225 ps |
| CPU time | 178.63 seconds |
| Started | Feb 08 06:59:22 PM UTC 25 |
| Finished | Feb 08 07:02:23 PM UTC 25 |
| Peak memory | 263932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300484626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.300484626 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.3806899510 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2432982916 ps |
| CPU time | 27.94 seconds |
| Started | Feb 08 06:59:19 PM UTC 25 |
| Finished | Feb 08 06:59:48 PM UTC 25 |
| Peak memory | 251640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806899510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3806899510 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2375201352 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1402014828 ps |
| CPU time | 46.64 seconds |
| Started | Feb 08 06:59:20 PM UTC 25 |
| Finished | Feb 08 07:00:08 PM UTC 25 |
| Peak memory | 267884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375201352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.2375201352 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.3549680083 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 696880133 ps |
| CPU time | 9.57 seconds |
| Started | Feb 08 06:59:15 PM UTC 25 |
| Finished | Feb 08 06:59:26 PM UTC 25 |
| Peak memory | 245504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549680083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3549680083 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1038191835 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 257940586113 ps |
| CPU time | 141.17 seconds |
| Started | Feb 08 06:59:16 PM UTC 25 |
| Finished | Feb 08 07:01:40 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038191835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1038191835 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2871774876 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 24547038158 ps |
| CPU time | 18.02 seconds |
| Started | Feb 08 06:59:14 PM UTC 25 |
| Finished | Feb 08 06:59:34 PM UTC 25 |
| Peak memory | 234912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871774876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2871774876 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1530174295 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 22733860198 ps |
| CPU time | 21.74 seconds |
| Started | Feb 08 06:59:14 PM UTC 25 |
| Finished | Feb 08 06:59:37 PM UTC 25 |
| Peak memory | 245152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530174295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1530174295 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.3616067077 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 927662841 ps |
| CPU time | 7.77 seconds |
| Started | Feb 08 06:59:21 PM UTC 25 |
| Finished | Feb 08 06:59:30 PM UTC 25 |
| Peak memory | 231412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616067077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.3616067077 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.3638234989 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 136064575591 ps |
| CPU time | 480.93 seconds |
| Started | Feb 08 06:59:23 PM UTC 25 |
| Finished | Feb 08 07:07:30 PM UTC 25 |
| Peak memory | 280376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638234989 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.3638234989 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.912269521 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 16550052470 ps |
| CPU time | 28.62 seconds |
| Started | Feb 08 06:59:13 PM UTC 25 |
| Finished | Feb 08 06:59:43 PM UTC 25 |
| Peak memory | 227760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912269521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.912269521 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.1153571648 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 286385860 ps |
| CPU time | 4.86 seconds |
| Started | Feb 08 06:59:13 PM UTC 25 |
| Finished | Feb 08 06:59:19 PM UTC 25 |
| Peak memory | 227508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153571648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1153571648 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.4154150457 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 18450299 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:59:13 PM UTC 25 |
| Finished | Feb 08 06:59:16 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154150457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4154150457 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2951213410 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 19982531 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:59:13 PM UTC 25 |
| Finished | Feb 08 06:59:15 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951213410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2951213410 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.2321665721 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 134532002 ps |
| CPU time | 3.5 seconds |
| Started | Feb 08 06:59:17 PM UTC 25 |
| Finished | Feb 08 06:59:21 PM UTC 25 |
| Peak memory | 245352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321665721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2321665721 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2182927231 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 12363968 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:59:52 PM UTC 25 |
| Finished | Feb 08 06:59:54 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182927231 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.2182927231 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2540205111 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 2033269887 ps |
| CPU time | 7.29 seconds |
| Started | Feb 08 06:59:38 PM UTC 25 |
| Finished | Feb 08 06:59:46 PM UTC 25 |
| Peak memory | 245304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540205111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2540205111 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.3061690050 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 15835472 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:59:26 PM UTC 25 |
| Finished | Feb 08 06:59:28 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061690050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3061690050 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3393265084 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2385318845 ps |
| CPU time | 39.62 seconds |
| Started | Feb 08 06:59:49 PM UTC 25 |
| Finished | Feb 08 07:00:30 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393265084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3393265084 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3598144228 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 21909489090 ps |
| CPU time | 124.82 seconds |
| Started | Feb 08 06:59:50 PM UTC 25 |
| Finished | Feb 08 07:01:57 PM UTC 25 |
| Peak memory | 261820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598144228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3598144228 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3703363706 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 10569796618 ps |
| CPU time | 33.74 seconds |
| Started | Feb 08 06:59:50 PM UTC 25 |
| Finished | Feb 08 07:00:25 PM UTC 25 |
| Peak memory | 266032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703363706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.3703363706 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.2580205456 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 399460535 ps |
| CPU time | 9.83 seconds |
| Started | Feb 08 06:59:41 PM UTC 25 |
| Finished | Feb 08 06:59:52 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580205456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2580205456 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3809556518 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 10360776058 ps |
| CPU time | 71.28 seconds |
| Started | Feb 08 06:59:43 PM UTC 25 |
| Finished | Feb 08 07:00:56 PM UTC 25 |
| Peak memory | 263912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809556518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.3809556518 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.2294705907 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1922858612 ps |
| CPU time | 21.68 seconds |
| Started | Feb 08 06:59:33 PM UTC 25 |
| Finished | Feb 08 06:59:56 PM UTC 25 |
| Peak memory | 235060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294705907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2294705907 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3876323101 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 11741983228 ps |
| CPU time | 29.7 seconds |
| Started | Feb 08 06:59:35 PM UTC 25 |
| Finished | Feb 08 07:00:06 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876323101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3876323101 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2709519027 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 928828361 ps |
| CPU time | 14.58 seconds |
| Started | Feb 08 06:59:33 PM UTC 25 |
| Finished | Feb 08 06:59:48 PM UTC 25 |
| Peak memory | 245428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709519027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.2709519027 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.584109863 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 208334308 ps |
| CPU time | 3.75 seconds |
| Started | Feb 08 06:59:31 PM UTC 25 |
| Finished | Feb 08 06:59:36 PM UTC 25 |
| Peak memory | 245316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584109863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.584109863 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.997447784 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 118703374 ps |
| CPU time | 6.08 seconds |
| Started | Feb 08 06:59:44 PM UTC 25 |
| Finished | Feb 08 06:59:51 PM UTC 25 |
| Peak memory | 233788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997447784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.997447784 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1787151315 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 447043557 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:59:50 PM UTC 25 |
| Finished | Feb 08 06:59:53 PM UTC 25 |
| Peak memory | 215972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787151315 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.1787151315 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1466747581 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 6698425346 ps |
| CPU time | 34.12 seconds |
| Started | Feb 08 06:59:28 PM UTC 25 |
| Finished | Feb 08 07:00:04 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466747581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1466747581 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1951406552 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 21329581361 ps |
| CPU time | 27.94 seconds |
| Started | Feb 08 06:59:27 PM UTC 25 |
| Finished | Feb 08 06:59:56 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951406552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1951406552 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.330737868 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 915660614 ps |
| CPU time | 8.61 seconds |
| Started | Feb 08 06:59:30 PM UTC 25 |
| Finished | Feb 08 06:59:40 PM UTC 25 |
| Peak memory | 227508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330737868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.330737868 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3592194910 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 23645433 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:59:29 PM UTC 25 |
| Finished | Feb 08 06:59:32 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592194910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3592194910 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.2405420458 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 404965864 ps |
| CPU time | 14.09 seconds |
| Started | Feb 08 06:59:37 PM UTC 25 |
| Finished | Feb 08 06:59:52 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405420458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2405420458 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.2380615644 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 12888093 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:22 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380615644 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.2380615644 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.795381831 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 214786026 ps |
| CPU time | 4.37 seconds |
| Started | Feb 08 07:00:01 PM UTC 25 |
| Finished | Feb 08 07:00:23 PM UTC 25 |
| Peak memory | 235132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795381831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.795381831 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.3573208634 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 15511810 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:59:54 PM UTC 25 |
| Finished | Feb 08 06:59:56 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573208634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3573208634 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2853802128 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 64083378640 ps |
| CPU time | 108.46 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:02:10 PM UTC 25 |
| Peak memory | 261900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853802128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2853802128 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1645021422 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 212264123450 ps |
| CPU time | 458.9 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:08:04 PM UTC 25 |
| Peak memory | 276176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645021422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.1645021422 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.257428712 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1710556408 ps |
| CPU time | 11.1 seconds |
| Started | Feb 08 07:00:03 PM UTC 25 |
| Finished | Feb 08 07:00:31 PM UTC 25 |
| Peak memory | 235076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257428712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.257428712 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.720320020 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 31565570874 ps |
| CPU time | 299.62 seconds |
| Started | Feb 08 07:00:09 PM UTC 25 |
| Finished | Feb 08 07:05:22 PM UTC 25 |
| Peak memory | 284352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720320020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.720320020 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.533549099 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 6048790621 ps |
| CPU time | 17.19 seconds |
| Started | Feb 08 06:59:58 PM UTC 25 |
| Finished | Feb 08 07:00:17 PM UTC 25 |
| Peak memory | 235204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533549099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.533549099 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.4087828750 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 12054516428 ps |
| CPU time | 68.37 seconds |
| Started | Feb 08 06:59:58 PM UTC 25 |
| Finished | Feb 08 07:01:09 PM UTC 25 |
| Peak memory | 245448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087828750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4087828750 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3062029544 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 571488289 ps |
| CPU time | 6.27 seconds |
| Started | Feb 08 06:59:56 PM UTC 25 |
| Finished | Feb 08 07:00:04 PM UTC 25 |
| Peak memory | 235116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062029544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.3062029544 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3639123399 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 563276488 ps |
| CPU time | 6.88 seconds |
| Started | Feb 08 06:59:56 PM UTC 25 |
| Finished | Feb 08 07:00:04 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639123399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3639123399 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2846160540 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1219328689 ps |
| CPU time | 13.37 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:34 PM UTC 25 |
| Peak memory | 233540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846160540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2846160540 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.1571494539 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 4952898760 ps |
| CPU time | 22.13 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:43 PM UTC 25 |
| Peak memory | 235308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571494539 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.1571494539 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.2726732629 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 2172167591 ps |
| CPU time | 14.2 seconds |
| Started | Feb 08 06:59:54 PM UTC 25 |
| Finished | Feb 08 07:00:10 PM UTC 25 |
| Peak memory | 227640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726732629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2726732629 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.127280015 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 621447916 ps |
| CPU time | 6.13 seconds |
| Started | Feb 08 06:59:54 PM UTC 25 |
| Finished | Feb 08 07:00:01 PM UTC 25 |
| Peak memory | 227480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127280015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.127280015 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.2644268433 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 13805080 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:59:56 PM UTC 25 |
| Finished | Feb 08 06:59:58 PM UTC 25 |
| Peak memory | 216012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644268433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2644268433 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2768535155 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 164781290 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:59:54 PM UTC 25 |
| Finished | Feb 08 06:59:56 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768535155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2768535155 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2279317674 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 12629337232 ps |
| CPU time | 19.9 seconds |
| Started | Feb 08 06:59:58 PM UTC 25 |
| Finished | Feb 08 07:00:20 PM UTC 25 |
| Peak memory | 251576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279317674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2279317674 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2038475585 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 39693536 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:48:08 PM UTC 25 |
| Finished | Feb 08 06:48:10 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038475585 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2038475585 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2150114448 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1548015841 ps |
| CPU time | 14.84 seconds |
| Started | Feb 08 06:48:04 PM UTC 25 |
| Finished | Feb 08 06:48:20 PM UTC 25 |
| Peak memory | 245388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150114448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2150114448 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.867487963 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 142625122 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 06:47:58 PM UTC 25 |
| Finished | Feb 08 06:48:00 PM UTC 25 |
| Peak memory | 216076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867487963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.867487963 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.386363452 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 18022004 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 06:48:05 PM UTC 25 |
| Finished | Feb 08 06:48:07 PM UTC 25 |
| Peak memory | 225836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386363452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.386363452 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1068426532 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4893412966 ps |
| CPU time | 19.76 seconds |
| Started | Feb 08 06:48:06 PM UTC 25 |
| Finished | Feb 08 06:48:27 PM UTC 25 |
| Peak memory | 229680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068426532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1068426532 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3519992144 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 728064929 ps |
| CPU time | 6.72 seconds |
| Started | Feb 08 06:48:04 PM UTC 25 |
| Finished | Feb 08 06:48:12 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519992144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3519992144 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2519892412 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 294174512 ps |
| CPU time | 3.04 seconds |
| Started | Feb 08 06:48:02 PM UTC 25 |
| Finished | Feb 08 06:48:07 PM UTC 25 |
| Peak memory | 235088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519892412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2519892412 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.419984855 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 307470034 ps |
| CPU time | 2.99 seconds |
| Started | Feb 08 06:48:02 PM UTC 25 |
| Finished | Feb 08 06:48:07 PM UTC 25 |
| Peak memory | 235136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419984855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.419984855 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3164122034 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1474409076 ps |
| CPU time | 10.21 seconds |
| Started | Feb 08 06:48:01 PM UTC 25 |
| Finished | Feb 08 06:48:13 PM UTC 25 |
| Peak memory | 245276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164122034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.3164122034 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4218265023 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 21521913269 ps |
| CPU time | 26.98 seconds |
| Started | Feb 08 06:48:01 PM UTC 25 |
| Finished | Feb 08 06:48:30 PM UTC 25 |
| Peak memory | 235188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218265023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4218265023 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3289650697 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 292483367 ps |
| CPU time | 6.64 seconds |
| Started | Feb 08 06:48:05 PM UTC 25 |
| Finished | Feb 08 06:48:13 PM UTC 25 |
| Peak memory | 231452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289650697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.3289650697 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3822321239 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 682468494 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:48:07 PM UTC 25 |
| Finished | Feb 08 06:48:10 PM UTC 25 |
| Peak memory | 257888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822321239 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3822321239 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.338409322 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2606735644 ps |
| CPU time | 14.34 seconds |
| Started | Feb 08 06:48:00 PM UTC 25 |
| Finished | Feb 08 06:48:16 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338409322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.338409322 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.536839160 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1973820139 ps |
| CPU time | 9.83 seconds |
| Started | Feb 08 06:47:59 PM UTC 25 |
| Finished | Feb 08 06:48:10 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536839160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.536839160 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2905461425 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 55476521 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:48:01 PM UTC 25 |
| Finished | Feb 08 06:48:04 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905461425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2905461425 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3875059547 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 128840327 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:48:00 PM UTC 25 |
| Finished | Feb 08 06:48:02 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875059547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3875059547 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1127385460 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1676830355 ps |
| CPU time | 5.91 seconds |
| Started | Feb 08 06:48:04 PM UTC 25 |
| Finished | Feb 08 06:48:11 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127385460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1127385460 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.1097583270 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 39353358 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 07:00:31 PM UTC 25 |
| Finished | Feb 08 07:00:34 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097583270 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.1097583270 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.676947518 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 171794356 ps |
| CPU time | 5.1 seconds |
| Started | Feb 08 07:00:24 PM UTC 25 |
| Finished | Feb 08 07:00:30 PM UTC 25 |
| Peak memory | 235072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676947518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.676947518 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.1868326314 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 20875528 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:22 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868326314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1868326314 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.2700167083 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 110113154075 ps |
| CPU time | 640.89 seconds |
| Started | Feb 08 07:00:29 PM UTC 25 |
| Finished | Feb 08 07:11:18 PM UTC 25 |
| Peak memory | 278192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700167083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2700167083 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1631362810 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1533094439 ps |
| CPU time | 18.24 seconds |
| Started | Feb 08 07:00:31 PM UTC 25 |
| Finished | Feb 08 07:00:51 PM UTC 25 |
| Peak memory | 229200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631362810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1631362810 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1504875919 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 14675201730 ps |
| CPU time | 62.04 seconds |
| Started | Feb 08 07:00:31 PM UTC 25 |
| Finished | Feb 08 07:01:35 PM UTC 25 |
| Peak memory | 261236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504875919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.1504875919 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2543555092 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3079275501 ps |
| CPU time | 17.41 seconds |
| Started | Feb 08 07:00:27 PM UTC 25 |
| Finished | Feb 08 07:00:46 PM UTC 25 |
| Peak memory | 235244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543555092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2543555092 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1024433522 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 7946874596 ps |
| CPU time | 60.72 seconds |
| Started | Feb 08 07:00:27 PM UTC 25 |
| Finished | Feb 08 07:01:29 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024433522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.1024433522 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.695660378 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 648933743 ps |
| CPU time | 10.68 seconds |
| Started | Feb 08 07:00:24 PM UTC 25 |
| Finished | Feb 08 07:00:36 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695660378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.695660378 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.2283437098 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1005469474 ps |
| CPU time | 19.91 seconds |
| Started | Feb 08 07:00:24 PM UTC 25 |
| Finished | Feb 08 07:00:45 PM UTC 25 |
| Peak memory | 249528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283437098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2283437098 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.486992764 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4294671545 ps |
| CPU time | 16.94 seconds |
| Started | Feb 08 07:00:24 PM UTC 25 |
| Finished | Feb 08 07:00:42 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486992764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.486992764 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2978982462 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 10355734106 ps |
| CPU time | 50.81 seconds |
| Started | Feb 08 07:00:21 PM UTC 25 |
| Finished | Feb 08 07:01:14 PM UTC 25 |
| Peak memory | 245420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978982462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2978982462 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3439712959 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3423880701 ps |
| CPU time | 17.38 seconds |
| Started | Feb 08 07:00:27 PM UTC 25 |
| Finished | Feb 08 07:00:46 PM UTC 25 |
| Peak memory | 231460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439712959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.3439712959 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1481630183 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 135805041727 ps |
| CPU time | 331.67 seconds |
| Started | Feb 08 07:00:31 PM UTC 25 |
| Finished | Feb 08 07:06:07 PM UTC 25 |
| Peak memory | 261760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481630183 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.1481630183 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.3857062093 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2316279052 ps |
| CPU time | 8.58 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:29 PM UTC 25 |
| Peak memory | 229756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857062093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3857062093 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1603982525 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3053910212 ps |
| CPU time | 5.51 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:26 PM UTC 25 |
| Peak memory | 227372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603982525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1603982525 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.1651344041 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 124772477 ps |
| CPU time | 3.93 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:25 PM UTC 25 |
| Peak memory | 227612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651344041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1651344041 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1698475413 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 322852049 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 07:00:19 PM UTC 25 |
| Finished | Feb 08 07:00:22 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698475413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1698475413 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.377846688 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3283185616 ps |
| CPU time | 15.76 seconds |
| Started | Feb 08 07:00:24 PM UTC 25 |
| Finished | Feb 08 07:00:41 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377846688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.377846688 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.410534042 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 59672840 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 07:00:46 PM UTC 25 |
| Finished | Feb 08 07:00:49 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410534042 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.410534042 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3471564264 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3894847113 ps |
| CPU time | 13.83 seconds |
| Started | Feb 08 07:00:42 PM UTC 25 |
| Finished | Feb 08 07:00:57 PM UTC 25 |
| Peak memory | 245444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471564264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3471564264 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.2801144843 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 109053102 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 07:00:33 PM UTC 25 |
| Finished | Feb 08 07:00:36 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801144843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2801144843 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.44257982 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1372943256 ps |
| CPU time | 15.75 seconds |
| Started | Feb 08 07:00:45 PM UTC 25 |
| Finished | Feb 08 07:01:02 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44257982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.44257982 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1374702402 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 36941807355 ps |
| CPU time | 254.46 seconds |
| Started | Feb 08 07:00:46 PM UTC 25 |
| Finished | Feb 08 07:05:05 PM UTC 25 |
| Peak memory | 261828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374702402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1374702402 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1241900006 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 10471511575 ps |
| CPU time | 76.63 seconds |
| Started | Feb 08 07:00:46 PM UTC 25 |
| Finished | Feb 08 07:02:05 PM UTC 25 |
| Peak memory | 261840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241900006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.1241900006 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.402170484 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1359893556 ps |
| CPU time | 30.86 seconds |
| Started | Feb 08 07:00:43 PM UTC 25 |
| Finished | Feb 08 07:01:16 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402170484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.402170484 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3793817288 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 193048983387 ps |
| CPU time | 324.78 seconds |
| Started | Feb 08 07:00:43 PM UTC 25 |
| Finished | Feb 08 07:06:13 PM UTC 25 |
| Peak memory | 268096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793817288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.3793817288 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1586880695 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 991526516 ps |
| CPU time | 6.62 seconds |
| Started | Feb 08 07:00:38 PM UTC 25 |
| Finished | Feb 08 07:00:46 PM UTC 25 |
| Peak memory | 235180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586880695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1586880695 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3149408503 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 18588479039 ps |
| CPU time | 44.07 seconds |
| Started | Feb 08 07:00:40 PM UTC 25 |
| Finished | Feb 08 07:01:25 PM UTC 25 |
| Peak memory | 235132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149408503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3149408503 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3585472655 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 275522064 ps |
| CPU time | 3.22 seconds |
| Started | Feb 08 07:00:37 PM UTC 25 |
| Finished | Feb 08 07:00:41 PM UTC 25 |
| Peak memory | 234412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585472655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.3585472655 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1812715768 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 188706841 ps |
| CPU time | 4.39 seconds |
| Started | Feb 08 07:00:37 PM UTC 25 |
| Finished | Feb 08 07:00:42 PM UTC 25 |
| Peak memory | 234916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812715768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1812715768 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.4168684723 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 482431429 ps |
| CPU time | 7.22 seconds |
| Started | Feb 08 07:00:44 PM UTC 25 |
| Finished | Feb 08 07:00:53 PM UTC 25 |
| Peak memory | 233464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168684723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.4168684723 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1248430823 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 944079076 ps |
| CPU time | 24.69 seconds |
| Started | Feb 08 07:00:46 PM UTC 25 |
| Finished | Feb 08 07:01:13 PM UTC 25 |
| Peak memory | 251576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248430823 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.1248430823 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.4215750200 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 7129570700 ps |
| CPU time | 17.63 seconds |
| Started | Feb 08 07:00:34 PM UTC 25 |
| Finished | Feb 08 07:00:53 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215750200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4215750200 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1015757577 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5979329397 ps |
| CPU time | 23.49 seconds |
| Started | Feb 08 07:00:34 PM UTC 25 |
| Finished | Feb 08 07:00:59 PM UTC 25 |
| Peak memory | 227624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015757577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1015757577 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.2812087312 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 98653205 ps |
| CPU time | 2.25 seconds |
| Started | Feb 08 07:00:36 PM UTC 25 |
| Finished | Feb 08 07:00:39 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812087312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2812087312 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.1502778024 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 86370521 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 07:00:35 PM UTC 25 |
| Finished | Feb 08 07:00:37 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502778024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1502778024 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.1358330834 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1502473411 ps |
| CPU time | 9.86 seconds |
| Started | Feb 08 07:00:42 PM UTC 25 |
| Finished | Feb 08 07:00:53 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358330834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1358330834 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.970235277 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 38571180 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 07:01:10 PM UTC 25 |
| Finished | Feb 08 07:01:12 PM UTC 25 |
| Peak memory | 215544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970235277 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.970235277 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.2607345366 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 63778433 ps |
| CPU time | 3.99 seconds |
| Started | Feb 08 07:00:56 PM UTC 25 |
| Finished | Feb 08 07:01:01 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607345366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2607345366 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2882170450 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 54422598 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 07:00:50 PM UTC 25 |
| Finished | Feb 08 07:00:52 PM UTC 25 |
| Peak memory | 216036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882170450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2882170450 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.3375786725 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3194428241 ps |
| CPU time | 56 seconds |
| Started | Feb 08 07:01:02 PM UTC 25 |
| Finished | Feb 08 07:02:00 PM UTC 25 |
| Peak memory | 278192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375786725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3375786725 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.4097846385 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 80050256756 ps |
| CPU time | 195.72 seconds |
| Started | Feb 08 07:01:03 PM UTC 25 |
| Finished | Feb 08 07:04:23 PM UTC 25 |
| Peak memory | 251632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097846385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4097846385 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.66229287 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 897358718 ps |
| CPU time | 28.88 seconds |
| Started | Feb 08 07:01:06 PM UTC 25 |
| Finished | Feb 08 07:01:36 PM UTC 25 |
| Peak memory | 251524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66229287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1 r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.66229287 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.236235483 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 149292737 ps |
| CPU time | 7.51 seconds |
| Started | Feb 08 07:00:57 PM UTC 25 |
| Finished | Feb 08 07:01:06 PM UTC 25 |
| Peak memory | 235188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236235483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.236235483 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.844705823 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 3297968705 ps |
| CPU time | 70.83 seconds |
| Started | Feb 08 07:00:58 PM UTC 25 |
| Finished | Feb 08 07:02:11 PM UTC 25 |
| Peak memory | 261888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844705823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.844705823 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2284160893 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 6979450911 ps |
| CPU time | 29.84 seconds |
| Started | Feb 08 07:00:54 PM UTC 25 |
| Finished | Feb 08 07:01:25 PM UTC 25 |
| Peak memory | 235200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284160893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2284160893 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.3490100759 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 54772477921 ps |
| CPU time | 78.72 seconds |
| Started | Feb 08 07:00:54 PM UTC 25 |
| Finished | Feb 08 07:02:15 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490100759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3490100759 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1506019356 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 588850678 ps |
| CPU time | 8.95 seconds |
| Started | Feb 08 07:00:54 PM UTC 25 |
| Finished | Feb 08 07:01:04 PM UTC 25 |
| Peak memory | 245428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506019356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1506019356 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1605475966 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 19046816236 ps |
| CPU time | 29.22 seconds |
| Started | Feb 08 07:00:54 PM UTC 25 |
| Finished | Feb 08 07:01:25 PM UTC 25 |
| Peak memory | 245412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605475966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1605475966 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.290800568 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2201501753 ps |
| CPU time | 14.57 seconds |
| Started | Feb 08 07:01:00 PM UTC 25 |
| Finished | Feb 08 07:01:16 PM UTC 25 |
| Peak memory | 233588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290800568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.290800568 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1082571103 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3848022854 ps |
| CPU time | 94.43 seconds |
| Started | Feb 08 07:01:07 PM UTC 25 |
| Finished | Feb 08 07:02:44 PM UTC 25 |
| Peak memory | 278336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082571103 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.1082571103 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.550936197 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 4767974761 ps |
| CPU time | 24.39 seconds |
| Started | Feb 08 07:00:52 PM UTC 25 |
| Finished | Feb 08 07:01:17 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550936197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.550936197 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3176217682 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1290364468 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 07:00:50 PM UTC 25 |
| Finished | Feb 08 07:00:53 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176217682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3176217682 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.2679944449 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 20555299 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 07:00:53 PM UTC 25 |
| Finished | Feb 08 07:00:55 PM UTC 25 |
| Peak memory | 216012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679944449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2679944449 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.868912298 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 179381320 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 07:00:53 PM UTC 25 |
| Finished | Feb 08 07:00:55 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868912298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.868912298 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.620445339 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 6856895701 ps |
| CPU time | 14.15 seconds |
| Started | Feb 08 07:00:56 PM UTC 25 |
| Finished | Feb 08 07:01:11 PM UTC 25 |
| Peak memory | 235180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620445339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.620445339 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.4007438254 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 70200224 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 07:01:25 PM UTC 25 |
| Finished | Feb 08 07:01:27 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007438254 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.4007438254 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2412965400 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 41933365 ps |
| CPU time | 3.49 seconds |
| Started | Feb 08 07:01:14 PM UTC 25 |
| Finished | Feb 08 07:01:19 PM UTC 25 |
| Peak memory | 245508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412965400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2412965400 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2601888504 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 19302705 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 07:01:10 PM UTC 25 |
| Finished | Feb 08 07:01:12 PM UTC 25 |
| Peak memory | 215492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601888504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2601888504 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.4202395570 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 350652937066 ps |
| CPU time | 650.42 seconds |
| Started | Feb 08 07:01:17 PM UTC 25 |
| Finished | Feb 08 07:12:15 PM UTC 25 |
| Peak memory | 265920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202395570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4202395570 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2743148248 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 326108509959 ps |
| CPU time | 223.77 seconds |
| Started | Feb 08 07:01:19 PM UTC 25 |
| Finished | Feb 08 07:05:06 PM UTC 25 |
| Peak memory | 278256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743148248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2743148248 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.3784472028 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 329900182 ps |
| CPU time | 9.62 seconds |
| Started | Feb 08 07:01:15 PM UTC 25 |
| Finished | Feb 08 07:01:26 PM UTC 25 |
| Peak memory | 255612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784472028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3784472028 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1014061502 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 28012575839 ps |
| CPU time | 162.72 seconds |
| Started | Feb 08 07:01:17 PM UTC 25 |
| Finished | Feb 08 07:04:02 PM UTC 25 |
| Peak memory | 278192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014061502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1014061502 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1589112846 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2478988931 ps |
| CPU time | 12.32 seconds |
| Started | Feb 08 07:01:13 PM UTC 25 |
| Finished | Feb 08 07:01:27 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589112846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1589112846 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2994699796 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 27151730546 ps |
| CPU time | 53.91 seconds |
| Started | Feb 08 07:01:13 PM UTC 25 |
| Finished | Feb 08 07:02:09 PM UTC 25 |
| Peak memory | 249524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994699796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2994699796 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.204119859 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 22064001405 ps |
| CPU time | 25.43 seconds |
| Started | Feb 08 07:01:13 PM UTC 25 |
| Finished | Feb 08 07:01:40 PM UTC 25 |
| Peak memory | 245408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204119859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.204119859 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3409152703 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1499852828 ps |
| CPU time | 10.66 seconds |
| Started | Feb 08 07:01:12 PM UTC 25 |
| Finished | Feb 08 07:01:24 PM UTC 25 |
| Peak memory | 247488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409152703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3409152703 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2302126640 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 89310659 ps |
| CPU time | 4.93 seconds |
| Started | Feb 08 07:01:17 PM UTC 25 |
| Finished | Feb 08 07:01:23 PM UTC 25 |
| Peak memory | 233708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302126640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.2302126640 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2894752374 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1812522624 ps |
| CPU time | 17.71 seconds |
| Started | Feb 08 07:01:10 PM UTC 25 |
| Finished | Feb 08 07:01:29 PM UTC 25 |
| Peak memory | 231628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894752374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2894752374 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.450689924 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 120229482551 ps |
| CPU time | 29.37 seconds |
| Started | Feb 08 07:01:10 PM UTC 25 |
| Finished | Feb 08 07:01:41 PM UTC 25 |
| Peak memory | 229692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450689924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.450689924 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.428318150 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 104159789 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 07:01:11 PM UTC 25 |
| Finished | Feb 08 07:01:14 PM UTC 25 |
| Peak memory | 227564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428318150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.428318150 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1483718164 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 83558473 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 07:01:10 PM UTC 25 |
| Finished | Feb 08 07:01:12 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483718164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1483718164 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.3942454865 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 12774515945 ps |
| CPU time | 19.33 seconds |
| Started | Feb 08 07:01:13 PM UTC 25 |
| Finished | Feb 08 07:01:34 PM UTC 25 |
| Peak memory | 235136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942454865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3942454865 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.1353701951 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 14066871 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 07:01:41 PM UTC 25 |
| Finished | Feb 08 07:01:43 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353701951 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.1353701951 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2103813679 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2279876730 ps |
| CPU time | 17.49 seconds |
| Started | Feb 08 07:01:30 PM UTC 25 |
| Finished | Feb 08 07:01:48 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103813679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2103813679 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2631278851 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 17149960 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 07:01:25 PM UTC 25 |
| Finished | Feb 08 07:01:27 PM UTC 25 |
| Peak memory | 215552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631278851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2631278851 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.778018913 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 6585187575 ps |
| CPU time | 98.33 seconds |
| Started | Feb 08 07:01:35 PM UTC 25 |
| Finished | Feb 08 07:03:15 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778018913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.778018913 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1900264581 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 459340616256 ps |
| CPU time | 599.43 seconds |
| Started | Feb 08 07:01:36 PM UTC 25 |
| Finished | Feb 08 07:11:43 PM UTC 25 |
| Peak memory | 261872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900264581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1900264581 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.848763300 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 27173135870 ps |
| CPU time | 223.7 seconds |
| Started | Feb 08 07:01:37 PM UTC 25 |
| Finished | Feb 08 07:05:24 PM UTC 25 |
| Peak memory | 263868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848763300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.848763300 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3314895527 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 5254402762 ps |
| CPU time | 36.22 seconds |
| Started | Feb 08 07:01:30 PM UTC 25 |
| Finished | Feb 08 07:02:07 PM UTC 25 |
| Peak memory | 261744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314895527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3314895527 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3170691134 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 233878494371 ps |
| CPU time | 166.9 seconds |
| Started | Feb 08 07:01:30 PM UTC 25 |
| Finished | Feb 08 07:04:20 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170691134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.3170691134 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.4094117247 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 5002801666 ps |
| CPU time | 14.67 seconds |
| Started | Feb 08 07:01:28 PM UTC 25 |
| Finished | Feb 08 07:01:45 PM UTC 25 |
| Peak memory | 245476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094117247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4094117247 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2798805406 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 4286393674 ps |
| CPU time | 20.7 seconds |
| Started | Feb 08 07:01:29 PM UTC 25 |
| Finished | Feb 08 07:01:51 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798805406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2798805406 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1190232382 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 9897426798 ps |
| CPU time | 24.62 seconds |
| Started | Feb 08 07:01:27 PM UTC 25 |
| Finished | Feb 08 07:01:53 PM UTC 25 |
| Peak memory | 265924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190232382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.1190232382 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.3729881980 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 13318069115 ps |
| CPU time | 21.32 seconds |
| Started | Feb 08 07:01:27 PM UTC 25 |
| Finished | Feb 08 07:01:50 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729881980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3729881980 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1626707183 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 715871328 ps |
| CPU time | 10.66 seconds |
| Started | Feb 08 07:01:31 PM UTC 25 |
| Finished | Feb 08 07:01:43 PM UTC 25 |
| Peak memory | 231416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626707183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.1626707183 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.381752199 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 83841951501 ps |
| CPU time | 1049.45 seconds |
| Started | Feb 08 07:01:40 PM UTC 25 |
| Finished | Feb 08 07:19:23 PM UTC 25 |
| Peak memory | 300780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381752199 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.381752199 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2561772288 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 33841986 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 07:01:25 PM UTC 25 |
| Finished | Feb 08 07:01:27 PM UTC 25 |
| Peak memory | 215900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561772288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2561772288 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.602246530 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1844530844 ps |
| CPU time | 18.61 seconds |
| Started | Feb 08 07:01:25 PM UTC 25 |
| Finished | Feb 08 07:01:45 PM UTC 25 |
| Peak memory | 227564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602246530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.602246530 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1317765191 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 29361395 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 07:01:26 PM UTC 25 |
| Finished | Feb 08 07:01:29 PM UTC 25 |
| Peak memory | 216312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317765191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1317765191 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1744857907 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 49055713 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 07:01:26 PM UTC 25 |
| Finished | Feb 08 07:01:29 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744857907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1744857907 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2878188676 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 855746571 ps |
| CPU time | 9.01 seconds |
| Started | Feb 08 07:01:29 PM UTC 25 |
| Finished | Feb 08 07:01:39 PM UTC 25 |
| Peak memory | 235036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878188676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2878188676 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.2273326720 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 26907370 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 07:01:54 PM UTC 25 |
| Finished | Feb 08 07:01:57 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273326720 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.2273326720 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3732218515 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 68094616 ps |
| CPU time | 2.86 seconds |
| Started | Feb 08 07:01:47 PM UTC 25 |
| Finished | Feb 08 07:01:51 PM UTC 25 |
| Peak memory | 235080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732218515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3732218515 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.1395243428 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 41019327 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 07:01:41 PM UTC 25 |
| Finished | Feb 08 07:01:43 PM UTC 25 |
| Peak memory | 215492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395243428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1395243428 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2373064236 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 9703806854 ps |
| CPU time | 142.67 seconds |
| Started | Feb 08 07:01:51 PM UTC 25 |
| Finished | Feb 08 07:04:16 PM UTC 25 |
| Peak memory | 267952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373064236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2373064236 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1806234890 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 6324594926 ps |
| CPU time | 41.67 seconds |
| Started | Feb 08 07:01:51 PM UTC 25 |
| Finished | Feb 08 07:02:34 PM UTC 25 |
| Peak memory | 235204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806234890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1806234890 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2470631207 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 108277015079 ps |
| CPU time | 217.8 seconds |
| Started | Feb 08 07:01:52 PM UTC 25 |
| Finished | Feb 08 07:05:33 PM UTC 25 |
| Peak memory | 261932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470631207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.2470631207 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.3741627258 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 1223156667 ps |
| CPU time | 17.75 seconds |
| Started | Feb 08 07:01:48 PM UTC 25 |
| Finished | Feb 08 07:02:07 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741627258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3741627258 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1122660769 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 11607126312 ps |
| CPU time | 156.14 seconds |
| Started | Feb 08 07:01:49 PM UTC 25 |
| Finished | Feb 08 07:04:28 PM UTC 25 |
| Peak memory | 278316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122660769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.1122660769 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.578857346 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1504251366 ps |
| CPU time | 11.03 seconds |
| Started | Feb 08 07:01:46 PM UTC 25 |
| Finished | Feb 08 07:01:58 PM UTC 25 |
| Peak memory | 235060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578857346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.578857346 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3264851700 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 18293353126 ps |
| CPU time | 55.74 seconds |
| Started | Feb 08 07:01:46 PM UTC 25 |
| Finished | Feb 08 07:02:43 PM UTC 25 |
| Peak memory | 261816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264851700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3264851700 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2743041706 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 4253813741 ps |
| CPU time | 7.15 seconds |
| Started | Feb 08 07:01:45 PM UTC 25 |
| Finished | Feb 08 07:01:53 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743041706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.2743041706 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1111722339 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 13096413020 ps |
| CPU time | 40.72 seconds |
| Started | Feb 08 07:01:44 PM UTC 25 |
| Finished | Feb 08 07:02:27 PM UTC 25 |
| Peak memory | 249536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111722339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1111722339 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.4196507662 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 553070478 ps |
| CPU time | 8.71 seconds |
| Started | Feb 08 07:01:50 PM UTC 25 |
| Finished | Feb 08 07:02:00 PM UTC 25 |
| Peak memory | 233908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196507662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.4196507662 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1666432351 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 120062909666 ps |
| CPU time | 562.82 seconds |
| Started | Feb 08 07:01:53 PM UTC 25 |
| Finished | Feb 08 07:11:23 PM UTC 25 |
| Peak memory | 284400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666432351 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1666432351 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.2178485385 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2728981680 ps |
| CPU time | 20.48 seconds |
| Started | Feb 08 07:01:43 PM UTC 25 |
| Finished | Feb 08 07:02:05 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178485385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2178485385 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3091608343 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 160447724 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 07:01:41 PM UTC 25 |
| Finished | Feb 08 07:01:45 PM UTC 25 |
| Peak memory | 217168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091608343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3091608343 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.531894485 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 54638636 ps |
| CPU time | 1.87 seconds |
| Started | Feb 08 07:01:44 PM UTC 25 |
| Finished | Feb 08 07:01:47 PM UTC 25 |
| Peak memory | 226856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531894485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.531894485 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3766426918 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 51300737 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 07:01:43 PM UTC 25 |
| Finished | Feb 08 07:01:46 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766426918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3766426918 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2775432076 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 13701189033 ps |
| CPU time | 17.76 seconds |
| Started | Feb 08 07:01:46 PM UTC 25 |
| Finished | Feb 08 07:02:05 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775432076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2775432076 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3458643839 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 12690027 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 07:02:13 PM UTC 25 |
| Finished | Feb 08 07:02:15 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458643839 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3458643839 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3820839762 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 174184474 ps |
| CPU time | 3.35 seconds |
| Started | Feb 08 07:02:06 PM UTC 25 |
| Finished | Feb 08 07:02:11 PM UTC 25 |
| Peak memory | 245320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820839762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3820839762 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.3936289304 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 14307679 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 07:01:57 PM UTC 25 |
| Finished | Feb 08 07:02:00 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936289304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3936289304 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.3220170958 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 11441486197 ps |
| CPU time | 61.11 seconds |
| Started | Feb 08 07:02:09 PM UTC 25 |
| Finished | Feb 08 07:03:12 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220170958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3220170958 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3538334775 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 22623038814 ps |
| CPU time | 258.67 seconds |
| Started | Feb 08 07:02:11 PM UTC 25 |
| Finished | Feb 08 07:06:34 PM UTC 25 |
| Peak memory | 284376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538334775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3538334775 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2877325100 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 7922962368 ps |
| CPU time | 139.02 seconds |
| Started | Feb 08 07:02:11 PM UTC 25 |
| Finished | Feb 08 07:04:33 PM UTC 25 |
| Peak memory | 272124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877325100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.2877325100 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.2579147544 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 6288204402 ps |
| CPU time | 13.28 seconds |
| Started | Feb 08 07:02:06 PM UTC 25 |
| Finished | Feb 08 07:02:21 PM UTC 25 |
| Peak memory | 235196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579147544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2579147544 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1130699411 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 47695896813 ps |
| CPU time | 403.99 seconds |
| Started | Feb 08 07:02:08 PM UTC 25 |
| Finished | Feb 08 07:08:58 PM UTC 25 |
| Peak memory | 263872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130699411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.1130699411 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2902342541 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 2230801594 ps |
| CPU time | 13.94 seconds |
| Started | Feb 08 07:02:04 PM UTC 25 |
| Finished | Feb 08 07:02:19 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902342541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2902342541 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.556883625 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 429976611 ps |
| CPU time | 13.54 seconds |
| Started | Feb 08 07:02:06 PM UTC 25 |
| Finished | Feb 08 07:02:21 PM UTC 25 |
| Peak memory | 245488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556883625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.556883625 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1485570304 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4761010644 ps |
| CPU time | 31.47 seconds |
| Started | Feb 08 07:02:04 PM UTC 25 |
| Finished | Feb 08 07:02:37 PM UTC 25 |
| Peak memory | 247476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485570304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1485570304 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1691869191 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 907162279 ps |
| CPU time | 8.41 seconds |
| Started | Feb 08 07:02:01 PM UTC 25 |
| Finished | Feb 08 07:02:10 PM UTC 25 |
| Peak memory | 245380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691869191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1691869191 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.321070224 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 390194272 ps |
| CPU time | 6.08 seconds |
| Started | Feb 08 07:02:08 PM UTC 25 |
| Finished | Feb 08 07:02:15 PM UTC 25 |
| Peak memory | 233524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321070224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.321070224 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1800426869 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 49860038 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 07:02:11 PM UTC 25 |
| Finished | Feb 08 07:02:14 PM UTC 25 |
| Peak memory | 215428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800426869 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1800426869 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.4033654653 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 9571286603 ps |
| CPU time | 26.03 seconds |
| Started | Feb 08 07:01:59 PM UTC 25 |
| Finished | Feb 08 07:02:26 PM UTC 25 |
| Peak memory | 231676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033654653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4033654653 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1390755966 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 883291637 ps |
| CPU time | 6.58 seconds |
| Started | Feb 08 07:01:57 PM UTC 25 |
| Finished | Feb 08 07:02:05 PM UTC 25 |
| Peak memory | 227620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390755966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1390755966 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3843763996 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 14006150 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 07:02:01 PM UTC 25 |
| Finished | Feb 08 07:02:03 PM UTC 25 |
| Peak memory | 216012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843763996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3843763996 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2566979460 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 50733777 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 07:02:01 PM UTC 25 |
| Finished | Feb 08 07:02:03 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566979460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2566979460 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1222311519 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 2002584568 ps |
| CPU time | 4.5 seconds |
| Started | Feb 08 07:02:06 PM UTC 25 |
| Finished | Feb 08 07:02:12 PM UTC 25 |
| Peak memory | 235112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222311519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1222311519 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.629290594 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 27749523 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 07:02:28 PM UTC 25 |
| Finished | Feb 08 07:02:30 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629290594 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.629290594 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1616839491 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3830372590 ps |
| CPU time | 11.78 seconds |
| Started | Feb 08 07:02:22 PM UTC 25 |
| Finished | Feb 08 07:02:35 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616839491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1616839491 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.153675239 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 29471983 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 07:02:13 PM UTC 25 |
| Finished | Feb 08 07:02:15 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153675239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.153675239 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.2224547110 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 25223465020 ps |
| CPU time | 91.62 seconds |
| Started | Feb 08 07:02:24 PM UTC 25 |
| Finished | Feb 08 07:03:58 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224547110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2224547110 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3894776055 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 206819507908 ps |
| CPU time | 241.71 seconds |
| Started | Feb 08 07:02:26 PM UTC 25 |
| Finished | Feb 08 07:06:31 PM UTC 25 |
| Peak memory | 268064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894776055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3894776055 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1971912623 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 24472033426 ps |
| CPU time | 264.5 seconds |
| Started | Feb 08 07:02:27 PM UTC 25 |
| Finished | Feb 08 07:06:55 PM UTC 25 |
| Peak memory | 268012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971912623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.1971912623 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1525218774 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1096903641 ps |
| CPU time | 13.56 seconds |
| Started | Feb 08 07:02:22 PM UTC 25 |
| Finished | Feb 08 07:02:37 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525218774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1525218774 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2244717716 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 21737307112 ps |
| CPU time | 65.08 seconds |
| Started | Feb 08 07:02:23 PM UTC 25 |
| Finished | Feb 08 07:03:30 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244717716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.2244717716 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3355637248 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 131330754 ps |
| CPU time | 2.92 seconds |
| Started | Feb 08 07:02:20 PM UTC 25 |
| Finished | Feb 08 07:02:24 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355637248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3355637248 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.425810417 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 487894362 ps |
| CPU time | 4.89 seconds |
| Started | Feb 08 07:02:21 PM UTC 25 |
| Finished | Feb 08 07:02:27 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425810417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.425810417 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2101596953 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 381800411 ps |
| CPU time | 4.61 seconds |
| Started | Feb 08 07:02:19 PM UTC 25 |
| Finished | Feb 08 07:02:25 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101596953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2101596953 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.1151080000 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 604586310 ps |
| CPU time | 2.81 seconds |
| Started | Feb 08 07:02:16 PM UTC 25 |
| Finished | Feb 08 07:02:20 PM UTC 25 |
| Peak memory | 245312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151080000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1151080000 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1123445912 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 819404385 ps |
| CPU time | 6.87 seconds |
| Started | Feb 08 07:02:24 PM UTC 25 |
| Finished | Feb 08 07:02:32 PM UTC 25 |
| Peak memory | 231480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123445912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.1123445912 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.3569631382 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 106217088 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 07:02:28 PM UTC 25 |
| Finished | Feb 08 07:02:30 PM UTC 25 |
| Peak memory | 216188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569631382 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.3569631382 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.523962476 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 21812848018 ps |
| CPU time | 48 seconds |
| Started | Feb 08 07:02:16 PM UTC 25 |
| Finished | Feb 08 07:03:05 PM UTC 25 |
| Peak memory | 227120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523962476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.523962476 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2547848412 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 847943467 ps |
| CPU time | 7.12 seconds |
| Started | Feb 08 07:02:15 PM UTC 25 |
| Finished | Feb 08 07:02:23 PM UTC 25 |
| Peak memory | 227552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547848412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2547848412 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.4210405581 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1636269501 ps |
| CPU time | 4.82 seconds |
| Started | Feb 08 07:02:16 PM UTC 25 |
| Finished | Feb 08 07:02:22 PM UTC 25 |
| Peak memory | 227572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210405581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4210405581 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1753760657 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 29056477 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 07:02:16 PM UTC 25 |
| Finished | Feb 08 07:02:18 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753760657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1753760657 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.875382286 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 1279549768 ps |
| CPU time | 9.02 seconds |
| Started | Feb 08 07:02:21 PM UTC 25 |
| Finished | Feb 08 07:02:31 PM UTC 25 |
| Peak memory | 245352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875382286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.875382286 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.798350721 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 80798991 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 07:02:44 PM UTC 25 |
| Finished | Feb 08 07:02:46 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798350721 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.798350721 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3505519685 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 445623330 ps |
| CPU time | 3.99 seconds |
| Started | Feb 08 07:02:35 PM UTC 25 |
| Finished | Feb 08 07:02:41 PM UTC 25 |
| Peak memory | 235064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505519685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3505519685 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.733159055 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 48120665 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 07:02:31 PM UTC 25 |
| Finished | Feb 08 07:02:33 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733159055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.733159055 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.870392355 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 8834663397 ps |
| CPU time | 64.92 seconds |
| Started | Feb 08 07:02:38 PM UTC 25 |
| Finished | Feb 08 07:03:44 PM UTC 25 |
| Peak memory | 261824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870392355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.870392355 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.369674277 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 19054650887 ps |
| CPU time | 301.67 seconds |
| Started | Feb 08 07:02:40 PM UTC 25 |
| Finished | Feb 08 07:07:46 PM UTC 25 |
| Peak memory | 278244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369674277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.369674277 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.396438825 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 30859852899 ps |
| CPU time | 274.49 seconds |
| Started | Feb 08 07:02:42 PM UTC 25 |
| Finished | Feb 08 07:07:20 PM UTC 25 |
| Peak memory | 261872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396438825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.396438825 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.960388968 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 1436712278 ps |
| CPU time | 25.78 seconds |
| Started | Feb 08 07:02:37 PM UTC 25 |
| Finished | Feb 08 07:03:04 PM UTC 25 |
| Peak memory | 235140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960388968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.960388968 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1141923478 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 119786466148 ps |
| CPU time | 271.73 seconds |
| Started | Feb 08 07:02:37 PM UTC 25 |
| Finished | Feb 08 07:07:12 PM UTC 25 |
| Peak memory | 267948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141923478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.1141923478 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1117324647 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 2669497329 ps |
| CPU time | 17.39 seconds |
| Started | Feb 08 07:02:34 PM UTC 25 |
| Finished | Feb 08 07:02:53 PM UTC 25 |
| Peak memory | 235180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117324647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1117324647 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.969678213 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 916724301 ps |
| CPU time | 13.45 seconds |
| Started | Feb 08 07:02:35 PM UTC 25 |
| Finished | Feb 08 07:02:50 PM UTC 25 |
| Peak memory | 241940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969678213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.969678213 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1310726185 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 71457467 ps |
| CPU time | 3.67 seconds |
| Started | Feb 08 07:02:34 PM UTC 25 |
| Finished | Feb 08 07:02:39 PM UTC 25 |
| Peak memory | 245504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310726185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.1310726185 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3713132300 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 736030597 ps |
| CPU time | 11.51 seconds |
| Started | Feb 08 07:02:34 PM UTC 25 |
| Finished | Feb 08 07:02:47 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713132300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3713132300 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2537515527 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 1296265193 ps |
| CPU time | 21.72 seconds |
| Started | Feb 08 07:02:38 PM UTC 25 |
| Finished | Feb 08 07:03:01 PM UTC 25 |
| Peak memory | 234208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537515527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2537515527 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.2953754312 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 119736062565 ps |
| CPU time | 572.47 seconds |
| Started | Feb 08 07:02:43 PM UTC 25 |
| Finished | Feb 08 07:12:22 PM UTC 25 |
| Peak memory | 278244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953754312 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.2953754312 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.4250406985 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 8726864651 ps |
| CPU time | 39.42 seconds |
| Started | Feb 08 07:02:31 PM UTC 25 |
| Finished | Feb 08 07:03:12 PM UTC 25 |
| Peak memory | 227624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250406985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4250406985 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3381993455 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 11441858 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 07:02:31 PM UTC 25 |
| Finished | Feb 08 07:02:33 PM UTC 25 |
| Peak memory | 215952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381993455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3381993455 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.1598875851 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 19149088 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 07:02:33 PM UTC 25 |
| Finished | Feb 08 07:02:35 PM UTC 25 |
| Peak memory | 216012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598875851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1598875851 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2926112487 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 77315844 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 07:02:32 PM UTC 25 |
| Finished | Feb 08 07:02:35 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926112487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2926112487 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.2943931267 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 434504843 ps |
| CPU time | 5.62 seconds |
| Started | Feb 08 07:02:35 PM UTC 25 |
| Finished | Feb 08 07:02:42 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943931267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2943931267 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.718262127 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 42633418 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 07:03:08 PM UTC 25 |
| Finished | Feb 08 07:03:10 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718262127 -assert nopostproc +UVM_TESTNAME=spi_de vice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.718262127 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3935638393 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 43848480 ps |
| CPU time | 2.63 seconds |
| Started | Feb 08 07:03:03 PM UTC 25 |
| Finished | Feb 08 07:03:06 PM UTC 25 |
| Peak memory | 235252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935638393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3935638393 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.1541297855 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 31360320 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 07:02:44 PM UTC 25 |
| Finished | Feb 08 07:02:46 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541297855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1541297855 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.1487632393 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 528857540 ps |
| CPU time | 15.73 seconds |
| Started | Feb 08 07:03:06 PM UTC 25 |
| Finished | Feb 08 07:03:23 PM UTC 25 |
| Peak memory | 251316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487632393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1487632393 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3623372335 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 187365018291 ps |
| CPU time | 310.44 seconds |
| Started | Feb 08 07:03:06 PM UTC 25 |
| Finished | Feb 08 07:08:21 PM UTC 25 |
| Peak memory | 265792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623372335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3623372335 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4141297842 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 4455837576 ps |
| CPU time | 25.25 seconds |
| Started | Feb 08 07:03:06 PM UTC 25 |
| Finished | Feb 08 07:03:33 PM UTC 25 |
| Peak memory | 229744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141297842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.4141297842 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.159431658 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 32270166 ps |
| CPU time | 3.62 seconds |
| Started | Feb 08 07:03:05 PM UTC 25 |
| Finished | Feb 08 07:03:10 PM UTC 25 |
| Peak memory | 245508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159431658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.159431658 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2236602039 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 52788537 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 07:03:05 PM UTC 25 |
| Finished | Feb 08 07:03:07 PM UTC 25 |
| Peak memory | 225832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236602039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.2236602039 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.441794386 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 107111230 ps |
| CPU time | 6.24 seconds |
| Started | Feb 08 07:02:56 PM UTC 25 |
| Finished | Feb 08 07:03:04 PM UTC 25 |
| Peak memory | 245380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441794386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.441794386 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.1634217431 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2007023406 ps |
| CPU time | 6.17 seconds |
| Started | Feb 08 07:02:58 PM UTC 25 |
| Finished | Feb 08 07:03:05 PM UTC 25 |
| Peak memory | 245384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634217431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1634217431 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.965750204 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 8359424489 ps |
| CPU time | 50.15 seconds |
| Started | Feb 08 07:02:53 PM UTC 25 |
| Finished | Feb 08 07:03:45 PM UTC 25 |
| Peak memory | 245360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965750204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.965750204 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2212794369 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 101212520 ps |
| CPU time | 3.21 seconds |
| Started | Feb 08 07:02:51 PM UTC 25 |
| Finished | Feb 08 07:02:56 PM UTC 25 |
| Peak memory | 244876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212794369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2212794369 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.514458223 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 807330170 ps |
| CPU time | 7.58 seconds |
| Started | Feb 08 07:03:05 PM UTC 25 |
| Finished | Feb 08 07:03:14 PM UTC 25 |
| Peak memory | 231476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514458223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.514458223 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1411300617 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 35158522969 ps |
| CPU time | 262.52 seconds |
| Started | Feb 08 07:03:07 PM UTC 25 |
| Finished | Feb 08 07:07:33 PM UTC 25 |
| Peak memory | 265964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411300617 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.1411300617 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1835584843 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 61878321731 ps |
| CPU time | 38.96 seconds |
| Started | Feb 08 07:02:47 PM UTC 25 |
| Finished | Feb 08 07:03:28 PM UTC 25 |
| Peak memory | 227640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835584843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1835584843 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3374708735 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 1495458384 ps |
| CPU time | 15.32 seconds |
| Started | Feb 08 07:02:47 PM UTC 25 |
| Finished | Feb 08 07:03:04 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374708735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3374708735 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.1552022327 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 59969666 ps |
| CPU time | 3.87 seconds |
| Started | Feb 08 07:02:51 PM UTC 25 |
| Finished | Feb 08 07:02:56 PM UTC 25 |
| Peak memory | 227396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552022327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1552022327 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.860332448 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 27834066 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 07:02:48 PM UTC 25 |
| Finished | Feb 08 07:02:51 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860332448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.860332448 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3972318600 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 223348109 ps |
| CPU time | 2.64 seconds |
| Started | Feb 08 07:03:02 PM UTC 25 |
| Finished | Feb 08 07:03:05 PM UTC 25 |
| Peak memory | 234720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972318600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3972318600 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.3933237411 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 18933633 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:48:21 PM UTC 25 |
| Finished | Feb 08 06:48:24 PM UTC 25 |
| Peak memory | 215896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933237411 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3933237411 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.4190852542 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 329554468 ps |
| CPU time | 4.64 seconds |
| Started | Feb 08 06:48:15 PM UTC 25 |
| Finished | Feb 08 06:48:21 PM UTC 25 |
| Peak memory | 245388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190852542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4190852542 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.176293375 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 62338341 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:48:08 PM UTC 25 |
| Finished | Feb 08 06:48:10 PM UTC 25 |
| Peak memory | 216076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176293375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.176293375 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2269517949 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 272350538 ps |
| CPU time | 6.14 seconds |
| Started | Feb 08 06:48:19 PM UTC 25 |
| Finished | Feb 08 06:48:26 PM UTC 25 |
| Peak memory | 229688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269517949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2269517949 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3235559423 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 123028712691 ps |
| CPU time | 275.47 seconds |
| Started | Feb 08 06:48:20 PM UTC 25 |
| Finished | Feb 08 06:53:00 PM UTC 25 |
| Peak memory | 278264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235559423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3235559423 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2423305752 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 56857392439 ps |
| CPU time | 345.78 seconds |
| Started | Feb 08 06:48:21 PM UTC 25 |
| Finished | Feb 08 06:54:12 PM UTC 25 |
| Peak memory | 261876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423305752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2423305752 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2501278625 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 246416698 ps |
| CPU time | 3.73 seconds |
| Started | Feb 08 06:48:16 PM UTC 25 |
| Finished | Feb 08 06:48:21 PM UTC 25 |
| Peak memory | 235096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501278625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2501278625 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1061904805 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 9067216298 ps |
| CPU time | 58.51 seconds |
| Started | Feb 08 06:48:16 PM UTC 25 |
| Finished | Feb 08 06:49:16 PM UTC 25 |
| Peak memory | 245340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061904805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.1061904805 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.4211321034 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 706614074 ps |
| CPU time | 6.75 seconds |
| Started | Feb 08 06:48:13 PM UTC 25 |
| Finished | Feb 08 06:48:21 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211321034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4211321034 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1473072191 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 16453416585 ps |
| CPU time | 84.38 seconds |
| Started | Feb 08 06:48:14 PM UTC 25 |
| Finished | Feb 08 06:49:40 PM UTC 25 |
| Peak memory | 245500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473072191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1473072191 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3124305700 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1360412872 ps |
| CPU time | 9.75 seconds |
| Started | Feb 08 06:48:13 PM UTC 25 |
| Finished | Feb 08 06:48:24 PM UTC 25 |
| Peak memory | 245364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124305700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.3124305700 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.638040314 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 76641737730 ps |
| CPU time | 28.27 seconds |
| Started | Feb 08 06:48:12 PM UTC 25 |
| Finished | Feb 08 06:48:41 PM UTC 25 |
| Peak memory | 245496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638040314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.638040314 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.820612226 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 4436258246 ps |
| CPU time | 5.22 seconds |
| Started | Feb 08 06:48:17 PM UTC 25 |
| Finished | Feb 08 06:48:23 PM UTC 25 |
| Peak memory | 231476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820612226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.820612226 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2042726063 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 16963226061 ps |
| CPU time | 162.72 seconds |
| Started | Feb 08 06:48:21 PM UTC 25 |
| Finished | Feb 08 06:51:07 PM UTC 25 |
| Peak memory | 300924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042726063 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2042726063 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.518315871 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 13281657859 ps |
| CPU time | 38.42 seconds |
| Started | Feb 08 06:48:11 PM UTC 25 |
| Finished | Feb 08 06:48:51 PM UTC 25 |
| Peak memory | 227760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518315871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.518315871 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1686420407 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 5750338359 ps |
| CPU time | 30.24 seconds |
| Started | Feb 08 06:48:10 PM UTC 25 |
| Finished | Feb 08 06:48:42 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686420407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1686420407 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.130071344 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 114532797 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 06:48:11 PM UTC 25 |
| Finished | Feb 08 06:48:15 PM UTC 25 |
| Peak memory | 227568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130071344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.130071344 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2831390394 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 78181867 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:48:11 PM UTC 25 |
| Finished | Feb 08 06:48:14 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831390394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2831390394 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2456064216 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1977273391 ps |
| CPU time | 6.29 seconds |
| Started | Feb 08 06:48:14 PM UTC 25 |
| Finished | Feb 08 06:48:21 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456064216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2456064216 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2676305453 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 13788006 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:48:35 PM UTC 25 |
| Finished | Feb 08 06:48:37 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676305453 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2676305453 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1220622260 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 145173041 ps |
| CPU time | 3.07 seconds |
| Started | Feb 08 06:48:27 PM UTC 25 |
| Finished | Feb 08 06:48:32 PM UTC 25 |
| Peak memory | 234704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220622260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1220622260 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.1565911853 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 15239426 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:48:22 PM UTC 25 |
| Finished | Feb 08 06:48:25 PM UTC 25 |
| Peak memory | 216020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565911853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1565911853 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.967216858 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 29362012114 ps |
| CPU time | 222.64 seconds |
| Started | Feb 08 06:48:31 PM UTC 25 |
| Finished | Feb 08 06:52:16 PM UTC 25 |
| Peak memory | 263856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967216858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.967216858 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1612339182 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3048419381 ps |
| CPU time | 51.45 seconds |
| Started | Feb 08 06:48:33 PM UTC 25 |
| Finished | Feb 08 06:49:26 PM UTC 25 |
| Peak memory | 261808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612339182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1612339182 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3973070307 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 121429014 ps |
| CPU time | 5.91 seconds |
| Started | Feb 08 06:48:27 PM UTC 25 |
| Finished | Feb 08 06:48:34 PM UTC 25 |
| Peak memory | 235244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973070307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3973070307 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1851714234 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 11584492821 ps |
| CPU time | 71.53 seconds |
| Started | Feb 08 06:48:28 PM UTC 25 |
| Finished | Feb 08 06:49:42 PM UTC 25 |
| Peak memory | 261472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851714234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.1851714234 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.1374853418 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 589769200 ps |
| CPU time | 5.6 seconds |
| Started | Feb 08 06:48:26 PM UTC 25 |
| Finished | Feb 08 06:48:33 PM UTC 25 |
| Peak memory | 235100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374853418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1374853418 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1961749358 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1091803391 ps |
| CPU time | 9.72 seconds |
| Started | Feb 08 06:48:26 PM UTC 25 |
| Finished | Feb 08 06:48:37 PM UTC 25 |
| Peak memory | 251436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961749358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1961749358 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.2614196601 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 915192506 ps |
| CPU time | 11.56 seconds |
| Started | Feb 08 06:48:25 PM UTC 25 |
| Finished | Feb 08 06:48:37 PM UTC 25 |
| Peak memory | 251632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614196601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.2614196601 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2052129614 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 62856984913 ps |
| CPU time | 37.28 seconds |
| Started | Feb 08 06:48:25 PM UTC 25 |
| Finished | Feb 08 06:49:03 PM UTC 25 |
| Peak memory | 235184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052129614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2052129614 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2306078885 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2515436187 ps |
| CPU time | 8.46 seconds |
| Started | Feb 08 06:48:28 PM UTC 25 |
| Finished | Feb 08 06:48:38 PM UTC 25 |
| Peak memory | 233416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306078885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2306078885 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2943615674 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4485704959 ps |
| CPU time | 14.43 seconds |
| Started | Feb 08 06:48:23 PM UTC 25 |
| Finished | Feb 08 06:48:38 PM UTC 25 |
| Peak memory | 227644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943615674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2943615674 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1374509259 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1039861572 ps |
| CPU time | 6.62 seconds |
| Started | Feb 08 06:48:22 PM UTC 25 |
| Finished | Feb 08 06:48:30 PM UTC 25 |
| Peak memory | 227696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374509259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1374509259 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.1314783406 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 48660067 ps |
| CPU time | 2.2 seconds |
| Started | Feb 08 06:48:25 PM UTC 25 |
| Finished | Feb 08 06:48:28 PM UTC 25 |
| Peak memory | 227352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314783406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1314783406 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.391177376 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 92830014 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:48:25 PM UTC 25 |
| Finished | Feb 08 06:48:27 PM UTC 25 |
| Peak memory | 215772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391177376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.391177376 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1468813678 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 16155400788 ps |
| CPU time | 29.07 seconds |
| Started | Feb 08 06:48:26 PM UTC 25 |
| Finished | Feb 08 06:48:57 PM UTC 25 |
| Peak memory | 235120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468813678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1468813678 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2358311260 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 33045352 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:48:53 PM UTC 25 |
| Finished | Feb 08 06:48:55 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358311260 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2358311260 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3355683663 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 38257096 ps |
| CPU time | 2.73 seconds |
| Started | Feb 08 06:48:43 PM UTC 25 |
| Finished | Feb 08 06:48:47 PM UTC 25 |
| Peak memory | 235084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355683663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3355683663 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2081700463 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 18511585 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:48:35 PM UTC 25 |
| Finished | Feb 08 06:48:37 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081700463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2081700463 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1788217462 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 144485993449 ps |
| CPU time | 312.29 seconds |
| Started | Feb 08 06:48:46 PM UTC 25 |
| Finished | Feb 08 06:54:03 PM UTC 25 |
| Peak memory | 261880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788217462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1788217462 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.997154993 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2526517364 ps |
| CPU time | 66.81 seconds |
| Started | Feb 08 06:48:46 PM UTC 25 |
| Finished | Feb 08 06:49:55 PM UTC 25 |
| Peak memory | 263952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997154993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.997154993 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.259951137 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 923660043 ps |
| CPU time | 10.13 seconds |
| Started | Feb 08 06:48:43 PM UTC 25 |
| Finished | Feb 08 06:48:55 PM UTC 25 |
| Peak memory | 245356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259951137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.259951137 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1921274870 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2506315564 ps |
| CPU time | 17.98 seconds |
| Started | Feb 08 06:48:43 PM UTC 25 |
| Finished | Feb 08 06:49:02 PM UTC 25 |
| Peak memory | 247488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921274870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.1921274870 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2437100387 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1639434138 ps |
| CPU time | 4.97 seconds |
| Started | Feb 08 06:48:39 PM UTC 25 |
| Finished | Feb 08 06:48:46 PM UTC 25 |
| Peak memory | 235056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437100387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2437100387 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3874528192 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 7106929072 ps |
| CPU time | 38.63 seconds |
| Started | Feb 08 06:48:39 PM UTC 25 |
| Finished | Feb 08 06:49:20 PM UTC 25 |
| Peak memory | 245456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874528192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3874528192 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1707648196 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 32891613895 ps |
| CPU time | 29.09 seconds |
| Started | Feb 08 06:48:38 PM UTC 25 |
| Finished | Feb 08 06:49:09 PM UTC 25 |
| Peak memory | 235104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707648196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.1707648196 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2349793555 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 882163179 ps |
| CPU time | 5.95 seconds |
| Started | Feb 08 06:48:38 PM UTC 25 |
| Finished | Feb 08 06:48:46 PM UTC 25 |
| Peak memory | 235036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349793555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2349793555 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3081255464 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1445322375 ps |
| CPU time | 8.41 seconds |
| Started | Feb 08 06:48:44 PM UTC 25 |
| Finished | Feb 08 06:48:54 PM UTC 25 |
| Peak memory | 231468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081255464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.3081255464 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1114942183 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 310429706548 ps |
| CPU time | 192.03 seconds |
| Started | Feb 08 06:48:48 PM UTC 25 |
| Finished | Feb 08 06:52:04 PM UTC 25 |
| Peak memory | 265948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114942183 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.1114942183 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2104321467 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 26864929406 ps |
| CPU time | 38.56 seconds |
| Started | Feb 08 06:48:38 PM UTC 25 |
| Finished | Feb 08 06:49:19 PM UTC 25 |
| Peak memory | 227404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104321467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2104321467 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.793318494 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 8607465589 ps |
| CPU time | 33.43 seconds |
| Started | Feb 08 06:48:38 PM UTC 25 |
| Finished | Feb 08 06:49:13 PM UTC 25 |
| Peak memory | 227480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793318494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.793318494 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2533394050 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 92968098 ps |
| CPU time | 2.76 seconds |
| Started | Feb 08 06:48:38 PM UTC 25 |
| Finished | Feb 08 06:48:43 PM UTC 25 |
| Peak memory | 227508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533394050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2533394050 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1089153293 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 41174476 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:48:38 PM UTC 25 |
| Finished | Feb 08 06:48:41 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089153293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1089153293 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3245192082 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 14506550013 ps |
| CPU time | 63.22 seconds |
| Started | Feb 08 06:48:41 PM UTC 25 |
| Finished | Feb 08 06:49:47 PM UTC 25 |
| Peak memory | 251580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245192082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3245192082 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3262106971 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 10450219 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:49:16 PM UTC 25 |
| Finished | Feb 08 06:49:18 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262106971 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3262106971 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.905149281 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2227211364 ps |
| CPU time | 7.84 seconds |
| Started | Feb 08 06:49:09 PM UTC 25 |
| Finished | Feb 08 06:49:18 PM UTC 25 |
| Peak memory | 245436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905149281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.905149281 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3008523331 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 101860560 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:48:54 PM UTC 25 |
| Finished | Feb 08 06:48:56 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008523331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3008523331 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1814715261 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 76278064 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:49:13 PM UTC 25 |
| Finished | Feb 08 06:49:15 PM UTC 25 |
| Peak memory | 225828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814715261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1814715261 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3466752561 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 80498431013 ps |
| CPU time | 244.94 seconds |
| Started | Feb 08 06:49:13 PM UTC 25 |
| Finished | Feb 08 06:53:21 PM UTC 25 |
| Peak memory | 268008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466752561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3466752561 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2497019429 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1356281753 ps |
| CPU time | 26.99 seconds |
| Started | Feb 08 06:49:14 PM UTC 25 |
| Finished | Feb 08 06:49:42 PM UTC 25 |
| Peak memory | 235176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497019429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.2497019429 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.492115001 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 4686182498 ps |
| CPU time | 21.46 seconds |
| Started | Feb 08 06:49:10 PM UTC 25 |
| Finished | Feb 08 06:49:33 PM UTC 25 |
| Peak memory | 245424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492115001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.492115001 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.321227359 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 24574544196 ps |
| CPU time | 65.81 seconds |
| Started | Feb 08 06:49:10 PM UTC 25 |
| Finished | Feb 08 06:50:18 PM UTC 25 |
| Peak memory | 251584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321227359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_ 1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.321227359 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2016107218 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 8827945463 ps |
| CPU time | 19.88 seconds |
| Started | Feb 08 06:49:03 PM UTC 25 |
| Finished | Feb 08 06:49:25 PM UTC 25 |
| Peak memory | 245380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016107218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2016107218 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.279391358 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 32216753598 ps |
| CPU time | 96.42 seconds |
| Started | Feb 08 06:49:04 PM UTC 25 |
| Finished | Feb 08 06:50:43 PM UTC 25 |
| Peak memory | 247476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279391358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.279391358 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2909110137 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 532950910 ps |
| CPU time | 17.32 seconds |
| Started | Feb 08 06:49:00 PM UTC 25 |
| Finished | Feb 08 06:49:19 PM UTC 25 |
| Peak memory | 261764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909110137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.2909110137 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2497729293 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 764350073 ps |
| CPU time | 6.31 seconds |
| Started | Feb 08 06:48:58 PM UTC 25 |
| Finished | Feb 08 06:49:06 PM UTC 25 |
| Peak memory | 235116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497729293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2497729293 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.727012785 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 445347794 ps |
| CPU time | 6.32 seconds |
| Started | Feb 08 06:49:12 PM UTC 25 |
| Finished | Feb 08 06:49:19 PM UTC 25 |
| Peak memory | 231412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727012785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.727012785 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.703505196 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 6551410359 ps |
| CPU time | 17.31 seconds |
| Started | Feb 08 06:48:56 PM UTC 25 |
| Finished | Feb 08 06:49:14 PM UTC 25 |
| Peak memory | 227524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703505196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.703505196 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3483321028 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4618425787 ps |
| CPU time | 11 seconds |
| Started | Feb 08 06:48:56 PM UTC 25 |
| Finished | Feb 08 06:49:08 PM UTC 25 |
| Peak memory | 227460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483321028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3483321028 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.867229436 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1213725640 ps |
| CPU time | 12.95 seconds |
| Started | Feb 08 06:48:58 PM UTC 25 |
| Finished | Feb 08 06:49:12 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867229436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.867229436 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2679955317 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 49081662 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:48:57 PM UTC 25 |
| Finished | Feb 08 06:48:59 PM UTC 25 |
| Peak memory | 216016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679955317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2679955317 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.159410158 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 280017558 ps |
| CPU time | 4.25 seconds |
| Started | Feb 08 06:49:06 PM UTC 25 |
| Finished | Feb 08 06:49:12 PM UTC 25 |
| Peak memory | 235052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159410158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.159410158 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.1744839663 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 11187583 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:49:35 PM UTC 25 |
| Finished | Feb 08 06:49:37 PM UTC 25 |
| Peak memory | 215836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744839663 -assert nopostproc +UVM_TESTNAME=spi_d evice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1744839663 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3676734622 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 62529971 ps |
| CPU time | 4.17 seconds |
| Started | Feb 08 06:49:25 PM UTC 25 |
| Finished | Feb 08 06:49:30 PM UTC 25 |
| Peak memory | 245368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676734622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3676734622 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.328457116 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 22904166 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:49:17 PM UTC 25 |
| Finished | Feb 08 06:49:19 PM UTC 25 |
| Peak memory | 216076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328457116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_S EQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.328457116 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3577920082 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 138164509658 ps |
| CPU time | 339.51 seconds |
| Started | Feb 08 06:49:31 PM UTC 25 |
| Finished | Feb 08 06:55:15 PM UTC 25 |
| Peak memory | 265900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577920082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3577920082 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2567025689 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 8268305508 ps |
| CPU time | 94.9 seconds |
| Started | Feb 08 06:49:33 PM UTC 25 |
| Finished | Feb 08 06:51:10 PM UTC 25 |
| Peak memory | 263916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567025689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.2567025689 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1032611264 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 72007198 ps |
| CPU time | 5.88 seconds |
| Started | Feb 08 06:49:26 PM UTC 25 |
| Finished | Feb 08 06:49:33 PM UTC 25 |
| Peak memory | 245376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032611264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1032611264 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2599215291 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3452783784 ps |
| CPU time | 26.86 seconds |
| Started | Feb 08 06:49:22 PM UTC 25 |
| Finished | Feb 08 06:49:51 PM UTC 25 |
| Peak memory | 245372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599215291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2599215291 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2304236494 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 47240371587 ps |
| CPU time | 106.12 seconds |
| Started | Feb 08 06:49:23 PM UTC 25 |
| Finished | Feb 08 06:51:11 PM UTC 25 |
| Peak memory | 245328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304236494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2304236494 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2663052391 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 130868833 ps |
| CPU time | 2.53 seconds |
| Started | Feb 08 06:49:20 PM UTC 25 |
| Finished | Feb 08 06:49:24 PM UTC 25 |
| Peak memory | 235060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663052391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device _1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.2663052391 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1117558599 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1076195820 ps |
| CPU time | 4.25 seconds |
| Started | Feb 08 06:49:20 PM UTC 25 |
| Finished | Feb 08 06:49:26 PM UTC 25 |
| Peak memory | 235124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117558599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1 w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1117558599 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1238741961 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 213786697 ps |
| CPU time | 5.85 seconds |
| Started | Feb 08 06:49:27 PM UTC 25 |
| Finished | Feb 08 06:49:34 PM UTC 25 |
| Peak memory | 233652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238741961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.1238741961 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4038014804 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 13228030969 ps |
| CPU time | 27.65 seconds |
| Started | Feb 08 06:49:19 PM UTC 25 |
| Finished | Feb 08 06:49:48 PM UTC 25 |
| Peak memory | 227580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038014804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4038014804 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3692752535 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3470406625 ps |
| CPU time | 12.49 seconds |
| Started | Feb 08 06:49:19 PM UTC 25 |
| Finished | Feb 08 06:49:33 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692752535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3692752535 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1143606404 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 148829593 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:49:20 PM UTC 25 |
| Finished | Feb 08 06:49:23 PM UTC 25 |
| Peak memory | 226608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143606404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1143606404 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3963098177 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 15879942 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:49:19 PM UTC 25 |
| Finished | Feb 08 06:49:22 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963098177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3963098177 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.1074103100 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 9204095407 ps |
| CPU time | 41.46 seconds |
| Started | Feb 08 06:49:24 PM UTC 25 |
| Finished | Feb 08 06:50:07 PM UTC 25 |
| Peak memory | 251520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074103100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_ SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1074103100 |
| Directory | /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |