| T623 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.1327540487 |
|
|
Feb 08 06:56:03 PM UTC 25 |
Feb 08 06:56:11 PM UTC 25 |
2980164892 ps |
| T224 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.2163894356 |
|
|
Feb 08 06:56:08 PM UTC 25 |
Feb 08 06:56:13 PM UTC 25 |
242334585 ps |
| T624 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2410182719 |
|
|
Feb 08 06:56:11 PM UTC 25 |
Feb 08 06:56:19 PM UTC 25 |
2120725953 ps |
| T365 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3672427997 |
|
|
Feb 08 06:56:02 PM UTC 25 |
Feb 08 06:56:20 PM UTC 25 |
3057812517 ps |
| T625 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2096938922 |
|
|
Feb 08 06:54:28 PM UTC 25 |
Feb 08 06:56:20 PM UTC 25 |
18064547322 ps |
| T626 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3693383191 |
|
|
Feb 08 06:56:09 PM UTC 25 |
Feb 08 06:56:22 PM UTC 25 |
1021200342 ps |
| T627 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.1435846185 |
|
|
Feb 08 06:56:02 PM UTC 25 |
Feb 08 06:56:24 PM UTC 25 |
3230525554 ps |
| T628 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.1264806291 |
|
|
Feb 08 06:56:22 PM UTC 25 |
Feb 08 06:56:24 PM UTC 25 |
66113627 ps |
| T629 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.1185936890 |
|
|
Feb 08 06:56:23 PM UTC 25 |
Feb 08 06:56:25 PM UTC 25 |
16717201 ps |
| T630 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.1821960793 |
|
|
Feb 08 06:56:08 PM UTC 25 |
Feb 08 06:56:27 PM UTC 25 |
4512740474 ps |
| T631 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1463232354 |
|
|
Feb 08 06:56:26 PM UTC 25 |
Feb 08 06:56:28 PM UTC 25 |
111190095 ps |
| T632 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.761351924 |
|
|
Feb 08 06:56:28 PM UTC 25 |
Feb 08 06:56:31 PM UTC 25 |
133974142 ps |
| T633 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3381831307 |
|
|
Feb 08 06:56:25 PM UTC 25 |
Feb 08 06:56:32 PM UTC 25 |
1910343977 ps |
| T634 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.2494753298 |
|
|
Feb 08 06:56:01 PM UTC 25 |
Feb 08 06:56:32 PM UTC 25 |
5391265288 ps |
| T635 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.2080169931 |
|
|
Feb 08 06:54:48 PM UTC 25 |
Feb 08 06:57:00 PM UTC 25 |
27327455893 ps |
| T636 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2418953957 |
|
|
Feb 08 06:56:29 PM UTC 25 |
Feb 08 06:56:34 PM UTC 25 |
263484503 ps |
| T272 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3012112962 |
|
|
Feb 08 06:53:32 PM UTC 25 |
Feb 08 06:56:35 PM UTC 25 |
85146315834 ps |
| T637 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3738979047 |
|
|
Feb 08 06:55:50 PM UTC 25 |
Feb 08 06:56:36 PM UTC 25 |
2265680732 ps |
| T638 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2731926017 |
|
|
Feb 08 06:56:32 PM UTC 25 |
Feb 08 06:56:38 PM UTC 25 |
254160933 ps |
| T187 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.1210134869 |
|
|
Feb 08 06:54:31 PM UTC 25 |
Feb 08 06:56:41 PM UTC 25 |
7371360896 ps |
| T639 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.2871225984 |
|
|
Feb 08 06:55:10 PM UTC 25 |
Feb 08 06:56:42 PM UTC 25 |
9971278289 ps |
| T640 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.690413240 |
|
|
Feb 08 06:56:36 PM UTC 25 |
Feb 08 06:56:43 PM UTC 25 |
1210408889 ps |
| T641 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.220218996 |
|
|
Feb 08 06:55:53 PM UTC 25 |
Feb 08 06:56:44 PM UTC 25 |
10371406845 ps |
| T642 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.2199614671 |
|
|
Feb 08 06:56:33 PM UTC 25 |
Feb 08 06:56:45 PM UTC 25 |
312223043 ps |
| T643 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.1683385438 |
|
|
Feb 08 06:56:56 PM UTC 25 |
Feb 08 06:57:03 PM UTC 25 |
1775004103 ps |
| T644 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.2500191034 |
|
|
Feb 08 06:56:37 PM UTC 25 |
Feb 08 06:56:48 PM UTC 25 |
278818546 ps |
| T645 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.124200922 |
|
|
Feb 08 06:55:51 PM UTC 25 |
Feb 08 06:56:51 PM UTC 25 |
8197017277 ps |
| T646 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.259666112 |
|
|
Feb 08 06:56:49 PM UTC 25 |
Feb 08 06:56:51 PM UTC 25 |
21879951 ps |
| T395 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1534303575 |
|
|
Feb 08 06:55:54 PM UTC 25 |
Feb 08 06:56:51 PM UTC 25 |
7631539542 ps |
| T647 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.3946119704 |
|
|
Feb 08 06:56:25 PM UTC 25 |
Feb 08 06:56:52 PM UTC 25 |
979123721 ps |
| T273 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.611473944 |
|
|
Feb 08 06:53:23 PM UTC 25 |
Feb 08 06:56:53 PM UTC 25 |
39769673587 ps |
| T648 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.1110736320 |
|
|
Feb 08 06:56:35 PM UTC 25 |
Feb 08 06:56:53 PM UTC 25 |
3409077978 ps |
| T649 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.3087325461 |
|
|
Feb 08 06:56:51 PM UTC 25 |
Feb 08 06:56:53 PM UTC 25 |
22004811 ps |
| T650 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.3713320929 |
|
|
Feb 08 06:56:53 PM UTC 25 |
Feb 08 06:56:56 PM UTC 25 |
157464027 ps |
| T651 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3414358528 |
|
|
Feb 08 06:56:43 PM UTC 25 |
Feb 08 06:56:56 PM UTC 25 |
3811904083 ps |
| T652 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.4053375478 |
|
|
Feb 08 06:56:53 PM UTC 25 |
Feb 08 06:56:56 PM UTC 25 |
72119179 ps |
| T653 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.2231465530 |
|
|
Feb 08 06:56:52 PM UTC 25 |
Feb 08 06:56:59 PM UTC 25 |
351789958 ps |
| T654 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1036433659 |
|
|
Feb 08 06:56:54 PM UTC 25 |
Feb 08 06:57:05 PM UTC 25 |
2340295781 ps |
| T655 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2911765911 |
|
|
Feb 08 06:55:58 PM UTC 25 |
Feb 08 06:57:05 PM UTC 25 |
34915826120 ps |
| T656 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.107898105 |
|
|
Feb 08 06:54:52 PM UTC 25 |
Feb 08 06:57:06 PM UTC 25 |
60371078166 ps |
| T657 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3491622504 |
|
|
Feb 08 06:56:52 PM UTC 25 |
Feb 08 06:57:06 PM UTC 25 |
2896666348 ps |
| T658 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1346306377 |
|
|
Feb 08 06:57:06 PM UTC 25 |
Feb 08 06:57:08 PM UTC 25 |
12632183 ps |
| T659 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.1421572310 |
|
|
Feb 08 06:56:33 PM UTC 25 |
Feb 08 06:57:09 PM UTC 25 |
5055693595 ps |
| T180 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.535475691 |
|
|
Feb 08 06:57:09 PM UTC 25 |
Feb 08 06:57:12 PM UTC 25 |
69598628 ps |
| T660 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.2815696405 |
|
|
Feb 08 06:57:10 PM UTC 25 |
Feb 08 06:57:13 PM UTC 25 |
28879865 ps |
| T661 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.1591830144 |
|
|
Feb 08 06:55:39 PM UTC 25 |
Feb 08 06:57:13 PM UTC 25 |
15015140244 ps |
| T225 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.1539902997 |
|
|
Feb 08 06:53:22 PM UTC 25 |
Feb 08 06:57:15 PM UTC 25 |
50620241539 ps |
| T254 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2542270994 |
|
|
Feb 08 06:52:23 PM UTC 25 |
Feb 08 06:57:15 PM UTC 25 |
291651845407 ps |
| T662 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.43910005 |
|
|
Feb 08 06:57:13 PM UTC 25 |
Feb 08 06:57:16 PM UTC 25 |
42976724 ps |
| T663 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.1897570885 |
|
|
Feb 08 06:57:01 PM UTC 25 |
Feb 08 06:57:16 PM UTC 25 |
4826050796 ps |
| T664 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2059289810 |
|
|
Feb 08 06:56:57 PM UTC 25 |
Feb 08 06:57:17 PM UTC 25 |
531323173 ps |
| T665 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.4231689445 |
|
|
Feb 08 06:57:15 PM UTC 25 |
Feb 08 06:57:18 PM UTC 25 |
76101631 ps |
| T311 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.2867877879 |
|
|
Feb 08 06:57:00 PM UTC 25 |
Feb 08 06:57:19 PM UTC 25 |
1042913487 ps |
| T666 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2213564979 |
|
|
Feb 08 06:57:17 PM UTC 25 |
Feb 08 06:57:23 PM UTC 25 |
156377038 ps |
| T667 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1763460290 |
|
|
Feb 08 06:57:06 PM UTC 25 |
Feb 08 06:57:24 PM UTC 25 |
14468957579 ps |
| T668 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.843459243 |
|
|
Feb 08 06:57:17 PM UTC 25 |
Feb 08 06:57:24 PM UTC 25 |
1963185641 ps |
| T669 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.1355757777 |
|
|
Feb 08 06:57:20 PM UTC 25 |
Feb 08 06:57:24 PM UTC 25 |
314640323 ps |
| T670 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.2546975251 |
|
|
Feb 08 06:57:18 PM UTC 25 |
Feb 08 06:57:24 PM UTC 25 |
1703168524 ps |
| T346 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2392144354 |
|
|
Feb 08 06:57:04 PM UTC 25 |
Feb 08 06:57:25 PM UTC 25 |
860967608 ps |
| T671 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.3584749046 |
|
|
Feb 08 06:57:46 PM UTC 25 |
Feb 08 06:58:13 PM UTC 25 |
4822813857 ps |
| T672 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.4220744196 |
|
|
Feb 08 06:57:19 PM UTC 25 |
Feb 08 06:57:25 PM UTC 25 |
275874355 ps |
| T673 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.2609367307 |
|
|
Feb 08 06:57:17 PM UTC 25 |
Feb 08 06:57:25 PM UTC 25 |
624203468 ps |
| T674 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.3682740575 |
|
|
Feb 08 06:57:13 PM UTC 25 |
Feb 08 06:57:26 PM UTC 25 |
8117820086 ps |
| T675 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1905718438 |
|
|
Feb 08 06:57:25 PM UTC 25 |
Feb 08 06:57:27 PM UTC 25 |
10673781 ps |
| T163 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.4272458746 |
|
|
Feb 08 06:51:13 PM UTC 25 |
Feb 08 06:57:29 PM UTC 25 |
548839552047 ps |
| T676 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.3130641350 |
|
|
Feb 08 06:56:13 PM UTC 25 |
Feb 08 06:57:29 PM UTC 25 |
6080636628 ps |
| T677 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.2696225838 |
|
|
Feb 08 06:57:27 PM UTC 25 |
Feb 08 06:57:30 PM UTC 25 |
12598482 ps |
| T678 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.958975788 |
|
|
Feb 08 06:57:29 PM UTC 25 |
Feb 08 06:57:31 PM UTC 25 |
18984203 ps |
| T679 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3196611213 |
|
|
Feb 08 06:56:40 PM UTC 25 |
Feb 08 06:57:31 PM UTC 25 |
1733761288 ps |
| T680 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3029569625 |
|
|
Feb 08 06:57:30 PM UTC 25 |
Feb 08 06:57:32 PM UTC 25 |
15684998 ps |
| T681 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2248465567 |
|
|
Feb 08 06:57:14 PM UTC 25 |
Feb 08 06:57:33 PM UTC 25 |
1000540320 ps |
| T682 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2199538551 |
|
|
Feb 08 06:57:31 PM UTC 25 |
Feb 08 06:57:33 PM UTC 25 |
17412843 ps |
| T683 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4272987378 |
|
|
Feb 08 06:57:23 PM UTC 25 |
Feb 08 06:57:33 PM UTC 25 |
2848281489 ps |
| T684 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2085618381 |
|
|
Feb 08 06:57:26 PM UTC 25 |
Feb 08 06:57:35 PM UTC 25 |
199443355 ps |
| T685 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.1579021744 |
|
|
Feb 08 06:56:58 PM UTC 25 |
Feb 08 06:57:37 PM UTC 25 |
43985031565 ps |
| T686 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1681683923 |
|
|
Feb 08 06:57:25 PM UTC 25 |
Feb 08 06:57:37 PM UTC 25 |
716051340 ps |
| T687 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.2560936459 |
|
|
Feb 08 06:57:32 PM UTC 25 |
Feb 08 06:57:37 PM UTC 25 |
2326994305 ps |
| T688 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.1547385558 |
|
|
Feb 08 06:57:24 PM UTC 25 |
Feb 08 06:57:37 PM UTC 25 |
672812900 ps |
| T689 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.1180449910 |
|
|
Feb 08 06:57:36 PM UTC 25 |
Feb 08 06:57:40 PM UTC 25 |
31796482 ps |
| T279 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3235193146 |
|
|
Feb 08 06:49:54 PM UTC 25 |
Feb 08 06:57:41 PM UTC 25 |
85350638720 ps |
| T690 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.3386713354 |
|
|
Feb 08 06:57:25 PM UTC 25 |
Feb 08 06:57:41 PM UTC 25 |
3968337321 ps |
| T691 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.1108218128 |
|
|
Feb 08 06:57:37 PM UTC 25 |
Feb 08 06:57:42 PM UTC 25 |
171871065 ps |
| T692 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.779508417 |
|
|
Feb 08 06:57:34 PM UTC 25 |
Feb 08 06:57:43 PM UTC 25 |
860363620 ps |
| T693 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1979909674 |
|
|
Feb 08 06:57:33 PM UTC 25 |
Feb 08 06:57:43 PM UTC 25 |
745451547 ps |
| T694 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2152057477 |
|
|
Feb 08 06:57:38 PM UTC 25 |
Feb 08 06:57:45 PM UTC 25 |
81106128 ps |
| T695 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.1601221473 |
|
|
Feb 08 06:57:43 PM UTC 25 |
Feb 08 06:57:45 PM UTC 25 |
14436401 ps |
| T79 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.2198434557 |
|
|
Feb 08 06:55:13 PM UTC 25 |
Feb 08 06:57:45 PM UTC 25 |
74917124675 ps |
| T84 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.92672138 |
|
|
Feb 08 06:57:32 PM UTC 25 |
Feb 08 06:57:46 PM UTC 25 |
2853452293 ps |
| T85 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.1070405856 |
|
|
Feb 08 06:57:44 PM UTC 25 |
Feb 08 06:57:46 PM UTC 25 |
14819567 ps |
| T86 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1367410482 |
|
|
Feb 08 06:57:46 PM UTC 25 |
Feb 08 06:57:48 PM UTC 25 |
23938473 ps |
| T87 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.491501624 |
|
|
Feb 08 06:55:40 PM UTC 25 |
Feb 08 06:57:49 PM UTC 25 |
25609779212 ps |
| T88 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.597531764 |
|
|
Feb 08 06:57:46 PM UTC 25 |
Feb 08 06:57:50 PM UTC 25 |
488813105 ps |
| T89 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2959733012 |
|
|
Feb 08 06:57:44 PM UTC 25 |
Feb 08 06:57:52 PM UTC 25 |
2139253811 ps |
| T90 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3736292957 |
|
|
Feb 08 06:57:47 PM UTC 25 |
Feb 08 06:57:55 PM UTC 25 |
792699906 ps |
| T91 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.359642851 |
|
|
Feb 08 06:57:47 PM UTC 25 |
Feb 08 06:57:55 PM UTC 25 |
205511691 ps |
| T92 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.990475815 |
|
|
Feb 08 06:57:31 PM UTC 25 |
Feb 08 06:57:55 PM UTC 25 |
1204252253 ps |
| T306 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.584244426 |
|
|
Feb 08 06:57:50 PM UTC 25 |
Feb 08 06:57:56 PM UTC 25 |
492558909 ps |
| T696 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1246032152 |
|
|
Feb 08 06:57:52 PM UTC 25 |
Feb 08 06:57:57 PM UTC 25 |
95109219 ps |
| T697 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.2112167221 |
|
|
Feb 08 06:57:49 PM UTC 25 |
Feb 08 06:57:59 PM UTC 25 |
771211304 ps |
| T80 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2176193409 |
|
|
Feb 08 06:51:01 PM UTC 25 |
Feb 08 06:58:01 PM UTC 25 |
47960606040 ps |
| T698 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.2791322816 |
|
|
Feb 08 06:57:38 PM UTC 25 |
Feb 08 06:58:02 PM UTC 25 |
2808362901 ps |
| T699 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.1654701266 |
|
|
Feb 08 06:56:53 PM UTC 25 |
Feb 08 06:58:02 PM UTC 25 |
13441782356 ps |
| T700 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2189326688 |
|
|
Feb 08 06:57:56 PM UTC 25 |
Feb 08 06:58:03 PM UTC 25 |
104503143 ps |
| T701 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.2284604566 |
|
|
Feb 08 06:55:53 PM UTC 25 |
Feb 08 06:58:04 PM UTC 25 |
38431458361 ps |
| T702 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.1814920885 |
|
|
Feb 08 06:58:03 PM UTC 25 |
Feb 08 06:58:05 PM UTC 25 |
16586395 ps |
| T703 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.3048364811 |
|
|
Feb 08 06:58:03 PM UTC 25 |
Feb 08 06:58:05 PM UTC 25 |
44694171 ps |
| T704 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3093878662 |
|
|
Feb 08 06:58:04 PM UTC 25 |
Feb 08 06:58:07 PM UTC 25 |
145928845 ps |
| T705 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.2096946694 |
|
|
Feb 08 06:57:34 PM UTC 25 |
Feb 08 06:58:07 PM UTC 25 |
9301706884 ps |
| T706 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.823085659 |
|
|
Feb 08 06:56:20 PM UTC 25 |
Feb 08 06:58:08 PM UTC 25 |
11235234829 ps |
| T707 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1753556194 |
|
|
Feb 08 06:58:06 PM UTC 25 |
Feb 08 06:58:08 PM UTC 25 |
29078834 ps |
| T708 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1840110694 |
|
|
Feb 08 06:51:15 PM UTC 25 |
Feb 08 06:58:10 PM UTC 25 |
44488778711 ps |
| T709 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.2228931768 |
|
|
Feb 08 06:58:06 PM UTC 25 |
Feb 08 06:58:10 PM UTC 25 |
110932073 ps |
| T710 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.3102133398 |
|
|
Feb 08 06:56:43 PM UTC 25 |
Feb 08 06:58:12 PM UTC 25 |
61865870430 ps |
| T711 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.1470716782 |
|
|
Feb 08 06:58:09 PM UTC 25 |
Feb 08 06:58:13 PM UTC 25 |
110864872 ps |
| T712 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.549071524 |
|
|
Feb 08 06:58:09 PM UTC 25 |
Feb 08 06:58:14 PM UTC 25 |
34036549 ps |
| T713 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1346455933 |
|
|
Feb 08 06:58:08 PM UTC 25 |
Feb 08 06:58:14 PM UTC 25 |
208065614 ps |
| T714 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.4217266049 |
|
|
Feb 08 06:58:10 PM UTC 25 |
Feb 08 06:58:15 PM UTC 25 |
333350918 ps |
| T715 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.912269521 |
|
|
Feb 08 06:59:13 PM UTC 25 |
Feb 08 06:59:43 PM UTC 25 |
16550052470 ps |
| T295 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.4083370200 |
|
|
Feb 08 06:55:35 PM UTC 25 |
Feb 08 06:58:17 PM UTC 25 |
9784769416 ps |
| T716 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3430404273 |
|
|
Feb 08 06:58:10 PM UTC 25 |
Feb 08 06:58:17 PM UTC 25 |
637328129 ps |
| T717 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.801707186 |
|
|
Feb 08 06:57:26 PM UTC 25 |
Feb 08 06:58:20 PM UTC 25 |
2533051237 ps |
| T718 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.3284769312 |
|
|
Feb 08 06:58:18 PM UTC 25 |
Feb 08 06:58:20 PM UTC 25 |
20089822 ps |
| T377 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.898312245 |
|
|
Feb 08 06:58:13 PM UTC 25 |
Feb 08 06:58:23 PM UTC 25 |
3959695576 ps |
| T719 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.2414075803 |
|
|
Feb 08 06:58:21 PM UTC 25 |
Feb 08 06:58:23 PM UTC 25 |
19632632 ps |
| T720 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1030638803 |
|
|
Feb 08 06:58:08 PM UTC 25 |
Feb 08 06:58:24 PM UTC 25 |
3141126771 ps |
| T721 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.1976484562 |
|
|
Feb 08 06:58:14 PM UTC 25 |
Feb 08 06:58:25 PM UTC 25 |
1956085488 ps |
| T722 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.1896525691 |
|
|
Feb 08 06:58:24 PM UTC 25 |
Feb 08 06:58:26 PM UTC 25 |
12944506 ps |
| T723 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3360536944 |
|
|
Feb 08 06:57:40 PM UTC 25 |
Feb 08 06:58:28 PM UTC 25 |
3420327266 ps |
| T724 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3273330920 |
|
|
Feb 08 06:54:00 PM UTC 25 |
Feb 08 06:58:29 PM UTC 25 |
43943016570 ps |
| T181 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.938798591 |
|
|
Feb 08 06:47:45 PM UTC 25 |
Feb 08 06:58:29 PM UTC 25 |
319398349341 ps |
| T725 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.2833400224 |
|
|
Feb 08 06:58:24 PM UTC 25 |
Feb 08 06:58:31 PM UTC 25 |
1999592905 ps |
| T726 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.3681174522 |
|
|
Feb 08 06:58:25 PM UTC 25 |
Feb 08 06:58:32 PM UTC 25 |
405429408 ps |
| T354 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.3394048787 |
|
|
Feb 08 06:51:12 PM UTC 25 |
Feb 08 06:58:32 PM UTC 25 |
179641308009 ps |
| T727 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2841323633 |
|
|
Feb 08 06:58:32 PM UTC 25 |
Feb 08 06:58:36 PM UTC 25 |
189106267 ps |
| T728 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3017244881 |
|
|
Feb 08 06:58:21 PM UTC 25 |
Feb 08 06:58:37 PM UTC 25 |
2302658347 ps |
| T729 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.631454556 |
|
|
Feb 08 06:57:34 PM UTC 25 |
Feb 08 06:58:38 PM UTC 25 |
25028747433 ps |
| T255 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.608187526 |
|
|
Feb 08 06:57:38 PM UTC 25 |
Feb 08 06:58:39 PM UTC 25 |
1512391837 ps |
| T730 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.1517577229 |
|
|
Feb 08 06:58:31 PM UTC 25 |
Feb 08 06:58:40 PM UTC 25 |
1061789351 ps |
| T731 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3528073749 |
|
|
Feb 08 06:58:28 PM UTC 25 |
Feb 08 06:58:41 PM UTC 25 |
543153338 ps |
| T732 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2692358348 |
|
|
Feb 08 06:58:26 PM UTC 25 |
Feb 08 06:58:43 PM UTC 25 |
4483004980 ps |
| T733 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1003099651 |
|
|
Feb 08 06:58:37 PM UTC 25 |
Feb 08 06:58:43 PM UTC 25 |
442177028 ps |
| T734 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2568451564 |
|
|
Feb 08 06:58:42 PM UTC 25 |
Feb 08 06:58:44 PM UTC 25 |
20250257 ps |
| T735 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.1662236282 |
|
|
Feb 08 06:58:43 PM UTC 25 |
Feb 08 06:58:46 PM UTC 25 |
56032035 ps |
| T736 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.457297924 |
|
|
Feb 08 06:58:27 PM UTC 25 |
Feb 08 06:58:47 PM UTC 25 |
1682176108 ps |
| T737 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.1677592372 |
|
|
Feb 08 06:58:46 PM UTC 25 |
Feb 08 06:58:49 PM UTC 25 |
147328969 ps |
| T738 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2321787112 |
|
|
Feb 08 06:57:55 PM UTC 25 |
Feb 08 06:58:50 PM UTC 25 |
14735959739 ps |
| T739 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.2049825994 |
|
|
Feb 08 06:58:05 PM UTC 25 |
Feb 08 06:58:51 PM UTC 25 |
7122828318 ps |
| T740 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.492973470 |
|
|
Feb 08 06:58:48 PM UTC 25 |
Feb 08 06:58:51 PM UTC 25 |
162353139 ps |
| T355 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1697782567 |
|
|
Feb 08 06:57:07 PM UTC 25 |
Feb 08 06:58:51 PM UTC 25 |
37693107740 ps |
| T741 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2908217881 |
|
|
Feb 08 06:58:16 PM UTC 25 |
Feb 08 06:58:54 PM UTC 25 |
5038247283 ps |
| T742 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3630554929 |
|
|
Feb 08 06:57:50 PM UTC 25 |
Feb 08 06:58:57 PM UTC 25 |
7697395135 ps |
| T347 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.2030625254 |
|
|
Feb 08 06:52:21 PM UTC 25 |
Feb 08 06:58:58 PM UTC 25 |
90746347796 ps |
| T743 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.1184432643 |
|
|
Feb 08 06:58:50 PM UTC 25 |
Feb 08 06:59:04 PM UTC 25 |
2228648101 ps |
| T744 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.685436928 |
|
|
Feb 08 06:58:44 PM UTC 25 |
Feb 08 06:59:07 PM UTC 25 |
11430513832 ps |
| T182 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.2520007300 |
|
|
Feb 08 06:56:21 PM UTC 25 |
Feb 08 06:59:09 PM UTC 25 |
60868660813 ps |
| T745 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.195437327 |
|
|
Feb 08 06:58:45 PM UTC 25 |
Feb 08 06:59:09 PM UTC 25 |
2644495473 ps |
| T746 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.298588486 |
|
|
Feb 08 06:58:52 PM UTC 25 |
Feb 08 06:59:09 PM UTC 25 |
1124512349 ps |
| T747 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1569890810 |
|
|
Feb 08 06:59:05 PM UTC 25 |
Feb 08 06:59:11 PM UTC 25 |
389395355 ps |
| T748 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.300714335 |
|
|
Feb 08 06:59:10 PM UTC 25 |
Feb 08 06:59:12 PM UTC 25 |
22217952 ps |
| T358 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1537817791 |
|
|
Feb 08 06:52:22 PM UTC 25 |
Feb 08 06:59:12 PM UTC 25 |
70314642274 ps |
| T749 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1913029317 |
|
|
Feb 08 06:57:42 PM UTC 25 |
Feb 08 06:59:13 PM UTC 25 |
24764687183 ps |
| T750 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1335878817 |
|
|
Feb 08 06:58:52 PM UTC 25 |
Feb 08 06:59:13 PM UTC 25 |
5342444235 ps |
| T751 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.3216184256 |
|
|
Feb 08 06:58:58 PM UTC 25 |
Feb 08 06:59:13 PM UTC 25 |
1975090233 ps |
| T752 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2854172487 |
|
|
Feb 08 06:58:55 PM UTC 25 |
Feb 08 06:59:13 PM UTC 25 |
15584975760 ps |
| T753 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.4264849207 |
|
|
Feb 08 06:59:12 PM UTC 25 |
Feb 08 06:59:14 PM UTC 25 |
94069027 ps |
| T754 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2951213410 |
|
|
Feb 08 06:59:13 PM UTC 25 |
Feb 08 06:59:15 PM UTC 25 |
19982531 ps |
| T755 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.4154150457 |
|
|
Feb 08 06:59:13 PM UTC 25 |
Feb 08 06:59:16 PM UTC 25 |
18450299 ps |
| T756 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.536980094 |
|
|
Feb 08 06:58:14 PM UTC 25 |
Feb 08 06:59:17 PM UTC 25 |
15886818309 ps |
| T757 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.321514708 |
|
|
Feb 08 06:57:58 PM UTC 25 |
Feb 08 06:59:18 PM UTC 25 |
2936261108 ps |
| T758 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.1153571648 |
|
|
Feb 08 06:59:13 PM UTC 25 |
Feb 08 06:59:19 PM UTC 25 |
286385860 ps |
| T759 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2830970749 |
|
|
Feb 08 06:58:33 PM UTC 25 |
Feb 08 06:59:20 PM UTC 25 |
13584103623 ps |
| T760 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.2753001695 |
|
|
Feb 08 06:58:30 PM UTC 25 |
Feb 08 06:59:21 PM UTC 25 |
3078341359 ps |
| T761 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.2321665721 |
|
|
Feb 08 06:59:17 PM UTC 25 |
Feb 08 06:59:21 PM UTC 25 |
134532002 ps |
| T762 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1308082674 |
|
|
Feb 08 06:58:40 PM UTC 25 |
Feb 08 06:59:21 PM UTC 25 |
1836365664 ps |
| T763 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3418262418 |
|
|
Feb 08 06:59:18 PM UTC 25 |
Feb 08 06:59:22 PM UTC 25 |
194812511 ps |
| T373 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.483832839 |
|
|
Feb 08 06:57:07 PM UTC 25 |
Feb 08 06:59:25 PM UTC 25 |
6839766778 ps |
| T764 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.2501478944 |
|
|
Feb 08 06:58:52 PM UTC 25 |
Feb 08 06:59:25 PM UTC 25 |
13995383920 ps |
| T765 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.3549680083 |
|
|
Feb 08 06:59:15 PM UTC 25 |
Feb 08 06:59:26 PM UTC 25 |
696880133 ps |
| T766 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.1157745835 |
|
|
Feb 08 06:59:25 PM UTC 25 |
Feb 08 06:59:27 PM UTC 25 |
57087259 ps |
| T767 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.3061690050 |
|
|
Feb 08 06:59:26 PM UTC 25 |
Feb 08 06:59:28 PM UTC 25 |
15835472 ps |
| T768 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.3616067077 |
|
|
Feb 08 06:59:21 PM UTC 25 |
Feb 08 06:59:30 PM UTC 25 |
927662841 ps |
| T351 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.3504880440 |
|
|
Feb 08 06:55:39 PM UTC 25 |
Feb 08 06:59:31 PM UTC 25 |
29637840105 ps |
| T769 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3592194910 |
|
|
Feb 08 06:59:29 PM UTC 25 |
Feb 08 06:59:32 PM UTC 25 |
23645433 ps |
| T770 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1160629195 |
|
|
Feb 08 06:51:41 PM UTC 25 |
Feb 08 06:59:32 PM UTC 25 |
48468138834 ps |
| T367 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2871774876 |
|
|
Feb 08 06:59:14 PM UTC 25 |
Feb 08 06:59:34 PM UTC 25 |
24547038158 ps |
| T771 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.584109863 |
|
|
Feb 08 06:59:31 PM UTC 25 |
Feb 08 06:59:36 PM UTC 25 |
208334308 ps |
| T772 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1530174295 |
|
|
Feb 08 06:59:14 PM UTC 25 |
Feb 08 06:59:37 PM UTC 25 |
22733860198 ps |
| T773 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.330737868 |
|
|
Feb 08 06:59:30 PM UTC 25 |
Feb 08 06:59:40 PM UTC 25 |
915660614 ps |
| T774 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1760684935 |
|
|
Feb 08 06:58:51 PM UTC 25 |
Feb 08 06:59:42 PM UTC 25 |
11163002802 ps |
| T775 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2540205111 |
|
|
Feb 08 06:59:38 PM UTC 25 |
Feb 08 06:59:46 PM UTC 25 |
2033269887 ps |
| T776 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.3806899510 |
|
|
Feb 08 06:59:19 PM UTC 25 |
Feb 08 06:59:48 PM UTC 25 |
2432982916 ps |
| T777 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2709519027 |
|
|
Feb 08 06:59:33 PM UTC 25 |
Feb 08 06:59:48 PM UTC 25 |
928828361 ps |
| T778 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.4294474764 |
|
|
Feb 08 06:58:15 PM UTC 25 |
Feb 08 06:59:49 PM UTC 25 |
130700424899 ps |
| T779 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.997447784 |
|
|
Feb 08 06:59:44 PM UTC 25 |
Feb 08 06:59:51 PM UTC 25 |
118703374 ps |
| T780 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.2580205456 |
|
|
Feb 08 06:59:41 PM UTC 25 |
Feb 08 06:59:52 PM UTC 25 |
399460535 ps |
| T781 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.2405420458 |
|
|
Feb 08 06:59:37 PM UTC 25 |
Feb 08 06:59:52 PM UTC 25 |
404965864 ps |
| T782 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.1790132995 |
|
|
Feb 08 06:59:10 PM UTC 25 |
Feb 08 06:59:52 PM UTC 25 |
5641942759 ps |
| T783 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1787151315 |
|
|
Feb 08 06:59:50 PM UTC 25 |
Feb 08 06:59:53 PM UTC 25 |
447043557 ps |
| T784 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2182927231 |
|
|
Feb 08 06:59:52 PM UTC 25 |
Feb 08 06:59:54 PM UTC 25 |
12363968 ps |
| T785 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.2294705907 |
|
|
Feb 08 06:59:33 PM UTC 25 |
Feb 08 06:59:56 PM UTC 25 |
1922858612 ps |
| T786 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.401346262 |
|
|
Feb 08 06:57:55 PM UTC 25 |
Feb 08 06:59:56 PM UTC 25 |
41208315641 ps |
| T787 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.3573208634 |
|
|
Feb 08 06:59:54 PM UTC 25 |
Feb 08 06:59:56 PM UTC 25 |
15511810 ps |
| T788 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2768535155 |
|
|
Feb 08 06:59:54 PM UTC 25 |
Feb 08 06:59:56 PM UTC 25 |
164781290 ps |
| T789 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1951406552 |
|
|
Feb 08 06:59:27 PM UTC 25 |
Feb 08 06:59:56 PM UTC 25 |
21329581361 ps |
| T790 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.2644268433 |
|
|
Feb 08 06:59:56 PM UTC 25 |
Feb 08 06:59:58 PM UTC 25 |
13805080 ps |
| T791 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.127280015 |
|
|
Feb 08 06:59:54 PM UTC 25 |
Feb 08 07:00:01 PM UTC 25 |
621447916 ps |
| T792 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.81455273 |
|
|
Feb 08 06:59:07 PM UTC 25 |
Feb 08 07:00:02 PM UTC 25 |
3250750544 ps |
| T45 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1949931240 |
|
|
Feb 08 06:58:02 PM UTC 25 |
Feb 08 07:00:03 PM UTC 25 |
68361685388 ps |
| T793 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1523817703 |
|
|
Feb 08 06:58:00 PM UTC 25 |
Feb 08 07:00:03 PM UTC 25 |
10696664348 ps |
| T794 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3062029544 |
|
|
Feb 08 06:59:56 PM UTC 25 |
Feb 08 07:00:04 PM UTC 25 |
571488289 ps |
| T795 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1466747581 |
|
|
Feb 08 06:59:28 PM UTC 25 |
Feb 08 07:00:04 PM UTC 25 |
6698425346 ps |
| T796 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3639123399 |
|
|
Feb 08 06:59:56 PM UTC 25 |
Feb 08 07:00:04 PM UTC 25 |
563276488 ps |
| T797 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3876323101 |
|
|
Feb 08 06:59:35 PM UTC 25 |
Feb 08 07:00:06 PM UTC 25 |
11741983228 ps |
| T798 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2375201352 |
|
|
Feb 08 06:59:20 PM UTC 25 |
Feb 08 07:00:08 PM UTC 25 |
1402014828 ps |
| T799 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.2726732629 |
|
|
Feb 08 06:59:54 PM UTC 25 |
Feb 08 07:00:10 PM UTC 25 |
2172167591 ps |
| T800 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.533549099 |
|
|
Feb 08 06:59:58 PM UTC 25 |
Feb 08 07:00:17 PM UTC 25 |
6048790621 ps |
| T801 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3190236711 |
|
|
Feb 08 06:59:22 PM UTC 25 |
Feb 08 07:00:18 PM UTC 25 |
8009926887 ps |
| T802 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2279317674 |
|
|
Feb 08 06:59:58 PM UTC 25 |
Feb 08 07:00:20 PM UTC 25 |
12629337232 ps |
| T803 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.2380615644 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:22 PM UTC 25 |
12888093 ps |
| T804 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.1868326314 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:22 PM UTC 25 |
20875528 ps |
| T805 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.603944600 |
|
|
Feb 08 06:56:44 PM UTC 25 |
Feb 08 07:00:22 PM UTC 25 |
47068195557 ps |
| T806 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1698475413 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:22 PM UTC 25 |
322852049 ps |
| T807 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.795381831 |
|
|
Feb 08 07:00:01 PM UTC 25 |
Feb 08 07:00:23 PM UTC 25 |
214786026 ps |
| T808 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.1651344041 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:25 PM UTC 25 |
124772477 ps |
| T809 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3703363706 |
|
|
Feb 08 06:59:50 PM UTC 25 |
Feb 08 07:00:25 PM UTC 25 |
10569796618 ps |
| T810 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1603982525 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:26 PM UTC 25 |
3053910212 ps |
| T811 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.757158092 |
|
|
Feb 08 06:59:08 PM UTC 25 |
Feb 08 07:00:27 PM UTC 25 |
4056348106 ps |
| T812 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.3857062093 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:29 PM UTC 25 |
2316279052 ps |
| T813 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3393265084 |
|
|
Feb 08 06:59:49 PM UTC 25 |
Feb 08 07:00:30 PM UTC 25 |
2385318845 ps |
| T368 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.611055164 |
|
|
Feb 08 06:55:06 PM UTC 25 |
Feb 08 07:00:30 PM UTC 25 |
643773470653 ps |
| T814 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.676947518 |
|
|
Feb 08 07:00:24 PM UTC 25 |
Feb 08 07:00:30 PM UTC 25 |
171794356 ps |
| T815 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.257428712 |
|
|
Feb 08 07:00:03 PM UTC 25 |
Feb 08 07:00:31 PM UTC 25 |
1710556408 ps |
| T816 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.1097583270 |
|
|
Feb 08 07:00:31 PM UTC 25 |
Feb 08 07:00:34 PM UTC 25 |
39353358 ps |
| T817 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2846160540 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:34 PM UTC 25 |
1219328689 ps |
| T46 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3374544124 |
|
|
Feb 08 06:54:28 PM UTC 25 |
Feb 08 07:00:34 PM UTC 25 |
62634296148 ps |
| T818 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.695660378 |
|
|
Feb 08 07:00:24 PM UTC 25 |
Feb 08 07:00:36 PM UTC 25 |
648933743 ps |
| T819 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.2801144843 |
|
|
Feb 08 07:00:33 PM UTC 25 |
Feb 08 07:00:36 PM UTC 25 |
109053102 ps |
| T820 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.1502778024 |
|
|
Feb 08 07:00:35 PM UTC 25 |
Feb 08 07:00:37 PM UTC 25 |
86370521 ps |
| T821 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.2812087312 |
|
|
Feb 08 07:00:36 PM UTC 25 |
Feb 08 07:00:39 PM UTC 25 |
98653205 ps |
| T822 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.377846688 |
|
|
Feb 08 07:00:24 PM UTC 25 |
Feb 08 07:00:41 PM UTC 25 |
3283185616 ps |
| T823 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3585472655 |
|
|
Feb 08 07:00:37 PM UTC 25 |
Feb 08 07:00:41 PM UTC 25 |
275522064 ps |
| T824 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.486992764 |
|
|
Feb 08 07:00:24 PM UTC 25 |
Feb 08 07:00:42 PM UTC 25 |
4294671545 ps |
| T825 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1812715768 |
|
|
Feb 08 07:00:37 PM UTC 25 |
Feb 08 07:00:42 PM UTC 25 |
188706841 ps |
| T826 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.1571494539 |
|
|
Feb 08 07:00:19 PM UTC 25 |
Feb 08 07:00:43 PM UTC 25 |
4952898760 ps |
| T827 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2639569526 |
|
|
Feb 08 06:58:58 PM UTC 25 |
Feb 08 07:00:44 PM UTC 25 |
15432347516 ps |
| T828 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.2283437098 |
|
|
Feb 08 07:00:24 PM UTC 25 |
Feb 08 07:00:45 PM UTC 25 |
1005469474 ps |
| T829 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3439712959 |
|
|
Feb 08 07:00:27 PM UTC 25 |
Feb 08 07:00:46 PM UTC 25 |
3423880701 ps |
| T830 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2543555092 |
|
|
Feb 08 07:00:27 PM UTC 25 |
Feb 08 07:00:46 PM UTC 25 |
3079275501 ps |
| T259 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1586880695 |
|
|
Feb 08 07:00:38 PM UTC 25 |
Feb 08 07:00:46 PM UTC 25 |
991526516 ps |
| T183 |
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2947001964 |
|
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Feb 08 06:58:41 PM UTC 25 |
Feb 08 07:00:49 PM UTC 25 |
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