SPI_DEVICE/2P Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.133m	101.646ms	48	50	96.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	83.051us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	121.382us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.620s	7.550ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.400s	935.729us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.980s	650.912us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	121.382us	20	20	100.00
		spi_device_csr_aliasing	24.400s	935.729us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	12.280us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.250s	68.579us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	csb_read	spi_device_csb_read	0.850s	29.486us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	66.277us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	14.637us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	19.860s	2.150ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	19.860s	2.150ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.690s	50.740ms	50	50	100.00
		spi_device_tpm_sts_read	1.220s	183.370us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.357m	14.139ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.180s	28.652ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.400s	59.236ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.400s	59.236ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	cmd_info_slots	spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	cmd_read_status	spi_device_intercept	15.950s	4.865ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	cmd_read_jedec	spi_device_intercept	15.950s	4.865ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	cmd_read_sfdp	spi_device_intercept	15.950s	4.865ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	cmd_fast_read	spi_device_intercept	15.950s	4.865ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	cmd_read_pipeline	spi_device_intercept	15.950s	4.865ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	flash_cmd_upload	spi_device_upload	45.450s	55.872ms	49	50	98.00
V2	mailbox_command	spi_device_mailbox	44.320s	15.056ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	44.320s	15.056ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	44.320s	15.056ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.121m	91.848ms	50	50	100.00
		spi_device_read_buffer_direct	7.490s	1.740ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	44.320s	15.056ms	50	50	100.00
		spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	quad_spi	spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	dual_spi	spi_device_flash_all	9.341m	109.735ms	48	50	96.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.580s	7.266ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.580s	7.266ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.133m	101.646ms	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.589m	95.205ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.418m	136.320ms	48	50	96.00
V2	alert_test	spi_device_alert_test	0.800s	43.381us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	12.874us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.970s	209.012us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.970s	209.012us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	83.051us	5	5	100.00
		spi_device_csr_rw	2.860s	121.382us	20	20	100.00
		spi_device_csr_aliasing	24.400s	935.729us	5	5	100.00
		spi_device_same_csr_outstanding	4.370s	581.109us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	83.051us	5	5	100.00
		spi_device_csr_rw	2.860s	121.382us	20	20	100.00
		spi_device_csr_aliasing	24.400s	935.729us	5	5	100.00
		spi_device_same_csr_outstanding	4.370s	581.109us	20	20	100.00
V2		TOTAL			975	980	99.49
V2S	tl_intg_err	spi_device_sec_cm	1.240s	329.660us	5	5	100.00
		spi_device_tl_intg_err	23.420s	1.069ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.420s	1.069ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1113	1120	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	98.37	94.16	98.61	89.36	97.10	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_all has 1 failures.

1.spi_device_flash_all.52642108016057173391434807985935315441803979265815319175492027657641432455449
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 6470543368 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe387c0) != exp '{'{other_status:'h32ced7, wel:'h0, busy:'h0}}
  UVM_INFO @ 8590191368 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/9
  UVM_INFO @ 11393849368 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/9
  UVM_INFO @ 13713662368 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/9
  UVM_INFO @ 15692053368 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/9

Test spi_device_flash_and_tpm has 1 failures.

1.spi_device_flash_and_tpm.45401335410926917243040535344671320888805475527665833794965217594110638349953
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 46093389958 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb9c23c) != exp '{'{other_status:'h2e708f, wel:'h1, busy:'h0}}
  UVM_INFO @ 46289769958 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/17
  UVM_INFO @ 48305464958 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/16
  UVM_INFO @ 55598909958 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/17
  UVM_INFO @ 57352669958 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/16

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_upload_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_upload has 1 failures.

0.spi_device_upload.44576044186714841049647232645267378389638730076908053931178743348066738755951
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_upload/latest/run.log

  UVM_ERROR @ 360083330 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 369892420 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 10, test op = 0x1
  UVM_INFO @ 430540616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1101) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_stress_all has 1 failures.

9.spi_device_stress_all.105557879032333311144356627723039847732900279911809249439747737513480945688940
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 25653783229 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 25693004229 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/11
  UVM_INFO @ 25742243229 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/15
  UVM_INFO @ 29583487229 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/11
  UVM_INFO @ 29624963229 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/15

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.addr_mode' is being accessed has 1 failures:

Test spi_device_stress_all has 1 failures.

13.spi_device_stress_all.70686583815150459798989365203113065489047431907513447867407512026509621498907
Line 301, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 78933342890 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.addr_mode' is being accessed
  UVM_INFO @ 79318610838 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/20
  UVM_INFO @ 79359176753 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/18
  UVM_INFO @ 81451295522 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/20
  UVM_INFO @ 81828872322 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/18

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm has 1 failures.
  - 27.spi_device_flash_and_tpm.102984528868330623063135759409445884999135457505662640083213926438412489757135
    Line 276, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:478) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 1 failures:

Test spi_device_flash_all has 1 failures.

43.spi_device_flash_all.98746227332858886490355425631150948676544183075235713823695687811765923147415
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 228647245269 ps: (spi_device_scoreboard.sv:478) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 263151948321 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/12
  UVM_INFO @ 294240127122 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/12
  UVM_INFO @ 322928928544 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/12
  UVM_INFO @ 366490385204 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/12