SPI_HOST Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.167m	106.842ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	101.056us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	40.657us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	639.289us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	65.720us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	32.798us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	40.657us	20	20	100.00
		spi_host_csr_aliasing	2.000s	65.720us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	34.420us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	18.129us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	4.000s	49.315us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.750m	3.639ms	50	50	100.00
		spi_host_error_cmd	4.000s	18.484us	50	50	100.00
		spi_host_event	20.367m	28.976ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.050m	27.323ms	50	50	100.00
V2	speed	spi_host_speed	5.050m	27.323ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.050m	27.323ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	2.817m	5.071ms	45	50	90.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	739.328us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.050m	27.323ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.050m	27.323ms	50	50	100.00
V2	duplex	spi_host_smoke	10.167m	106.842ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.167m	106.842ms	49	50	98.00
V2	stress_all	spi_host_stress_all	2.250m	12.194ms	48	50	96.00
V2	spien	spi_host_spien	6.900m	18.631ms	50	50	100.00
V2	stall	spi_host_status_stall	11.883m	24.991ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.300m	6.662ms	48	50	96.00
V2	alert_test	spi_host_alert_test	3.000s	27.169us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	38.922us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	220.653us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	220.653us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	101.056us	5	5	100.00
		spi_host_csr_rw	4.000s	40.657us	20	20	100.00
		spi_host_csr_aliasing	2.000s	65.720us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	34.344us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	101.056us	5	5	100.00
		spi_host_csr_rw	4.000s	40.657us	20	20	100.00
		spi_host_csr_aliasing	2.000s	65.720us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	34.344us	20	20	100.00
V2		TOTAL			679	690	98.41
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	46.022us	20	20	100.00
		spi_host_sec_cm	4.000s	238.444us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	46.022us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			818	830	98.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	98.19	95.98	99.74	96.16	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:

Test spi_host_smoke has 1 failures.

33.spi_host_smoke.3619026481
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_smoke/latest/run.log

  UVM_FATAL @ 103278142650 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd53bcb94) == 0x0
  UVM_INFO @ 103278142650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_idlecsbactive has 1 failures.

41.spi_host_idlecsbactive.3223755067
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_idlecsbactive/latest/run.log

  UVM_FATAL @ 10044221212 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x28fd2f94) == 0x0
  UVM_INFO @ 10044221212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_stress_all has 2 failures.

46.spi_host_stress_all.381077850
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 18277580838 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6f4a5954) == 0x0
  UVM_INFO @ 18277580838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.spi_host_stress_all.3543859456
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 18164506686 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x31de2c94) == 0x0
  UVM_INFO @ 18164506686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_sw_reset has 1 failures.

47.spi_host_sw_reset.4172389417
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 19826558545 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3731f1d4) == 0x0
  UVM_INFO @ 19826558545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 3 failures:

Test spi_host_sw_reset has 3 failures.

1.spi_host_sw_reset.1421791610
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 11391993197 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2d2a1f14) == 0x0
  UVM_INFO @ 11391993197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.spi_host_sw_reset.3576617250
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10004658946 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbb0ef754) == 0x0
  UVM_INFO @ 10004658946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_idlecsbactive has 1 failures.
  - 21.spi_host_idlecsbactive.3007836989
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10059845888 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7b70e3d4) == 0x0
  UVM_INFO @ 10059845888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 27.spi_host_status_stall.4249952674
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_sw_reset has 1 failures.
  - 36.spi_host_sw_reset.1822114207
    Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 11585728005 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x53dcf714) == 0x0
  UVM_INFO @ 11585728005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 48.spi_host_status_stall.1777789096
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```