93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.183m | 23.348ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 21.572us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 19.272us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 6.000s | 459.922us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 49.556us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 5.000s | 112.031us | 4 | 20 | 20.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 19.272us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 49.556us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 16.718us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 18.624us | 5 | 5 | 100.00 |
| V1 | TOTAL | 96 | 115 | 83.48 | |||
| V2 | performance | spi_host_performance | 4.000s | 41.836us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.017m | 7.802ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 27.796us | 50 | 50 | 100.00 | ||
| spi_host_event | 24.700m | 34.668ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 7.133m | 76.402ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 7.133m | 76.402ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 7.133m | 76.402ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 4.567m | 10.229ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 9.000s | 359.295us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 7.133m | 76.402ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 7.133m | 76.402ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 9.183m | 23.348ms | 47 | 50 | 94.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.183m | 23.348ms | 47 | 50 | 94.00 |
| V2 | stress_all | spi_host_stress_all | 4.167m | 8.486ms | 47 | 50 | 94.00 |
| V2 | spien | spi_host_spien | 6.917m | 35.939ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 10.250m | 56.582ms | 45 | 50 | 90.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 38.000s | 1.406ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 4.000s | 16.486us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 21.155us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 117.884us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 117.884us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 21.572us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.272us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 49.556us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 18.413us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 21.572us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.272us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 49.556us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 18.413us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 682 | 690 | 98.84 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 462.761us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 67.823us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 462.761us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 803 | 830 | 96.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 6 | 75.00 |
| V2 | 15 | 15 | 13 | 86.67 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.08 | 98.13 | 95.98 | 99.73 | 96.70 | 95.70 | 100.00 | 98.60 | 90.87 |
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [spi_host_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 9 failures:
2.spi_host_csr_mem_rw_with_rand_reset.18494512030301113662711803135372435784365617838286044320736443608945406584794
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 19071309 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.spi_host_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 19071309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_csr_mem_rw_with_rand_reset.105927860108512727261770478860996867829627237632837535266452681299802104438267
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 29482769 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.spi_host_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 29482769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (cip_base_vseq.sv:757) [spi_host_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 7 failures:
0.spi_host_csr_mem_rw_with_rand_reset.78682159158031194165444663280200385234117298466586854759181683288799453080329
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 19154945 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.spi_host_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 19154945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_csr_mem_rw_with_rand_reset.114683856379839029988336141362782658683729687940879850837210224455231589622766
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 38943305 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.spi_host_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 38943305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
Test spi_host_smoke has 2 failures.
4.spi_host_smoke.24820697805269125748227148495917539542678695737558573848557469398832950941696
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 96938768687 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x429e17d4) == 0x0
UVM_INFO @ 96938768687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_smoke.94545395473597502283774707576093898334631602114404101913635321651512319403642
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_smoke/latest/run.log
UVM_FATAL @ 100149724526 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8032bcd4) == 0x0
UVM_INFO @ 100149724526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
12.spi_host_status_stall.74008723872073103191718685507216795104496136220366765005974165240128676459810
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_FATAL @ 62632154015 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1abe7614) == 0x0
UVM_INFO @ 62632154015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 2 failures.
30.spi_host_stress_all.41054600612634703859782940269052628209563305633132674274532078332659880246679
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_stress_all/latest/run.log
UVM_FATAL @ 13465262211 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xdf179354) == 0x0
UVM_INFO @ 13465262211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.spi_host_stress_all.11106030431855975037271413757408481226881477577488671839697852741758980119373
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_stress_all/latest/run.log
UVM_FATAL @ 17675313461 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa129bb14) == 0x0
UVM_INFO @ 17675313461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
35.spi_host_status_stall.72273326819511833527367966408833211723028960497006188876806522090846174725559
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_status_stall/latest/run.log
UVM_FATAL @ 16687766438 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6953d314) == 0x1
UVM_INFO @ 16687766438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_status_stall.70067326655711980351745113645123907764922058635805135501100765859626332424302
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
UVM_FATAL @ 12634952856 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x21f61094) == 0x1
UVM_INFO @ 12634952856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.spi_host_smoke.69934852741389127330113606276229617537430364249295755914835930866194181475980
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
10.spi_host_status_stall.111391942411380759065988915779322993101807663965674388230875304814024285323162
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 13307579496 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x39f18c14) == 0x1
UVM_INFO @ 13307579496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
15.spi_host_stress_all.56106913800095613640939272378767911470686645096839484179411784638231986106574
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_stress_all/latest/run.log
UVM_FATAL @ 11602094314 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xaf591594) == 0x0
UVM_INFO @ 11602094314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
33.spi_host_status_stall.13721941715622847486495507766693617295992124679171356395872773921265277669379
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_FATAL @ 105657022006 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6c16f554) == 0x0
UVM_INFO @ 105657022006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---