SRAM_CTRL/MAIN Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.731m	1.659ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.790s	36.690us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	25.200us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.870s	112.949us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	19.586us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.110s	5.919ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	25.200us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	19.586us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.354m	42.103ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.745m	6.547ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.841m	9.258ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.957m	11.655ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.871m	638.303ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	39.000m	21.246ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	32.575m	193.453ms	47	50	94.00
V2	executable	sram_ctrl_executable	40.443m	78.456ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.723m	886.473us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.113m	51.370ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.708m	3.179ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.921m	818.171us	50	50	100.00
V2	regwen	sram_ctrl_regwen	36.020m	300.861ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.440s	3.365ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.801h	467.854ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.760s	13.032us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.900s	536.105us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.900s	536.105us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.790s	36.690us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	25.200us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	19.586us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	89.092us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.790s	36.690us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	25.200us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	19.586us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	89.092us	20	20	100.00
V2		TOTAL			727	740	98.24
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	54.220s	7.130ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.160s	452.182us	5	5	100.00
		sram_ctrl_tl_intg_err	2.550s	288.170us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.160s	452.182us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.550s	288.170us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	36.020m	300.861ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	25.200us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.443m	78.456ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.443m	78.456ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.443m	78.456ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	32.575m	193.453ms	47	50	94.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	54.220s	7.130ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.731m	1.659ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.731m	1.659ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.443m	78.456ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.160s	452.182us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	32.575m	193.453ms	47	50	94.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.160s	452.182us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.160s	452.182us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.731m	1.659ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.160s	452.182us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.018m	6.935ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1026	1040	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	11	68.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	100.00	97.91	100.00	100.00	99.72	99.70	98.52

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:405) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 7 failures:

Test sram_ctrl_stress_all has 4 failures.

22.sram_ctrl_stress_all.51982912265778343152177461706348318365281700683516045697885434064892152081165
Line 366, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 13906250549 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 13906250549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.sram_ctrl_stress_all.80282222958640626396910040234566020888099815917772268207899360930355634107853
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 11261313203 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 11261313203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test sram_ctrl_lc_escalation has 3 failures.

29.sram_ctrl_lc_escalation.57651350853290893592303549346503064730423111062455025819847541108939318166332
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 7796643657 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 7796643657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.sram_ctrl_lc_escalation.1177306915627815479140674943127500034207238239719279741007190880516204850298
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 496625735 ps: (sram_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 496625735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 9.sram_ctrl_stress_all.73100202328957608035137517571128407077313212443450640346746010569563615522282
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 358961433 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 358961433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 41.sram_ctrl_stress_all.23348539069592930382840623021589112756613003732046714082161050672918025237869
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 1292364731 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 1292364731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 7.sram_ctrl_bijection.67126278575078603891989236062268637240607538285098191032113292479260220546735
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 16.sram_ctrl_executable.18608579962296548142517961529178767959408946881675650910390477953503700127581
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 49252191386 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xb393033e
  UVM_INFO @ 49252191386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 25.sram_ctrl_stress_all.18480500586143452692262837594589389572510474314953100916447380819224834771443
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest/run.log
```
      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 558262900 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 558262900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.sram_ctrl_stress_all_with_rand_reset.54069576936314822128793130718103699159208708166058503888355554118061993251233
    Line 319, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6113648215 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6113648215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 49.sram_ctrl_regwen.33216450261285085670679752770658358187101532998208424612807139853934687950270
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 53299777109 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x35f698
  UVM_INFO @ 53299777109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```