| T306 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3117387786 |
|
|
Sep 18 10:37:13 AM UTC 24 |
Sep 18 10:38:55 AM UTC 24 |
3643530469 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.934511225 |
|
|
Sep 18 10:32:03 AM UTC 24 |
Sep 18 10:38:59 AM UTC 24 |
5814898967 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3835059187 |
|
|
Sep 18 10:38:37 AM UTC 24 |
Sep 18 10:39:00 AM UTC 24 |
4784668595 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2215143845 |
|
|
Sep 18 10:39:02 AM UTC 24 |
Sep 18 10:39:31 AM UTC 24 |
1587531749 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.4239804749 |
|
|
Sep 18 10:23:04 AM UTC 24 |
Sep 18 10:39:33 AM UTC 24 |
123588754950 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2024995719 |
|
|
Sep 18 10:37:12 AM UTC 24 |
Sep 18 10:39:41 AM UTC 24 |
39478649335 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1001079102 |
|
|
Sep 18 10:39:14 AM UTC 24 |
Sep 18 10:39:43 AM UTC 24 |
2763513046 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1185342991 |
|
|
Sep 18 10:38:59 AM UTC 24 |
Sep 18 10:39:47 AM UTC 24 |
6562078467 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.609455004 |
|
|
Sep 18 10:39:44 AM UTC 24 |
Sep 18 10:39:51 AM UTC 24 |
1412808593 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3572740075 |
|
|
Sep 18 10:37:33 AM UTC 24 |
Sep 18 10:40:01 AM UTC 24 |
1976777236 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.1551039517 |
|
|
Sep 18 10:22:15 AM UTC 24 |
Sep 18 10:40:14 AM UTC 24 |
100228827912 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.792396328 |
|
|
Sep 18 10:01:22 AM UTC 24 |
Sep 18 10:40:44 AM UTC 24 |
146281565125 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1026771458 |
|
|
Sep 18 10:40:45 AM UTC 24 |
Sep 18 10:40:47 AM UTC 24 |
100177601 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.531532769 |
|
|
Sep 18 10:32:22 AM UTC 24 |
Sep 18 10:40:49 AM UTC 24 |
19364570455 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3071976865 |
|
|
Sep 18 10:39:52 AM UTC 24 |
Sep 18 10:41:00 AM UTC 24 |
1015948046 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.2509442183 |
|
|
Sep 18 10:40:48 AM UTC 24 |
Sep 18 10:41:15 AM UTC 24 |
1185984807 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1942745134 |
|
|
Sep 18 10:40:02 AM UTC 24 |
Sep 18 10:41:40 AM UTC 24 |
26178791353 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.3709487413 |
|
|
Sep 18 10:29:51 AM UTC 24 |
Sep 18 10:41:46 AM UTC 24 |
41363930875 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1942133540 |
|
|
Sep 18 10:41:41 AM UTC 24 |
Sep 18 10:41:52 AM UTC 24 |
734510758 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3025725812 |
|
|
Sep 18 10:35:47 AM UTC 24 |
Sep 18 10:42:04 AM UTC 24 |
10777326428 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.465805938 |
|
|
Sep 18 10:41:52 AM UTC 24 |
Sep 18 10:42:04 AM UTC 24 |
4459887780 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1287487221 |
|
|
Sep 18 10:12:33 AM UTC 24 |
Sep 18 10:42:14 AM UTC 24 |
64599697649 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.272321833 |
|
|
Sep 18 10:42:04 AM UTC 24 |
Sep 18 10:42:42 AM UTC 24 |
728524334 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2014680671 |
|
|
Sep 18 10:35:54 AM UTC 24 |
Sep 18 10:42:54 AM UTC 24 |
22701890039 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3301935766 |
|
|
Sep 18 10:38:19 AM UTC 24 |
Sep 18 10:42:58 AM UTC 24 |
18236377479 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3805612325 |
|
|
Sep 18 10:42:59 AM UTC 24 |
Sep 18 10:43:05 AM UTC 24 |
715200905 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3307137660 |
|
|
Sep 18 10:36:49 AM UTC 24 |
Sep 18 10:43:44 AM UTC 24 |
3107073145 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2278858138 |
|
|
Sep 18 10:42:05 AM UTC 24 |
Sep 18 10:43:57 AM UTC 24 |
19384443765 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1271284955 |
|
|
Sep 18 10:42:55 AM UTC 24 |
Sep 18 10:44:46 AM UTC 24 |
1205938160 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1720102300 |
|
|
Sep 18 10:41:16 AM UTC 24 |
Sep 18 10:45:08 AM UTC 24 |
3470555322 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2702366067 |
|
|
Sep 18 10:45:09 AM UTC 24 |
Sep 18 10:45:11 AM UTC 24 |
15957974 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2240372415 |
|
|
Sep 18 10:31:41 AM UTC 24 |
Sep 18 10:45:15 AM UTC 24 |
9305373491 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3801554373 |
|
|
Sep 18 10:45:12 AM UTC 24 |
Sep 18 10:45:38 AM UTC 24 |
880895674 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.945679935 |
|
|
Sep 18 10:36:30 AM UTC 24 |
Sep 18 10:45:39 AM UTC 24 |
26726101133 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2425171234 |
|
|
Sep 18 10:19:48 AM UTC 24 |
Sep 18 10:45:41 AM UTC 24 |
28082389595 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.449490789 |
|
|
Sep 18 10:43:57 AM UTC 24 |
Sep 18 10:46:00 AM UTC 24 |
1883313692 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1982841713 |
|
|
Sep 18 10:45:42 AM UTC 24 |
Sep 18 10:46:13 AM UTC 24 |
1244842315 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.847744991 |
|
|
Sep 18 10:05:48 AM UTC 24 |
Sep 18 10:46:15 AM UTC 24 |
72582974160 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3475439413 |
|
|
Sep 18 10:02:36 AM UTC 24 |
Sep 18 10:46:33 AM UTC 24 |
115038789311 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1329688487 |
|
|
Sep 18 10:39:48 AM UTC 24 |
Sep 18 10:46:38 AM UTC 24 |
31469747916 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.668823483 |
|
|
Sep 18 10:43:45 AM UTC 24 |
Sep 18 10:46:45 AM UTC 24 |
9691540052 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3554572992 |
|
|
Sep 18 10:46:35 AM UTC 24 |
Sep 18 10:46:47 AM UTC 24 |
2892986903 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.2216453250 |
|
|
Sep 18 10:36:36 AM UTC 24 |
Sep 18 10:46:50 AM UTC 24 |
46447765064 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.3789034755 |
|
|
Sep 18 10:46:51 AM UTC 24 |
Sep 18 10:46:56 AM UTC 24 |
692885196 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2344592938 |
|
|
Sep 18 10:46:16 AM UTC 24 |
Sep 18 10:47:02 AM UTC 24 |
780616607 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3785117802 |
|
|
Sep 18 10:35:42 AM UTC 24 |
Sep 18 10:47:18 AM UTC 24 |
39653245017 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.4214286672 |
|
|
Sep 18 10:46:13 AM UTC 24 |
Sep 18 10:47:27 AM UTC 24 |
3003865022 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.2241956573 |
|
|
Sep 18 10:29:54 AM UTC 24 |
Sep 18 10:47:49 AM UTC 24 |
15087664159 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3723216674 |
|
|
Sep 18 10:47:50 AM UTC 24 |
Sep 18 10:47:52 AM UTC 24 |
30545691 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.3413684784 |
|
|
Sep 18 10:22:53 AM UTC 24 |
Sep 18 10:47:52 AM UTC 24 |
266383290249 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1572399047 |
|
|
Sep 18 10:47:18 AM UTC 24 |
Sep 18 10:48:04 AM UTC 24 |
3223612885 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2093354324 |
|
|
Sep 18 10:47:53 AM UTC 24 |
Sep 18 10:48:34 AM UTC 24 |
1749223306 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.276797503 |
|
|
Sep 18 10:38:56 AM UTC 24 |
Sep 18 10:48:38 AM UTC 24 |
72989769965 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.518981358 |
|
|
Sep 18 10:48:38 AM UTC 24 |
Sep 18 10:49:02 AM UTC 24 |
2201855797 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2759849468 |
|
|
Sep 18 10:35:29 AM UTC 24 |
Sep 18 10:49:12 AM UTC 24 |
17030910501 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.2609954970 |
|
|
Sep 18 10:39:42 AM UTC 24 |
Sep 18 10:49:13 AM UTC 24 |
17119236522 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4231754045 |
|
|
Sep 18 10:43:05 AM UTC 24 |
Sep 18 10:49:19 AM UTC 24 |
27677597168 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1557163082 |
|
|
Sep 18 10:49:20 AM UTC 24 |
Sep 18 10:49:38 AM UTC 24 |
4074959290 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1013970302 |
|
|
Sep 18 10:47:02 AM UTC 24 |
Sep 18 10:50:03 AM UTC 24 |
21803925977 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3158954017 |
|
|
Sep 18 10:49:12 AM UTC 24 |
Sep 18 10:50:06 AM UTC 24 |
737495731 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.2878331927 |
|
|
Sep 18 10:49:14 AM UTC 24 |
Sep 18 10:50:21 AM UTC 24 |
3191776493 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1082157967 |
|
|
Sep 18 10:50:21 AM UTC 24 |
Sep 18 10:50:29 AM UTC 24 |
4806186647 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1190758503 |
|
|
Sep 18 10:32:00 AM UTC 24 |
Sep 18 10:50:30 AM UTC 24 |
15533848167 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.200213664 |
|
|
Sep 18 10:39:34 AM UTC 24 |
Sep 18 10:50:37 AM UTC 24 |
17445082927 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1430991687 |
|
|
Sep 18 10:45:40 AM UTC 24 |
Sep 18 10:50:48 AM UTC 24 |
4564175286 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.610163108 |
|
|
Sep 18 10:50:37 AM UTC 24 |
Sep 18 10:50:54 AM UTC 24 |
1161800203 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3171725131 |
|
|
Sep 18 10:50:55 AM UTC 24 |
Sep 18 10:50:57 AM UTC 24 |
46866450 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1205075707 |
|
|
Sep 18 10:46:01 AM UTC 24 |
Sep 18 10:51:22 AM UTC 24 |
43669673867 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.3459986631 |
|
|
Sep 18 10:42:43 AM UTC 24 |
Sep 18 10:51:32 AM UTC 24 |
32922577646 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3429310851 |
|
|
Sep 18 10:15:41 AM UTC 24 |
Sep 18 10:51:41 AM UTC 24 |
91173287055 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1175002436 |
|
|
Sep 18 10:41:46 AM UTC 24 |
Sep 18 10:51:52 AM UTC 24 |
133029576096 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.1710736116 |
|
|
Sep 18 10:50:58 AM UTC 24 |
Sep 18 10:51:56 AM UTC 24 |
4298093326 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1820658939 |
|
|
Sep 18 10:51:53 AM UTC 24 |
Sep 18 10:52:12 AM UTC 24 |
998410712 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1873176029 |
|
|
Sep 18 10:50:30 AM UTC 24 |
Sep 18 10:52:22 AM UTC 24 |
10265385131 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.723525211 |
|
|
Sep 18 10:50:07 AM UTC 24 |
Sep 18 10:52:24 AM UTC 24 |
19102165617 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.1305123386 |
|
|
Sep 18 10:46:57 AM UTC 24 |
Sep 18 10:52:40 AM UTC 24 |
14127551184 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3987790357 |
|
|
Sep 18 10:52:23 AM UTC 24 |
Sep 18 10:52:57 AM UTC 24 |
902240349 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2144275832 |
|
|
Sep 18 10:40:50 AM UTC 24 |
Sep 18 10:53:03 AM UTC 24 |
10769302439 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.420499104 |
|
|
Sep 18 10:52:13 AM UTC 24 |
Sep 18 10:53:16 AM UTC 24 |
2958056301 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.661695268 |
|
|
Sep 18 10:53:16 AM UTC 24 |
Sep 18 10:53:21 AM UTC 24 |
685005344 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.2553523746 |
|
|
Sep 18 10:46:39 AM UTC 24 |
Sep 18 10:53:28 AM UTC 24 |
30382908426 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.986117104 |
|
|
Sep 18 10:39:32 AM UTC 24 |
Sep 18 10:53:42 AM UTC 24 |
22197095546 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.4255194629 |
|
|
Sep 18 10:52:25 AM UTC 24 |
Sep 18 10:53:43 AM UTC 24 |
38148568352 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.167734278 |
|
|
Sep 18 10:46:46 AM UTC 24 |
Sep 18 10:53:45 AM UTC 24 |
11659922519 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3871289120 |
|
|
Sep 18 10:53:44 AM UTC 24 |
Sep 18 10:53:45 AM UTC 24 |
46712198 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.4112934733 |
|
|
Sep 18 10:49:03 AM UTC 24 |
Sep 18 10:53:53 AM UTC 24 |
21309106458 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.4224343504 |
|
|
Sep 18 10:42:15 AM UTC 24 |
Sep 18 10:54:02 AM UTC 24 |
11102675046 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4197628940 |
|
|
Sep 18 10:53:29 AM UTC 24 |
Sep 18 10:54:06 AM UTC 24 |
5684681270 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3902522075 |
|
|
Sep 18 10:29:49 AM UTC 24 |
Sep 18 10:54:17 AM UTC 24 |
21547380682 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.3469890125 |
|
|
Sep 18 10:53:46 AM UTC 24 |
Sep 18 10:54:31 AM UTC 24 |
782536522 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1071760454 |
|
|
Sep 18 10:35:09 AM UTC 24 |
Sep 18 10:54:37 AM UTC 24 |
50973931143 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1772090048 |
|
|
Sep 18 10:53:47 AM UTC 24 |
Sep 18 10:54:42 AM UTC 24 |
39558829807 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3241131397 |
|
|
Sep 18 10:38:05 AM UTC 24 |
Sep 18 10:55:03 AM UTC 24 |
27171964602 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3654250720 |
|
|
Sep 18 10:54:31 AM UTC 24 |
Sep 18 10:55:07 AM UTC 24 |
5949313550 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.638568842 |
|
|
Sep 18 10:50:29 AM UTC 24 |
Sep 18 10:55:14 AM UTC 24 |
7885278973 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1711389405 |
|
|
Sep 18 10:54:39 AM UTC 24 |
Sep 18 10:55:20 AM UTC 24 |
1523838810 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1875285426 |
|
|
Sep 18 10:55:21 AM UTC 24 |
Sep 18 10:55:29 AM UTC 24 |
1879474602 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.1086204563 |
|
|
Sep 18 10:48:34 AM UTC 24 |
Sep 18 10:55:31 AM UTC 24 |
82383235397 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.4056645018 |
|
|
Sep 18 10:51:42 AM UTC 24 |
Sep 18 10:55:41 AM UTC 24 |
3645784652 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2871919207 |
|
|
Sep 18 10:54:06 AM UTC 24 |
Sep 18 10:55:55 AM UTC 24 |
1090694400 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2873592587 |
|
|
Sep 18 10:52:58 AM UTC 24 |
Sep 18 10:56:05 AM UTC 24 |
2558444859 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1441686340 |
|
|
Sep 18 10:56:06 AM UTC 24 |
Sep 18 10:56:07 AM UTC 24 |
37727069 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1661084262 |
|
|
Sep 18 10:53:28 AM UTC 24 |
Sep 18 10:56:19 AM UTC 24 |
4495168298 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3299461053 |
|
|
Sep 18 10:33:25 AM UTC 24 |
Sep 18 10:56:25 AM UTC 24 |
55930626376 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.4150584692 |
|
|
Sep 18 10:56:09 AM UTC 24 |
Sep 18 10:56:43 AM UTC 24 |
14521345238 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2778596189 |
|
|
Sep 18 10:55:42 AM UTC 24 |
Sep 18 10:56:47 AM UTC 24 |
1598139783 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1774680759 |
|
|
Sep 18 10:46:48 AM UTC 24 |
Sep 18 10:57:04 AM UTC 24 |
18267651631 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.288392364 |
|
|
Sep 18 10:54:43 AM UTC 24 |
Sep 18 10:57:09 AM UTC 24 |
11590708999 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3622537058 |
|
|
Sep 18 10:56:48 AM UTC 24 |
Sep 18 10:57:10 AM UTC 24 |
537477958 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.631584238 |
|
|
Sep 18 10:26:41 AM UTC 24 |
Sep 18 10:57:12 AM UTC 24 |
21819841348 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.979951562 |
|
|
Sep 18 10:57:10 AM UTC 24 |
Sep 18 10:57:43 AM UTC 24 |
724182669 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.3464109391 |
|
|
Sep 18 10:38:17 AM UTC 24 |
Sep 18 10:57:43 AM UTC 24 |
59035823596 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1613311463 |
|
|
Sep 18 10:57:11 AM UTC 24 |
Sep 18 10:58:03 AM UTC 24 |
3097583611 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2717021466 |
|
|
Sep 18 10:51:57 AM UTC 24 |
Sep 18 10:58:05 AM UTC 24 |
5464069503 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2717660869 |
|
|
Sep 18 10:57:13 AM UTC 24 |
Sep 18 10:58:05 AM UTC 24 |
18230409306 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1957752092 |
|
|
Sep 18 10:58:06 AM UTC 24 |
Sep 18 10:58:13 AM UTC 24 |
1351252985 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3460798531 |
|
|
Sep 18 10:55:32 AM UTC 24 |
Sep 18 10:58:36 AM UTC 24 |
9759389571 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.433289685 |
|
|
Sep 18 10:57:45 AM UTC 24 |
Sep 18 10:58:36 AM UTC 24 |
11222199992 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.757568229 |
|
|
Sep 18 10:45:16 AM UTC 24 |
Sep 18 10:59:02 AM UTC 24 |
8240023138 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4165081704 |
|
|
Sep 18 10:59:02 AM UTC 24 |
Sep 18 10:59:04 AM UTC 24 |
19289833 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3084973901 |
|
|
Sep 18 10:58:37 AM UTC 24 |
Sep 18 10:59:17 AM UTC 24 |
1810733831 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2950798397 |
|
|
Sep 18 10:56:44 AM UTC 24 |
Sep 18 10:59:26 AM UTC 24 |
2707486486 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3698736721 |
|
|
Sep 18 10:58:14 AM UTC 24 |
Sep 18 10:59:31 AM UTC 24 |
9565310735 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2910091241 |
|
|
Sep 18 10:54:03 AM UTC 24 |
Sep 18 10:59:31 AM UTC 24 |
23246818880 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2505752879 |
|
|
Sep 18 10:53:21 AM UTC 24 |
Sep 18 10:59:46 AM UTC 24 |
20708370048 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.3264694559 |
|
|
Sep 18 10:59:32 AM UTC 24 |
Sep 18 10:59:46 AM UTC 24 |
693673742 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1685309515 |
|
|
Sep 18 10:59:05 AM UTC 24 |
Sep 18 10:59:51 AM UTC 24 |
833028234 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.3944156736 |
|
|
Sep 18 10:59:47 AM UTC 24 |
Sep 18 11:00:18 AM UTC 24 |
736651968 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2750144947 |
|
|
Sep 18 10:54:18 AM UTC 24 |
Sep 18 11:00:20 AM UTC 24 |
57265888070 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2248174475 |
|
|
Sep 18 11:00:19 AM UTC 24 |
Sep 18 11:00:34 AM UTC 24 |
1204485136 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2103575235 |
|
|
Sep 18 10:59:52 AM UTC 24 |
Sep 18 11:00:43 AM UTC 24 |
751434954 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1100376715 |
|
|
Sep 18 10:56:21 AM UTC 24 |
Sep 18 11:01:16 AM UTC 24 |
3849037984 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.614714542 |
|
|
Sep 18 11:01:17 AM UTC 24 |
Sep 18 11:01:24 AM UTC 24 |
345366314 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.119680404 |
|
|
Sep 18 10:55:29 AM UTC 24 |
Sep 18 11:01:24 AM UTC 24 |
57668283107 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.4013831773 |
|
|
Sep 18 10:15:08 AM UTC 24 |
Sep 18 11:02:08 AM UTC 24 |
93464524052 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2440982742 |
|
|
Sep 18 10:52:41 AM UTC 24 |
Sep 18 11:02:19 AM UTC 24 |
15040653077 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1396054225 |
|
|
Sep 18 10:59:32 AM UTC 24 |
Sep 18 11:02:48 AM UTC 24 |
5508131920 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3288918118 |
|
|
Sep 18 11:01:25 AM UTC 24 |
Sep 18 11:02:50 AM UTC 24 |
964370820 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2511132356 |
|
|
Sep 18 11:02:49 AM UTC 24 |
Sep 18 11:02:51 AM UTC 24 |
19059202 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.1052549407 |
|
|
Sep 18 10:59:19 AM UTC 24 |
Sep 18 11:02:53 AM UTC 24 |
20803969996 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2712335747 |
|
|
Sep 18 10:08:01 AM UTC 24 |
Sep 18 11:03:02 AM UTC 24 |
451396273322 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.3813908121 |
|
|
Sep 18 11:02:51 AM UTC 24 |
Sep 18 11:03:14 AM UTC 24 |
7473358981 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3244746921 |
|
|
Sep 18 11:02:08 AM UTC 24 |
Sep 18 11:04:03 AM UTC 24 |
20564145610 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.2268760716 |
|
|
Sep 18 10:25:37 AM UTC 24 |
Sep 18 11:04:41 AM UTC 24 |
96007885078 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2843126687 |
|
|
Sep 18 11:03:15 AM UTC 24 |
Sep 18 11:05:13 AM UTC 24 |
5169707762 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3012546168 |
|
|
Sep 18 11:04:42 AM UTC 24 |
Sep 18 11:05:14 AM UTC 24 |
1535893656 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.780869745 |
|
|
Sep 18 10:57:05 AM UTC 24 |
Sep 18 11:05:15 AM UTC 24 |
7910026725 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.51477773 |
|
|
Sep 18 11:05:14 AM UTC 24 |
Sep 18 11:05:40 AM UTC 24 |
774489438 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2815299004 |
|
|
Sep 18 10:58:06 AM UTC 24 |
Sep 18 11:05:50 AM UTC 24 |
21320206229 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.575350002 |
|
|
Sep 18 10:55:05 AM UTC 24 |
Sep 18 11:06:14 AM UTC 24 |
42820690047 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1015401128 |
|
|
Sep 18 11:06:15 AM UTC 24 |
Sep 18 11:06:22 AM UTC 24 |
1866707222 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2678432874 |
|
|
Sep 18 11:00:35 AM UTC 24 |
Sep 18 11:06:32 AM UTC 24 |
5641140490 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.4081332077 |
|
|
Sep 18 11:05:15 AM UTC 24 |
Sep 18 11:06:42 AM UTC 24 |
27151675584 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3296984590 |
|
|
Sep 18 10:51:23 AM UTC 24 |
Sep 18 11:07:01 AM UTC 24 |
8911397841 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.482019125 |
|
|
Sep 18 11:01:25 AM UTC 24 |
Sep 18 11:07:37 AM UTC 24 |
29167683749 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2187242039 |
|
|
Sep 18 11:07:38 AM UTC 24 |
Sep 18 11:07:40 AM UTC 24 |
13592013 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3709331776 |
|
|
Sep 18 10:55:15 AM UTC 24 |
Sep 18 11:08:08 AM UTC 24 |
90615753305 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.69828375 |
|
|
Sep 18 10:41:01 AM UTC 24 |
Sep 18 11:08:14 AM UTC 24 |
51859917836 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1345503453 |
|
|
Sep 18 11:07:41 AM UTC 24 |
Sep 18 11:08:31 AM UTC 24 |
1662730954 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2958448507 |
|
|
Sep 18 11:06:43 AM UTC 24 |
Sep 18 11:08:40 AM UTC 24 |
2740306755 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.694372502 |
|
|
Sep 18 10:50:04 AM UTC 24 |
Sep 18 11:08:41 AM UTC 24 |
23858941340 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.2035716795 |
|
|
Sep 18 11:00:44 AM UTC 24 |
Sep 18 11:08:43 AM UTC 24 |
19601676465 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3474780187 |
|
|
Sep 18 11:08:41 AM UTC 24 |
Sep 18 11:09:02 AM UTC 24 |
3672756625 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3110213079 |
|
|
Sep 18 10:01:38 AM UTC 24 |
Sep 18 11:09:09 AM UTC 24 |
123396066752 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.1010186119 |
|
|
Sep 18 10:55:08 AM UTC 24 |
Sep 18 11:09:29 AM UTC 24 |
36929115353 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1144134049 |
|
|
Sep 18 11:06:33 AM UTC 24 |
Sep 18 11:09:38 AM UTC 24 |
20897523149 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3522558454 |
|
|
Sep 18 11:09:09 AM UTC 24 |
Sep 18 11:09:44 AM UTC 24 |
10131161265 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.184050046 |
|
|
Sep 18 11:08:44 AM UTC 24 |
Sep 18 11:10:09 AM UTC 24 |
3188629305 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1052951692 |
|
|
Sep 18 11:10:11 AM UTC 24 |
Sep 18 11:10:18 AM UTC 24 |
365504098 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3496685293 |
|
|
Sep 18 11:03:03 AM UTC 24 |
Sep 18 11:10:31 AM UTC 24 |
21125328447 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1513751994 |
|
|
Sep 18 10:47:53 AM UTC 24 |
Sep 18 11:10:31 AM UTC 24 |
116277471301 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1577228429 |
|
|
Sep 18 11:09:03 AM UTC 24 |
Sep 18 11:10:34 AM UTC 24 |
854105831 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.366463709 |
|
|
Sep 18 10:57:45 AM UTC 24 |
Sep 18 11:10:48 AM UTC 24 |
28022889126 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3442638782 |
|
|
Sep 18 10:51:33 AM UTC 24 |
Sep 18 11:10:49 AM UTC 24 |
52423894977 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.197312839 |
|
|
Sep 18 11:10:49 AM UTC 24 |
Sep 18 11:10:51 AM UTC 24 |
15761491 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.31871784 |
|
|
Sep 18 11:05:50 AM UTC 24 |
Sep 18 11:10:57 AM UTC 24 |
6379195026 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.130224660 |
|
|
Sep 18 11:08:33 AM UTC 24 |
Sep 18 11:11:06 AM UTC 24 |
5792128202 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.540481707 |
|
|
Sep 18 11:10:50 AM UTC 24 |
Sep 18 11:11:07 AM UTC 24 |
2547294977 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.622204812 |
|
|
Sep 18 11:10:32 AM UTC 24 |
Sep 18 11:11:08 AM UTC 24 |
679720181 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3230392449 |
|
|
Sep 18 11:04:05 AM UTC 24 |
Sep 18 11:11:13 AM UTC 24 |
51115754721 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3076843214 |
|
|
Sep 18 11:11:14 AM UTC 24 |
Sep 18 11:11:25 AM UTC 24 |
4152621142 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.434060317 |
|
|
Sep 18 10:59:47 AM UTC 24 |
Sep 18 11:11:26 AM UTC 24 |
102068747001 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2477013892 |
|
|
Sep 18 11:06:23 AM UTC 24 |
Sep 18 11:11:32 AM UTC 24 |
103514814051 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.64189388 |
|
|
Sep 18 11:11:26 AM UTC 24 |
Sep 18 11:11:59 AM UTC 24 |
721620925 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.445785637 |
|
|
Sep 18 10:53:03 AM UTC 24 |
Sep 18 11:12:04 AM UTC 24 |
48036432845 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3068933136 |
|
|
Sep 18 11:10:32 AM UTC 24 |
Sep 18 11:12:07 AM UTC 24 |
5370673649 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.760247591 |
|
|
Sep 18 11:12:07 AM UTC 24 |
Sep 18 11:12:14 AM UTC 24 |
2800528830 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.1607942304 |
|
|
Sep 18 11:09:39 AM UTC 24 |
Sep 18 11:12:34 AM UTC 24 |
9831509221 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3971718304 |
|
|
Sep 18 11:11:08 AM UTC 24 |
Sep 18 11:12:56 AM UTC 24 |
3550240661 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2890365131 |
|
|
Sep 18 11:11:27 AM UTC 24 |
Sep 18 11:13:03 AM UTC 24 |
28928670067 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3149020950 |
|
|
Sep 18 11:02:52 AM UTC 24 |
Sep 18 11:13:16 AM UTC 24 |
13760857627 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.837921956 |
|
|
Sep 18 11:13:17 AM UTC 24 |
Sep 18 11:13:19 AM UTC 24 |
16139086 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3172717531 |
|
|
Sep 18 10:49:39 AM UTC 24 |
Sep 18 11:13:26 AM UTC 24 |
161325356408 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3149539508 |
|
|
Sep 18 11:12:57 AM UTC 24 |
Sep 18 11:13:30 AM UTC 24 |
1216461067 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.438426239 |
|
|
Sep 18 10:58:04 AM UTC 24 |
Sep 18 11:13:41 AM UTC 24 |
17606952648 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.2800252586 |
|
|
Sep 18 11:08:42 AM UTC 24 |
Sep 18 11:13:52 AM UTC 24 |
120840285377 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2757450397 |
|
|
Sep 18 11:13:20 AM UTC 24 |
Sep 18 11:13:52 AM UTC 24 |
4901916542 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2127233277 |
|
|
Sep 18 11:12:00 AM UTC 24 |
Sep 18 11:13:56 AM UTC 24 |
10336072745 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3239947308 |
|
|
Sep 18 11:12:36 AM UTC 24 |
Sep 18 11:14:00 AM UTC 24 |
2446782225 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3314072440 |
|
|
Sep 18 11:13:53 AM UTC 24 |
Sep 18 11:14:13 AM UTC 24 |
644685541 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3295461520 |
|
|
Sep 18 11:13:57 AM UTC 24 |
Sep 18 11:14:16 AM UTC 24 |
1440893123 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1895319280 |
|
|
Sep 18 11:08:08 AM UTC 24 |
Sep 18 11:14:30 AM UTC 24 |
6347153414 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.860018260 |
|
|
Sep 18 11:14:01 AM UTC 24 |
Sep 18 11:14:31 AM UTC 24 |
1250302637 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2045569786 |
|
|
Sep 18 11:14:14 AM UTC 24 |
Sep 18 11:15:01 AM UTC 24 |
7004132968 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2878363310 |
|
|
Sep 18 11:15:02 AM UTC 24 |
Sep 18 11:15:09 AM UTC 24 |
689545381 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1700934942 |
|
|
Sep 18 11:09:30 AM UTC 24 |
Sep 18 11:15:49 AM UTC 24 |
29563434727 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3407272851 |
|
|
Sep 18 11:10:19 AM UTC 24 |
Sep 18 11:16:04 AM UTC 24 |
14247173503 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2319447300 |
|
|
Sep 18 11:16:05 AM UTC 24 |
Sep 18 11:16:39 AM UTC 24 |
1381956754 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1921350593 |
|
|
Sep 18 11:13:54 AM UTC 24 |
Sep 18 11:17:21 AM UTC 24 |
7661271877 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2275758588 |
|
|
Sep 18 11:17:22 AM UTC 24 |
Sep 18 11:17:24 AM UTC 24 |
15107364 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2203933246 |
|
|
Sep 18 11:05:40 AM UTC 24 |
Sep 18 11:17:28 AM UTC 24 |
60176466329 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.4229029444 |
|
|
Sep 18 11:00:20 AM UTC 24 |
Sep 18 11:17:31 AM UTC 24 |
57509120228 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.3338142253 |
|
|
Sep 18 11:17:25 AM UTC 24 |
Sep 18 11:18:01 AM UTC 24 |
1787546960 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.3533233853 |
|
|
Sep 18 11:12:05 AM UTC 24 |
Sep 18 11:18:13 AM UTC 24 |
2129811599 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1481906461 |
|
|
Sep 18 11:15:10 AM UTC 24 |
Sep 18 11:18:20 AM UTC 24 |
2743912977 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.890134490 |
|
|
Sep 18 11:18:13 AM UTC 24 |
Sep 18 11:18:37 AM UTC 24 |
1191078271 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1635239412 |
|
|
Sep 18 11:15:50 AM UTC 24 |
Sep 18 11:18:44 AM UTC 24 |
19678625458 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2107402200 |
|
|
Sep 18 11:11:08 AM UTC 24 |
Sep 18 11:19:11 AM UTC 24 |
24775080320 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.377014547 |
|
|
Sep 18 11:19:12 AM UTC 24 |
Sep 18 11:19:19 AM UTC 24 |
1421164963 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.852945805 |
|
|
Sep 18 11:11:09 AM UTC 24 |
Sep 18 11:19:31 AM UTC 24 |
91515584076 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2460769793 |
|
|
Sep 18 11:18:38 AM UTC 24 |
Sep 18 11:19:34 AM UTC 24 |
810269160 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3282756747 |
|
|
Sep 18 11:12:16 AM UTC 24 |
Sep 18 11:19:41 AM UTC 24 |
28226378496 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1113743754 |
|
|
Sep 18 11:19:42 AM UTC 24 |
Sep 18 11:19:49 AM UTC 24 |
682600805 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.2360234362 |
|
|
Sep 18 11:14:31 AM UTC 24 |
Sep 18 11:19:58 AM UTC 24 |
8420975902 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.13486349 |
|
|
Sep 18 11:18:45 AM UTC 24 |
Sep 18 11:20:05 AM UTC 24 |
961502738 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1946142934 |
|
|
Sep 18 11:05:16 AM UTC 24 |
Sep 18 11:20:28 AM UTC 24 |
14186539614 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2580402942 |
|
|
Sep 18 11:20:05 AM UTC 24 |
Sep 18 11:20:40 AM UTC 24 |
2894218793 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.2942802756 |
|
|
Sep 18 11:20:41 AM UTC 24 |
Sep 18 11:20:43 AM UTC 24 |
39113434 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.4148619323 |
|
|
Sep 18 11:20:44 AM UTC 24 |
Sep 18 11:20:51 AM UTC 24 |
1067361712 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3422456516 |
|
|
Sep 18 11:19:59 AM UTC 24 |
Sep 18 11:21:30 AM UTC 24 |
1932843301 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2572829113 |
|
|
Sep 18 11:13:42 AM UTC 24 |
Sep 18 11:21:31 AM UTC 24 |
4635040948 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.1847825929 |
|
|
Sep 18 11:10:57 AM UTC 24 |
Sep 18 11:21:35 AM UTC 24 |
30374249887 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.321248973 |
|
|
Sep 18 11:19:50 AM UTC 24 |
Sep 18 11:22:24 AM UTC 24 |
2061932343 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3443029781 |
|
|
Sep 18 11:21:35 AM UTC 24 |
Sep 18 11:22:44 AM UTC 24 |
846252302 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.960679651 |
|
|
Sep 18 11:20:52 AM UTC 24 |
Sep 18 11:22:49 AM UTC 24 |
3458579315 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.1955858417 |
|
|
Sep 18 11:10:52 AM UTC 24 |
Sep 18 11:22:49 AM UTC 24 |
14572297472 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3671173044 |
|
|
Sep 18 11:08:14 AM UTC 24 |
Sep 18 11:22:51 AM UTC 24 |
38591095677 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2342198444 |
|
|
Sep 18 11:22:50 AM UTC 24 |
Sep 18 11:23:03 AM UTC 24 |
790840271 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3230013138 |
|
|
Sep 18 11:18:01 AM UTC 24 |
Sep 18 11:23:43 AM UTC 24 |
3959029638 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2769027747 |
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|
Sep 18 11:19:20 AM UTC 24 |
Sep 18 11:23:54 AM UTC 24 |
5182038142 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.900685226 |
|
|
Sep 18 11:23:55 AM UTC 24 |
Sep 18 11:24:02 AM UTC 24 |
360716357 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.758687881 |
|
|
Sep 18 11:09:44 AM UTC 24 |
Sep 18 11:24:16 AM UTC 24 |
3186447552 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2293465284 |
|
|
Sep 18 11:14:17 AM UTC 24 |
Sep 18 11:24:21 AM UTC 24 |
82613261101 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.223248798 |
|
|
Sep 18 11:13:30 AM UTC 24 |
Sep 18 11:24:25 AM UTC 24 |
30287927526 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2203844544 |
|
|
Sep 18 11:22:45 AM UTC 24 |
Sep 18 11:24:34 AM UTC 24 |
3178284434 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.401433934 |
|
|
Sep 18 11:24:35 AM UTC 24 |
Sep 18 11:24:37 AM UTC 24 |
42465826 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.600184992 |
|
|
Sep 18 11:24:22 AM UTC 24 |
Sep 18 11:24:42 AM UTC 24 |
316932760 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.211373878 |
|
|
Sep 18 11:22:50 AM UTC 24 |
Sep 18 11:24:53 AM UTC 24 |
65696216849 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.768020490 |
|
|
Sep 18 11:24:38 AM UTC 24 |
Sep 18 11:25:19 AM UTC 24 |
8513321227 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.3360775674 |
|
|
Sep 18 10:48:05 AM UTC 24 |
Sep 18 11:26:07 AM UTC 24 |
33126016972 ps |