| T800 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.2730976491 |
|
|
Sep 18 12:10:55 PM UTC 24 |
Sep 18 12:15:15 PM UTC 24 |
30970629666 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.2939482719 |
|
|
Sep 18 12:14:17 PM UTC 24 |
Sep 18 12:15:17 PM UTC 24 |
767002385 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.3500776743 |
|
|
Sep 18 12:01:53 PM UTC 24 |
Sep 18 12:15:40 PM UTC 24 |
65716847691 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.2321414783 |
|
|
Sep 18 11:42:18 AM UTC 24 |
Sep 18 12:16:40 PM UTC 24 |
143870374990 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2804156705 |
|
|
Sep 18 12:09:47 PM UTC 24 |
Sep 18 12:16:48 PM UTC 24 |
29080443351 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1379770939 |
|
|
Sep 18 12:15:18 PM UTC 24 |
Sep 18 12:16:58 PM UTC 24 |
858931724 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.146219041 |
|
|
Sep 18 12:08:33 PM UTC 24 |
Sep 18 12:17:22 PM UTC 24 |
57919902342 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2905517317 |
|
|
Sep 18 12:26:17 PM UTC 24 |
Sep 18 12:29:25 PM UTC 24 |
5971276530 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2934984149 |
|
|
Sep 18 12:10:18 PM UTC 24 |
Sep 18 12:17:23 PM UTC 24 |
33607488309 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.4086113783 |
|
|
Sep 18 11:55:10 AM UTC 24 |
Sep 18 12:17:30 PM UTC 24 |
34941539553 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1866003940 |
|
|
Sep 18 12:16:40 PM UTC 24 |
Sep 18 12:17:36 PM UTC 24 |
1538092477 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.913032661 |
|
|
Sep 18 12:17:37 PM UTC 24 |
Sep 18 12:17:43 PM UTC 24 |
595477871 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2142791902 |
|
|
Sep 18 12:16:50 PM UTC 24 |
Sep 18 12:17:53 PM UTC 24 |
1535278472 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1762535124 |
|
|
Sep 18 12:03:43 PM UTC 24 |
Sep 18 12:17:54 PM UTC 24 |
8904517669 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1555681452 |
|
|
Sep 18 12:00:26 PM UTC 24 |
Sep 18 12:18:00 PM UTC 24 |
84281427985 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2971605531 |
|
|
Sep 18 12:16:59 PM UTC 24 |
Sep 18 12:18:02 PM UTC 24 |
19371583270 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3432057653 |
|
|
Sep 18 12:17:54 PM UTC 24 |
Sep 18 12:18:04 PM UTC 24 |
215495001 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4271086930 |
|
|
Sep 18 12:18:04 PM UTC 24 |
Sep 18 12:18:06 PM UTC 24 |
31701985 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.163822893 |
|
|
Sep 18 12:00:37 PM UTC 24 |
Sep 18 12:18:17 PM UTC 24 |
18869561271 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.788548588 |
|
|
Sep 18 11:58:53 AM UTC 24 |
Sep 18 12:18:25 PM UTC 24 |
66205850529 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.3805306489 |
|
|
Sep 18 12:18:05 PM UTC 24 |
Sep 18 12:18:33 PM UTC 24 |
2695457240 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1641339161 |
|
|
Sep 18 12:07:37 PM UTC 24 |
Sep 18 12:18:34 PM UTC 24 |
37607878171 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.4053007247 |
|
|
Sep 18 11:58:28 AM UTC 24 |
Sep 18 12:19:01 PM UTC 24 |
14665180139 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2190604738 |
|
|
Sep 18 12:18:34 PM UTC 24 |
Sep 18 12:19:01 PM UTC 24 |
3204993793 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.4222342134 |
|
|
Sep 18 12:19:03 PM UTC 24 |
Sep 18 12:19:13 PM UTC 24 |
680816404 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1048204292 |
|
|
Sep 18 12:19:02 PM UTC 24 |
Sep 18 12:19:53 PM UTC 24 |
2078087210 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2159594032 |
|
|
Sep 18 12:03:14 PM UTC 24 |
Sep 18 12:19:55 PM UTC 24 |
53112044347 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.4050575346 |
|
|
Sep 18 12:10:52 PM UTC 24 |
Sep 18 12:20:25 PM UTC 24 |
13326480574 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2962134311 |
|
|
Sep 18 12:19:14 PM UTC 24 |
Sep 18 12:20:50 PM UTC 24 |
7771323041 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.106287151 |
|
|
Sep 18 12:14:19 PM UTC 24 |
Sep 18 12:20:58 PM UTC 24 |
2633803003 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1826438779 |
|
|
Sep 18 12:20:52 PM UTC 24 |
Sep 18 12:20:59 PM UTC 24 |
627140247 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2842847019 |
|
|
Sep 18 12:15:17 PM UTC 24 |
Sep 18 12:21:35 PM UTC 24 |
20567912130 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1223131610 |
|
|
Sep 18 12:17:54 PM UTC 24 |
Sep 18 12:21:38 PM UTC 24 |
4925886380 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3511090185 |
|
|
Sep 18 12:21:36 PM UTC 24 |
Sep 18 12:21:54 PM UTC 24 |
245875685 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.540264995 |
|
|
Sep 18 12:14:24 PM UTC 24 |
Sep 18 12:21:56 PM UTC 24 |
7189416319 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1177329152 |
|
|
Sep 18 12:21:55 PM UTC 24 |
Sep 18 12:21:57 PM UTC 24 |
16176812 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.4228516739 |
|
|
Sep 18 11:28:06 AM UTC 24 |
Sep 18 12:22:06 PM UTC 24 |
142054111434 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3550111130 |
|
|
Sep 18 11:58:26 AM UTC 24 |
Sep 18 12:22:18 PM UTC 24 |
30226766364 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1356343982 |
|
|
Sep 18 12:18:27 PM UTC 24 |
Sep 18 12:22:32 PM UTC 24 |
4027380669 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.789904992 |
|
|
Sep 18 12:21:00 PM UTC 24 |
Sep 18 12:22:36 PM UTC 24 |
2952390397 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1825266045 |
|
|
Sep 18 12:21:57 PM UTC 24 |
Sep 18 12:22:57 PM UTC 24 |
757776890 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.1526792607 |
|
|
Sep 18 12:17:24 PM UTC 24 |
Sep 18 12:23:04 PM UTC 24 |
39487270701 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3743377104 |
|
|
Sep 18 12:22:33 PM UTC 24 |
Sep 18 12:23:07 PM UTC 24 |
933604676 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2986202841 |
|
|
Sep 18 12:23:05 PM UTC 24 |
Sep 18 12:23:43 PM UTC 24 |
751291080 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.2904346229 |
|
|
Sep 18 12:15:41 PM UTC 24 |
Sep 18 12:23:50 PM UTC 24 |
62421505513 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1439538560 |
|
|
Sep 18 12:08:14 PM UTC 24 |
Sep 18 12:23:53 PM UTC 24 |
14482224024 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2071830252 |
|
|
Sep 18 12:08:24 PM UTC 24 |
Sep 18 12:23:57 PM UTC 24 |
13297651830 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.129118141 |
|
|
Sep 18 12:23:08 PM UTC 24 |
Sep 18 12:24:03 PM UTC 24 |
8101785822 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4286234878 |
|
|
Sep 18 12:23:58 PM UTC 24 |
Sep 18 12:24:04 PM UTC 24 |
1242826455 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.1100715313 |
|
|
Sep 18 12:08:20 PM UTC 24 |
Sep 18 12:24:25 PM UTC 24 |
25755179994 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.390223254 |
|
|
Sep 18 12:09:53 PM UTC 24 |
Sep 18 12:24:27 PM UTC 24 |
168407894723 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.4248108801 |
|
|
Sep 18 12:22:58 PM UTC 24 |
Sep 18 12:24:36 PM UTC 24 |
791059692 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2026521913 |
|
|
Sep 18 12:24:37 PM UTC 24 |
Sep 18 12:24:39 PM UTC 24 |
37218946 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2294224204 |
|
|
Sep 18 12:24:26 PM UTC 24 |
Sep 18 12:24:48 PM UTC 24 |
461481247 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2871562215 |
|
|
Sep 18 12:18:35 PM UTC 24 |
Sep 18 12:25:09 PM UTC 24 |
51351047509 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1511900243 |
|
|
Sep 18 12:06:44 PM UTC 24 |
Sep 18 12:25:20 PM UTC 24 |
35595357196 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3128994146 |
|
|
Sep 18 12:17:44 PM UTC 24 |
Sep 18 12:25:35 PM UTC 24 |
20710821238 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.646593154 |
|
|
Sep 18 12:24:41 PM UTC 24 |
Sep 18 12:25:49 PM UTC 24 |
3789991463 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.860563836 |
|
|
Sep 18 11:13:04 AM UTC 24 |
Sep 18 12:25:55 PM UTC 24 |
289747003798 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.1785208953 |
|
|
Sep 18 12:25:35 PM UTC 24 |
Sep 18 12:25:56 PM UTC 24 |
928735118 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.2230856784 |
|
|
Sep 18 12:11:10 PM UTC 24 |
Sep 18 12:25:58 PM UTC 24 |
83578101946 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.5443191 |
|
|
Sep 18 11:56:40 AM UTC 24 |
Sep 18 12:25:59 PM UTC 24 |
88843365727 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.353391837 |
|
|
Sep 18 12:25:57 PM UTC 24 |
Sep 18 12:26:16 PM UTC 24 |
2995220754 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1415358927 |
|
|
Sep 18 12:25:57 PM UTC 24 |
Sep 18 12:26:22 PM UTC 24 |
1412486517 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1332047527 |
|
|
Sep 18 12:20:26 PM UTC 24 |
Sep 18 12:26:31 PM UTC 24 |
32485194587 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4228218364 |
|
|
Sep 18 12:24:04 PM UTC 24 |
Sep 18 12:26:38 PM UTC 24 |
38518388097 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.803776757 |
|
|
Sep 18 12:26:32 PM UTC 24 |
Sep 18 12:26:39 PM UTC 24 |
3350731625 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1852333970 |
|
|
Sep 18 12:24:06 PM UTC 24 |
Sep 18 12:27:03 PM UTC 24 |
9121836972 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2071132507 |
|
|
Sep 18 12:22:19 PM UTC 24 |
Sep 18 12:27:12 PM UTC 24 |
3248065471 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2950844134 |
|
|
Sep 18 12:20:59 PM UTC 24 |
Sep 18 12:27:13 PM UTC 24 |
21337933093 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2249759432 |
|
|
Sep 18 12:27:14 PM UTC 24 |
Sep 18 12:27:16 PM UTC 24 |
17704712 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.772061105 |
|
|
Sep 18 12:27:04 PM UTC 24 |
Sep 18 12:27:18 PM UTC 24 |
245685930 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.51771769 |
|
|
Sep 18 12:27:18 PM UTC 24 |
Sep 18 12:27:39 PM UTC 24 |
994670606 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1369882173 |
|
|
Sep 18 12:18:17 PM UTC 24 |
Sep 18 12:27:43 PM UTC 24 |
7257707093 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.791145072 |
|
|
Sep 18 12:25:58 PM UTC 24 |
Sep 18 12:27:46 PM UTC 24 |
8487892459 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.959906071 |
|
|
Sep 18 12:24:49 PM UTC 24 |
Sep 18 12:28:07 PM UTC 24 |
3060088589 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3926725044 |
|
|
Sep 18 12:19:56 PM UTC 24 |
Sep 18 12:28:13 PM UTC 24 |
75034736573 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2510833032 |
|
|
Sep 18 12:27:47 PM UTC 24 |
Sep 18 12:28:27 PM UTC 24 |
14502640684 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.139982287 |
|
|
Sep 18 12:28:14 PM UTC 24 |
Sep 18 12:28:27 PM UTC 24 |
4788967147 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3621903051 |
|
|
Sep 18 12:17:31 PM UTC 24 |
Sep 18 12:28:51 PM UTC 24 |
4721047081 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.326554974 |
|
|
Sep 18 12:28:27 PM UTC 24 |
Sep 18 12:28:56 PM UTC 24 |
13831282527 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2383517453 |
|
|
Sep 18 12:22:37 PM UTC 24 |
Sep 18 12:29:02 PM UTC 24 |
29555741667 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.828177791 |
|
|
Sep 18 12:19:54 PM UTC 24 |
Sep 18 12:29:14 PM UTC 24 |
20756835312 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.472023425 |
|
|
Sep 18 12:29:15 PM UTC 24 |
Sep 18 12:29:24 PM UTC 24 |
2102682324 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1151400418 |
|
|
Sep 18 12:25:20 PM UTC 24 |
Sep 18 12:29:26 PM UTC 24 |
13793471446 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2415808618 |
|
|
Sep 18 12:06:30 PM UTC 24 |
Sep 18 12:29:29 PM UTC 24 |
67201412239 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2476996782 |
|
|
Sep 18 12:26:40 PM UTC 24 |
Sep 18 12:29:37 PM UTC 24 |
2484225180 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1282818511 |
|
|
Sep 18 12:29:37 PM UTC 24 |
Sep 18 12:29:40 PM UTC 24 |
44514189 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2226891326 |
|
|
Sep 18 12:25:50 PM UTC 24 |
Sep 18 12:29:50 PM UTC 24 |
9531299218 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.4181447935 |
|
|
Sep 18 12:13:54 PM UTC 24 |
Sep 18 12:30:00 PM UTC 24 |
24937822393 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3081330040 |
|
|
Sep 18 12:26:00 PM UTC 24 |
Sep 18 12:30:02 PM UTC 24 |
74280966711 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2664018470 |
|
|
Sep 18 12:29:41 PM UTC 24 |
Sep 18 12:30:05 PM UTC 24 |
1721641601 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2823743825 |
|
|
Sep 18 12:29:27 PM UTC 24 |
Sep 18 12:30:25 PM UTC 24 |
7190272796 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.162151993 |
|
|
Sep 18 12:17:23 PM UTC 24 |
Sep 18 12:30:28 PM UTC 24 |
27178544717 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1060382090 |
|
|
Sep 18 12:28:27 PM UTC 24 |
Sep 18 12:30:51 PM UTC 24 |
26127360087 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2896769465 |
|
|
Sep 18 10:31:26 AM UTC 24 |
Sep 18 12:30:52 PM UTC 24 |
312791360057 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2483245075 |
|
|
Sep 18 12:29:26 PM UTC 24 |
Sep 18 12:30:59 PM UTC 24 |
9630006224 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.924402449 |
|
|
Sep 18 12:30:52 PM UTC 24 |
Sep 18 12:31:07 PM UTC 24 |
730876934 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.952069489 |
|
|
Sep 18 12:30:06 PM UTC 24 |
Sep 18 12:31:13 PM UTC 24 |
817512963 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3809030551 |
|
|
Sep 18 12:30:29 PM UTC 24 |
Sep 18 12:31:22 PM UTC 24 |
790625659 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3634726447 |
|
|
Sep 18 12:31:23 PM UTC 24 |
Sep 18 12:31:30 PM UTC 24 |
343975810 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1163763742 |
|
|
Sep 18 12:29:25 PM UTC 24 |
Sep 18 12:31:53 PM UTC 24 |
10963622368 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2493421153 |
|
|
Sep 18 12:26:39 PM UTC 24 |
Sep 18 12:32:23 PM UTC 24 |
18155418171 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1689020340 |
|
|
Sep 18 12:28:08 PM UTC 24 |
Sep 18 12:32:54 PM UTC 24 |
100410345230 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1855235160 |
|
|
Sep 18 12:32:24 PM UTC 24 |
Sep 18 12:33:37 PM UTC 24 |
2476483382 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3123713383 |
|
|
Sep 18 12:27:44 PM UTC 24 |
Sep 18 12:33:39 PM UTC 24 |
13477263488 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.367606618 |
|
|
Sep 18 12:33:38 PM UTC 24 |
Sep 18 12:33:40 PM UTC 24 |
15610711 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.930627609 |
|
|
Sep 18 12:31:31 PM UTC 24 |
Sep 18 12:34:09 PM UTC 24 |
7893761789 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.1931167091 |
|
|
Sep 18 11:59:13 AM UTC 24 |
Sep 18 12:34:23 PM UTC 24 |
522064834072 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3682246059 |
|
|
Sep 18 12:31:54 PM UTC 24 |
Sep 18 12:34:30 PM UTC 24 |
5154946544 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.351390617 |
|
|
Sep 18 12:30:53 PM UTC 24 |
Sep 18 12:34:36 PM UTC 24 |
59515389676 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3331397746 |
|
|
Sep 18 12:31:00 PM UTC 24 |
Sep 18 12:35:12 PM UTC 24 |
11584670231 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3799215375 |
|
|
Sep 18 12:30:02 PM UTC 24 |
Sep 18 12:35:56 PM UTC 24 |
16626647121 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3237771531 |
|
|
Sep 18 12:23:54 PM UTC 24 |
Sep 18 12:36:45 PM UTC 24 |
28192882334 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.272942273 |
|
|
Sep 18 12:30:27 PM UTC 24 |
Sep 18 12:36:46 PM UTC 24 |
44976380791 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4059460364 |
|
|
Sep 18 12:28:52 PM UTC 24 |
Sep 18 12:37:02 PM UTC 24 |
9584074362 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.3845961173 |
|
|
Sep 18 12:29:02 PM UTC 24 |
Sep 18 12:37:28 PM UTC 24 |
35939421565 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1537933601 |
|
|
Sep 18 12:18:06 PM UTC 24 |
Sep 18 12:37:51 PM UTC 24 |
106691830532 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.107381785 |
|
|
Sep 18 11:34:20 AM UTC 24 |
Sep 18 12:37:55 PM UTC 24 |
181321796967 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1010664468 |
|
|
Sep 18 12:29:51 PM UTC 24 |
Sep 18 12:38:21 PM UTC 24 |
98379367680 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2478794119 |
|
|
Sep 18 11:53:16 AM UTC 24 |
Sep 18 12:38:30 PM UTC 24 |
230027982310 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3329814454 |
|
|
Sep 18 12:26:24 PM UTC 24 |
Sep 18 12:38:40 PM UTC 24 |
11400439750 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1657304696 |
|
|
Sep 18 11:48:38 AM UTC 24 |
Sep 18 12:38:42 PM UTC 24 |
443527412567 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.1761797939 |
|
|
Sep 18 11:45:45 AM UTC 24 |
Sep 18 12:38:55 PM UTC 24 |
982039666846 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.183638481 |
|
|
Sep 18 12:21:57 PM UTC 24 |
Sep 18 12:39:19 PM UTC 24 |
14973528322 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1175359864 |
|
|
Sep 18 11:48:12 AM UTC 24 |
Sep 18 12:39:32 PM UTC 24 |
428987752053 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1410952786 |
|
|
Sep 18 12:27:19 PM UTC 24 |
Sep 18 12:39:48 PM UTC 24 |
93586059956 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3938510540 |
|
|
Sep 18 12:23:52 PM UTC 24 |
Sep 18 12:40:15 PM UTC 24 |
18840140184 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.2104814599 |
|
|
Sep 18 12:23:44 PM UTC 24 |
Sep 18 12:41:50 PM UTC 24 |
59629111743 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.21469948 |
|
|
Sep 18 11:39:14 AM UTC 24 |
Sep 18 12:42:48 PM UTC 24 |
460427864771 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1556162595 |
|
|
Sep 18 11:24:26 AM UTC 24 |
Sep 18 12:43:01 PM UTC 24 |
283494650179 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.4077689151 |
|
|
Sep 18 12:27:40 PM UTC 24 |
Sep 18 12:44:21 PM UTC 24 |
73050163968 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1310946121 |
|
|
Sep 18 12:31:08 PM UTC 24 |
Sep 18 12:46:25 PM UTC 24 |
23529093270 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.4181881100 |
|
|
Sep 18 12:05:59 PM UTC 24 |
Sep 18 12:47:56 PM UTC 24 |
108797214689 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2597045087 |
|
|
Sep 18 12:31:13 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
30802110497 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2440616602 |
|
|
Sep 18 12:01:14 PM UTC 24 |
Sep 18 12:50:35 PM UTC 24 |
33796626696 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.62156149 |
|
|
Sep 18 12:28:57 PM UTC 24 |
Sep 18 12:51:42 PM UTC 24 |
311759208377 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1032192319 |
|
|
Sep 18 11:45:24 AM UTC 24 |
Sep 18 12:51:44 PM UTC 24 |
272624223818 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1637622588 |
|
|
Sep 18 12:18:02 PM UTC 24 |
Sep 18 12:51:50 PM UTC 24 |
27154184995 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1296261871 |
|
|
Sep 18 11:58:36 AM UTC 24 |
Sep 18 12:51:52 PM UTC 24 |
141021634504 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.978691083 |
|
|
Sep 18 12:27:12 PM UTC 24 |
Sep 18 12:52:22 PM UTC 24 |
19554947309 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.1223364987 |
|
|
Sep 18 12:22:06 PM UTC 24 |
Sep 18 12:53:45 PM UTC 24 |
424809714423 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4027071539 |
|
|
Sep 18 10:19:27 AM UTC 24 |
Sep 18 01:03:31 PM UTC 24 |
2212455757597 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.2667435466 |
|
|
Sep 18 12:25:10 PM UTC 24 |
Sep 18 01:06:03 PM UTC 24 |
132471489330 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.163948918 |
|
|
Sep 18 11:56:13 AM UTC 24 |
Sep 18 01:09:42 PM UTC 24 |
213968919103 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.4035488700 |
|
|
Sep 18 11:30:34 AM UTC 24 |
Sep 18 01:11:34 PM UTC 24 |
967290394590 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.1587067122 |
|
|
Sep 18 12:30:01 PM UTC 24 |
Sep 18 01:13:49 PM UTC 24 |
165251062484 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.191434045 |
|
|
Sep 18 12:09:22 PM UTC 24 |
Sep 18 01:21:54 PM UTC 24 |
57367355319 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.652089937 |
|
|
Sep 18 12:24:28 PM UTC 24 |
Sep 18 01:22:21 PM UTC 24 |
64432393996 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3648558902 |
|
|
Sep 18 11:52:36 AM UTC 24 |
Sep 18 01:26:03 PM UTC 24 |
340512291165 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1650631274 |
|
|
Sep 18 12:32:55 PM UTC 24 |
Sep 18 01:27:23 PM UTC 24 |
230108067046 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2804897217 |
|
|
Sep 18 11:20:29 AM UTC 24 |
Sep 18 01:28:17 PM UTC 24 |
1227686762123 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.293951489 |
|
|
Sep 18 11:16:40 AM UTC 24 |
Sep 18 01:37:26 PM UTC 24 |
358506536307 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.356757910 |
|
|
Sep 18 12:29:30 PM UTC 24 |
Sep 18 01:48:14 PM UTC 24 |
1038774735845 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3813759801 |
|
|
Sep 18 12:21:39 PM UTC 24 |
Sep 18 01:52:49 PM UTC 24 |
429281135677 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2648519941 |
|
|
Sep 18 08:20:51 AM UTC 24 |
Sep 18 08:20:53 AM UTC 24 |
46507941 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3889798075 |
|
|
Sep 18 08:20:51 AM UTC 24 |
Sep 18 08:20:53 AM UTC 24 |
225185705 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.258908047 |
|
|
Sep 18 08:20:48 AM UTC 24 |
Sep 18 08:20:53 AM UTC 24 |
621778065 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2113213717 |
|
|
Sep 18 08:20:52 AM UTC 24 |
Sep 18 08:20:54 AM UTC 24 |
43712374 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1583889077 |
|
|
Sep 18 08:20:52 AM UTC 24 |
Sep 18 08:20:54 AM UTC 24 |
35068308 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.235703208 |
|
|
Sep 18 08:20:48 AM UTC 24 |
Sep 18 08:20:54 AM UTC 24 |
566296629 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2987491046 |
|
|
Sep 18 08:20:51 AM UTC 24 |
Sep 18 08:20:54 AM UTC 24 |
46365291 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.987647936 |
|
|
Sep 18 08:20:54 AM UTC 24 |
Sep 18 08:20:56 AM UTC 24 |
15469688 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.252546890 |
|
|
Sep 18 08:20:54 AM UTC 24 |
Sep 18 08:20:56 AM UTC 24 |
20821748 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.471879878 |
|
|
Sep 18 08:20:55 AM UTC 24 |
Sep 18 08:20:57 AM UTC 24 |
20067503 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1948509682 |
|
|
Sep 18 08:20:55 AM UTC 24 |
Sep 18 08:20:57 AM UTC 24 |
20957563 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1158317490 |
|
|
Sep 18 08:20:54 AM UTC 24 |
Sep 18 08:20:58 AM UTC 24 |
529231680 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1929507998 |
|
|
Sep 18 08:20:53 AM UTC 24 |
Sep 18 08:20:59 AM UTC 24 |
168111645 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2549910958 |
|
|
Sep 18 08:20:57 AM UTC 24 |
Sep 18 08:21:00 AM UTC 24 |
167958647 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2982568500 |
|
|
Sep 18 08:20:58 AM UTC 24 |
Sep 18 08:21:00 AM UTC 24 |
12268200 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3042703715 |
|
|
Sep 18 08:20:58 AM UTC 24 |
Sep 18 08:21:00 AM UTC 24 |
96109316 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3100457051 |
|
|
Sep 18 08:20:55 AM UTC 24 |
Sep 18 08:21:00 AM UTC 24 |
201516451 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2112548885 |
|
|
Sep 18 08:20:52 AM UTC 24 |
Sep 18 08:21:01 AM UTC 24 |
360743670 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3768364122 |
|
|
Sep 18 08:20:57 AM UTC 24 |
Sep 18 08:21:02 AM UTC 24 |
144960018 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.331833815 |
|
|
Sep 18 08:21:00 AM UTC 24 |
Sep 18 08:21:02 AM UTC 24 |
68314637 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2972362463 |
|
|
Sep 18 08:20:59 AM UTC 24 |
Sep 18 08:21:02 AM UTC 24 |
73405442 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.48427173 |
|
|
Sep 18 08:21:01 AM UTC 24 |
Sep 18 08:21:03 AM UTC 24 |
49684961 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.367743418 |
|
|
Sep 18 08:20:56 AM UTC 24 |
Sep 18 08:21:03 AM UTC 24 |
360147813 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3896237762 |
|
|
Sep 18 08:21:02 AM UTC 24 |
Sep 18 08:21:04 AM UTC 24 |
12055135 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2621451500 |
|
|
Sep 18 08:21:03 AM UTC 24 |
Sep 18 08:21:04 AM UTC 24 |
142666898 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.61527984 |
|
|
Sep 18 08:21:03 AM UTC 24 |
Sep 18 08:21:05 AM UTC 24 |
99080135 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2986519934 |
|
|
Sep 18 08:21:04 AM UTC 24 |
Sep 18 08:21:06 AM UTC 24 |
47075832 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.111015360 |
|
|
Sep 18 08:21:04 AM UTC 24 |
Sep 18 08:21:06 AM UTC 24 |
23399293 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.732304785 |
|
|
Sep 18 08:21:01 AM UTC 24 |
Sep 18 08:21:07 AM UTC 24 |
361756396 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.976070871 |
|
|
Sep 18 08:21:01 AM UTC 24 |
Sep 18 08:21:09 AM UTC 24 |
467893947 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4054277676 |
|
|
Sep 18 08:21:07 AM UTC 24 |
Sep 18 08:21:09 AM UTC 24 |
23503654 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.581570570 |
|
|
Sep 18 08:21:01 AM UTC 24 |
Sep 18 08:21:09 AM UTC 24 |
9554251554 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2214803044 |
|
|
Sep 18 08:21:08 AM UTC 24 |
Sep 18 08:21:10 AM UTC 24 |
19000727 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.945646470 |
|
|
Sep 18 08:21:05 AM UTC 24 |
Sep 18 08:21:11 AM UTC 24 |
3459950610 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2655697929 |
|
|
Sep 18 08:21:06 AM UTC 24 |
Sep 18 08:21:11 AM UTC 24 |
73043145 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3320102999 |
|
|
Sep 18 08:21:09 AM UTC 24 |
Sep 18 08:21:12 AM UTC 24 |
30977130 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1497551384 |
|
|
Sep 18 08:21:07 AM UTC 24 |
Sep 18 08:21:12 AM UTC 24 |
779752122 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1239132106 |
|
|
Sep 18 08:21:10 AM UTC 24 |
Sep 18 08:21:12 AM UTC 24 |
19416125 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2613754836 |
|
|
Sep 18 08:21:10 AM UTC 24 |
Sep 18 08:21:12 AM UTC 24 |
23724340 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.316262430 |
|
|
Sep 18 08:21:13 AM UTC 24 |
Sep 18 08:21:15 AM UTC 24 |
14907248 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1813699459 |
|
|
Sep 18 08:21:13 AM UTC 24 |
Sep 18 08:21:15 AM UTC 24 |
97446765 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3478031520 |
|
|
Sep 18 08:21:15 AM UTC 24 |
Sep 18 08:21:17 AM UTC 24 |
37784484 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4105949083 |
|
|
Sep 18 08:21:15 AM UTC 24 |
Sep 18 08:21:17 AM UTC 24 |
14296839 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3263541552 |
|
|
Sep 18 08:21:12 AM UTC 24 |
Sep 18 08:21:17 AM UTC 24 |
115902129 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3477245744 |
|
|
Sep 18 08:21:14 AM UTC 24 |
Sep 18 08:21:18 AM UTC 24 |
101159942 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1689498698 |
|
|
Sep 18 08:21:13 AM UTC 24 |
Sep 18 08:21:18 AM UTC 24 |
230617716 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.536329052 |
|
|
Sep 18 08:21:14 AM UTC 24 |
Sep 18 08:21:18 AM UTC 24 |
172218674 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3889263563 |
|
|
Sep 18 08:21:11 AM UTC 24 |
Sep 18 08:21:18 AM UTC 24 |
357432580 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3467121273 |
|
|
Sep 18 08:21:13 AM UTC 24 |
Sep 18 08:21:20 AM UTC 24 |
374571392 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.942305492 |
|
|
Sep 18 08:21:19 AM UTC 24 |
Sep 18 08:21:21 AM UTC 24 |
39312799 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2545858985 |
|
|
Sep 18 08:21:19 AM UTC 24 |
Sep 18 08:21:21 AM UTC 24 |
37673715 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1661030894 |
|
|
Sep 18 08:20:48 AM UTC 24 |
Sep 18 08:21:22 AM UTC 24 |
3899417588 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.189330545 |
|
|
Sep 18 08:21:19 AM UTC 24 |
Sep 18 08:21:22 AM UTC 24 |
101989347 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3870488479 |
|
|
Sep 18 08:21:16 AM UTC 24 |
Sep 18 08:21:23 AM UTC 24 |
2557065094 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.785257859 |
|
|
Sep 18 08:21:19 AM UTC 24 |
Sep 18 08:21:24 AM UTC 24 |
2230219038 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2204810281 |
|
|
Sep 18 08:21:22 AM UTC 24 |
Sep 18 08:21:24 AM UTC 24 |
70640368 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1109506634 |
|
|
Sep 18 08:21:19 AM UTC 24 |
Sep 18 08:21:25 AM UTC 24 |
146379842 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3338619856 |
|
|
Sep 18 08:21:21 AM UTC 24 |
Sep 18 08:21:25 AM UTC 24 |
372373708 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2874191557 |
|
|
Sep 18 08:21:23 AM UTC 24 |
Sep 18 08:21:25 AM UTC 24 |
46674656 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.722376891 |
|
|
Sep 18 08:21:21 AM UTC 24 |
Sep 18 08:21:26 AM UTC 24 |
770186524 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3552880199 |
|
|
Sep 18 08:20:53 AM UTC 24 |
Sep 18 08:21:27 AM UTC 24 |
7415254008 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.34016910 |
|
|
Sep 18 08:21:26 AM UTC 24 |
Sep 18 08:21:28 AM UTC 24 |
44928232 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4053599191 |
|
|
Sep 18 08:21:26 AM UTC 24 |
Sep 18 08:21:28 AM UTC 24 |
19830179 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3388397394 |
|
|
Sep 18 08:21:25 AM UTC 24 |
Sep 18 08:21:29 AM UTC 24 |
95100008 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.769173454 |
|
|
Sep 18 08:21:23 AM UTC 24 |
Sep 18 08:21:29 AM UTC 24 |
412216168 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.756537638 |
|
|
Sep 18 08:21:25 AM UTC 24 |
Sep 18 08:21:30 AM UTC 24 |
71529691 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2804877765 |
|
|
Sep 18 08:21:28 AM UTC 24 |
Sep 18 08:21:30 AM UTC 24 |
15084038 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2378214328 |
|
|
Sep 18 08:21:28 AM UTC 24 |
Sep 18 08:21:30 AM UTC 24 |
16070533 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3873442079 |
|
|
Sep 18 08:21:27 AM UTC 24 |
Sep 18 08:21:30 AM UTC 24 |
272670414 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.29302036 |
|
|
Sep 18 08:21:26 AM UTC 24 |
Sep 18 08:21:31 AM UTC 24 |
1193436389 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1099392151 |
|
|
Sep 18 08:21:30 AM UTC 24 |
Sep 18 08:21:32 AM UTC 24 |
14110287 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2955912359 |
|
|
Sep 18 08:21:30 AM UTC 24 |
Sep 18 08:21:32 AM UTC 24 |
19773712 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2372766026 |
|
|
Sep 18 08:21:29 AM UTC 24 |
Sep 18 08:21:33 AM UTC 24 |
292781073 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3181194121 |
|
|
Sep 18 08:21:26 AM UTC 24 |
Sep 18 08:21:33 AM UTC 24 |
482157735 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.399788646 |
|
|
Sep 18 08:21:30 AM UTC 24 |
Sep 18 08:21:34 AM UTC 24 |
699320618 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2644589557 |
|
|
Sep 18 08:21:34 AM UTC 24 |
Sep 18 08:21:36 AM UTC 24 |
57267279 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.962544626 |
|
|
Sep 18 08:21:28 AM UTC 24 |
Sep 18 08:21:36 AM UTC 24 |
3809875585 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1035811864 |
|
|
Sep 18 08:21:34 AM UTC 24 |
Sep 18 08:21:37 AM UTC 24 |
139156971 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2068564635 |
|
|
Sep 18 08:20:57 AM UTC 24 |
Sep 18 08:21:37 AM UTC 24 |
14780576829 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3861029916 |
|
|
Sep 18 08:21:35 AM UTC 24 |
Sep 18 08:21:37 AM UTC 24 |
27963249 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.70087532 |
|
|
Sep 18 08:21:33 AM UTC 24 |
Sep 18 08:21:37 AM UTC 24 |
151832912 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2026878553 |
|
|
Sep 18 08:21:31 AM UTC 24 |
Sep 18 08:21:39 AM UTC 24 |
753853163 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4219512913 |
|
|
Sep 18 08:21:37 AM UTC 24 |
Sep 18 08:21:39 AM UTC 24 |
32767049 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1247772426 |
|
|
Sep 18 08:21:37 AM UTC 24 |
Sep 18 08:21:39 AM UTC 24 |
14757359 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3633840755 |
|
|
Sep 18 08:21:35 AM UTC 24 |
Sep 18 08:21:40 AM UTC 24 |
728751815 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1738160476 |
|
|
Sep 18 08:21:36 AM UTC 24 |
Sep 18 08:21:41 AM UTC 24 |
65292382 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.722128387 |
|
|
Sep 18 08:21:40 AM UTC 24 |
Sep 18 08:21:42 AM UTC 24 |
29860240 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1149774604 |
|
|
Sep 18 08:21:40 AM UTC 24 |
Sep 18 08:21:42 AM UTC 24 |
31982130 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2445558556 |
|
|
Sep 18 08:21:38 AM UTC 24 |
Sep 18 08:21:42 AM UTC 24 |
211902223 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.606397129 |
|
|
Sep 18 08:21:37 AM UTC 24 |
Sep 18 08:21:42 AM UTC 24 |
288852308 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.427455095 |
|
|
Sep 18 08:21:38 AM UTC 24 |
Sep 18 08:21:43 AM UTC 24 |
60234959 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.732788089 |
|
|
Sep 18 08:21:38 AM UTC 24 |
Sep 18 08:21:43 AM UTC 24 |
1221538738 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.864911912 |
|
|
Sep 18 08:21:42 AM UTC 24 |
Sep 18 08:21:44 AM UTC 24 |
18588667 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1988223326 |
|
|
Sep 18 08:21:43 AM UTC 24 |
Sep 18 08:21:45 AM UTC 24 |
117320448 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2629315349 |
|
|
Sep 18 08:21:42 AM UTC 24 |
Sep 18 08:21:45 AM UTC 24 |
349529770 ps |