| T553 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.551554923 |
|
|
Sep 18 11:24:43 AM UTC 24 |
Sep 18 11:26:30 AM UTC 24 |
7702483604 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.378015748 |
|
|
Sep 18 11:26:08 AM UTC 24 |
Sep 18 11:26:48 AM UTC 24 |
1489999247 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.198821521 |
|
|
Sep 18 11:24:04 AM UTC 24 |
Sep 18 11:27:17 AM UTC 24 |
35918117681 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.1505955894 |
|
|
Sep 18 10:45:39 AM UTC 24 |
Sep 18 11:27:20 AM UTC 24 |
193111078994 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.996974791 |
|
|
Sep 18 11:27:18 AM UTC 24 |
Sep 18 11:27:26 AM UTC 24 |
676304157 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.534739585 |
|
|
Sep 18 10:53:54 AM UTC 24 |
Sep 18 11:27:42 AM UTC 24 |
58089293462 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2533891714 |
|
|
Sep 18 11:21:32 AM UTC 24 |
Sep 18 11:27:53 AM UTC 24 |
3671659328 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.572288412 |
|
|
Sep 18 11:24:17 AM UTC 24 |
Sep 18 11:27:54 AM UTC 24 |
5275035128 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2249687954 |
|
|
Sep 18 11:22:52 AM UTC 24 |
Sep 18 11:27:54 AM UTC 24 |
6255797989 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.513172595 |
|
|
Sep 18 11:27:55 AM UTC 24 |
Sep 18 11:28:02 AM UTC 24 |
345922751 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1056843444 |
|
|
Sep 18 11:26:49 AM UTC 24 |
Sep 18 11:28:02 AM UTC 24 |
3122414237 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2880036862 |
|
|
Sep 18 10:02:34 AM UTC 24 |
Sep 18 11:28:05 AM UTC 24 |
221637067653 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.3766234295 |
|
|
Sep 18 11:14:30 AM UTC 24 |
Sep 18 11:28:06 AM UTC 24 |
6992638168 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3316148958 |
|
|
Sep 18 11:28:06 AM UTC 24 |
Sep 18 11:28:08 AM UTC 24 |
54006213 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2795809223 |
|
|
Sep 18 11:25:19 AM UTC 24 |
Sep 18 11:28:32 AM UTC 24 |
5756395596 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.52113680 |
|
|
Sep 18 11:22:26 AM UTC 24 |
Sep 18 11:28:40 AM UTC 24 |
5128174206 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.1527562889 |
|
|
Sep 18 11:28:09 AM UTC 24 |
Sep 18 11:28:45 AM UTC 24 |
6276573045 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1538555166 |
|
|
Sep 18 11:11:33 AM UTC 24 |
Sep 18 11:28:51 AM UTC 24 |
25112464784 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.408947064 |
|
|
Sep 18 11:27:21 AM UTC 24 |
Sep 18 11:28:54 AM UTC 24 |
71379408643 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2355429110 |
|
|
Sep 18 11:13:26 AM UTC 24 |
Sep 18 11:28:54 AM UTC 24 |
36154492679 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2191662892 |
|
|
Sep 18 11:28:52 AM UTC 24 |
Sep 18 11:29:15 AM UTC 24 |
5951809076 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2944166965 |
|
|
Sep 18 11:28:56 AM UTC 24 |
Sep 18 11:29:32 AM UTC 24 |
2811601561 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3362551866 |
|
|
Sep 18 11:23:03 AM UTC 24 |
Sep 18 11:29:45 AM UTC 24 |
116554817833 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1082722012 |
|
|
Sep 18 11:18:21 AM UTC 24 |
Sep 18 11:29:45 AM UTC 24 |
22567884639 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1894947091 |
|
|
Sep 18 11:28:03 AM UTC 24 |
Sep 18 11:29:54 AM UTC 24 |
4910520715 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.4151270550 |
|
|
Sep 18 11:28:03 AM UTC 24 |
Sep 18 11:30:03 AM UTC 24 |
17313964797 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.4199799532 |
|
|
Sep 18 11:30:04 AM UTC 24 |
Sep 18 11:30:10 AM UTC 24 |
1350472797 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.1246234205 |
|
|
Sep 18 11:19:32 AM UTC 24 |
Sep 18 11:30:17 AM UTC 24 |
26979462515 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.2296378153 |
|
|
Sep 18 11:27:54 AM UTC 24 |
Sep 18 11:30:26 AM UTC 24 |
5190118767 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.4072625687 |
|
|
Sep 18 11:17:29 AM UTC 24 |
Sep 18 11:30:33 AM UTC 24 |
89883473075 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3664686879 |
|
|
Sep 18 11:29:16 AM UTC 24 |
Sep 18 11:30:35 AM UTC 24 |
794755388 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2657338051 |
|
|
Sep 18 11:30:35 AM UTC 24 |
Sep 18 11:30:37 AM UTC 24 |
15611107 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.80256656 |
|
|
Sep 18 11:29:32 AM UTC 24 |
Sep 18 11:30:40 AM UTC 24 |
6371425083 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.2764039254 |
|
|
Sep 18 11:27:55 AM UTC 24 |
Sep 18 11:30:48 AM UTC 24 |
10335325874 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.4235557403 |
|
|
Sep 18 11:30:38 AM UTC 24 |
Sep 18 11:31:15 AM UTC 24 |
3267347221 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1543194490 |
|
|
Sep 18 11:30:27 AM UTC 24 |
Sep 18 11:31:34 AM UTC 24 |
3740968332 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4092724105 |
|
|
Sep 18 11:30:11 AM UTC 24 |
Sep 18 11:32:14 AM UTC 24 |
2040211039 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.669609358 |
|
|
Sep 18 10:10:25 AM UTC 24 |
Sep 18 11:32:15 AM UTC 24 |
794430561028 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.308069593 |
|
|
Sep 18 11:31:36 AM UTC 24 |
Sep 18 11:32:19 AM UTC 24 |
2945389980 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1940750139 |
|
|
Sep 18 11:28:46 AM UTC 24 |
Sep 18 11:32:33 AM UTC 24 |
2602154520 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.2226480615 |
|
|
Sep 18 11:19:35 AM UTC 24 |
Sep 18 11:32:37 AM UTC 24 |
6734235439 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2118082427 |
|
|
Sep 18 11:32:20 AM UTC 24 |
Sep 18 11:32:37 AM UTC 24 |
2978348169 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3797263713 |
|
|
Sep 18 11:32:15 AM UTC 24 |
Sep 18 11:32:46 AM UTC 24 |
1519367282 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3364527121 |
|
|
Sep 18 11:30:18 AM UTC 24 |
Sep 18 11:33:12 AM UTC 24 |
10098263358 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.4183330158 |
|
|
Sep 18 11:33:13 AM UTC 24 |
Sep 18 11:33:20 AM UTC 24 |
694072848 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.93030852 |
|
|
Sep 18 11:26:31 AM UTC 24 |
Sep 18 11:33:34 AM UTC 24 |
16824048831 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2757605668 |
|
|
Sep 18 10:55:55 AM UTC 24 |
Sep 18 11:33:52 AM UTC 24 |
541402379021 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.3203967066 |
|
|
Sep 18 11:23:44 AM UTC 24 |
Sep 18 11:34:19 AM UTC 24 |
56164755740 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.856116101 |
|
|
Sep 18 11:32:33 AM UTC 24 |
Sep 18 11:34:25 AM UTC 24 |
46747247857 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.237296284 |
|
|
Sep 18 11:34:27 AM UTC 24 |
Sep 18 11:34:29 AM UTC 24 |
13507814 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.899514214 |
|
|
Sep 18 10:01:17 AM UTC 24 |
Sep 18 11:34:46 AM UTC 24 |
194450029224 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1835366129 |
|
|
Sep 18 11:34:30 AM UTC 24 |
Sep 18 11:34:55 AM UTC 24 |
1774256218 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.891044987 |
|
|
Sep 18 11:33:52 AM UTC 24 |
Sep 18 11:35:54 AM UTC 24 |
6880039296 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3850920029 |
|
|
Sep 18 11:33:34 AM UTC 24 |
Sep 18 11:36:00 AM UTC 24 |
2457411576 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.17666479 |
|
|
Sep 18 11:28:55 AM UTC 24 |
Sep 18 11:36:13 AM UTC 24 |
15586618810 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1942729221 |
|
|
Sep 18 11:36:01 AM UTC 24 |
Sep 18 11:36:16 AM UTC 24 |
951110485 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.407162434 |
|
|
Sep 18 11:29:45 AM UTC 24 |
Sep 18 11:37:40 AM UTC 24 |
9483045333 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3440962646 |
|
|
Sep 18 11:37:40 AM UTC 24 |
Sep 18 11:37:52 AM UTC 24 |
5173576495 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1320526467 |
|
|
Sep 18 11:31:16 AM UTC 24 |
Sep 18 11:37:55 AM UTC 24 |
4988041030 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3569881588 |
|
|
Sep 18 11:36:17 AM UTC 24 |
Sep 18 11:38:06 AM UTC 24 |
2823160801 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3132955438 |
|
|
Sep 18 10:47:28 AM UTC 24 |
Sep 18 11:38:18 AM UTC 24 |
121954742167 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.932646285 |
|
|
Sep 18 11:29:55 AM UTC 24 |
Sep 18 11:38:28 AM UTC 24 |
66966920564 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.183300474 |
|
|
Sep 18 11:30:41 AM UTC 24 |
Sep 18 11:38:29 AM UTC 24 |
22361644495 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3881041309 |
|
|
Sep 18 11:37:54 AM UTC 24 |
Sep 18 11:38:37 AM UTC 24 |
6040280055 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.1471678963 |
|
|
Sep 18 11:38:29 AM UTC 24 |
Sep 18 11:38:37 AM UTC 24 |
1405336151 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3643876485 |
|
|
Sep 18 11:02:54 AM UTC 24 |
Sep 18 11:39:13 AM UTC 24 |
546814022317 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2013603831 |
|
|
Sep 18 10:56:26 AM UTC 24 |
Sep 18 11:39:18 AM UTC 24 |
138753222851 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3329324739 |
|
|
Sep 18 11:33:21 AM UTC 24 |
Sep 18 11:39:21 AM UTC 24 |
4153358118 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3278809284 |
|
|
Sep 18 11:39:19 AM UTC 24 |
Sep 18 11:39:21 AM UTC 24 |
42519357 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.3657175404 |
|
|
Sep 18 11:39:22 AM UTC 24 |
Sep 18 11:39:42 AM UTC 24 |
2887978409 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1698704494 |
|
|
Sep 18 10:53:44 AM UTC 24 |
Sep 18 11:39:51 AM UTC 24 |
76996013376 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3320235031 |
|
|
Sep 18 11:32:38 AM UTC 24 |
Sep 18 11:39:58 AM UTC 24 |
26139648543 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1573636196 |
|
|
Sep 18 11:38:38 AM UTC 24 |
Sep 18 11:39:58 AM UTC 24 |
2993216649 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1152823572 |
|
|
Sep 18 11:35:56 AM UTC 24 |
Sep 18 11:39:59 AM UTC 24 |
17166261421 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2190920910 |
|
|
Sep 18 11:39:59 AM UTC 24 |
Sep 18 11:40:11 AM UTC 24 |
5268026891 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1848066284 |
|
|
Sep 18 11:38:38 AM UTC 24 |
Sep 18 11:40:27 AM UTC 24 |
5566539152 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2958275290 |
|
|
Sep 18 11:28:33 AM UTC 24 |
Sep 18 11:40:34 AM UTC 24 |
19511404390 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3531074364 |
|
|
Sep 18 11:32:14 AM UTC 24 |
Sep 18 11:40:35 AM UTC 24 |
78716630375 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.3216899235 |
|
|
Sep 18 11:27:43 AM UTC 24 |
Sep 18 11:40:51 AM UTC 24 |
13868260174 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2998826020 |
|
|
Sep 18 11:40:12 AM UTC 24 |
Sep 18 11:40:53 AM UTC 24 |
2901362520 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1720872144 |
|
|
Sep 18 11:40:54 AM UTC 24 |
Sep 18 11:41:01 AM UTC 24 |
680425716 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3832657381 |
|
|
Sep 18 11:40:00 AM UTC 24 |
Sep 18 11:41:19 AM UTC 24 |
1490107602 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3334473607 |
|
|
Sep 18 11:38:29 AM UTC 24 |
Sep 18 11:41:29 AM UTC 24 |
10394260919 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2097353129 |
|
|
Sep 18 11:30:49 AM UTC 24 |
Sep 18 11:41:39 AM UTC 24 |
16411426890 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.792908837 |
|
|
Sep 18 11:45:34 AM UTC 24 |
Sep 18 11:45:44 AM UTC 24 |
1736048794 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2494781623 |
|
|
Sep 18 11:40:28 AM UTC 24 |
Sep 18 11:41:41 AM UTC 24 |
8136332380 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1419274402 |
|
|
Sep 18 11:41:42 AM UTC 24 |
Sep 18 11:41:44 AM UTC 24 |
12585751 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.865520679 |
|
|
Sep 18 11:29:47 AM UTC 24 |
Sep 18 11:42:11 AM UTC 24 |
8678607390 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3277921426 |
|
|
Sep 18 11:41:29 AM UTC 24 |
Sep 18 11:42:17 AM UTC 24 |
682141820 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.343934460 |
|
|
Sep 18 10:59:27 AM UTC 24 |
Sep 18 11:42:54 AM UTC 24 |
626828151821 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2407312728 |
|
|
Sep 18 11:41:45 AM UTC 24 |
Sep 18 11:43:33 AM UTC 24 |
18640027371 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.1692330247 |
|
|
Sep 18 11:39:52 AM UTC 24 |
Sep 18 11:43:43 AM UTC 24 |
12692118643 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.582454682 |
|
|
Sep 18 11:36:14 AM UTC 24 |
Sep 18 11:43:45 AM UTC 24 |
43748964461 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2370800572 |
|
|
Sep 18 11:41:02 AM UTC 24 |
Sep 18 11:43:55 AM UTC 24 |
54474040998 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3201909204 |
|
|
Sep 18 11:43:46 AM UTC 24 |
Sep 18 11:43:58 AM UTC 24 |
1402524912 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.745265683 |
|
|
Sep 18 11:43:34 AM UTC 24 |
Sep 18 11:44:00 AM UTC 24 |
6227560385 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.4122526267 |
|
|
Sep 18 10:44:47 AM UTC 24 |
Sep 18 11:44:01 AM UTC 24 |
234923241967 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.630620323 |
|
|
Sep 18 11:43:59 AM UTC 24 |
Sep 18 11:44:27 AM UTC 24 |
4802335200 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3864176896 |
|
|
Sep 18 11:32:47 AM UTC 24 |
Sep 18 11:44:29 AM UTC 24 |
43103641997 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.327546490 |
|
|
Sep 18 11:44:30 AM UTC 24 |
Sep 18 11:44:36 AM UTC 24 |
360080867 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3738184517 |
|
|
Sep 18 11:07:02 AM UTC 24 |
Sep 18 11:44:38 AM UTC 24 |
104139535357 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1346229458 |
|
|
Sep 18 11:41:20 AM UTC 24 |
Sep 18 11:44:43 AM UTC 24 |
4477622213 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1457035512 |
|
|
Sep 18 11:43:56 AM UTC 24 |
Sep 18 11:45:23 AM UTC 24 |
1570790280 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1163535887 |
|
|
Sep 18 10:24:45 AM UTC 24 |
Sep 18 11:45:30 AM UTC 24 |
115803913579 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.958548372 |
|
|
Sep 18 11:45:31 AM UTC 24 |
Sep 18 11:45:33 AM UTC 24 |
14732020 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1087458067 |
|
|
Sep 18 10:58:37 AM UTC 24 |
Sep 18 11:45:44 AM UTC 24 |
110165673170 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2162437224 |
|
|
Sep 18 11:55:46 AM UTC 24 |
Sep 18 12:00:02 PM UTC 24 |
3945457696 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.857706476 |
|
|
Sep 18 11:44:44 AM UTC 24 |
Sep 18 11:46:06 AM UTC 24 |
2395952141 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.5972951 |
|
|
Sep 18 11:34:47 AM UTC 24 |
Sep 18 11:46:07 AM UTC 24 |
20185939842 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3416542287 |
|
|
Sep 18 11:42:12 AM UTC 24 |
Sep 18 11:46:16 AM UTC 24 |
5741787926 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.274832891 |
|
|
Sep 18 11:44:39 AM UTC 24 |
Sep 18 11:46:27 AM UTC 24 |
3457125152 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1409168806 |
|
|
Sep 18 11:27:28 AM UTC 24 |
Sep 18 11:46:33 AM UTC 24 |
60026099217 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.4188100355 |
|
|
Sep 18 11:28:41 AM UTC 24 |
Sep 18 11:46:45 AM UTC 24 |
61114008545 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2301305358 |
|
|
Sep 18 11:46:28 AM UTC 24 |
Sep 18 11:46:54 AM UTC 24 |
5475623286 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1083548160 |
|
|
Sep 18 11:39:59 AM UTC 24 |
Sep 18 11:46:55 AM UTC 24 |
6842329763 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1741410036 |
|
|
Sep 18 11:46:09 AM UTC 24 |
Sep 18 11:47:06 AM UTC 24 |
4362966008 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.2005450460 |
|
|
Sep 18 11:42:55 AM UTC 24 |
Sep 18 11:47:46 AM UTC 24 |
15448128830 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.76487413 |
|
|
Sep 18 11:46:46 AM UTC 24 |
Sep 18 11:47:47 AM UTC 24 |
19392482293 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.429527981 |
|
|
Sep 18 11:47:47 AM UTC 24 |
Sep 18 11:47:54 AM UTC 24 |
1405152239 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.850308352 |
|
|
Sep 18 11:46:33 AM UTC 24 |
Sep 18 11:48:09 AM UTC 24 |
912854182 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3107001943 |
|
|
Sep 18 11:44:01 AM UTC 24 |
Sep 18 11:48:11 AM UTC 24 |
15071178264 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.581207392 |
|
|
Sep 18 11:44:36 AM UTC 24 |
Sep 18 11:48:18 AM UTC 24 |
16435260766 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3901087211 |
|
|
Sep 18 11:48:20 AM UTC 24 |
Sep 18 11:48:22 AM UTC 24 |
19050458 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2703111476 |
|
|
Sep 18 11:40:36 AM UTC 24 |
Sep 18 11:48:35 AM UTC 24 |
22052642453 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.47225997 |
|
|
Sep 18 11:48:23 AM UTC 24 |
Sep 18 11:48:37 AM UTC 24 |
437698418 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2120055691 |
|
|
Sep 18 11:48:10 AM UTC 24 |
Sep 18 11:48:45 AM UTC 24 |
866894660 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2323125674 |
|
|
Sep 18 10:03:43 AM UTC 24 |
Sep 18 11:48:46 AM UTC 24 |
1035940235962 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3082035653 |
|
|
Sep 18 11:48:48 AM UTC 24 |
Sep 18 11:49:56 AM UTC 24 |
2768519321 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1417310561 |
|
|
Sep 18 11:47:48 AM UTC 24 |
Sep 18 11:50:34 AM UTC 24 |
2040094954 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.637145768 |
|
|
Sep 18 11:47:54 AM UTC 24 |
Sep 18 11:51:03 AM UTC 24 |
2527646721 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2582580234 |
|
|
Sep 18 11:32:38 AM UTC 24 |
Sep 18 11:51:07 AM UTC 24 |
64368646839 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3026251524 |
|
|
Sep 18 10:22:27 AM UTC 24 |
Sep 18 11:51:16 AM UTC 24 |
209063203520 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.4152122499 |
|
|
Sep 18 11:46:17 AM UTC 24 |
Sep 18 11:51:21 AM UTC 24 |
3932468009 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.329584933 |
|
|
Sep 18 11:50:35 AM UTC 24 |
Sep 18 11:51:52 AM UTC 24 |
3114348977 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1758686913 |
|
|
Sep 18 11:44:02 AM UTC 24 |
Sep 18 11:52:23 AM UTC 24 |
11043907902 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3292060197 |
|
|
Sep 18 11:51:08 AM UTC 24 |
Sep 18 11:52:24 AM UTC 24 |
23025552981 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3128711127 |
|
|
Sep 18 11:51:04 AM UTC 24 |
Sep 18 11:52:30 AM UTC 24 |
3199231448 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1684692881 |
|
|
Sep 18 11:52:25 AM UTC 24 |
Sep 18 11:52:32 AM UTC 24 |
1397199209 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.2005903782 |
|
|
Sep 18 11:46:08 AM UTC 24 |
Sep 18 11:52:35 AM UTC 24 |
5258535017 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1612912624 |
|
|
Sep 18 11:43:43 AM UTC 24 |
Sep 18 11:53:02 AM UTC 24 |
22160358739 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2394846622 |
|
|
Sep 18 11:53:03 AM UTC 24 |
Sep 18 11:53:05 AM UTC 24 |
40158435 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.113579481 |
|
|
Sep 18 11:53:06 AM UTC 24 |
Sep 18 11:53:14 AM UTC 24 |
2143778640 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.735584445 |
|
|
Sep 18 11:39:22 AM UTC 24 |
Sep 18 11:53:15 AM UTC 24 |
22789364836 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.717673352 |
|
|
Sep 18 11:48:46 AM UTC 24 |
Sep 18 11:53:19 AM UTC 24 |
3987119540 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2050048658 |
|
|
Sep 18 11:52:32 AM UTC 24 |
Sep 18 11:53:20 AM UTC 24 |
1187733288 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2638573092 |
|
|
Sep 18 11:53:21 AM UTC 24 |
Sep 18 11:54:04 AM UTC 24 |
1874811220 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1101810143 |
|
|
Sep 18 11:52:30 AM UTC 24 |
Sep 18 11:54:06 AM UTC 24 |
11426090191 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2786803529 |
|
|
Sep 18 11:51:17 AM UTC 24 |
Sep 18 11:54:37 AM UTC 24 |
10512225920 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.2943860270 |
|
|
Sep 18 11:38:19 AM UTC 24 |
Sep 18 11:54:44 AM UTC 24 |
29329902688 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1936130946 |
|
|
Sep 18 11:54:38 AM UTC 24 |
Sep 18 11:54:51 AM UTC 24 |
2118528041 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3294872439 |
|
|
Sep 18 11:54:45 AM UTC 24 |
Sep 18 11:55:09 AM UTC 24 |
3210229509 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1998228901 |
|
|
Sep 18 11:46:55 AM UTC 24 |
Sep 18 11:55:16 AM UTC 24 |
91772684035 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2737950318 |
|
|
Sep 18 11:54:06 AM UTC 24 |
Sep 18 11:55:36 AM UTC 24 |
797135647 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1151740427 |
|
|
Sep 18 11:55:38 AM UTC 24 |
Sep 18 11:55:45 AM UTC 24 |
871810314 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.2789471814 |
|
|
Sep 18 11:39:42 AM UTC 24 |
Sep 18 11:55:46 AM UTC 24 |
192482769306 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1709708724 |
|
|
Sep 18 11:52:25 AM UTC 24 |
Sep 18 11:56:00 AM UTC 24 |
7159953874 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.217153746 |
|
|
Sep 18 11:49:57 AM UTC 24 |
Sep 18 11:56:12 AM UTC 24 |
13042556542 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1960524912 |
|
|
Sep 18 11:40:36 AM UTC 24 |
Sep 18 11:56:22 AM UTC 24 |
58991692315 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3282467016 |
|
|
Sep 18 11:56:23 AM UTC 24 |
Sep 18 11:56:25 AM UTC 24 |
12148043 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.886372523 |
|
|
Sep 18 11:37:56 AM UTC 24 |
Sep 18 11:56:38 AM UTC 24 |
75945506270 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3826427438 |
|
|
Sep 18 11:56:26 AM UTC 24 |
Sep 18 11:56:40 AM UTC 24 |
3039762782 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.670902601 |
|
|
Sep 18 11:46:56 AM UTC 24 |
Sep 18 11:56:55 AM UTC 24 |
17873053726 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1657465551 |
|
|
Sep 18 11:56:00 AM UTC 24 |
Sep 18 11:56:57 AM UTC 24 |
1641021326 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.307299910 |
|
|
Sep 18 11:02:20 AM UTC 24 |
Sep 18 11:57:11 AM UTC 24 |
222364417130 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1529375716 |
|
|
Sep 18 11:56:59 AM UTC 24 |
Sep 18 11:57:12 AM UTC 24 |
2034872924 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.22092593 |
|
|
Sep 18 11:53:20 AM UTC 24 |
Sep 18 11:57:19 AM UTC 24 |
10473839131 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.1513218924 |
|
|
Sep 18 11:21:30 AM UTC 24 |
Sep 18 11:57:36 AM UTC 24 |
89741487154 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4006266038 |
|
|
Sep 18 10:12:10 AM UTC 24 |
Sep 18 11:58:09 AM UTC 24 |
62403508280 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4035549555 |
|
|
Sep 18 10:37:37 AM UTC 24 |
Sep 18 11:58:25 AM UTC 24 |
316505876248 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.678939502 |
|
|
Sep 18 11:38:07 AM UTC 24 |
Sep 18 11:58:27 AM UTC 24 |
86888672318 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.462790898 |
|
|
Sep 18 11:56:39 AM UTC 24 |
Sep 18 11:58:27 AM UTC 24 |
6201212170 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1851849943 |
|
|
Sep 18 11:57:20 AM UTC 24 |
Sep 18 11:58:28 AM UTC 24 |
1514468744 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.2902731154 |
|
|
Sep 18 11:40:52 AM UTC 24 |
Sep 18 11:58:34 AM UTC 24 |
60918137671 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1707540911 |
|
|
Sep 18 11:58:28 AM UTC 24 |
Sep 18 11:58:35 AM UTC 24 |
1605969588 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1063043419 |
|
|
Sep 18 11:57:13 AM UTC 24 |
Sep 18 11:58:35 AM UTC 24 |
790513139 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3780084401 |
|
|
Sep 18 11:55:47 AM UTC 24 |
Sep 18 11:58:39 AM UTC 24 |
20727824081 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2849567997 |
|
|
Sep 18 11:58:39 AM UTC 24 |
Sep 18 11:58:41 AM UTC 24 |
15469568 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2259356232 |
|
|
Sep 18 11:57:37 AM UTC 24 |
Sep 18 11:58:51 AM UTC 24 |
6315514234 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.893626278 |
|
|
Sep 18 11:58:42 AM UTC 24 |
Sep 18 11:59:12 AM UTC 24 |
1938503959 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2011460635 |
|
|
Sep 18 11:44:27 AM UTC 24 |
Sep 18 11:59:22 AM UTC 24 |
26149606906 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1782913675 |
|
|
Sep 18 11:58:35 AM UTC 24 |
Sep 18 11:59:55 AM UTC 24 |
1474012943 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.356451274 |
|
|
Sep 18 11:47:07 AM UTC 24 |
Sep 18 12:00:01 PM UTC 24 |
2950598202 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2077710816 |
|
|
Sep 18 10:50:49 AM UTC 24 |
Sep 18 12:00:07 PM UTC 24 |
238307059253 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2046020725 |
|
|
Sep 18 11:59:56 AM UTC 24 |
Sep 18 12:00:19 PM UTC 24 |
1394600074 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3483525184 |
|
|
Sep 18 12:00:08 PM UTC 24 |
Sep 18 12:00:25 PM UTC 24 |
2884143013 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2883893793 |
|
|
Sep 18 11:51:21 AM UTC 24 |
Sep 18 12:00:36 PM UTC 24 |
5062012858 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1757511467 |
|
|
Sep 18 11:54:05 AM UTC 24 |
Sep 18 12:00:52 PM UTC 24 |
8469519604 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.228453453 |
|
|
Sep 18 10:27:48 AM UTC 24 |
Sep 18 12:00:53 PM UTC 24 |
71978388941 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.31629195 |
|
|
Sep 18 12:00:54 PM UTC 24 |
Sep 18 12:01:01 PM UTC 24 |
352824235 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.469187182 |
|
|
Sep 18 11:56:55 AM UTC 24 |
Sep 18 12:01:02 PM UTC 24 |
24454119508 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.1014436639 |
|
|
Sep 18 12:00:07 PM UTC 24 |
Sep 18 12:01:11 PM UTC 24 |
762463871 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.183634200 |
|
|
Sep 18 12:00:20 PM UTC 24 |
Sep 18 12:01:13 PM UTC 24 |
36020928942 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.4071306035 |
|
|
Sep 18 11:58:29 AM UTC 24 |
Sep 18 12:01:25 PM UTC 24 |
35913333846 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.995059172 |
|
|
Sep 18 12:01:27 PM UTC 24 |
Sep 18 12:01:29 PM UTC 24 |
51307852 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.510853732 |
|
|
Sep 18 12:01:30 PM UTC 24 |
Sep 18 12:01:45 PM UTC 24 |
1446281506 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.3164823735 |
|
|
Sep 18 11:51:54 AM UTC 24 |
Sep 18 12:01:52 PM UTC 24 |
1969801920 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2148729386 |
|
|
Sep 18 11:48:35 AM UTC 24 |
Sep 18 12:01:57 PM UTC 24 |
37127329762 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.785918567 |
|
|
Sep 18 11:17:32 AM UTC 24 |
Sep 18 12:02:28 PM UTC 24 |
403191237837 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.908749115 |
|
|
Sep 18 12:01:12 PM UTC 24 |
Sep 18 12:02:39 PM UTC 24 |
6915409608 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4148276744 |
|
|
Sep 18 11:59:23 AM UTC 24 |
Sep 18 12:02:53 PM UTC 24 |
2944112806 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3434714928 |
|
|
Sep 18 11:53:15 AM UTC 24 |
Sep 18 12:02:56 PM UTC 24 |
56517772249 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.77798442 |
|
|
Sep 18 11:58:36 AM UTC 24 |
Sep 18 12:03:10 PM UTC 24 |
35601969239 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.820623771 |
|
|
Sep 18 12:02:29 PM UTC 24 |
Sep 18 12:03:13 PM UTC 24 |
1638062050 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.186358342 |
|
|
Sep 18 12:01:04 PM UTC 24 |
Sep 18 12:03:36 PM UTC 24 |
10180289038 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1387224617 |
|
|
Sep 18 12:02:53 PM UTC 24 |
Sep 18 12:03:42 PM UTC 24 |
770954265 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.1340968735 |
|
|
Sep 18 12:02:56 PM UTC 24 |
Sep 18 12:03:49 PM UTC 24 |
763934341 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4186435612 |
|
|
Sep 18 12:03:51 PM UTC 24 |
Sep 18 12:03:58 PM UTC 24 |
2260526576 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.620589285 |
|
|
Sep 18 12:03:12 PM UTC 24 |
Sep 18 12:04:55 PM UTC 24 |
13891615078 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.770087814 |
|
|
Sep 18 11:55:16 AM UTC 24 |
Sep 18 12:05:25 PM UTC 24 |
15975966709 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.225484956 |
|
|
Sep 18 11:45:44 AM UTC 24 |
Sep 18 12:05:58 PM UTC 24 |
38973456034 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1482123817 |
|
|
Sep 18 12:05:26 PM UTC 24 |
Sep 18 12:06:23 PM UTC 24 |
5105864323 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.737752920 |
|
|
Sep 18 12:06:25 PM UTC 24 |
Sep 18 12:06:27 PM UTC 24 |
11877695 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.278650417 |
|
|
Sep 18 12:01:59 PM UTC 24 |
Sep 18 12:06:29 PM UTC 24 |
4391311546 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.597482637 |
|
|
Sep 18 12:04:57 PM UTC 24 |
Sep 18 12:06:43 PM UTC 24 |
2789647840 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.363108103 |
|
|
Sep 18 11:10:35 AM UTC 24 |
Sep 18 12:07:14 PM UTC 24 |
18935204516 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2437125053 |
|
|
Sep 18 12:01:02 PM UTC 24 |
Sep 18 12:07:20 PM UTC 24 |
299773433780 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4129538754 |
|
|
Sep 18 12:06:28 PM UTC 24 |
Sep 18 12:07:36 PM UTC 24 |
1196306763 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1765153954 |
|
|
Sep 18 12:02:40 PM UTC 24 |
Sep 18 12:07:39 PM UTC 24 |
11108846923 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.870602655 |
|
|
Sep 18 12:07:40 PM UTC 24 |
Sep 18 12:07:59 PM UTC 24 |
3154665944 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.585953518 |
|
|
Sep 18 12:07:21 PM UTC 24 |
Sep 18 12:08:11 PM UTC 24 |
3256530707 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.521019542 |
|
|
Sep 18 11:57:12 AM UTC 24 |
Sep 18 12:08:12 PM UTC 24 |
74007666788 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1122398558 |
|
|
Sep 18 12:08:00 PM UTC 24 |
Sep 18 12:08:19 PM UTC 24 |
3864149562 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.3906674588 |
|
|
Sep 18 11:34:56 AM UTC 24 |
Sep 18 12:08:23 PM UTC 24 |
28301356377 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3433017656 |
|
|
Sep 18 12:00:02 PM UTC 24 |
Sep 18 12:08:25 PM UTC 24 |
7742249907 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3183920692 |
|
|
Sep 18 12:08:26 PM UTC 24 |
Sep 18 12:08:33 PM UTC 24 |
358519169 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1615302932 |
|
|
Sep 18 12:08:13 PM UTC 24 |
Sep 18 12:08:48 PM UTC 24 |
7840025185 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2181146795 |
|
|
Sep 18 11:24:53 AM UTC 24 |
Sep 18 12:09:05 PM UTC 24 |
505857558421 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2975356878 |
|
|
Sep 18 12:09:06 PM UTC 24 |
Sep 18 12:09:22 PM UTC 24 |
3106828493 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.3437666915 |
|
|
Sep 18 12:03:59 PM UTC 24 |
Sep 18 12:09:34 PM UTC 24 |
20691244287 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2595344493 |
|
|
Sep 18 12:09:35 PM UTC 24 |
Sep 18 12:09:38 PM UTC 24 |
23631564 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3791734697 |
|
|
Sep 18 11:41:40 AM UTC 24 |
Sep 18 12:09:46 PM UTC 24 |
32773072971 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1714409423 |
|
|
Sep 18 12:09:39 PM UTC 24 |
Sep 18 12:09:52 PM UTC 24 |
4082347765 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.923147103 |
|
|
Sep 18 11:54:52 AM UTC 24 |
Sep 18 12:10:06 PM UTC 24 |
177066592644 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1885330064 |
|
|
Sep 18 10:40:14 AM UTC 24 |
Sep 18 12:10:15 PM UTC 24 |
329134106783 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2348824807 |
|
|
Sep 18 12:03:37 PM UTC 24 |
Sep 18 12:10:17 PM UTC 24 |
33256078588 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3962950577 |
|
|
Sep 18 12:08:50 PM UTC 24 |
Sep 18 12:10:31 PM UTC 24 |
2637214933 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3659234955 |
|
|
Sep 18 11:58:11 AM UTC 24 |
Sep 18 12:10:34 PM UTC 24 |
55563326972 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2774557186 |
|
|
Sep 18 12:10:16 PM UTC 24 |
Sep 18 12:10:44 PM UTC 24 |
8127089155 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.841450972 |
|
|
Sep 18 12:10:34 PM UTC 24 |
Sep 18 12:10:51 PM UTC 24 |
4537689900 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2562524317 |
|
|
Sep 18 12:00:53 PM UTC 24 |
Sep 18 12:10:54 PM UTC 24 |
7699753509 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3861438807 |
|
|
Sep 18 12:10:32 PM UTC 24 |
Sep 18 12:11:10 PM UTC 24 |
5498839669 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.3130803886 |
|
|
Sep 18 12:10:45 PM UTC 24 |
Sep 18 12:11:10 PM UTC 24 |
6498949067 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2439000115 |
|
|
Sep 18 12:11:12 PM UTC 24 |
Sep 18 12:11:17 PM UTC 24 |
1689154572 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2237966559 |
|
|
Sep 18 12:01:46 PM UTC 24 |
Sep 18 12:12:18 PM UTC 24 |
16138826894 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1823223611 |
|
|
Sep 18 12:07:15 PM UTC 24 |
Sep 18 12:12:56 PM UTC 24 |
4879345047 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.857430565 |
|
|
Sep 18 12:12:57 PM UTC 24 |
Sep 18 12:13:53 PM UTC 24 |
10252153249 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3436511724 |
|
|
Sep 18 12:11:18 PM UTC 24 |
Sep 18 12:14:12 PM UTC 24 |
6923245070 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3299085349 |
|
|
Sep 18 12:14:13 PM UTC 24 |
Sep 18 12:14:16 PM UTC 24 |
16494216 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1135022969 |
|
|
Sep 18 12:12:20 PM UTC 24 |
Sep 18 12:14:17 PM UTC 24 |
2689607019 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3939245696 |
|
|
Sep 18 12:10:06 PM UTC 24 |
Sep 18 12:14:23 PM UTC 24 |
3417626635 ps |