| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.92 | 99.17 | 94.27 | 99.72 | 100.00 | 95.89 | 99.13 | 97.26 |
| T1008 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1370947280 | Sep 18 08:21:40 AM UTC 24 | Sep 18 08:21:46 AM UTC 24 | 430086840 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.325184819 | Sep 18 08:21:44 AM UTC 24 | Sep 18 08:21:46 AM UTC 24 | 12927580 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3681047781 | Sep 18 08:21:41 AM UTC 24 | Sep 18 08:21:47 AM UTC 24 | 213172636 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1262734279 | Sep 18 08:21:44 AM UTC 24 | Sep 18 08:21:47 AM UTC 24 | 324088104 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2983907056 | Sep 18 08:21:45 AM UTC 24 | Sep 18 08:21:48 AM UTC 24 | 76319676 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3390373187 | Sep 18 08:21:13 AM UTC 24 | Sep 18 08:21:48 AM UTC 24 | 14801707588 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1240822452 | Sep 18 08:21:44 AM UTC 24 | Sep 18 08:21:49 AM UTC 24 | 31571498 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2662633633 | Sep 18 08:21:48 AM UTC 24 | Sep 18 08:21:50 AM UTC 24 | 28864909 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2750239490 | Sep 18 08:21:47 AM UTC 24 | Sep 18 08:21:50 AM UTC 24 | 257983447 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.8703782 | Sep 18 08:21:48 AM UTC 24 | Sep 18 08:21:50 AM UTC 24 | 15111762 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2071440242 | Sep 18 08:21:43 AM UTC 24 | Sep 18 08:21:50 AM UTC 24 | 356459593 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1197352291 | Sep 18 08:21:47 AM UTC 24 | Sep 18 08:21:51 AM UTC 24 | 73455406 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3432123348 | Sep 18 08:21:50 AM UTC 24 | Sep 18 08:21:52 AM UTC 24 | 12842030 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2581251644 | Sep 18 08:21:47 AM UTC 24 | Sep 18 08:21:53 AM UTC 24 | 2457534944 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2970789548 | Sep 18 08:21:51 AM UTC 24 | Sep 18 08:21:53 AM UTC 24 | 34000852 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2883453118 | Sep 18 08:21:50 AM UTC 24 | Sep 18 08:21:54 AM UTC 24 | 584331201 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1087982391 | Sep 18 08:21:50 AM UTC 24 | Sep 18 08:21:54 AM UTC 24 | 52831815 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.156119168 | Sep 18 08:21:49 AM UTC 24 | Sep 18 08:21:55 AM UTC 24 | 746370930 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2446876047 | Sep 18 08:21:54 AM UTC 24 | Sep 18 08:21:56 AM UTC 24 | 27152315 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1754989099 | Sep 18 08:21:55 AM UTC 24 | Sep 18 08:21:57 AM UTC 24 | 27963010 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2083940181 | Sep 18 08:21:54 AM UTC 24 | Sep 18 08:21:57 AM UTC 24 | 109053332 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.615722755 | Sep 18 08:21:18 AM UTC 24 | Sep 18 08:21:58 AM UTC 24 | 24590549810 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2657100884 | Sep 18 08:21:01 AM UTC 24 | Sep 18 08:21:58 AM UTC 24 | 61661142012 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3883614282 | Sep 18 08:21:51 AM UTC 24 | Sep 18 08:21:59 AM UTC 24 | 370292714 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1637633120 | Sep 18 08:21:52 AM UTC 24 | Sep 18 08:21:59 AM UTC 24 | 116549639 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1468412791 | Sep 18 08:21:26 AM UTC 24 | Sep 18 08:22:01 AM UTC 24 | 10635304306 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3133047548 | Sep 18 08:21:55 AM UTC 24 | Sep 18 08:22:02 AM UTC 24 | 2052308704 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2850918844 | Sep 18 08:21:20 AM UTC 24 | Sep 18 08:22:04 AM UTC 24 | 7393925615 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.919584708 | Sep 18 08:21:05 AM UTC 24 | Sep 18 08:22:06 AM UTC 24 | 14254973908 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.74103516 | Sep 18 08:21:24 AM UTC 24 | Sep 18 08:22:08 AM UTC 24 | 28460776571 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1003806082 | Sep 18 08:21:28 AM UTC 24 | Sep 18 08:22:09 AM UTC 24 | 15415185838 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1221474634 | Sep 18 08:21:12 AM UTC 24 | Sep 18 08:22:13 AM UTC 24 | 7453806253 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3805185444 | Sep 18 08:21:38 AM UTC 24 | Sep 18 08:22:15 AM UTC 24 | 16817983990 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2567434424 | Sep 18 08:21:51 AM UTC 24 | Sep 18 08:22:24 AM UTC 24 | 14770199727 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4216997540 | Sep 18 08:21:41 AM UTC 24 | Sep 18 08:22:27 AM UTC 24 | 24675201722 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1909511309 | Sep 18 08:21:31 AM UTC 24 | Sep 18 08:22:29 AM UTC 24 | 7134455788 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1529819238 | Sep 18 08:21:47 AM UTC 24 | Sep 18 08:22:45 AM UTC 24 | 28191735726 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2066321105 | Sep 18 08:21:35 AM UTC 24 | Sep 18 08:22:52 AM UTC 24 | 31977120612 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3172197963 | Sep 18 08:21:43 AM UTC 24 | Sep 18 08:23:05 AM UTC 24 | 7213581883 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.371643389 | Sep 18 08:21:49 AM UTC 24 | Sep 18 08:23:08 AM UTC 24 | 29434550769 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.582472791 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 747544173 ps |
| CPU time | 19.47 seconds |
| Started | Sep 18 10:01:24 AM UTC 24 |
| Finished | Sep 18 10:01:45 AM UTC 24 |
| Peak memory | 256204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582472791 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.582472791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.696544689 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8925341496 ps |
| CPU time | 87.87 seconds |
| Started | Sep 18 10:01:37 AM UTC 24 |
| Finished | Sep 18 10:03:07 AM UTC 24 |
| Peak memory | 319756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696544689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.696544689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.526067104 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 402645997 ps |
| CPU time | 2.45 seconds |
| Started | Sep 18 10:01:38 AM UTC 24 |
| Finished | Sep 18 10:01:42 AM UTC 24 |
| Peak memory | 248172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526067104 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.526067104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2501197079 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7695145461 ps |
| CPU time | 512.28 seconds |
| Started | Sep 18 10:01:16 AM UTC 24 |
| Finished | Sep 18 10:09:55 AM UTC 24 |
| Peak memory | 366876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501197079 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2501197079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2810803129 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 6287409927 ps |
| CPU time | 44.83 seconds |
| Started | Sep 18 10:04:41 AM UTC 24 |
| Finished | Sep 18 10:05:27 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810803129 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2810803129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.581570570 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 9554251554 ps |
| CPU time | 7.09 seconds |
| Started | Sep 18 08:21:01 AM UTC 24 |
| Finished | Sep 18 08:21:09 AM UTC 24 |
| Peak memory | 213772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5815 70570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_i ntg_err.581570570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1429708918 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 31065440256 ps |
| CPU time | 385.23 seconds |
| Started | Sep 18 10:01:14 AM UTC 24 |
| Finished | Sep 18 10:07:44 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429708918 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_ac cess_b2b.1429708918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2351236169 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9293862882 ps |
| CPU time | 73.18 seconds |
| Started | Sep 18 10:01:17 AM UTC 24 |
| Finished | Sep 18 10:02:32 AM UTC 24 |
| Peak memory | 325968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351236169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2351236169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1888771088 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5492373903 ps |
| CPU time | 1061.39 seconds |
| Started | Sep 18 10:04:56 AM UTC 24 |
| Finished | Sep 18 10:22:49 AM UTC 24 |
| Peak memory | 389400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888771088 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1888771088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2113213717 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 43712374 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 08:20:52 AM UTC 24 |
| Finished | Sep 18 08:20:54 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113213 717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_al iasing.2113213717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.681303623 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 29656884988 ps |
| CPU time | 1068.69 seconds |
| Started | Sep 18 10:11:39 AM UTC 24 |
| Finished | Sep 18 10:29:39 AM UTC 24 |
| Peak memory | 389316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681303623 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.681303623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.676428936 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 683026295 ps |
| CPU time | 5.19 seconds |
| Started | Sep 18 10:01:16 AM UTC 24 |
| Finished | Sep 18 10:01:22 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676428936 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.676428936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1728286515 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2656825570 ps |
| CPU time | 120.81 seconds |
| Started | Sep 18 10:01:17 AM UTC 24 |
| Finished | Sep 18 10:03:21 AM UTC 24 |
| Peak memory | 222624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728286515 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.1728286515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.357577351 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 25191255022 ps |
| CPU time | 868.89 seconds |
| Started | Sep 18 10:01:31 AM UTC 24 |
| Finished | Sep 18 10:16:10 AM UTC 24 |
| Peak memory | 383416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357577351 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.357577351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2288252785 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 25992285997 ps |
| CPU time | 76.49 seconds |
| Started | Sep 18 10:17:04 AM UTC 24 |
| Finished | Sep 18 10:18:23 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288252785 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2288252785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.189363786 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 39708400 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 10:01:42 AM UTC 24 |
| Finished | Sep 18 10:01:45 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189363786 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.189363786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.606397129 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 288852308 ps |
| CPU time | 4.3 seconds |
| Started | Sep 18 08:21:37 AM UTC 24 |
| Finished | Sep 18 08:21:42 AM UTC 24 |
| Peak memory | 223928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6063 97129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_ intg_err.606397129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.942305492 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 39312799 ps |
| CPU time | 1 seconds |
| Started | Sep 18 08:21:19 AM UTC 24 |
| Finished | Sep 18 08:21:21 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942305492 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.942305492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2629315349 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 349529770 ps |
| CPU time | 2.6 seconds |
| Started | Sep 18 08:21:42 AM UTC 24 |
| Finished | Sep 18 08:21:45 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629 315349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl _intg_err.2629315349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2883453118 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 584331201 ps |
| CPU time | 3.12 seconds |
| Started | Sep 18 08:21:50 AM UTC 24 |
| Finished | Sep 18 08:21:54 AM UTC 24 |
| Peak memory | 223940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883 453118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl _intg_err.2883453118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.127893119 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3623660266 ps |
| CPU time | 38.75 seconds |
| Started | Sep 18 10:22:23 AM UTC 24 |
| Finished | Sep 18 10:23:04 AM UTC 24 |
| Peak memory | 229264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127893119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.127893119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2560442736 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 57961683047 ps |
| CPU time | 130.83 seconds |
| Started | Sep 18 10:01:15 AM UTC 24 |
| Finished | Sep 18 10:03:28 AM UTC 24 |
| Peak memory | 222840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560442736 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.2560442736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1661030894 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3899417588 ps |
| CPU time | 32.27 seconds |
| Started | Sep 18 08:20:48 AM UTC 24 |
| Finished | Sep 18 08:21:22 AM UTC 24 |
| Peak memory | 213548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 661030894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ passthru_mem_tl_intg_err.1661030894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2987491046 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 46365291 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 08:20:51 AM UTC 24 |
| Finished | Sep 18 08:20:54 AM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987491 046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bi t_bash.2987491046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3889798075 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 225185705 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 08:20:51 AM UTC 24 |
| Finished | Sep 18 08:20:53 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889798 075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw _reset.3889798075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2112548885 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 360743670 ps |
| CPU time | 7.73 seconds |
| Started | Sep 18 08:20:52 AM UTC 24 |
| Finished | Sep 18 08:21:01 AM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2112548885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2112548885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2648519941 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 46507941 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 08:20:51 AM UTC 24 |
| Finished | Sep 18 08:20:53 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648519941 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2648519941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1583889077 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 35068308 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 08:20:52 AM UTC 24 |
| Finished | Sep 18 08:20:54 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1583889077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram _ctrl_same_csr_outstanding.1583889077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.235703208 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 566296629 ps |
| CPU time | 4.99 seconds |
| Started | Sep 18 08:20:48 AM UTC 24 |
| Finished | Sep 18 08:20:54 AM UTC 24 |
| Peak memory | 224256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235703208 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.235703208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.258908047 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 621778065 ps |
| CPU time | 4.02 seconds |
| Started | Sep 18 08:20:48 AM UTC 24 |
| Finished | Sep 18 08:20:53 AM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589 08047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_i ntg_err.258908047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.471879878 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 20067503 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 08:20:55 AM UTC 24 |
| Finished | Sep 18 08:20:57 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4718798 78 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_ali asing.471879878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3100457051 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 201516451 ps |
| CPU time | 3.61 seconds |
| Started | Sep 18 08:20:55 AM UTC 24 |
| Finished | Sep 18 08:21:00 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100457 051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bi t_bash.3100457051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.987647936 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 15469688 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 08:20:54 AM UTC 24 |
| Finished | Sep 18 08:20:56 AM UTC 24 |
| Peak memory | 212492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9876479 36 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_ reset.987647936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.367743418 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 360147813 ps |
| CPU time | 6.85 seconds |
| Started | Sep 18 08:20:56 AM UTC 24 |
| Finished | Sep 18 08:21:03 AM UTC 24 |
| Peak memory | 223932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=367743418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.367743418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.252546890 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 20821748 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 08:20:54 AM UTC 24 |
| Finished | Sep 18 08:20:56 AM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252546890 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.252546890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3552880199 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 7415254008 ps |
| CPU time | 32.49 seconds |
| Started | Sep 18 08:20:53 AM UTC 24 |
| Finished | Sep 18 08:21:27 AM UTC 24 |
| Peak memory | 213628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 552880199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ passthru_mem_tl_intg_err.3552880199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1948509682 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 20957563 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 08:20:55 AM UTC 24 |
| Finished | Sep 18 08:20:57 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1948509682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram _ctrl_same_csr_outstanding.1948509682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1929507998 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 168111645 ps |
| CPU time | 5.01 seconds |
| Started | Sep 18 08:20:53 AM UTC 24 |
| Finished | Sep 18 08:20:59 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929507998 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.1929507998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1158317490 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 529231680 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 08:20:54 AM UTC 24 |
| Finished | Sep 18 08:20:58 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158 317490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_ intg_err.1158317490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.962544626 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3809875585 ps |
| CPU time | 7.35 seconds |
| Started | Sep 18 08:21:28 AM UTC 24 |
| Finished | Sep 18 08:21:36 AM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=962544626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.962544626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2804877765 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 15084038 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 08:21:28 AM UTC 24 |
| Finished | Sep 18 08:21:30 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804877765 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2804877765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1468412791 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 10635304306 ps |
| CPU time | 33.76 seconds |
| Started | Sep 18 08:21:26 AM UTC 24 |
| Finished | Sep 18 08:22:01 AM UTC 24 |
| Peak memory | 213616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 468412791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _passthru_mem_tl_intg_err.1468412791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2378214328 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 16070533 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 08:21:28 AM UTC 24 |
| Finished | Sep 18 08:21:30 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2378214328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sra m_ctrl_same_csr_outstanding.2378214328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3181194121 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 482157735 ps |
| CPU time | 6.72 seconds |
| Started | Sep 18 08:21:26 AM UTC 24 |
| Finished | Sep 18 08:21:33 AM UTC 24 |
| Peak memory | 224252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181194121 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.3181194121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3873442079 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 272670414 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 08:21:27 AM UTC 24 |
| Finished | Sep 18 08:21:30 AM UTC 24 |
| Peak memory | 224132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873 442079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl _intg_err.3873442079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2026878553 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 753853163 ps |
| CPU time | 6.34 seconds |
| Started | Sep 18 08:21:31 AM UTC 24 |
| Finished | Sep 18 08:21:39 AM UTC 24 |
| Peak memory | 223840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2026878553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2026878553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1099392151 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 14110287 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 08:21:30 AM UTC 24 |
| Finished | Sep 18 08:21:32 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099392151 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.1099392151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1003806082 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 15415185838 ps |
| CPU time | 38.98 seconds |
| Started | Sep 18 08:21:28 AM UTC 24 |
| Finished | Sep 18 08:22:09 AM UTC 24 |
| Peak memory | 213544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 003806082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _passthru_mem_tl_intg_err.1003806082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2955912359 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 19773712 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 08:21:30 AM UTC 24 |
| Finished | Sep 18 08:21:32 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2955912359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sra m_ctrl_same_csr_outstanding.2955912359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2372766026 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 292781073 ps |
| CPU time | 3.13 seconds |
| Started | Sep 18 08:21:29 AM UTC 24 |
| Finished | Sep 18 08:21:33 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372766026 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.2372766026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.399788646 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 699320618 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 08:21:30 AM UTC 24 |
| Finished | Sep 18 08:21:34 AM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997 88646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_ intg_err.399788646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3633840755 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 728751815 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 08:21:35 AM UTC 24 |
| Finished | Sep 18 08:21:40 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3633840755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3633840755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2644589557 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 57267279 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 08:21:34 AM UTC 24 |
| Finished | Sep 18 08:21:36 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644589557 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.2644589557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1909511309 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 7134455788 ps |
| CPU time | 56.23 seconds |
| Started | Sep 18 08:21:31 AM UTC 24 |
| Finished | Sep 18 08:22:29 AM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 909511309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _passthru_mem_tl_intg_err.1909511309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3861029916 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 27963249 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 08:21:35 AM UTC 24 |
| Finished | Sep 18 08:21:37 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3861029916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sra m_ctrl_same_csr_outstanding.3861029916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.70087532 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 151832912 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 08:21:33 AM UTC 24 |
| Finished | Sep 18 08:21:37 AM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70087532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.70087532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1035811864 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 139156971 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 08:21:34 AM UTC 24 |
| Finished | Sep 18 08:21:37 AM UTC 24 |
| Peak memory | 223944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035 811864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl _intg_err.1035811864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.732788089 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 1221538738 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 08:21:38 AM UTC 24 |
| Finished | Sep 18 08:21:43 AM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=732788089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.732788089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4219512913 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 32767049 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 08:21:37 AM UTC 24 |
| Finished | Sep 18 08:21:39 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219512913 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.4219512913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2066321105 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 31977120612 ps |
| CPU time | 75.86 seconds |
| Started | Sep 18 08:21:35 AM UTC 24 |
| Finished | Sep 18 08:22:52 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 066321105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _passthru_mem_tl_intg_err.2066321105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1247772426 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 14757359 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 08:21:37 AM UTC 24 |
| Finished | Sep 18 08:21:39 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1247772426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sra m_ctrl_same_csr_outstanding.1247772426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1738160476 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 65292382 ps |
| CPU time | 3.74 seconds |
| Started | Sep 18 08:21:36 AM UTC 24 |
| Finished | Sep 18 08:21:41 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738160476 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.1738160476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1370947280 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 430086840 ps |
| CPU time | 5.33 seconds |
| Started | Sep 18 08:21:40 AM UTC 24 |
| Finished | Sep 18 08:21:46 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1370947280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1370947280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.722128387 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 29860240 ps |
| CPU time | 1 seconds |
| Started | Sep 18 08:21:40 AM UTC 24 |
| Finished | Sep 18 08:21:42 AM UTC 24 |
| Peak memory | 212504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722128387 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.722128387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3805185444 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 16817983990 ps |
| CPU time | 35.32 seconds |
| Started | Sep 18 08:21:38 AM UTC 24 |
| Finished | Sep 18 08:22:15 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 805185444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _passthru_mem_tl_intg_err.3805185444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1149774604 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 31982130 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 08:21:40 AM UTC 24 |
| Finished | Sep 18 08:21:42 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1149774604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra m_ctrl_same_csr_outstanding.1149774604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.427455095 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 60234959 ps |
| CPU time | 3.45 seconds |
| Started | Sep 18 08:21:38 AM UTC 24 |
| Finished | Sep 18 08:21:43 AM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427455095 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.427455095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2445558556 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 211902223 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 08:21:38 AM UTC 24 |
| Finished | Sep 18 08:21:42 AM UTC 24 |
| Peak memory | 223932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445 558556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl _intg_err.2445558556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2071440242 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 356459593 ps |
| CPU time | 6.02 seconds |
| Started | Sep 18 08:21:43 AM UTC 24 |
| Finished | Sep 18 08:21:50 AM UTC 24 |
| Peak memory | 224264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2071440242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2071440242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.864911912 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 18588667 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 08:21:42 AM UTC 24 |
| Finished | Sep 18 08:21:44 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864911912 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.864911912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4216997540 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 24675201722 ps |
| CPU time | 44.64 seconds |
| Started | Sep 18 08:21:41 AM UTC 24 |
| Finished | Sep 18 08:22:27 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 216997540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _passthru_mem_tl_intg_err.4216997540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1988223326 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 117320448 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 08:21:43 AM UTC 24 |
| Finished | Sep 18 08:21:45 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1988223326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sra m_ctrl_same_csr_outstanding.1988223326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3681047781 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 213172636 ps |
| CPU time | 5.39 seconds |
| Started | Sep 18 08:21:41 AM UTC 24 |
| Finished | Sep 18 08:21:47 AM UTC 24 |
| Peak memory | 224076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681047781 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.3681047781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2581251644 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 2457534944 ps |
| CPU time | 5.33 seconds |
| Started | Sep 18 08:21:47 AM UTC 24 |
| Finished | Sep 18 08:21:53 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2581251644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2581251644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.325184819 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 12927580 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 08:21:44 AM UTC 24 |
| Finished | Sep 18 08:21:46 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325184819 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.325184819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3172197963 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 7213581883 ps |
| CPU time | 79.6 seconds |
| Started | Sep 18 08:21:43 AM UTC 24 |
| Finished | Sep 18 08:23:05 AM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 172197963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _passthru_mem_tl_intg_err.3172197963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2983907056 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 76319676 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 08:21:45 AM UTC 24 |
| Finished | Sep 18 08:21:48 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2983907056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sra m_ctrl_same_csr_outstanding.2983907056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1240822452 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 31571498 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 08:21:44 AM UTC 24 |
| Finished | Sep 18 08:21:49 AM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240822452 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.1240822452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1262734279 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 324088104 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 08:21:44 AM UTC 24 |
| Finished | Sep 18 08:21:47 AM UTC 24 |
| Peak memory | 213688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262 734279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl _intg_err.1262734279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.156119168 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 746370930 ps |
| CPU time | 4.82 seconds |
| Started | Sep 18 08:21:49 AM UTC 24 |
| Finished | Sep 18 08:21:55 AM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=156119168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.156119168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2662633633 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 28864909 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 08:21:48 AM UTC 24 |
| Finished | Sep 18 08:21:50 AM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662633633 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.2662633633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1529819238 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 28191735726 ps |
| CPU time | 57.45 seconds |
| Started | Sep 18 08:21:47 AM UTC 24 |
| Finished | Sep 18 08:22:45 AM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 529819238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _passthru_mem_tl_intg_err.1529819238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.8703782 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 15111762 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 08:21:48 AM UTC 24 |
| Finished | Sep 18 08:21:50 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=8703782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_c trl_same_csr_outstanding.8703782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1197352291 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 73455406 ps |
| CPU time | 3.84 seconds |
| Started | Sep 18 08:21:47 AM UTC 24 |
| Finished | Sep 18 08:21:51 AM UTC 24 |
| Peak memory | 213820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197352291 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.1197352291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2750239490 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 257983447 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 08:21:47 AM UTC 24 |
| Finished | Sep 18 08:21:50 AM UTC 24 |
| Peak memory | 224196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750 239490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl _intg_err.2750239490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3883614282 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 370292714 ps |
| CPU time | 6.2 seconds |
| Started | Sep 18 08:21:51 AM UTC 24 |
| Finished | Sep 18 08:21:59 AM UTC 24 |
| Peak memory | 223796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3883614282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3883614282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3432123348 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 12842030 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 08:21:50 AM UTC 24 |
| Finished | Sep 18 08:21:52 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432123348 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.3432123348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.371643389 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 29434550769 ps |
| CPU time | 77.51 seconds |
| Started | Sep 18 08:21:49 AM UTC 24 |
| Finished | Sep 18 08:23:08 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 71643389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ passthru_mem_tl_intg_err.371643389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2970789548 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 34000852 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 08:21:51 AM UTC 24 |
| Finished | Sep 18 08:21:53 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2970789548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra m_ctrl_same_csr_outstanding.2970789548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1087982391 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 52831815 ps |
| CPU time | 3.22 seconds |
| Started | Sep 18 08:21:50 AM UTC 24 |
| Finished | Sep 18 08:21:54 AM UTC 24 |
| Peak memory | 213820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087982391 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.1087982391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3133047548 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 2052308704 ps |
| CPU time | 5.93 seconds |
| Started | Sep 18 08:21:55 AM UTC 24 |
| Finished | Sep 18 08:22:02 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3133047548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3133047548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2446876047 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 27152315 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 08:21:54 AM UTC 24 |
| Finished | Sep 18 08:21:56 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446876047 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.2446876047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2567434424 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 14770199727 ps |
| CPU time | 31.6 seconds |
| Started | Sep 18 08:21:51 AM UTC 24 |
| Finished | Sep 18 08:22:24 AM UTC 24 |
| Peak memory | 213616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 567434424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _passthru_mem_tl_intg_err.2567434424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1754989099 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 27963010 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 08:21:55 AM UTC 24 |
| Finished | Sep 18 08:21:57 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1754989099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sra m_ctrl_same_csr_outstanding.1754989099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1637633120 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 116549639 ps |
| CPU time | 5.89 seconds |
| Started | Sep 18 08:21:52 AM UTC 24 |
| Finished | Sep 18 08:21:59 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637633120 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.1637633120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2083940181 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 109053332 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 08:21:54 AM UTC 24 |
| Finished | Sep 18 08:21:57 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083 940181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl _intg_err.2083940181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.331833815 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 68314637 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 08:21:00 AM UTC 24 |
| Finished | Sep 18 08:21:02 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318338 15 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_ali asing.331833815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2972362463 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 73405442 ps |
| CPU time | 2.13 seconds |
| Started | Sep 18 08:20:59 AM UTC 24 |
| Finished | Sep 18 08:21:02 AM UTC 24 |
| Peak memory | 213632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972362 463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bi t_bash.2972362463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3042703715 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 96109316 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 08:20:58 AM UTC 24 |
| Finished | Sep 18 08:21:00 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042703 715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw _reset.3042703715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.732304785 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 361756396 ps |
| CPU time | 4.59 seconds |
| Started | Sep 18 08:21:01 AM UTC 24 |
| Finished | Sep 18 08:21:07 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=732304785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.732304785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2982568500 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 12268200 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 08:20:58 AM UTC 24 |
| Finished | Sep 18 08:21:00 AM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982568500 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.2982568500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2068564635 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 14780576829 ps |
| CPU time | 38.92 seconds |
| Started | Sep 18 08:20:57 AM UTC 24 |
| Finished | Sep 18 08:21:37 AM UTC 24 |
| Peak memory | 213624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 068564635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ passthru_mem_tl_intg_err.2068564635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.48427173 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 49684961 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 08:21:01 AM UTC 24 |
| Finished | Sep 18 08:21:03 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=48427173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c trl_same_csr_outstanding.48427173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3768364122 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 144960018 ps |
| CPU time | 4.35 seconds |
| Started | Sep 18 08:20:57 AM UTC 24 |
| Finished | Sep 18 08:21:02 AM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768364122 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.3768364122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2549910958 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 167958647 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 08:20:57 AM UTC 24 |
| Finished | Sep 18 08:21:00 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549 910958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_ intg_err.2549910958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.111015360 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 23399293 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 08:21:04 AM UTC 24 |
| Finished | Sep 18 08:21:06 AM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110153 60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_ali asing.111015360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.61527984 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 99080135 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 08:21:03 AM UTC 24 |
| Finished | Sep 18 08:21:05 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6152798 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_ bash.61527984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3896237762 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 12055135 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 08:21:02 AM UTC 24 |
| Finished | Sep 18 08:21:04 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896237 762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw _reset.3896237762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.945646470 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3459950610 ps |
| CPU time | 5.06 seconds |
| Started | Sep 18 08:21:05 AM UTC 24 |
| Finished | Sep 18 08:21:11 AM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=945646470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.945646470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2621451500 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 142666898 ps |
| CPU time | 1 seconds |
| Started | Sep 18 08:21:03 AM UTC 24 |
| Finished | Sep 18 08:21:04 AM UTC 24 |
| Peak memory | 212504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621451500 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.2621451500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2657100884 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 61661142012 ps |
| CPU time | 55.18 seconds |
| Started | Sep 18 08:21:01 AM UTC 24 |
| Finished | Sep 18 08:21:58 AM UTC 24 |
| Peak memory | 213756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 657100884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ passthru_mem_tl_intg_err.2657100884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2986519934 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 47075832 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 08:21:04 AM UTC 24 |
| Finished | Sep 18 08:21:06 AM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2986519934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram _ctrl_same_csr_outstanding.2986519934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.976070871 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 467893947 ps |
| CPU time | 6.33 seconds |
| Started | Sep 18 08:21:01 AM UTC 24 |
| Finished | Sep 18 08:21:09 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976070871 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.976070871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1239132106 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 19416125 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 08:21:10 AM UTC 24 |
| Finished | Sep 18 08:21:12 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239132 106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_al iasing.1239132106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3320102999 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 30977130 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 08:21:09 AM UTC 24 |
| Finished | Sep 18 08:21:12 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320102 999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bi t_bash.3320102999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4054277676 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 23503654 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 08:21:07 AM UTC 24 |
| Finished | Sep 18 08:21:09 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054277 676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw _reset.4054277676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3889263563 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 357432580 ps |
| CPU time | 5.99 seconds |
| Started | Sep 18 08:21:11 AM UTC 24 |
| Finished | Sep 18 08:21:18 AM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3889263563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3889263563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2214803044 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 19000727 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 08:21:08 AM UTC 24 |
| Finished | Sep 18 08:21:10 AM UTC 24 |
| Peak memory | 212504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214803044 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.2214803044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.919584708 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 14254973908 ps |
| CPU time | 59.24 seconds |
| Started | Sep 18 08:21:05 AM UTC 24 |
| Finished | Sep 18 08:22:06 AM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 19584708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_p assthru_mem_tl_intg_err.919584708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2613754836 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 23724340 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 08:21:10 AM UTC 24 |
| Finished | Sep 18 08:21:12 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2613754836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram _ctrl_same_csr_outstanding.2613754836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2655697929 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 73043145 ps |
| CPU time | 4.29 seconds |
| Started | Sep 18 08:21:06 AM UTC 24 |
| Finished | Sep 18 08:21:11 AM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655697929 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.2655697929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1497551384 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 779752122 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 08:21:07 AM UTC 24 |
| Finished | Sep 18 08:21:12 AM UTC 24 |
| Peak memory | 213704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497 551384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_ intg_err.1497551384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3467121273 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 374571392 ps |
| CPU time | 6.22 seconds |
| Started | Sep 18 08:21:13 AM UTC 24 |
| Finished | Sep 18 08:21:20 AM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3467121273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3467121273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.316262430 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 14907248 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 08:21:13 AM UTC 24 |
| Finished | Sep 18 08:21:15 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316262430 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.316262430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1221474634 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 7453806253 ps |
| CPU time | 59.68 seconds |
| Started | Sep 18 08:21:12 AM UTC 24 |
| Finished | Sep 18 08:22:13 AM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 221474634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ passthru_mem_tl_intg_err.1221474634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1813699459 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 97446765 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 08:21:13 AM UTC 24 |
| Finished | Sep 18 08:21:15 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1813699459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram _ctrl_same_csr_outstanding.1813699459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3263541552 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 115902129 ps |
| CPU time | 4.92 seconds |
| Started | Sep 18 08:21:12 AM UTC 24 |
| Finished | Sep 18 08:21:17 AM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263541552 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3263541552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1689498698 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 230617716 ps |
| CPU time | 3.9 seconds |
| Started | Sep 18 08:21:13 AM UTC 24 |
| Finished | Sep 18 08:21:18 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689 498698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_ intg_err.1689498698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3870488479 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2557065094 ps |
| CPU time | 5.78 seconds |
| Started | Sep 18 08:21:16 AM UTC 24 |
| Finished | Sep 18 08:21:23 AM UTC 24 |
| Peak memory | 231208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3870488479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3870488479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3478031520 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 37784484 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 08:21:15 AM UTC 24 |
| Finished | Sep 18 08:21:17 AM UTC 24 |
| Peak memory | 212504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478031520 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.3478031520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3390373187 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 14801707588 ps |
| CPU time | 33.64 seconds |
| Started | Sep 18 08:21:13 AM UTC 24 |
| Finished | Sep 18 08:21:48 AM UTC 24 |
| Peak memory | 213548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 390373187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ passthru_mem_tl_intg_err.3390373187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4105949083 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 14296839 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 08:21:15 AM UTC 24 |
| Finished | Sep 18 08:21:17 AM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4105949083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram _ctrl_same_csr_outstanding.4105949083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3477245744 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 101159942 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 08:21:14 AM UTC 24 |
| Finished | Sep 18 08:21:18 AM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477245744 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3477245744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.536329052 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 172218674 ps |
| CPU time | 2.87 seconds |
| Started | Sep 18 08:21:14 AM UTC 24 |
| Finished | Sep 18 08:21:18 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5363 29052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_i ntg_err.536329052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.785257859 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2230219038 ps |
| CPU time | 4.35 seconds |
| Started | Sep 18 08:21:19 AM UTC 24 |
| Finished | Sep 18 08:21:24 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=785257859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.785257859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.615722755 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 24590549810 ps |
| CPU time | 38.02 seconds |
| Started | Sep 18 08:21:18 AM UTC 24 |
| Finished | Sep 18 08:21:58 AM UTC 24 |
| Peak memory | 223928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 15722755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_p assthru_mem_tl_intg_err.615722755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2545858985 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 37673715 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 08:21:19 AM UTC 24 |
| Finished | Sep 18 08:21:21 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2545858985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram _ctrl_same_csr_outstanding.2545858985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1109506634 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 146379842 ps |
| CPU time | 5.22 seconds |
| Started | Sep 18 08:21:19 AM UTC 24 |
| Finished | Sep 18 08:21:25 AM UTC 24 |
| Peak memory | 213768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109506634 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.1109506634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.189330545 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 101989347 ps |
| CPU time | 2.51 seconds |
| Started | Sep 18 08:21:19 AM UTC 24 |
| Finished | Sep 18 08:21:22 AM UTC 24 |
| Peak memory | 223944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893 30545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_i ntg_err.189330545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.769173454 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 412216168 ps |
| CPU time | 5.03 seconds |
| Started | Sep 18 08:21:23 AM UTC 24 |
| Finished | Sep 18 08:21:29 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=769173454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.769173454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2204810281 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 70640368 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 08:21:22 AM UTC 24 |
| Finished | Sep 18 08:21:24 AM UTC 24 |
| Peak memory | 212504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204810281 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.2204810281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2850918844 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 7393925615 ps |
| CPU time | 42.49 seconds |
| Started | Sep 18 08:21:20 AM UTC 24 |
| Finished | Sep 18 08:22:04 AM UTC 24 |
| Peak memory | 213692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 850918844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ passthru_mem_tl_intg_err.2850918844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2874191557 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 46674656 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 08:21:23 AM UTC 24 |
| Finished | Sep 18 08:21:25 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2874191557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram _ctrl_same_csr_outstanding.2874191557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3338619856 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 372373708 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 08:21:21 AM UTC 24 |
| Finished | Sep 18 08:21:25 AM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338619856 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.3338619856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.722376891 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 770186524 ps |
| CPU time | 3.84 seconds |
| Started | Sep 18 08:21:21 AM UTC 24 |
| Finished | Sep 18 08:21:26 AM UTC 24 |
| Peak memory | 213704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7223 76891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_i ntg_err.722376891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.29302036 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 1193436389 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 08:21:26 AM UTC 24 |
| Finished | Sep 18 08:21:31 AM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=29302036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.29302036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.34016910 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 44928232 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 08:21:26 AM UTC 24 |
| Finished | Sep 18 08:21:28 AM UTC 24 |
| Peak memory | 213072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34016910 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.34016910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.74103516 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 28460776571 ps |
| CPU time | 42.78 seconds |
| Started | Sep 18 08:21:24 AM UTC 24 |
| Finished | Sep 18 08:22:08 AM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 4103516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa ssthru_mem_tl_intg_err.74103516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4053599191 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 19830179 ps |
| CPU time | 1 seconds |
| Started | Sep 18 08:21:26 AM UTC 24 |
| Finished | Sep 18 08:21:28 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4053599191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram _ctrl_same_csr_outstanding.4053599191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.756537638 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 71529691 ps |
| CPU time | 3.25 seconds |
| Started | Sep 18 08:21:25 AM UTC 24 |
| Finished | Sep 18 08:21:30 AM UTC 24 |
| Peak memory | 224056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756537638 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.756537638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3388397394 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 95100008 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 08:21:25 AM UTC 24 |
| Finished | Sep 18 08:21:29 AM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388 397394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_ intg_err.3388397394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2903694069 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 15948256305 ps |
| CPU time | 615.96 seconds |
| Started | Sep 18 10:01:15 AM UTC 24 |
| Finished | Sep 18 10:11:38 AM UTC 24 |
| Peak memory | 389332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903694069 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_durin g_key_req.2903694069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.431962838 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 114128042 ps |
| CPU time | 0.76 seconds |
| Started | Sep 18 10:01:19 AM UTC 24 |
| Finished | Sep 18 10:01:20 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431962838 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.431962838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.2444133857 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 102689964735 ps |
| CPU time | 2128.71 seconds |
| Started | Sep 18 10:01:13 AM UTC 24 |
| Finished | Sep 18 10:37:04 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444133857 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.2444133857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.1945504025 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 20861109102 ps |
| CPU time | 637.26 seconds |
| Started | Sep 18 10:01:15 AM UTC 24 |
| Finished | Sep 18 10:11:59 AM UTC 24 |
| Peak memory | 387360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945504025 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.1945504025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3521480909 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1442682600 ps |
| CPU time | 15.74 seconds |
| Started | Sep 18 10:01:15 AM UTC 24 |
| Finished | Sep 18 10:01:32 AM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3521480909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m ax_throughput.3521480909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2883054351 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7190116965 ps |
| CPU time | 169.81 seconds |
| Started | Sep 18 10:01:16 AM UTC 24 |
| Finished | Sep 18 10:04:09 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883054351 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2883054351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.233744089 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 120077071543 ps |
| CPU time | 1248.7 seconds |
| Started | Sep 18 10:01:13 AM UTC 24 |
| Finished | Sep 18 10:22:15 AM UTC 24 |
| Peak memory | 389568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233744089 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.233744089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2419479131 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4119247398 ps |
| CPU time | 15.2 seconds |
| Started | Sep 18 10:01:14 AM UTC 24 |
| Finished | Sep 18 10:01:30 AM UTC 24 |
| Peak memory | 212404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419479131 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.2419479131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1661085990 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 663223429 ps |
| CPU time | 4.51 seconds |
| Started | Sep 18 10:01:18 AM UTC 24 |
| Finished | Sep 18 10:01:24 AM UTC 24 |
| Peak memory | 248120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661085990 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1661085990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.1045583340 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1983428177 ps |
| CPU time | 16.02 seconds |
| Started | Sep 18 10:01:13 AM UTC 24 |
| Finished | Sep 18 10:01:30 AM UTC 24 |
| Peak memory | 212608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045583340 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1045583340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.899514214 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 194450029224 ps |
| CPU time | 5546.75 seconds |
| Started | Sep 18 10:01:17 AM UTC 24 |
| Finished | Sep 18 11:34:46 AM UTC 24 |
| Peak memory | 401176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89951421 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.899514214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.445463812 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 10651478837 ps |
| CPU time | 379.29 seconds |
| Started | Sep 18 10:01:14 AM UTC 24 |
| Finished | Sep 18 10:07:38 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445463812 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.445463812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.397288920 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1568494344 ps |
| CPU time | 78.23 seconds |
| Started | Sep 18 10:01:15 AM UTC 24 |
| Finished | Sep 18 10:02:35 AM UTC 24 |
| Peak memory | 383184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =397288920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_t hroughput_w_partial_write.397288920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2489992157 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 45038315661 ps |
| CPU time | 374.53 seconds |
| Started | Sep 18 10:01:31 AM UTC 24 |
| Finished | Sep 18 10:07:50 AM UTC 24 |
| Peak memory | 383264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489992157 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin g_key_req.2489992157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.792396328 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 146281565125 ps |
| CPU time | 2337.59 seconds |
| Started | Sep 18 10:01:22 AM UTC 24 |
| Finished | Sep 18 10:40:44 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792396328 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.792396328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.670327708 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 15068555650 ps |
| CPU time | 123.61 seconds |
| Started | Sep 18 10:01:30 AM UTC 24 |
| Finished | Sep 18 10:03:36 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670327708 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.670327708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.709197583 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 761392057 ps |
| CPU time | 74.77 seconds |
| Started | Sep 18 10:01:26 AM UTC 24 |
| Finished | Sep 18 10:02:43 AM UTC 24 |
| Peak memory | 368792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 709197583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ma x_throughput.709197583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1666681195 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 6350239944 ps |
| CPU time | 177.62 seconds |
| Started | Sep 18 10:01:36 AM UTC 24 |
| Finished | Sep 18 10:04:36 AM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666681195 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.1666681195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2959538334 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14607739399 ps |
| CPU time | 182.14 seconds |
| Started | Sep 18 10:01:34 AM UTC 24 |
| Finished | Sep 18 10:04:40 AM UTC 24 |
| Peak memory | 222664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959538334 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2959538334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3364104176 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 9459981438 ps |
| CPU time | 549.02 seconds |
| Started | Sep 18 10:01:22 AM UTC 24 |
| Finished | Sep 18 10:10:38 AM UTC 24 |
| Peak memory | 385228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364104176 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.3364104176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1538547810 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 14229378195 ps |
| CPU time | 295.19 seconds |
| Started | Sep 18 10:01:25 AM UTC 24 |
| Finished | Sep 18 10:06:25 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538547810 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_ac cess_b2b.1538547810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3626609400 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 345697598 ps |
| CPU time | 4.03 seconds |
| Started | Sep 18 10:01:32 AM UTC 24 |
| Finished | Sep 18 10:01:37 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626609400 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3626609400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.2736998335 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6668108835 ps |
| CPU time | 61.84 seconds |
| Started | Sep 18 10:01:31 AM UTC 24 |
| Finished | Sep 18 10:02:35 AM UTC 24 |
| Peak memory | 279000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736998335 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2736998335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.2077951911 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14842706965 ps |
| CPU time | 45.36 seconds |
| Started | Sep 18 10:01:19 AM UTC 24 |
| Finished | Sep 18 10:02:05 AM UTC 24 |
| Peak memory | 334100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077951911 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2077951911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3110213079 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 123396066752 ps |
| CPU time | 4006.86 seconds |
| Started | Sep 18 10:01:38 AM UTC 24 |
| Finished | Sep 18 11:09:09 AM UTC 24 |
| Peak memory | 390868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31102130 79 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.3110213079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.4107626566 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 12310892757 ps |
| CPU time | 261.46 seconds |
| Started | Sep 18 10:01:22 AM UTC 24 |
| Finished | Sep 18 10:05:47 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107626566 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.4107626566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.4270223 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 699145555 ps |
| CPU time | 16.41 seconds |
| Started | Sep 18 10:01:30 AM UTC 24 |
| Finished | Sep 18 10:01:47 AM UTC 24 |
| Peak memory | 252188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4270223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_thr oughput_w_partial_write.4270223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.613627019 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 34151898406 ps |
| CPU time | 462.22 seconds |
| Started | Sep 18 10:22:05 AM UTC 24 |
| Finished | Sep 18 10:29:53 AM UTC 24 |
| Peak memory | 383196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613627019 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_durin g_key_req.613627019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1521899025 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 23381318 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 10:22:40 AM UTC 24 |
| Finished | Sep 18 10:22:41 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521899025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1521899025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2425171234 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 28082389595 ps |
| CPU time | 1534.46 seconds |
| Started | Sep 18 10:19:48 AM UTC 24 |
| Finished | Sep 18 10:45:41 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425171234 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.2425171234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1015110687 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 21305187462 ps |
| CPU time | 453.88 seconds |
| Started | Sep 18 10:22:11 AM UTC 24 |
| Finished | Sep 18 10:29:50 AM UTC 24 |
| Peak memory | 377320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015110687 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1015110687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1305905724 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 60510553564 ps |
| CPU time | 115.72 seconds |
| Started | Sep 18 10:21:52 AM UTC 24 |
| Finished | Sep 18 10:23:50 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305905724 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.1305905724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1564577777 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4776963950 ps |
| CPU time | 82.37 seconds |
| Started | Sep 18 10:20:51 AM UTC 24 |
| Finished | Sep 18 10:22:15 AM UTC 24 |
| Peak memory | 381136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1564577777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ max_throughput.1564577777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.464509282 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4398242340 ps |
| CPU time | 186.72 seconds |
| Started | Sep 18 10:22:23 AM UTC 24 |
| Finished | Sep 18 10:25:33 AM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464509282 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.464509282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.715464209 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 18319544209 ps |
| CPU time | 216.28 seconds |
| Started | Sep 18 10:22:21 AM UTC 24 |
| Finished | Sep 18 10:26:01 AM UTC 24 |
| Peak memory | 222700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715464209 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.715464209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.601196559 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 277375971062 ps |
| CPU time | 869.64 seconds |
| Started | Sep 18 10:19:34 AM UTC 24 |
| Finished | Sep 18 10:34:13 AM UTC 24 |
| Peak memory | 383260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601196559 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.601196559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1627961330 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2197385469 ps |
| CPU time | 71.12 seconds |
| Started | Sep 18 10:20:38 AM UTC 24 |
| Finished | Sep 18 10:21:51 AM UTC 24 |
| Peak memory | 346592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627961330 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.1627961330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4098030956 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 16466599555 ps |
| CPU time | 387.22 seconds |
| Started | Sep 18 10:20:45 AM UTC 24 |
| Finished | Sep 18 10:27:18 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098030956 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_a ccess_b2b.4098030956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3012392100 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 697741633 ps |
| CPU time | 5.82 seconds |
| Started | Sep 18 10:22:16 AM UTC 24 |
| Finished | Sep 18 10:22:23 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012392100 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3012392100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.1551039517 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 100228827912 ps |
| CPU time | 1066.68 seconds |
| Started | Sep 18 10:22:15 AM UTC 24 |
| Finished | Sep 18 10:40:14 AM UTC 24 |
| Peak memory | 387352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551039517 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1551039517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1865467282 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1869872994 ps |
| CPU time | 33.37 seconds |
| Started | Sep 18 10:19:31 AM UTC 24 |
| Finished | Sep 18 10:20:05 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865467282 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1865467282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3026251524 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 209063203520 ps |
| CPU time | 5272.85 seconds |
| Started | Sep 18 10:22:27 AM UTC 24 |
| Finished | Sep 18 11:51:16 AM UTC 24 |
| Peak memory | 395292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30262515 24 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_a ll.3026251524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.817755998 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5711169401 ps |
| CPU time | 383.58 seconds |
| Started | Sep 18 10:20:06 AM UTC 24 |
| Finished | Sep 18 10:26:35 AM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817755998 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.817755998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.4012987873 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3118413843 ps |
| CPU time | 56.84 seconds |
| Started | Sep 18 10:21:11 AM UTC 24 |
| Finished | Sep 18 10:22:10 AM UTC 24 |
| Peak memory | 377040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4012987873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _throughput_w_partial_write.4012987873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.308302743 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 10459713518 ps |
| CPU time | 744.83 seconds |
| Started | Sep 18 10:23:45 AM UTC 24 |
| Finished | Sep 18 10:36:19 AM UTC 24 |
| Peak memory | 389404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308302743 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_durin g_key_req.308302743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1252287452 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 19291522 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 10:25:28 AM UTC 24 |
| Finished | Sep 18 10:25:30 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252287452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1252287452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.3413684784 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 266383290249 ps |
| CPU time | 1482.34 seconds |
| Started | Sep 18 10:22:53 AM UTC 24 |
| Finished | Sep 18 10:47:52 AM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413684784 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.3413684784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2526797044 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 19076336805 ps |
| CPU time | 130.77 seconds |
| Started | Sep 18 10:23:50 AM UTC 24 |
| Finished | Sep 18 10:26:03 AM UTC 24 |
| Peak memory | 370908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526797044 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2526797044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3219062832 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 13585301330 ps |
| CPU time | 12.95 seconds |
| Started | Sep 18 10:23:34 AM UTC 24 |
| Finished | Sep 18 10:23:48 AM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219062832 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.3219062832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2351705399 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3267470461 ps |
| CPU time | 75.42 seconds |
| Started | Sep 18 10:23:08 AM UTC 24 |
| Finished | Sep 18 10:24:25 AM UTC 24 |
| Peak memory | 362784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2351705399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ max_throughput.2351705399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3653941998 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 10892339306 ps |
| CPU time | 98.84 seconds |
| Started | Sep 18 10:24:26 AM UTC 24 |
| Finished | Sep 18 10:26:07 AM UTC 24 |
| Peak memory | 222568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653941998 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.3653941998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2688429121 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 32877263798 ps |
| CPU time | 163.44 seconds |
| Started | Sep 18 10:24:16 AM UTC 24 |
| Finished | Sep 18 10:27:02 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688429121 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.2688429121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3008005100 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 8175639213 ps |
| CPU time | 511.64 seconds |
| Started | Sep 18 10:22:50 AM UTC 24 |
| Finished | Sep 18 10:31:27 AM UTC 24 |
| Peak memory | 381204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008005100 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.3008005100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4283116191 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3654448132 ps |
| CPU time | 30.59 seconds |
| Started | Sep 18 10:23:02 AM UTC 24 |
| Finished | Sep 18 10:23:34 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283116191 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.4283116191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.4239804749 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 123588754950 ps |
| CPU time | 975.99 seconds |
| Started | Sep 18 10:23:04 AM UTC 24 |
| Finished | Sep 18 10:39:33 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239804749 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_a ccess_b2b.4239804749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3411479847 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 746554731 ps |
| CPU time | 5.57 seconds |
| Started | Sep 18 10:24:08 AM UTC 24 |
| Finished | Sep 18 10:24:15 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411479847 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3411479847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.1057050948 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 33310492917 ps |
| CPU time | 203.89 seconds |
| Started | Sep 18 10:23:51 AM UTC 24 |
| Finished | Sep 18 10:27:18 AM UTC 24 |
| Peak memory | 350428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057050948 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1057050948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2039250825 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 10665257602 ps |
| CPU time | 23.48 seconds |
| Started | Sep 18 10:22:43 AM UTC 24 |
| Finished | Sep 18 10:23:07 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039250825 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2039250825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1163535887 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 115803913579 ps |
| CPU time | 4793.43 seconds |
| Started | Sep 18 10:24:45 AM UTC 24 |
| Finished | Sep 18 11:45:30 AM UTC 24 |
| Peak memory | 393060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11635358 87 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_a ll.1163535887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1846011333 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2666559349 ps |
| CPU time | 183.45 seconds |
| Started | Sep 18 10:24:43 AM UTC 24 |
| Finished | Sep 18 10:27:49 AM UTC 24 |
| Peak memory | 356624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846011333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1846011333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2011053830 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2168208904 ps |
| CPU time | 219.08 seconds |
| Started | Sep 18 10:22:58 AM UTC 24 |
| Finished | Sep 18 10:26:40 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011053830 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.2011053830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.376717517 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2881951919 ps |
| CPU time | 35.42 seconds |
| Started | Sep 18 10:23:08 AM UTC 24 |
| Finished | Sep 18 10:23:45 AM UTC 24 |
| Peak memory | 289044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =376717517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ throughput_w_partial_write.376717517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.631584238 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 21819841348 ps |
| CPU time | 1811.52 seconds |
| Started | Sep 18 10:26:41 AM UTC 24 |
| Finished | Sep 18 10:57:12 AM UTC 24 |
| Peak memory | 388968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631584238 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_durin g_key_req.631584238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.4025714795 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 13889286 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 10:27:50 AM UTC 24 |
| Finished | Sep 18 10:27:52 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025714795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.4025714795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.2268760716 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 96007885078 ps |
| CPU time | 2318.64 seconds |
| Started | Sep 18 10:25:37 AM UTC 24 |
| Finished | Sep 18 11:04:41 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268760716 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.2268760716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.3932552667 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 7813959699 ps |
| CPU time | 587.16 seconds |
| Started | Sep 18 10:26:41 AM UTC 24 |
| Finished | Sep 18 10:36:35 AM UTC 24 |
| Peak memory | 374996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932552667 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.3932552667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3790374645 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 9213470099 ps |
| CPU time | 79.27 seconds |
| Started | Sep 18 10:26:35 AM UTC 24 |
| Finished | Sep 18 10:27:56 AM UTC 24 |
| Peak memory | 222628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790374645 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.3790374645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.719734161 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 741618729 ps |
| CPU time | 31.08 seconds |
| Started | Sep 18 10:26:08 AM UTC 24 |
| Finished | Sep 18 10:26:40 AM UTC 24 |
| Peak memory | 332252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 719734161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_m ax_throughput.719734161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.649386206 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3030143357 ps |
| CPU time | 91.11 seconds |
| Started | Sep 18 10:27:19 AM UTC 24 |
| Finished | Sep 18 10:28:52 AM UTC 24 |
| Peak memory | 222892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649386206 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.649386206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1164868015 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1979897316 ps |
| CPU time | 161.07 seconds |
| Started | Sep 18 10:27:19 AM UTC 24 |
| Finished | Sep 18 10:30:03 AM UTC 24 |
| Peak memory | 222628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164868015 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.1164868015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2808253439 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 15670650496 ps |
| CPU time | 389.94 seconds |
| Started | Sep 18 10:25:33 AM UTC 24 |
| Finished | Sep 18 10:32:08 AM UTC 24 |
| Peak memory | 387536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808253439 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.2808253439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.73572892 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1378590542 ps |
| CPU time | 29.31 seconds |
| Started | Sep 18 10:26:02 AM UTC 24 |
| Finished | Sep 18 10:26:32 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73572892 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.73572892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2473024637 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5564519817 ps |
| CPU time | 353.49 seconds |
| Started | Sep 18 10:26:04 AM UTC 24 |
| Finished | Sep 18 10:32:02 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473024637 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_a ccess_b2b.2473024637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.284185738 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1412898746 ps |
| CPU time | 4.03 seconds |
| Started | Sep 18 10:27:17 AM UTC 24 |
| Finished | Sep 18 10:27:22 AM UTC 24 |
| Peak memory | 212440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284185738 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.284185738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.716661122 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 16705754286 ps |
| CPU time | 376.43 seconds |
| Started | Sep 18 10:27:02 AM UTC 24 |
| Finished | Sep 18 10:33:24 AM UTC 24 |
| Peak memory | 377300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716661122 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.716661122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.1476348707 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 348229491 ps |
| CPU time | 7.05 seconds |
| Started | Sep 18 10:25:31 AM UTC 24 |
| Finished | Sep 18 10:25:40 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476348707 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1476348707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.228453453 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 71978388941 ps |
| CPU time | 5527.96 seconds |
| Started | Sep 18 10:27:48 AM UTC 24 |
| Finished | Sep 18 12:00:53 PM UTC 24 |
| Peak memory | 386844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22845345 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.228453453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3550755321 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 533706443 ps |
| CPU time | 23.2 seconds |
| Started | Sep 18 10:27:23 AM UTC 24 |
| Finished | Sep 18 10:27:47 AM UTC 24 |
| Peak memory | 224704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550755321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3550755321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.539643204 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 57389789581 ps |
| CPU time | 372.67 seconds |
| Started | Sep 18 10:25:41 AM UTC 24 |
| Finished | Sep 18 10:31:59 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539643204 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.539643204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3548139587 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3922259288 ps |
| CPU time | 40.9 seconds |
| Started | Sep 18 10:26:33 AM UTC 24 |
| Finished | Sep 18 10:27:15 AM UTC 24 |
| Peak memory | 327960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3548139587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _throughput_w_partial_write.3548139587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3902522075 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 21547380682 ps |
| CPU time | 1453.78 seconds |
| Started | Sep 18 10:29:49 AM UTC 24 |
| Finished | Sep 18 10:54:17 AM UTC 24 |
| Peak memory | 391380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902522075 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_duri ng_key_req.3902522075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1575069932 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 12084620 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 10:31:28 AM UTC 24 |
| Finished | Sep 18 10:31:30 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575069932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1575069932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.4118841698 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 27600145320 ps |
| CPU time | 486.98 seconds |
| Started | Sep 18 10:28:02 AM UTC 24 |
| Finished | Sep 18 10:36:16 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118841698 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.4118841698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.3709487413 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 41363930875 ps |
| CPU time | 706.39 seconds |
| Started | Sep 18 10:29:51 AM UTC 24 |
| Finished | Sep 18 10:41:46 AM UTC 24 |
| Peak memory | 385316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709487413 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.3709487413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.4016016694 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 50433343620 ps |
| CPU time | 94.69 seconds |
| Started | Sep 18 10:29:45 AM UTC 24 |
| Finished | Sep 18 10:31:22 AM UTC 24 |
| Peak memory | 222572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016016694 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.4016016694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.669086800 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 9846680037 ps |
| CPU time | 25.24 seconds |
| Started | Sep 18 10:29:18 AM UTC 24 |
| Finished | Sep 18 10:29:44 AM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 669086800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_m ax_throughput.669086800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2890120539 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5322259362 ps |
| CPU time | 100.03 seconds |
| Started | Sep 18 10:31:23 AM UTC 24 |
| Finished | Sep 18 10:33:05 AM UTC 24 |
| Peak memory | 222840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890120539 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2890120539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3047391052 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 7209519560 ps |
| CPU time | 218.52 seconds |
| Started | Sep 18 10:30:11 AM UTC 24 |
| Finished | Sep 18 10:33:53 AM UTC 24 |
| Peak memory | 222640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047391052 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3047391052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.654857029 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 21071574125 ps |
| CPU time | 467.83 seconds |
| Started | Sep 18 10:27:57 AM UTC 24 |
| Finished | Sep 18 10:35:50 AM UTC 24 |
| Peak memory | 381404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654857029 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.654857029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.659882614 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1087935355 ps |
| CPU time | 23.38 seconds |
| Started | Sep 18 10:28:52 AM UTC 24 |
| Finished | Sep 18 10:29:17 AM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659882614 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.659882614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3362318327 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 6680656143 ps |
| CPU time | 500.12 seconds |
| Started | Sep 18 10:29:06 AM UTC 24 |
| Finished | Sep 18 10:37:32 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362318327 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_a ccess_b2b.3362318327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3638720803 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 446189881 ps |
| CPU time | 6.12 seconds |
| Started | Sep 18 10:30:03 AM UTC 24 |
| Finished | Sep 18 10:30:10 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638720803 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3638720803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.2241956573 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 15087664159 ps |
| CPU time | 1063.7 seconds |
| Started | Sep 18 10:29:54 AM UTC 24 |
| Finished | Sep 18 10:47:49 AM UTC 24 |
| Peak memory | 381404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241956573 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2241956573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1980632789 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1582392047 ps |
| CPU time | 7.17 seconds |
| Started | Sep 18 10:27:53 AM UTC 24 |
| Finished | Sep 18 10:28:01 AM UTC 24 |
| Peak memory | 218484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980632789 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1980632789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2896769465 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 312791360057 ps |
| CPU time | 7093.57 seconds |
| Started | Sep 18 10:31:26 AM UTC 24 |
| Finished | Sep 18 12:30:52 PM UTC 24 |
| Peak memory | 394976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28967694 65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_a ll.2896769465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2705847342 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1271104004 ps |
| CPU time | 15.87 seconds |
| Started | Sep 18 10:31:23 AM UTC 24 |
| Finished | Sep 18 10:31:40 AM UTC 24 |
| Peak memory | 222848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705847342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2705847342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.4160032060 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 22353417838 ps |
| CPU time | 405.37 seconds |
| Started | Sep 18 10:28:28 AM UTC 24 |
| Finished | Sep 18 10:35:20 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160032060 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.4160032060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1857302553 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 820978715 ps |
| CPU time | 99.46 seconds |
| Started | Sep 18 10:29:40 AM UTC 24 |
| Finished | Sep 18 10:31:21 AM UTC 24 |
| Peak memory | 381140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1857302553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _throughput_w_partial_write.1857302553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3299461053 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 55930626376 ps |
| CPU time | 1365.12 seconds |
| Started | Sep 18 10:33:25 AM UTC 24 |
| Finished | Sep 18 10:56:25 AM UTC 24 |
| Peak memory | 389328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299461053 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_duri ng_key_req.3299461053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3065205553 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 12443685 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 10:35:20 AM UTC 24 |
| Finished | Sep 18 10:35:22 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065205553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3065205553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1190758503 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 15533848167 ps |
| CPU time | 1096.76 seconds |
| Started | Sep 18 10:32:00 AM UTC 24 |
| Finished | Sep 18 10:50:30 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190758503 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.1190758503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.1293035933 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 33137616960 ps |
| CPU time | 277.93 seconds |
| Started | Sep 18 10:33:54 AM UTC 24 |
| Finished | Sep 18 10:38:36 AM UTC 24 |
| Peak memory | 311584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293035933 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.1293035933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.742070171 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 12306538340 ps |
| CPU time | 119.94 seconds |
| Started | Sep 18 10:33:06 AM UTC 24 |
| Finished | Sep 18 10:35:08 AM UTC 24 |
| Peak memory | 226748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742070171 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.742070171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3265700162 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 717511197 ps |
| CPU time | 9.91 seconds |
| Started | Sep 18 10:32:29 AM UTC 24 |
| Finished | Sep 18 10:32:40 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3265700162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ max_throughput.3265700162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2487328780 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 5458356229 ps |
| CPU time | 214.73 seconds |
| Started | Sep 18 10:34:26 AM UTC 24 |
| Finished | Sep 18 10:38:05 AM UTC 24 |
| Peak memory | 222572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487328780 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2487328780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3768738854 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 8223597220 ps |
| CPU time | 167.67 seconds |
| Started | Sep 18 10:34:22 AM UTC 24 |
| Finished | Sep 18 10:37:13 AM UTC 24 |
| Peak memory | 222660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768738854 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.3768738854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2240372415 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 9305373491 ps |
| CPU time | 805.53 seconds |
| Started | Sep 18 10:31:41 AM UTC 24 |
| Finished | Sep 18 10:45:15 AM UTC 24 |
| Peak memory | 385544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240372415 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.2240372415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1010313240 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 539128096 ps |
| CPU time | 109.02 seconds |
| Started | Sep 18 10:32:09 AM UTC 24 |
| Finished | Sep 18 10:34:01 AM UTC 24 |
| Peak memory | 375000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010313240 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1010313240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.531532769 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 19364570455 ps |
| CPU time | 501.15 seconds |
| Started | Sep 18 10:32:22 AM UTC 24 |
| Finished | Sep 18 10:40:49 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531532769 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_ac cess_b2b.531532769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3227968055 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1777828472 ps |
| CPU time | 7.33 seconds |
| Started | Sep 18 10:34:13 AM UTC 24 |
| Finished | Sep 18 10:34:22 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227968055 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3227968055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.4069171950 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5231601392 ps |
| CPU time | 250.65 seconds |
| Started | Sep 18 10:34:01 AM UTC 24 |
| Finished | Sep 18 10:38:16 AM UTC 24 |
| Peak memory | 352532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069171950 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.4069171950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.3609641833 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1126212187 ps |
| CPU time | 48.15 seconds |
| Started | Sep 18 10:31:31 AM UTC 24 |
| Finished | Sep 18 10:32:21 AM UTC 24 |
| Peak memory | 311440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609641833 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3609641833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1071760454 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 50973931143 ps |
| CPU time | 1155.02 seconds |
| Started | Sep 18 10:35:09 AM UTC 24 |
| Finished | Sep 18 10:54:37 AM UTC 24 |
| Peak memory | 383436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10717604 54 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_a ll.1071760454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3857901645 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3627518443 ps |
| CPU time | 68.2 seconds |
| Started | Sep 18 10:34:32 AM UTC 24 |
| Finished | Sep 18 10:35:41 AM UTC 24 |
| Peak memory | 224756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857901645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3857901645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.934511225 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 5814898967 ps |
| CPU time | 409.78 seconds |
| Started | Sep 18 10:32:03 AM UTC 24 |
| Finished | Sep 18 10:38:59 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934511225 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.934511225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2645840928 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3125908800 ps |
| CPU time | 108.1 seconds |
| Started | Sep 18 10:32:41 AM UTC 24 |
| Finished | Sep 18 10:34:31 AM UTC 24 |
| Peak memory | 381396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2645840928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _throughput_w_partial_write.2645840928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.945679935 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 26726101133 ps |
| CPU time | 542.25 seconds |
| Started | Sep 18 10:36:30 AM UTC 24 |
| Finished | Sep 18 10:45:39 AM UTC 24 |
| Peak memory | 387360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945679935 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_durin g_key_req.945679935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2252721448 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 14127065 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 10:37:50 AM UTC 24 |
| Finished | Sep 18 10:37:52 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252721448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2252721448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3785117802 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 39653245017 ps |
| CPU time | 687.07 seconds |
| Started | Sep 18 10:35:42 AM UTC 24 |
| Finished | Sep 18 10:47:18 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785117802 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.3785117802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.2216453250 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 46447765064 ps |
| CPU time | 607.11 seconds |
| Started | Sep 18 10:36:36 AM UTC 24 |
| Finished | Sep 18 10:46:50 AM UTC 24 |
| Peak memory | 385316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216453250 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.2216453250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3542459856 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 41542486418 ps |
| CPU time | 74.33 seconds |
| Started | Sep 18 10:36:20 AM UTC 24 |
| Finished | Sep 18 10:37:36 AM UTC 24 |
| Peak memory | 222628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542459856 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.3542459856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.4017472463 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2688116541 ps |
| CPU time | 13.38 seconds |
| Started | Sep 18 10:36:15 AM UTC 24 |
| Finished | Sep 18 10:36:29 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4017472463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ max_throughput.4017472463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3117387786 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3643530469 ps |
| CPU time | 99.72 seconds |
| Started | Sep 18 10:37:13 AM UTC 24 |
| Finished | Sep 18 10:38:55 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117387786 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.3117387786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2024995719 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 39478649335 ps |
| CPU time | 145.89 seconds |
| Started | Sep 18 10:37:12 AM UTC 24 |
| Finished | Sep 18 10:39:41 AM UTC 24 |
| Peak memory | 222660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024995719 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.2024995719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2759849468 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 17030910501 ps |
| CPU time | 813.45 seconds |
| Started | Sep 18 10:35:29 AM UTC 24 |
| Finished | Sep 18 10:49:12 AM UTC 24 |
| Peak memory | 389320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759849468 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.2759849468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.621376958 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1937409365 ps |
| CPU time | 20.99 seconds |
| Started | Sep 18 10:35:51 AM UTC 24 |
| Finished | Sep 18 10:36:14 AM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621376958 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.621376958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2014680671 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 22701890039 ps |
| CPU time | 413.86 seconds |
| Started | Sep 18 10:35:54 AM UTC 24 |
| Finished | Sep 18 10:42:54 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014680671 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_a ccess_b2b.2014680671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1468809374 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 574464411 ps |
| CPU time | 5.06 seconds |
| Started | Sep 18 10:37:05 AM UTC 24 |
| Finished | Sep 18 10:37:11 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468809374 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1468809374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3307137660 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3107073145 ps |
| CPU time | 410.12 seconds |
| Started | Sep 18 10:36:49 AM UTC 24 |
| Finished | Sep 18 10:43:44 AM UTC 24 |
| Peak memory | 369112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307137660 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3307137660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.402580719 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 400048232 ps |
| CPU time | 29.78 seconds |
| Started | Sep 18 10:35:23 AM UTC 24 |
| Finished | Sep 18 10:35:54 AM UTC 24 |
| Peak memory | 301272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402580719 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.402580719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4035549555 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 316505876248 ps |
| CPU time | 4797.86 seconds |
| Started | Sep 18 10:37:37 AM UTC 24 |
| Finished | Sep 18 11:58:25 AM UTC 24 |
| Peak memory | 391196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40355495 55 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_a ll.4035549555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3572740075 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1976777236 ps |
| CPU time | 146.36 seconds |
| Started | Sep 18 10:37:33 AM UTC 24 |
| Finished | Sep 18 10:40:01 AM UTC 24 |
| Peak memory | 329936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572740075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3572740075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3025725812 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 10777326428 ps |
| CPU time | 371.45 seconds |
| Started | Sep 18 10:35:47 AM UTC 24 |
| Finished | Sep 18 10:42:04 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025725812 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.3025725812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3036007821 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2977890399 ps |
| CPU time | 29.78 seconds |
| Started | Sep 18 10:36:17 AM UTC 24 |
| Finished | Sep 18 10:36:48 AM UTC 24 |
| Peak memory | 284948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3036007821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _throughput_w_partial_write.3036007821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.986117104 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 22197095546 ps |
| CPU time | 841.21 seconds |
| Started | Sep 18 10:39:32 AM UTC 24 |
| Finished | Sep 18 10:53:42 AM UTC 24 |
| Peak memory | 383460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986117104 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_durin g_key_req.986117104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1026771458 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 100177601 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 10:40:45 AM UTC 24 |
| Finished | Sep 18 10:40:47 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026771458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1026771458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.3464109391 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 59035823596 ps |
| CPU time | 1152.98 seconds |
| Started | Sep 18 10:38:17 AM UTC 24 |
| Finished | Sep 18 10:57:43 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464109391 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.3464109391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.200213664 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 17445082927 ps |
| CPU time | 655.72 seconds |
| Started | Sep 18 10:39:34 AM UTC 24 |
| Finished | Sep 18 10:50:37 AM UTC 24 |
| Peak memory | 381196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200213664 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.200213664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1001079102 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2763513046 ps |
| CPU time | 28.38 seconds |
| Started | Sep 18 10:39:14 AM UTC 24 |
| Finished | Sep 18 10:39:43 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001079102 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1001079102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1185342991 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6562078467 ps |
| CPU time | 45.88 seconds |
| Started | Sep 18 10:38:59 AM UTC 24 |
| Finished | Sep 18 10:39:47 AM UTC 24 |
| Peak memory | 307672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1185342991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ max_throughput.1185342991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3071976865 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1015948046 ps |
| CPU time | 65.68 seconds |
| Started | Sep 18 10:39:52 AM UTC 24 |
| Finished | Sep 18 10:41:00 AM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071976865 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.3071976865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1329688487 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 31469747916 ps |
| CPU time | 404.53 seconds |
| Started | Sep 18 10:39:48 AM UTC 24 |
| Finished | Sep 18 10:46:38 AM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329688487 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.1329688487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3241131397 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 27171964602 ps |
| CPU time | 1007.11 seconds |
| Started | Sep 18 10:38:05 AM UTC 24 |
| Finished | Sep 18 10:55:03 AM UTC 24 |
| Peak memory | 373196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241131397 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3241131397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3835059187 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4784668595 ps |
| CPU time | 22.01 seconds |
| Started | Sep 18 10:38:37 AM UTC 24 |
| Finished | Sep 18 10:39:00 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835059187 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.3835059187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.276797503 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 72989769965 ps |
| CPU time | 574 seconds |
| Started | Sep 18 10:38:56 AM UTC 24 |
| Finished | Sep 18 10:48:38 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276797503 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_ac cess_b2b.276797503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.609455004 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1412808593 ps |
| CPU time | 6.14 seconds |
| Started | Sep 18 10:39:44 AM UTC 24 |
| Finished | Sep 18 10:39:51 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609455004 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.609455004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.2609954970 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 17119236522 ps |
| CPU time | 563.95 seconds |
| Started | Sep 18 10:39:42 AM UTC 24 |
| Finished | Sep 18 10:49:13 AM UTC 24 |
| Peak memory | 375260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609954970 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2609954970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.1270547323 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2664574947 ps |
| CPU time | 24.18 seconds |
| Started | Sep 18 10:37:53 AM UTC 24 |
| Finished | Sep 18 10:38:18 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270547323 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1270547323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1885330064 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 329134106783 ps |
| CPU time | 5344.45 seconds |
| Started | Sep 18 10:40:14 AM UTC 24 |
| Finished | Sep 18 12:10:15 PM UTC 24 |
| Peak memory | 401248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18853300 64 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_a ll.1885330064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1942745134 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 26178791353 ps |
| CPU time | 96.29 seconds |
| Started | Sep 18 10:40:02 AM UTC 24 |
| Finished | Sep 18 10:41:40 AM UTC 24 |
| Peak memory | 354716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942745134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1942745134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3301935766 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 18236377479 ps |
| CPU time | 274.8 seconds |
| Started | Sep 18 10:38:19 AM UTC 24 |
| Finished | Sep 18 10:42:58 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301935766 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.3301935766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2215143845 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1587531749 ps |
| CPU time | 28.18 seconds |
| Started | Sep 18 10:39:02 AM UTC 24 |
| Finished | Sep 18 10:39:31 AM UTC 24 |
| Peak memory | 278744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2215143845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _throughput_w_partial_write.2215143845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.4224343504 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 11102675046 ps |
| CPU time | 698.5 seconds |
| Started | Sep 18 10:42:15 AM UTC 24 |
| Finished | Sep 18 10:54:02 AM UTC 24 |
| Peak memory | 385376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224343504 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_duri ng_key_req.4224343504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2702366067 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 15957974 ps |
| CPU time | 1 seconds |
| Started | Sep 18 10:45:09 AM UTC 24 |
| Finished | Sep 18 10:45:11 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702366067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2702366067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.69828375 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 51859917836 ps |
| CPU time | 1615.2 seconds |
| Started | Sep 18 10:41:01 AM UTC 24 |
| Finished | Sep 18 11:08:14 AM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69828375 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.69828375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.3459986631 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 32922577646 ps |
| CPU time | 522.82 seconds |
| Started | Sep 18 10:42:43 AM UTC 24 |
| Finished | Sep 18 10:51:32 AM UTC 24 |
| Peak memory | 385236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459986631 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.3459986631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2278858138 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 19384443765 ps |
| CPU time | 110.1 seconds |
| Started | Sep 18 10:42:05 AM UTC 24 |
| Finished | Sep 18 10:43:57 AM UTC 24 |
| Peak memory | 226796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278858138 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2278858138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.465805938 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4459887780 ps |
| CPU time | 10.76 seconds |
| Started | Sep 18 10:41:52 AM UTC 24 |
| Finished | Sep 18 10:42:04 AM UTC 24 |
| Peak memory | 222652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 465805938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_m ax_throughput.465805938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.668823483 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 9691540052 ps |
| CPU time | 176.32 seconds |
| Started | Sep 18 10:43:45 AM UTC 24 |
| Finished | Sep 18 10:46:45 AM UTC 24 |
| Peak memory | 222604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668823483 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.668823483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4231754045 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 27677597168 ps |
| CPU time | 368.68 seconds |
| Started | Sep 18 10:43:05 AM UTC 24 |
| Finished | Sep 18 10:49:19 AM UTC 24 |
| Peak memory | 222652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231754045 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.4231754045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2144275832 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 10769302439 ps |
| CPU time | 725.4 seconds |
| Started | Sep 18 10:40:50 AM UTC 24 |
| Finished | Sep 18 10:53:03 AM UTC 24 |
| Peak memory | 381128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144275832 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.2144275832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1942133540 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 734510758 ps |
| CPU time | 9.43 seconds |
| Started | Sep 18 10:41:41 AM UTC 24 |
| Finished | Sep 18 10:41:52 AM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942133540 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1942133540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1175002436 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 133029576096 ps |
| CPU time | 598.11 seconds |
| Started | Sep 18 10:41:46 AM UTC 24 |
| Finished | Sep 18 10:51:52 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175002436 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_a ccess_b2b.1175002436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3805612325 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 715200905 ps |
| CPU time | 4.57 seconds |
| Started | Sep 18 10:42:59 AM UTC 24 |
| Finished | Sep 18 10:43:05 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805612325 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3805612325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1271284955 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1205938160 ps |
| CPU time | 108.3 seconds |
| Started | Sep 18 10:42:55 AM UTC 24 |
| Finished | Sep 18 10:44:46 AM UTC 24 |
| Peak memory | 288984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271284955 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1271284955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.2509442183 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1185984807 ps |
| CPU time | 26.39 seconds |
| Started | Sep 18 10:40:48 AM UTC 24 |
| Finished | Sep 18 10:41:15 AM UTC 24 |
| Peak memory | 212608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509442183 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2509442183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.4122526267 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 234923241967 ps |
| CPU time | 3514.57 seconds |
| Started | Sep 18 10:44:47 AM UTC 24 |
| Finished | Sep 18 11:44:01 AM UTC 24 |
| Peak memory | 401172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41225262 67 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_a ll.4122526267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.449490789 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1883313692 ps |
| CPU time | 120.14 seconds |
| Started | Sep 18 10:43:57 AM UTC 24 |
| Finished | Sep 18 10:46:00 AM UTC 24 |
| Peak memory | 336344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449490789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.449490789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1720102300 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3470555322 ps |
| CPU time | 228.3 seconds |
| Started | Sep 18 10:41:16 AM UTC 24 |
| Finished | Sep 18 10:45:08 AM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720102300 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.1720102300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.272321833 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 728524334 ps |
| CPU time | 36.53 seconds |
| Started | Sep 18 10:42:04 AM UTC 24 |
| Finished | Sep 18 10:42:42 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =272321833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ throughput_w_partial_write.272321833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.2553523746 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 30382908426 ps |
| CPU time | 403.84 seconds |
| Started | Sep 18 10:46:39 AM UTC 24 |
| Finished | Sep 18 10:53:28 AM UTC 24 |
| Peak memory | 356556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553523746 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_duri ng_key_req.2553523746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3723216674 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 30545691 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 10:47:50 AM UTC 24 |
| Finished | Sep 18 10:47:52 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723216674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3723216674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.1505955894 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 193111078994 ps |
| CPU time | 2474.34 seconds |
| Started | Sep 18 10:45:39 AM UTC 24 |
| Finished | Sep 18 11:27:20 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505955894 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.1505955894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.167734278 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 11659922519 ps |
| CPU time | 413 seconds |
| Started | Sep 18 10:46:46 AM UTC 24 |
| Finished | Sep 18 10:53:45 AM UTC 24 |
| Peak memory | 385304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167734278 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.167734278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3554572992 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2892986903 ps |
| CPU time | 10.88 seconds |
| Started | Sep 18 10:46:35 AM UTC 24 |
| Finished | Sep 18 10:46:47 AM UTC 24 |
| Peak memory | 224600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554572992 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.3554572992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.4214286672 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3003865022 ps |
| CPU time | 71.69 seconds |
| Started | Sep 18 10:46:13 AM UTC 24 |
| Finished | Sep 18 10:47:27 AM UTC 24 |
| Peak memory | 358612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4214286672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ max_throughput.4214286672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1013970302 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 21803925977 ps |
| CPU time | 177.9 seconds |
| Started | Sep 18 10:47:02 AM UTC 24 |
| Finished | Sep 18 10:50:03 AM UTC 24 |
| Peak memory | 222680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013970302 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.1013970302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.1305123386 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 14127551184 ps |
| CPU time | 338.03 seconds |
| Started | Sep 18 10:46:57 AM UTC 24 |
| Finished | Sep 18 10:52:40 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305123386 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.1305123386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.757568229 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 8240023138 ps |
| CPU time | 816.25 seconds |
| Started | Sep 18 10:45:16 AM UTC 24 |
| Finished | Sep 18 10:59:02 AM UTC 24 |
| Peak memory | 389332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757568229 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.757568229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1982841713 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1244842315 ps |
| CPU time | 29.56 seconds |
| Started | Sep 18 10:45:42 AM UTC 24 |
| Finished | Sep 18 10:46:13 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982841713 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.1982841713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1205075707 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 43669673867 ps |
| CPU time | 316.59 seconds |
| Started | Sep 18 10:46:01 AM UTC 24 |
| Finished | Sep 18 10:51:22 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205075707 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_a ccess_b2b.1205075707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.3789034755 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 692885196 ps |
| CPU time | 3.46 seconds |
| Started | Sep 18 10:46:51 AM UTC 24 |
| Finished | Sep 18 10:46:56 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789034755 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3789034755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1774680759 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 18267651631 ps |
| CPU time | 609.59 seconds |
| Started | Sep 18 10:46:48 AM UTC 24 |
| Finished | Sep 18 10:57:04 AM UTC 24 |
| Peak memory | 389392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774680759 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1774680759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3801554373 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 880895674 ps |
| CPU time | 25 seconds |
| Started | Sep 18 10:45:12 AM UTC 24 |
| Finished | Sep 18 10:45:38 AM UTC 24 |
| Peak memory | 262432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801554373 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3801554373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3132955438 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 121954742167 ps |
| CPU time | 3018.29 seconds |
| Started | Sep 18 10:47:28 AM UTC 24 |
| Finished | Sep 18 11:38:18 AM UTC 24 |
| Peak memory | 397152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31329554 38 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a ll.3132955438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1572399047 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3223612885 ps |
| CPU time | 43.76 seconds |
| Started | Sep 18 10:47:18 AM UTC 24 |
| Finished | Sep 18 10:48:04 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572399047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1572399047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1430991687 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4564175286 ps |
| CPU time | 303.33 seconds |
| Started | Sep 18 10:45:40 AM UTC 24 |
| Finished | Sep 18 10:50:48 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430991687 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.1430991687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2344592938 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 780616607 ps |
| CPU time | 44.75 seconds |
| Started | Sep 18 10:46:16 AM UTC 24 |
| Finished | Sep 18 10:47:02 AM UTC 24 |
| Peak memory | 319832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2344592938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _throughput_w_partial_write.2344592938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3172717531 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 161325356408 ps |
| CPU time | 1411.72 seconds |
| Started | Sep 18 10:49:39 AM UTC 24 |
| Finished | Sep 18 11:13:26 AM UTC 24 |
| Peak memory | 388964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172717531 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_duri ng_key_req.3172717531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3171725131 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 46866450 ps |
| CPU time | 1 seconds |
| Started | Sep 18 10:50:55 AM UTC 24 |
| Finished | Sep 18 10:50:57 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171725131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3171725131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.3360775674 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 33126016972 ps |
| CPU time | 2258.33 seconds |
| Started | Sep 18 10:48:05 AM UTC 24 |
| Finished | Sep 18 11:26:07 AM UTC 24 |
| Peak memory | 214008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360775674 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.3360775674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.694372502 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 23858941340 ps |
| CPU time | 1104.31 seconds |
| Started | Sep 18 10:50:04 AM UTC 24 |
| Finished | Sep 18 11:08:41 AM UTC 24 |
| Peak memory | 385232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694372502 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.694372502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1557163082 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4074959290 ps |
| CPU time | 16.84 seconds |
| Started | Sep 18 10:49:20 AM UTC 24 |
| Finished | Sep 18 10:49:38 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557163082 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.1557163082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3158954017 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 737495731 ps |
| CPU time | 52.05 seconds |
| Started | Sep 18 10:49:12 AM UTC 24 |
| Finished | Sep 18 10:50:06 AM UTC 24 |
| Peak memory | 317720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3158954017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ max_throughput.3158954017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1873176029 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 10265385131 ps |
| CPU time | 109.71 seconds |
| Started | Sep 18 10:50:30 AM UTC 24 |
| Finished | Sep 18 10:52:22 AM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873176029 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1873176029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.638568842 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 7885278973 ps |
| CPU time | 280.67 seconds |
| Started | Sep 18 10:50:29 AM UTC 24 |
| Finished | Sep 18 10:55:14 AM UTC 24 |
| Peak memory | 222632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638568842 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.638568842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1513751994 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 116277471301 ps |
| CPU time | 1344.58 seconds |
| Started | Sep 18 10:47:53 AM UTC 24 |
| Finished | Sep 18 11:10:31 AM UTC 24 |
| Peak memory | 391196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513751994 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1513751994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.518981358 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2201855797 ps |
| CPU time | 22.89 seconds |
| Started | Sep 18 10:48:38 AM UTC 24 |
| Finished | Sep 18 10:49:02 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518981358 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.518981358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.4112934733 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 21309106458 ps |
| CPU time | 285.9 seconds |
| Started | Sep 18 10:49:03 AM UTC 24 |
| Finished | Sep 18 10:53:53 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112934733 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_a ccess_b2b.4112934733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1082157967 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4806186647 ps |
| CPU time | 6.36 seconds |
| Started | Sep 18 10:50:21 AM UTC 24 |
| Finished | Sep 18 10:50:29 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082157967 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1082157967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.723525211 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 19102165617 ps |
| CPU time | 134.55 seconds |
| Started | Sep 18 10:50:07 AM UTC 24 |
| Finished | Sep 18 10:52:24 AM UTC 24 |
| Peak memory | 307396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723525211 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.723525211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2093354324 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1749223306 ps |
| CPU time | 39.58 seconds |
| Started | Sep 18 10:47:53 AM UTC 24 |
| Finished | Sep 18 10:48:34 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093354324 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2093354324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2077710816 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 238307059253 ps |
| CPU time | 4113.08 seconds |
| Started | Sep 18 10:50:49 AM UTC 24 |
| Finished | Sep 18 12:00:07 PM UTC 24 |
| Peak memory | 392920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20777108 16 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a ll.2077710816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.610163108 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1161800203 ps |
| CPU time | 15.14 seconds |
| Started | Sep 18 10:50:37 AM UTC 24 |
| Finished | Sep 18 10:50:54 AM UTC 24 |
| Peak memory | 222580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610163108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.610163108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.1086204563 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 82383235397 ps |
| CPU time | 410.64 seconds |
| Started | Sep 18 10:48:34 AM UTC 24 |
| Finished | Sep 18 10:55:31 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086204563 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.1086204563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.2878331927 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3191776493 ps |
| CPU time | 65.41 seconds |
| Started | Sep 18 10:49:14 AM UTC 24 |
| Finished | Sep 18 10:50:21 AM UTC 24 |
| Peak memory | 360724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2878331927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _throughput_w_partial_write.2878331927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.87580095 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 43004553452 ps |
| CPU time | 491.26 seconds |
| Started | Sep 18 10:02:03 AM UTC 24 |
| Finished | Sep 18 10:10:21 AM UTC 24 |
| Peak memory | 389604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87580095 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_ key_req.87580095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3737375633 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15826904 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 10:02:35 AM UTC 24 |
| Finished | Sep 18 10:02:37 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737375633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3737375633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.1704149629 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 55506231928 ps |
| CPU time | 1204.67 seconds |
| Started | Sep 18 10:01:46 AM UTC 24 |
| Finished | Sep 18 10:22:04 AM UTC 24 |
| Peak memory | 212280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704149629 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.1704149629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.836581789 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9642433817 ps |
| CPU time | 387.63 seconds |
| Started | Sep 18 10:02:06 AM UTC 24 |
| Finished | Sep 18 10:08:39 AM UTC 24 |
| Peak memory | 358684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836581789 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.836581789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.26538221 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 50225053920 ps |
| CPU time | 99.05 seconds |
| Started | Sep 18 10:02:01 AM UTC 24 |
| Finished | Sep 18 10:03:42 AM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26538221 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.26538221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1584110272 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 695619470 ps |
| CPU time | 11.88 seconds |
| Started | Sep 18 10:01:49 AM UTC 24 |
| Finished | Sep 18 10:02:02 AM UTC 24 |
| Peak memory | 233616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1584110272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_m ax_throughput.1584110272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1123791723 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2515357405 ps |
| CPU time | 99.66 seconds |
| Started | Sep 18 10:02:15 AM UTC 24 |
| Finished | Sep 18 10:03:57 AM UTC 24 |
| Peak memory | 222816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123791723 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.1123791723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2961158356 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 41324505051 ps |
| CPU time | 209.92 seconds |
| Started | Sep 18 10:02:09 AM UTC 24 |
| Finished | Sep 18 10:05:42 AM UTC 24 |
| Peak memory | 222560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961158356 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.2961158356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4124054963 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 14756148700 ps |
| CPU time | 496.37 seconds |
| Started | Sep 18 10:01:44 AM UTC 24 |
| Finished | Sep 18 10:10:07 AM UTC 24 |
| Peak memory | 383256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124054963 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.4124054963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.895318946 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2087018015 ps |
| CPU time | 19.92 seconds |
| Started | Sep 18 10:01:46 AM UTC 24 |
| Finished | Sep 18 10:02:07 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895318946 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.895318946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2353985028 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 24060484475 ps |
| CPU time | 642.14 seconds |
| Started | Sep 18 10:01:48 AM UTC 24 |
| Finished | Sep 18 10:12:38 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353985028 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_ac cess_b2b.2353985028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.277317312 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 357100385 ps |
| CPU time | 6.25 seconds |
| Started | Sep 18 10:02:08 AM UTC 24 |
| Finished | Sep 18 10:02:16 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277317312 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.277317312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2695569602 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6472803759 ps |
| CPU time | 313.39 seconds |
| Started | Sep 18 10:02:06 AM UTC 24 |
| Finished | Sep 18 10:07:24 AM UTC 24 |
| Peak memory | 352468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695569602 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2695569602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3207993441 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1618220485 ps |
| CPU time | 5.24 seconds |
| Started | Sep 18 10:02:35 AM UTC 24 |
| Finished | Sep 18 10:02:42 AM UTC 24 |
| Peak memory | 248124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207993441 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3207993441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1277569704 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1482333379 ps |
| CPU time | 50.15 seconds |
| Started | Sep 18 10:01:42 AM UTC 24 |
| Finished | Sep 18 10:02:35 AM UTC 24 |
| Peak memory | 346528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277569704 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1277569704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2880036862 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 221637067653 ps |
| CPU time | 5083.36 seconds |
| Started | Sep 18 10:02:34 AM UTC 24 |
| Finished | Sep 18 11:28:05 AM UTC 24 |
| Peak memory | 405264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28800368 62 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.2880036862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2258612533 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4726421363 ps |
| CPU time | 18.27 seconds |
| Started | Sep 18 10:02:17 AM UTC 24 |
| Finished | Sep 18 10:02:36 AM UTC 24 |
| Peak memory | 228876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258612533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2258612533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2469471390 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 46506842166 ps |
| CPU time | 359.5 seconds |
| Started | Sep 18 10:01:46 AM UTC 24 |
| Finished | Sep 18 10:07:50 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469471390 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.2469471390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3184221807 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1552361316 ps |
| CPU time | 32.83 seconds |
| Started | Sep 18 10:02:00 AM UTC 24 |
| Finished | Sep 18 10:02:34 AM UTC 24 |
| Peak memory | 311504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3184221807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ throughput_w_partial_write.3184221807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2440982742 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 15040653077 ps |
| CPU time | 571.49 seconds |
| Started | Sep 18 10:52:41 AM UTC 24 |
| Finished | Sep 18 11:02:19 AM UTC 24 |
| Peak memory | 389592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440982742 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_duri ng_key_req.2440982742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3871289120 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 46712198 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 10:53:44 AM UTC 24 |
| Finished | Sep 18 10:53:45 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871289120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3871289120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3442638782 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 52423894977 ps |
| CPU time | 1143.17 seconds |
| Started | Sep 18 10:51:33 AM UTC 24 |
| Finished | Sep 18 11:10:49 AM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442638782 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3442638782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2873592587 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2558444859 ps |
| CPU time | 184.3 seconds |
| Started | Sep 18 10:52:58 AM UTC 24 |
| Finished | Sep 18 10:56:05 AM UTC 24 |
| Peak memory | 379172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873592587 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.2873592587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.4255194629 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 38148568352 ps |
| CPU time | 75.94 seconds |
| Started | Sep 18 10:52:25 AM UTC 24 |
| Finished | Sep 18 10:53:43 AM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255194629 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.4255194629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.420499104 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2958056301 ps |
| CPU time | 61.36 seconds |
| Started | Sep 18 10:52:13 AM UTC 24 |
| Finished | Sep 18 10:53:16 AM UTC 24 |
| Peak memory | 338264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 420499104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_m ax_throughput.420499104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1661084262 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 4495168298 ps |
| CPU time | 168.33 seconds |
| Started | Sep 18 10:53:28 AM UTC 24 |
| Finished | Sep 18 10:56:19 AM UTC 24 |
| Peak memory | 222612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661084262 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.1661084262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2505752879 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 20708370048 ps |
| CPU time | 379.47 seconds |
| Started | Sep 18 10:53:21 AM UTC 24 |
| Finished | Sep 18 10:59:46 AM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505752879 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.2505752879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3296984590 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 8911397841 ps |
| CPU time | 926.84 seconds |
| Started | Sep 18 10:51:23 AM UTC 24 |
| Finished | Sep 18 11:07:01 AM UTC 24 |
| Peak memory | 389392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296984590 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.3296984590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1820658939 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 998410712 ps |
| CPU time | 17.07 seconds |
| Started | Sep 18 10:51:53 AM UTC 24 |
| Finished | Sep 18 10:52:12 AM UTC 24 |
| Peak memory | 212404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820658939 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.1820658939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2717021466 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 5464069503 ps |
| CPU time | 362.09 seconds |
| Started | Sep 18 10:51:57 AM UTC 24 |
| Finished | Sep 18 10:58:05 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717021466 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_a ccess_b2b.2717021466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.661695268 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 685005344 ps |
| CPU time | 3.49 seconds |
| Started | Sep 18 10:53:16 AM UTC 24 |
| Finished | Sep 18 10:53:21 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661695268 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.661695268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.445785637 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 48036432845 ps |
| CPU time | 1128.27 seconds |
| Started | Sep 18 10:53:03 AM UTC 24 |
| Finished | Sep 18 11:12:04 AM UTC 24 |
| Peak memory | 389316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445785637 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.445785637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.1710736116 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4298093326 ps |
| CPU time | 56.88 seconds |
| Started | Sep 18 10:50:58 AM UTC 24 |
| Finished | Sep 18 10:51:56 AM UTC 24 |
| Peak memory | 323864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710736116 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1710736116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1698704494 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 76996013376 ps |
| CPU time | 2737.7 seconds |
| Started | Sep 18 10:53:44 AM UTC 24 |
| Finished | Sep 18 11:39:51 AM UTC 24 |
| Peak memory | 397080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16987044 94 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_a ll.1698704494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4197628940 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5684681270 ps |
| CPU time | 34.89 seconds |
| Started | Sep 18 10:53:29 AM UTC 24 |
| Finished | Sep 18 10:54:06 AM UTC 24 |
| Peak memory | 222648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197628940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.4197628940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.4056645018 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3645784652 ps |
| CPU time | 235.77 seconds |
| Started | Sep 18 10:51:42 AM UTC 24 |
| Finished | Sep 18 10:55:41 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056645018 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.4056645018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3987790357 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 902240349 ps |
| CPU time | 32.63 seconds |
| Started | Sep 18 10:52:23 AM UTC 24 |
| Finished | Sep 18 10:52:57 AM UTC 24 |
| Peak memory | 291224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3987790357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _throughput_w_partial_write.3987790357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.575350002 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 42820690047 ps |
| CPU time | 661.51 seconds |
| Started | Sep 18 10:55:05 AM UTC 24 |
| Finished | Sep 18 11:06:14 AM UTC 24 |
| Peak memory | 383184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575350002 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_durin g_key_req.575350002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1441686340 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 37727069 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 10:56:06 AM UTC 24 |
| Finished | Sep 18 10:56:07 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441686340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1441686340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.534739585 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 58089293462 ps |
| CPU time | 2004.93 seconds |
| Started | Sep 18 10:53:54 AM UTC 24 |
| Finished | Sep 18 11:27:42 AM UTC 24 |
| Peak memory | 214272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534739585 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.534739585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.1010186119 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 36929115353 ps |
| CPU time | 851.5 seconds |
| Started | Sep 18 10:55:08 AM UTC 24 |
| Finished | Sep 18 11:09:29 AM UTC 24 |
| Peak memory | 385312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010186119 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.1010186119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.288392364 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 11590708999 ps |
| CPU time | 144.1 seconds |
| Started | Sep 18 10:54:43 AM UTC 24 |
| Finished | Sep 18 10:57:09 AM UTC 24 |
| Peak memory | 222640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288392364 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.288392364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3654250720 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5949313550 ps |
| CPU time | 33.84 seconds |
| Started | Sep 18 10:54:31 AM UTC 24 |
| Finished | Sep 18 10:55:07 AM UTC 24 |
| Peak memory | 295384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3654250720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ max_throughput.3654250720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3460798531 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 9759389571 ps |
| CPU time | 180.53 seconds |
| Started | Sep 18 10:55:32 AM UTC 24 |
| Finished | Sep 18 10:58:36 AM UTC 24 |
| Peak memory | 222676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460798531 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.3460798531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.119680404 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 57668283107 ps |
| CPU time | 350.42 seconds |
| Started | Sep 18 10:55:29 AM UTC 24 |
| Finished | Sep 18 11:01:24 AM UTC 24 |
| Peak memory | 222648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119680404 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.119680404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1772090048 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 39558829807 ps |
| CPU time | 53.78 seconds |
| Started | Sep 18 10:53:47 AM UTC 24 |
| Finished | Sep 18 10:54:42 AM UTC 24 |
| Peak memory | 278988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772090048 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.1772090048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2871919207 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1090694400 ps |
| CPU time | 106.2 seconds |
| Started | Sep 18 10:54:06 AM UTC 24 |
| Finished | Sep 18 10:55:55 AM UTC 24 |
| Peak memory | 379032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871919207 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2871919207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2750144947 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 57265888070 ps |
| CPU time | 356.54 seconds |
| Started | Sep 18 10:54:18 AM UTC 24 |
| Finished | Sep 18 11:00:20 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750144947 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_a ccess_b2b.2750144947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1875285426 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1879474602 ps |
| CPU time | 5.73 seconds |
| Started | Sep 18 10:55:21 AM UTC 24 |
| Finished | Sep 18 10:55:29 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875285426 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1875285426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3709331776 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 90615753305 ps |
| CPU time | 764.4 seconds |
| Started | Sep 18 10:55:15 AM UTC 24 |
| Finished | Sep 18 11:08:08 AM UTC 24 |
| Peak memory | 383184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709331776 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3709331776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.3469890125 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 782536522 ps |
| CPU time | 43.46 seconds |
| Started | Sep 18 10:53:46 AM UTC 24 |
| Finished | Sep 18 10:54:31 AM UTC 24 |
| Peak memory | 336016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469890125 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3469890125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2757605668 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 541402379021 ps |
| CPU time | 2251.95 seconds |
| Started | Sep 18 10:55:55 AM UTC 24 |
| Finished | Sep 18 11:33:52 AM UTC 24 |
| Peak memory | 388876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27576056 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_a ll.2757605668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2778596189 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1598139783 ps |
| CPU time | 62.69 seconds |
| Started | Sep 18 10:55:42 AM UTC 24 |
| Finished | Sep 18 10:56:47 AM UTC 24 |
| Peak memory | 224704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778596189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2778596189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2910091241 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 23246818880 ps |
| CPU time | 324.04 seconds |
| Started | Sep 18 10:54:03 AM UTC 24 |
| Finished | Sep 18 10:59:31 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910091241 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.2910091241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1711389405 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1523838810 ps |
| CPU time | 40.14 seconds |
| Started | Sep 18 10:54:39 AM UTC 24 |
| Finished | Sep 18 10:55:20 AM UTC 24 |
| Peak memory | 301268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1711389405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _throughput_w_partial_write.1711389405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.366463709 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 28022889126 ps |
| CPU time | 775.17 seconds |
| Started | Sep 18 10:57:45 AM UTC 24 |
| Finished | Sep 18 11:10:48 AM UTC 24 |
| Peak memory | 383268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366463709 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_durin g_key_req.366463709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4165081704 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 19289833 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 10:59:02 AM UTC 24 |
| Finished | Sep 18 10:59:04 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165081704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.4165081704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2013603831 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 138753222851 ps |
| CPU time | 2544.1 seconds |
| Started | Sep 18 10:56:26 AM UTC 24 |
| Finished | Sep 18 11:39:18 AM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013603831 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.2013603831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.433289685 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 11222199992 ps |
| CPU time | 50.23 seconds |
| Started | Sep 18 10:57:45 AM UTC 24 |
| Finished | Sep 18 10:58:36 AM UTC 24 |
| Peak memory | 307608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433289685 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.433289685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2717660869 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 18230409306 ps |
| CPU time | 49.96 seconds |
| Started | Sep 18 10:57:13 AM UTC 24 |
| Finished | Sep 18 10:58:05 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717660869 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.2717660869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.979951562 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 724182669 ps |
| CPU time | 31.67 seconds |
| Started | Sep 18 10:57:10 AM UTC 24 |
| Finished | Sep 18 10:57:43 AM UTC 24 |
| Peak memory | 301200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 979951562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_m ax_throughput.979951562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3698736721 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 9565310735 ps |
| CPU time | 75.09 seconds |
| Started | Sep 18 10:58:14 AM UTC 24 |
| Finished | Sep 18 10:59:31 AM UTC 24 |
| Peak memory | 224624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698736721 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.3698736721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2815299004 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 21320206229 ps |
| CPU time | 456.91 seconds |
| Started | Sep 18 10:58:06 AM UTC 24 |
| Finished | Sep 18 11:05:50 AM UTC 24 |
| Peak memory | 212616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815299004 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.2815299004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1100376715 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3849037984 ps |
| CPU time | 291.98 seconds |
| Started | Sep 18 10:56:21 AM UTC 24 |
| Finished | Sep 18 11:01:16 AM UTC 24 |
| Peak memory | 387268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100376715 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.1100376715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3622537058 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 537477958 ps |
| CPU time | 21.07 seconds |
| Started | Sep 18 10:56:48 AM UTC 24 |
| Finished | Sep 18 10:57:10 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622537058 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.3622537058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.780869745 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 7910026725 ps |
| CPU time | 483.43 seconds |
| Started | Sep 18 10:57:05 AM UTC 24 |
| Finished | Sep 18 11:05:15 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780869745 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_ac cess_b2b.780869745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1957752092 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1351252985 ps |
| CPU time | 6.16 seconds |
| Started | Sep 18 10:58:06 AM UTC 24 |
| Finished | Sep 18 10:58:13 AM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957752092 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1957752092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.438426239 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 17606952648 ps |
| CPU time | 926.46 seconds |
| Started | Sep 18 10:58:04 AM UTC 24 |
| Finished | Sep 18 11:13:41 AM UTC 24 |
| Peak memory | 391632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438426239 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.438426239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.4150584692 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 14521345238 ps |
| CPU time | 33.18 seconds |
| Started | Sep 18 10:56:09 AM UTC 24 |
| Finished | Sep 18 10:56:43 AM UTC 24 |
| Peak memory | 212340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150584692 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.4150584692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1087458067 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 110165673170 ps |
| CPU time | 2796.49 seconds |
| Started | Sep 18 10:58:37 AM UTC 24 |
| Finished | Sep 18 11:45:44 AM UTC 24 |
| Peak memory | 384788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10874580 67 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_a ll.1087458067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3084973901 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1810733831 ps |
| CPU time | 38.81 seconds |
| Started | Sep 18 10:58:37 AM UTC 24 |
| Finished | Sep 18 10:59:17 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084973901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3084973901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2950798397 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2707486486 ps |
| CPU time | 158.95 seconds |
| Started | Sep 18 10:56:44 AM UTC 24 |
| Finished | Sep 18 10:59:26 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950798397 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2950798397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1613311463 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3097583611 ps |
| CPU time | 49.64 seconds |
| Started | Sep 18 10:57:11 AM UTC 24 |
| Finished | Sep 18 10:58:03 AM UTC 24 |
| Peak memory | 317648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1613311463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _throughput_w_partial_write.1613311463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.4229029444 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 57509120228 ps |
| CPU time | 1018.82 seconds |
| Started | Sep 18 11:00:20 AM UTC 24 |
| Finished | Sep 18 11:17:31 AM UTC 24 |
| Peak memory | 383148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229029444 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_duri ng_key_req.4229029444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2511132356 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 19059202 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 11:02:49 AM UTC 24 |
| Finished | Sep 18 11:02:51 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511132356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2511132356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.343934460 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 626828151821 ps |
| CPU time | 2578.57 seconds |
| Started | Sep 18 10:59:27 AM UTC 24 |
| Finished | Sep 18 11:42:54 AM UTC 24 |
| Peak memory | 214284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343934460 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.343934460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2678432874 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5641140490 ps |
| CPU time | 352.34 seconds |
| Started | Sep 18 11:00:35 AM UTC 24 |
| Finished | Sep 18 11:06:32 AM UTC 24 |
| Peak memory | 373160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678432874 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.2678432874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2248174475 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1204485136 ps |
| CPU time | 13.14 seconds |
| Started | Sep 18 11:00:19 AM UTC 24 |
| Finished | Sep 18 11:00:34 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248174475 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2248174475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.3944156736 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 736651968 ps |
| CPU time | 30.12 seconds |
| Started | Sep 18 10:59:47 AM UTC 24 |
| Finished | Sep 18 11:00:18 AM UTC 24 |
| Peak memory | 311768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3944156736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ max_throughput.3944156736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3288918118 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 964370820 ps |
| CPU time | 83.41 seconds |
| Started | Sep 18 11:01:25 AM UTC 24 |
| Finished | Sep 18 11:02:50 AM UTC 24 |
| Peak memory | 222832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288918118 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3288918118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.482019125 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 29167683749 ps |
| CPU time | 366.78 seconds |
| Started | Sep 18 11:01:25 AM UTC 24 |
| Finished | Sep 18 11:07:37 AM UTC 24 |
| Peak memory | 222604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482019125 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.482019125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.1052549407 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 20803969996 ps |
| CPU time | 210.49 seconds |
| Started | Sep 18 10:59:19 AM UTC 24 |
| Finished | Sep 18 11:02:53 AM UTC 24 |
| Peak memory | 336140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052549407 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.1052549407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.3264694559 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 693673742 ps |
| CPU time | 13.21 seconds |
| Started | Sep 18 10:59:32 AM UTC 24 |
| Finished | Sep 18 10:59:46 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264694559 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.3264694559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.434060317 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 102068747001 ps |
| CPU time | 690.39 seconds |
| Started | Sep 18 10:59:47 AM UTC 24 |
| Finished | Sep 18 11:11:26 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434060317 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_ac cess_b2b.434060317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.614714542 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 345366314 ps |
| CPU time | 5.93 seconds |
| Started | Sep 18 11:01:17 AM UTC 24 |
| Finished | Sep 18 11:01:24 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614714542 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.614714542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.2035716795 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 19601676465 ps |
| CPU time | 473.45 seconds |
| Started | Sep 18 11:00:44 AM UTC 24 |
| Finished | Sep 18 11:08:43 AM UTC 24 |
| Peak memory | 387348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035716795 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2035716795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1685309515 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 833028234 ps |
| CPU time | 44.28 seconds |
| Started | Sep 18 10:59:05 AM UTC 24 |
| Finished | Sep 18 10:59:51 AM UTC 24 |
| Peak memory | 315612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685309515 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1685309515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.307299910 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 222364417130 ps |
| CPU time | 3257 seconds |
| Started | Sep 18 11:02:20 AM UTC 24 |
| Finished | Sep 18 11:57:11 AM UTC 24 |
| Peak memory | 388952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30729991 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.307299910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3244746921 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 20564145610 ps |
| CPU time | 112.26 seconds |
| Started | Sep 18 11:02:08 AM UTC 24 |
| Finished | Sep 18 11:04:03 AM UTC 24 |
| Peak memory | 226804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244746921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3244746921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1396054225 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 5508131920 ps |
| CPU time | 193 seconds |
| Started | Sep 18 10:59:32 AM UTC 24 |
| Finished | Sep 18 11:02:48 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396054225 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1396054225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2103575235 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 751434954 ps |
| CPU time | 49.08 seconds |
| Started | Sep 18 10:59:52 AM UTC 24 |
| Finished | Sep 18 11:00:43 AM UTC 24 |
| Peak memory | 311440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2103575235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _throughput_w_partial_write.2103575235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1946142934 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 14186539614 ps |
| CPU time | 900.71 seconds |
| Started | Sep 18 11:05:16 AM UTC 24 |
| Finished | Sep 18 11:20:28 AM UTC 24 |
| Peak memory | 385308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946142934 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_duri ng_key_req.1946142934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2187242039 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 13592013 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 11:07:38 AM UTC 24 |
| Finished | Sep 18 11:07:40 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187242039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2187242039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3643876485 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 546814022317 ps |
| CPU time | 2155.65 seconds |
| Started | Sep 18 11:02:54 AM UTC 24 |
| Finished | Sep 18 11:39:13 AM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643876485 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3643876485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2203933246 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 60176466329 ps |
| CPU time | 700.28 seconds |
| Started | Sep 18 11:05:40 AM UTC 24 |
| Finished | Sep 18 11:17:28 AM UTC 24 |
| Peak memory | 389600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203933246 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.2203933246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.4081332077 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 27151675584 ps |
| CPU time | 85.41 seconds |
| Started | Sep 18 11:05:15 AM UTC 24 |
| Finished | Sep 18 11:06:42 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081332077 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.4081332077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3012546168 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1535893656 ps |
| CPU time | 31.02 seconds |
| Started | Sep 18 11:04:42 AM UTC 24 |
| Finished | Sep 18 11:05:14 AM UTC 24 |
| Peak memory | 327896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3012546168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ max_throughput.3012546168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1144134049 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 20897523149 ps |
| CPU time | 182.6 seconds |
| Started | Sep 18 11:06:33 AM UTC 24 |
| Finished | Sep 18 11:09:38 AM UTC 24 |
| Peak memory | 222752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144134049 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.1144134049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2477013892 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 103514814051 ps |
| CPU time | 305.14 seconds |
| Started | Sep 18 11:06:23 AM UTC 24 |
| Finished | Sep 18 11:11:32 AM UTC 24 |
| Peak memory | 222580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477013892 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.2477013892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3149020950 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 13760857627 ps |
| CPU time | 616.52 seconds |
| Started | Sep 18 11:02:52 AM UTC 24 |
| Finished | Sep 18 11:13:16 AM UTC 24 |
| Peak memory | 387452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149020950 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.3149020950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2843126687 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 5169707762 ps |
| CPU time | 115.87 seconds |
| Started | Sep 18 11:03:15 AM UTC 24 |
| Finished | Sep 18 11:05:13 AM UTC 24 |
| Peak memory | 379164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843126687 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.2843126687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3230392449 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 51115754721 ps |
| CPU time | 422.45 seconds |
| Started | Sep 18 11:04:05 AM UTC 24 |
| Finished | Sep 18 11:11:13 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230392449 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a ccess_b2b.3230392449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1015401128 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1866707222 ps |
| CPU time | 6.06 seconds |
| Started | Sep 18 11:06:15 AM UTC 24 |
| Finished | Sep 18 11:06:22 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015401128 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1015401128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.31871784 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 6379195026 ps |
| CPU time | 301.75 seconds |
| Started | Sep 18 11:05:50 AM UTC 24 |
| Finished | Sep 18 11:10:57 AM UTC 24 |
| Peak memory | 377104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31871784 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.31871784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.3813908121 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 7473358981 ps |
| CPU time | 21.47 seconds |
| Started | Sep 18 11:02:51 AM UTC 24 |
| Finished | Sep 18 11:03:14 AM UTC 24 |
| Peak memory | 282904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813908121 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3813908121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3738184517 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 104139535357 ps |
| CPU time | 2231.08 seconds |
| Started | Sep 18 11:07:02 AM UTC 24 |
| Finished | Sep 18 11:44:38 AM UTC 24 |
| Peak memory | 241436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37381845 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_a ll.3738184517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2958448507 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2740306755 ps |
| CPU time | 114.52 seconds |
| Started | Sep 18 11:06:43 AM UTC 24 |
| Finished | Sep 18 11:08:40 AM UTC 24 |
| Peak memory | 391440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958448507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2958448507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3496685293 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 21125328447 ps |
| CPU time | 441.99 seconds |
| Started | Sep 18 11:03:03 AM UTC 24 |
| Finished | Sep 18 11:10:31 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496685293 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.3496685293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.51477773 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 774489438 ps |
| CPU time | 24.63 seconds |
| Started | Sep 18 11:05:14 AM UTC 24 |
| Finished | Sep 18 11:05:40 AM UTC 24 |
| Peak memory | 278664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =51477773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t hroughput_w_partial_write.51477773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1700934942 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 29563434727 ps |
| CPU time | 373.86 seconds |
| Started | Sep 18 11:09:30 AM UTC 24 |
| Finished | Sep 18 11:15:49 AM UTC 24 |
| Peak memory | 381404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700934942 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_duri ng_key_req.1700934942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.197312839 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 15761491 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 11:10:49 AM UTC 24 |
| Finished | Sep 18 11:10:51 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197312839 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.197312839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3671173044 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 38591095677 ps |
| CPU time | 866.87 seconds |
| Started | Sep 18 11:08:14 AM UTC 24 |
| Finished | Sep 18 11:22:51 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671173044 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.3671173044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.1607942304 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 9831509221 ps |
| CPU time | 172.36 seconds |
| Started | Sep 18 11:09:39 AM UTC 24 |
| Finished | Sep 18 11:12:34 AM UTC 24 |
| Peak memory | 365020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607942304 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.1607942304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3522558454 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 10131161265 ps |
| CPU time | 32.87 seconds |
| Started | Sep 18 11:09:09 AM UTC 24 |
| Finished | Sep 18 11:09:44 AM UTC 24 |
| Peak memory | 226796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522558454 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.3522558454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.184050046 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3188629305 ps |
| CPU time | 83.49 seconds |
| Started | Sep 18 11:08:44 AM UTC 24 |
| Finished | Sep 18 11:10:09 AM UTC 24 |
| Peak memory | 381212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 184050046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_m ax_throughput.184050046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3068933136 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 5370673649 ps |
| CPU time | 93.29 seconds |
| Started | Sep 18 11:10:32 AM UTC 24 |
| Finished | Sep 18 11:12:07 AM UTC 24 |
| Peak memory | 222568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068933136 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.3068933136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3407272851 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 14247173503 ps |
| CPU time | 340.46 seconds |
| Started | Sep 18 11:10:19 AM UTC 24 |
| Finished | Sep 18 11:16:04 AM UTC 24 |
| Peak memory | 222696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407272851 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.3407272851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1895319280 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 6347153414 ps |
| CPU time | 376.17 seconds |
| Started | Sep 18 11:08:08 AM UTC 24 |
| Finished | Sep 18 11:14:30 AM UTC 24 |
| Peak memory | 373008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895319280 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.1895319280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3474780187 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3672756625 ps |
| CPU time | 19.87 seconds |
| Started | Sep 18 11:08:41 AM UTC 24 |
| Finished | Sep 18 11:09:02 AM UTC 24 |
| Peak memory | 212648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474780187 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3474780187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.2800252586 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 120840285377 ps |
| CPU time | 305.41 seconds |
| Started | Sep 18 11:08:42 AM UTC 24 |
| Finished | Sep 18 11:13:52 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800252586 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_a ccess_b2b.2800252586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1052951692 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 365504098 ps |
| CPU time | 5.92 seconds |
| Started | Sep 18 11:10:11 AM UTC 24 |
| Finished | Sep 18 11:10:18 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052951692 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1052951692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.758687881 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3186447552 ps |
| CPU time | 861.87 seconds |
| Started | Sep 18 11:09:44 AM UTC 24 |
| Finished | Sep 18 11:24:16 AM UTC 24 |
| Peak memory | 385288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758687881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.758687881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1345503453 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1662730954 ps |
| CPU time | 48.47 seconds |
| Started | Sep 18 11:07:41 AM UTC 24 |
| Finished | Sep 18 11:08:31 AM UTC 24 |
| Peak memory | 317636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345503453 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1345503453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.363108103 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 18935204516 ps |
| CPU time | 3363.9 seconds |
| Started | Sep 18 11:10:35 AM UTC 24 |
| Finished | Sep 18 12:07:14 PM UTC 24 |
| Peak memory | 392920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36310810 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.363108103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.622204812 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 679720181 ps |
| CPU time | 34.89 seconds |
| Started | Sep 18 11:10:32 AM UTC 24 |
| Finished | Sep 18 11:11:08 AM UTC 24 |
| Peak memory | 222580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622204812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.622204812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.130224660 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 5792128202 ps |
| CPU time | 150.56 seconds |
| Started | Sep 18 11:08:33 AM UTC 24 |
| Finished | Sep 18 11:11:06 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130224660 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.130224660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1577228429 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 854105831 ps |
| CPU time | 87.94 seconds |
| Started | Sep 18 11:09:03 AM UTC 24 |
| Finished | Sep 18 11:10:34 AM UTC 24 |
| Peak memory | 370832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1577228429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _throughput_w_partial_write.1577228429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1538555166 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 25112464784 ps |
| CPU time | 1025.76 seconds |
| Started | Sep 18 11:11:33 AM UTC 24 |
| Finished | Sep 18 11:28:51 AM UTC 24 |
| Peak memory | 383452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538555166 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_duri ng_key_req.1538555166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.837921956 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 16139086 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 11:13:17 AM UTC 24 |
| Finished | Sep 18 11:13:19 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837921956 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.837921956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.1847825929 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 30374249887 ps |
| CPU time | 629.17 seconds |
| Started | Sep 18 11:10:57 AM UTC 24 |
| Finished | Sep 18 11:21:35 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847825929 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.1847825929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2127233277 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 10336072745 ps |
| CPU time | 113.62 seconds |
| Started | Sep 18 11:12:00 AM UTC 24 |
| Finished | Sep 18 11:13:56 AM UTC 24 |
| Peak memory | 348640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127233277 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.2127233277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2890365131 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 28928670067 ps |
| CPU time | 93.48 seconds |
| Started | Sep 18 11:11:27 AM UTC 24 |
| Finished | Sep 18 11:13:03 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890365131 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.2890365131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3076843214 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 4152621142 ps |
| CPU time | 9.94 seconds |
| Started | Sep 18 11:11:14 AM UTC 24 |
| Finished | Sep 18 11:11:25 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3076843214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ max_throughput.3076843214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3239947308 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2446782225 ps |
| CPU time | 82.55 seconds |
| Started | Sep 18 11:12:36 AM UTC 24 |
| Finished | Sep 18 11:14:00 AM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239947308 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.3239947308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3282756747 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 28226378496 ps |
| CPU time | 439.22 seconds |
| Started | Sep 18 11:12:16 AM UTC 24 |
| Finished | Sep 18 11:19:41 AM UTC 24 |
| Peak memory | 222788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282756747 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.3282756747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.1955858417 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 14572297472 ps |
| CPU time | 708.63 seconds |
| Started | Sep 18 11:10:52 AM UTC 24 |
| Finished | Sep 18 11:22:49 AM UTC 24 |
| Peak memory | 383180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955858417 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.1955858417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3971718304 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3550240661 ps |
| CPU time | 106 seconds |
| Started | Sep 18 11:11:08 AM UTC 24 |
| Finished | Sep 18 11:12:56 AM UTC 24 |
| Peak memory | 379288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971718304 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.3971718304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.852945805 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 91515584076 ps |
| CPU time | 496.49 seconds |
| Started | Sep 18 11:11:09 AM UTC 24 |
| Finished | Sep 18 11:19:31 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852945805 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_ac cess_b2b.852945805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.760247591 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2800528830 ps |
| CPU time | 5.97 seconds |
| Started | Sep 18 11:12:07 AM UTC 24 |
| Finished | Sep 18 11:12:14 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760247591 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.760247591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.3533233853 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2129811599 ps |
| CPU time | 362.08 seconds |
| Started | Sep 18 11:12:05 AM UTC 24 |
| Finished | Sep 18 11:18:13 AM UTC 24 |
| Peak memory | 387216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533233853 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3533233853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.540481707 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2547294977 ps |
| CPU time | 15.01 seconds |
| Started | Sep 18 11:10:50 AM UTC 24 |
| Finished | Sep 18 11:11:07 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540481707 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.540481707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.860563836 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 289747003798 ps |
| CPU time | 4326.04 seconds |
| Started | Sep 18 11:13:04 AM UTC 24 |
| Finished | Sep 18 12:25:55 PM UTC 24 |
| Peak memory | 405272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86056383 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.860563836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3149539508 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1216461067 ps |
| CPU time | 31.35 seconds |
| Started | Sep 18 11:12:57 AM UTC 24 |
| Finished | Sep 18 11:13:30 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149539508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3149539508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2107402200 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 24775080320 ps |
| CPU time | 476.5 seconds |
| Started | Sep 18 11:11:08 AM UTC 24 |
| Finished | Sep 18 11:19:11 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107402200 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.2107402200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.64189388 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 721620925 ps |
| CPU time | 32.05 seconds |
| Started | Sep 18 11:11:26 AM UTC 24 |
| Finished | Sep 18 11:11:59 AM UTC 24 |
| Peak memory | 284876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =64189388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t hroughput_w_partial_write.64189388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2293465284 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 82613261101 ps |
| CPU time | 596.94 seconds |
| Started | Sep 18 11:14:17 AM UTC 24 |
| Finished | Sep 18 11:24:21 AM UTC 24 |
| Peak memory | 368924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293465284 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_duri ng_key_req.2293465284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2275758588 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 15107364 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 11:17:22 AM UTC 24 |
| Finished | Sep 18 11:17:24 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275758588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.2275758588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.223248798 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 30287927526 ps |
| CPU time | 646.56 seconds |
| Started | Sep 18 11:13:30 AM UTC 24 |
| Finished | Sep 18 11:24:25 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223248798 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.223248798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.3766234295 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 6992638168 ps |
| CPU time | 805.46 seconds |
| Started | Sep 18 11:14:30 AM UTC 24 |
| Finished | Sep 18 11:28:06 AM UTC 24 |
| Peak memory | 383268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766234295 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.3766234295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2045569786 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 7004132968 ps |
| CPU time | 45.4 seconds |
| Started | Sep 18 11:14:14 AM UTC 24 |
| Finished | Sep 18 11:15:01 AM UTC 24 |
| Peak memory | 222704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045569786 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.2045569786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3295461520 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1440893123 ps |
| CPU time | 17.97 seconds |
| Started | Sep 18 11:13:57 AM UTC 24 |
| Finished | Sep 18 11:14:16 AM UTC 24 |
| Peak memory | 247956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3295461520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ max_throughput.3295461520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1635239412 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 19678625458 ps |
| CPU time | 171.23 seconds |
| Started | Sep 18 11:15:50 AM UTC 24 |
| Finished | Sep 18 11:18:44 AM UTC 24 |
| Peak memory | 222572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635239412 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1635239412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1481906461 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2743912977 ps |
| CPU time | 187.03 seconds |
| Started | Sep 18 11:15:10 AM UTC 24 |
| Finished | Sep 18 11:18:20 AM UTC 24 |
| Peak memory | 222592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481906461 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.1481906461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2355429110 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 36154492679 ps |
| CPU time | 917.43 seconds |
| Started | Sep 18 11:13:26 AM UTC 24 |
| Finished | Sep 18 11:28:54 AM UTC 24 |
| Peak memory | 389304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355429110 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2355429110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3314072440 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 644685541 ps |
| CPU time | 19.2 seconds |
| Started | Sep 18 11:13:53 AM UTC 24 |
| Finished | Sep 18 11:14:13 AM UTC 24 |
| Peak memory | 278672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314072440 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.3314072440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1921350593 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 7661271877 ps |
| CPU time | 203.85 seconds |
| Started | Sep 18 11:13:54 AM UTC 24 |
| Finished | Sep 18 11:17:21 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921350593 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_a ccess_b2b.1921350593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2878363310 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 689545381 ps |
| CPU time | 6.32 seconds |
| Started | Sep 18 11:15:02 AM UTC 24 |
| Finished | Sep 18 11:15:09 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878363310 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2878363310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.2360234362 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 8420975902 ps |
| CPU time | 322.22 seconds |
| Started | Sep 18 11:14:31 AM UTC 24 |
| Finished | Sep 18 11:19:58 AM UTC 24 |
| Peak memory | 381400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360234362 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2360234362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2757450397 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 4901916542 ps |
| CPU time | 30.58 seconds |
| Started | Sep 18 11:13:20 AM UTC 24 |
| Finished | Sep 18 11:13:52 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757450397 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2757450397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.293951489 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 358506536307 ps |
| CPU time | 8357.95 seconds |
| Started | Sep 18 11:16:40 AM UTC 24 |
| Finished | Sep 18 01:37:26 PM UTC 24 |
| Peak memory | 388932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29395148 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.293951489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2319447300 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1381956754 ps |
| CPU time | 32.73 seconds |
| Started | Sep 18 11:16:05 AM UTC 24 |
| Finished | Sep 18 11:16:39 AM UTC 24 |
| Peak memory | 222884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319447300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2319447300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2572829113 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4635040948 ps |
| CPU time | 463.26 seconds |
| Started | Sep 18 11:13:42 AM UTC 24 |
| Finished | Sep 18 11:21:31 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572829113 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2572829113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.860018260 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1250302637 ps |
| CPU time | 28.5 seconds |
| Started | Sep 18 11:14:01 AM UTC 24 |
| Finished | Sep 18 11:14:31 AM UTC 24 |
| Peak memory | 278676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =860018260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ throughput_w_partial_write.860018260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2769027747 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 5182038142 ps |
| CPU time | 269.93 seconds |
| Started | Sep 18 11:19:20 AM UTC 24 |
| Finished | Sep 18 11:23:54 AM UTC 24 |
| Peak memory | 377104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769027747 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_duri ng_key_req.2769027747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.2942802756 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 39113434 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 11:20:41 AM UTC 24 |
| Finished | Sep 18 11:20:43 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942802756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2942802756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.785918567 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 403191237837 ps |
| CPU time | 2665.28 seconds |
| Started | Sep 18 11:17:32 AM UTC 24 |
| Finished | Sep 18 12:02:28 PM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785918567 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.785918567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.1246234205 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 26979462515 ps |
| CPU time | 637.67 seconds |
| Started | Sep 18 11:19:32 AM UTC 24 |
| Finished | Sep 18 11:30:17 AM UTC 24 |
| Peak memory | 377316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246234205 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.1246234205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.377014547 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1421164963 ps |
| CPU time | 6.35 seconds |
| Started | Sep 18 11:19:12 AM UTC 24 |
| Finished | Sep 18 11:19:19 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377014547 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.377014547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2460769793 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 810269160 ps |
| CPU time | 53.62 seconds |
| Started | Sep 18 11:18:38 AM UTC 24 |
| Finished | Sep 18 11:19:34 AM UTC 24 |
| Peak memory | 336288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2460769793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ max_throughput.2460769793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3422456516 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1932843301 ps |
| CPU time | 88.21 seconds |
| Started | Sep 18 11:19:59 AM UTC 24 |
| Finished | Sep 18 11:21:30 AM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422456516 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.3422456516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.321248973 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2061932343 ps |
| CPU time | 151.01 seconds |
| Started | Sep 18 11:19:50 AM UTC 24 |
| Finished | Sep 18 11:22:24 AM UTC 24 |
| Peak memory | 222796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321248973 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.321248973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.4072625687 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 89883473075 ps |
| CPU time | 775.63 seconds |
| Started | Sep 18 11:17:29 AM UTC 24 |
| Finished | Sep 18 11:30:33 AM UTC 24 |
| Peak memory | 389584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072625687 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.4072625687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.890134490 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1191078271 ps |
| CPU time | 22.82 seconds |
| Started | Sep 18 11:18:13 AM UTC 24 |
| Finished | Sep 18 11:18:37 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890134490 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.890134490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1082722012 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 22567884639 ps |
| CPU time | 674.92 seconds |
| Started | Sep 18 11:18:21 AM UTC 24 |
| Finished | Sep 18 11:29:45 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082722012 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_a ccess_b2b.1082722012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1113743754 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 682600805 ps |
| CPU time | 6.07 seconds |
| Started | Sep 18 11:19:42 AM UTC 24 |
| Finished | Sep 18 11:19:49 AM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113743754 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1113743754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.2226480615 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 6734235439 ps |
| CPU time | 772.54 seconds |
| Started | Sep 18 11:19:35 AM UTC 24 |
| Finished | Sep 18 11:32:37 AM UTC 24 |
| Peak memory | 391436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226480615 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2226480615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.3338142253 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1787546960 ps |
| CPU time | 34.54 seconds |
| Started | Sep 18 11:17:25 AM UTC 24 |
| Finished | Sep 18 11:18:01 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338142253 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3338142253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2804897217 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 1227686762123 ps |
| CPU time | 7583.35 seconds |
| Started | Sep 18 11:20:29 AM UTC 24 |
| Finished | Sep 18 01:28:17 PM UTC 24 |
| Peak memory | 392976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28048972 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a ll.2804897217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2580402942 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2894218793 ps |
| CPU time | 33.43 seconds |
| Started | Sep 18 11:20:05 AM UTC 24 |
| Finished | Sep 18 11:20:40 AM UTC 24 |
| Peak memory | 222912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580402942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2580402942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3230013138 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3959029638 ps |
| CPU time | 337.22 seconds |
| Started | Sep 18 11:18:01 AM UTC 24 |
| Finished | Sep 18 11:23:43 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230013138 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.3230013138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.13486349 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 961502738 ps |
| CPU time | 78.32 seconds |
| Started | Sep 18 11:18:45 AM UTC 24 |
| Finished | Sep 18 11:20:05 AM UTC 24 |
| Peak memory | 358536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =13486349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t hroughput_w_partial_write.13486349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2249687954 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 6255797989 ps |
| CPU time | 297.37 seconds |
| Started | Sep 18 11:22:52 AM UTC 24 |
| Finished | Sep 18 11:27:54 AM UTC 24 |
| Peak memory | 360624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249687954 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_duri ng_key_req.2249687954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.401433934 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 42465826 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 11:24:35 AM UTC 24 |
| Finished | Sep 18 11:24:37 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401433934 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.401433934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.1513218924 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 89741487154 ps |
| CPU time | 2140.17 seconds |
| Started | Sep 18 11:21:30 AM UTC 24 |
| Finished | Sep 18 11:57:36 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513218924 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.1513218924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3362551866 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 116554817833 ps |
| CPU time | 396.18 seconds |
| Started | Sep 18 11:23:03 AM UTC 24 |
| Finished | Sep 18 11:29:45 AM UTC 24 |
| Peak memory | 338140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362551866 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3362551866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.211373878 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 65696216849 ps |
| CPU time | 120.58 seconds |
| Started | Sep 18 11:22:50 AM UTC 24 |
| Finished | Sep 18 11:24:53 AM UTC 24 |
| Peak memory | 222632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211373878 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.211373878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2203844544 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3178284434 ps |
| CPU time | 107.24 seconds |
| Started | Sep 18 11:22:45 AM UTC 24 |
| Finished | Sep 18 11:24:34 AM UTC 24 |
| Peak memory | 383256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2203844544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ max_throughput.2203844544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.572288412 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 5275035128 ps |
| CPU time | 213.39 seconds |
| Started | Sep 18 11:24:17 AM UTC 24 |
| Finished | Sep 18 11:27:54 AM UTC 24 |
| Peak memory | 222680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572288412 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.572288412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.198821521 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 35918117681 ps |
| CPU time | 190.12 seconds |
| Started | Sep 18 11:24:04 AM UTC 24 |
| Finished | Sep 18 11:27:17 AM UTC 24 |
| Peak memory | 222632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198821521 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.198821521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.960679651 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3458579315 ps |
| CPU time | 114.59 seconds |
| Started | Sep 18 11:20:52 AM UTC 24 |
| Finished | Sep 18 11:22:49 AM UTC 24 |
| Peak memory | 377104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960679651 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.960679651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3443029781 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 846252302 ps |
| CPU time | 66.67 seconds |
| Started | Sep 18 11:21:35 AM UTC 24 |
| Finished | Sep 18 11:22:44 AM UTC 24 |
| Peak memory | 340376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443029781 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.3443029781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.52113680 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 5128174206 ps |
| CPU time | 368.9 seconds |
| Started | Sep 18 11:22:26 AM UTC 24 |
| Finished | Sep 18 11:28:40 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52113680 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc ess_b2b.52113680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.900685226 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 360716357 ps |
| CPU time | 5.97 seconds |
| Started | Sep 18 11:23:55 AM UTC 24 |
| Finished | Sep 18 11:24:02 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900685226 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.900685226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.3203967066 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 56164755740 ps |
| CPU time | 627.94 seconds |
| Started | Sep 18 11:23:44 AM UTC 24 |
| Finished | Sep 18 11:34:19 AM UTC 24 |
| Peak memory | 387540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203967066 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3203967066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.4148619323 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1067361712 ps |
| CPU time | 6.13 seconds |
| Started | Sep 18 11:20:44 AM UTC 24 |
| Finished | Sep 18 11:20:51 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148619323 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.4148619323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1556162595 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 283494650179 ps |
| CPU time | 4667.46 seconds |
| Started | Sep 18 11:24:26 AM UTC 24 |
| Finished | Sep 18 12:43:01 PM UTC 24 |
| Peak memory | 393248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15561625 95 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_a ll.1556162595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.600184992 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 316932760 ps |
| CPU time | 18.96 seconds |
| Started | Sep 18 11:24:22 AM UTC 24 |
| Finished | Sep 18 11:24:42 AM UTC 24 |
| Peak memory | 222648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600184992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.600184992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2533891714 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3671659328 ps |
| CPU time | 375.03 seconds |
| Started | Sep 18 11:21:32 AM UTC 24 |
| Finished | Sep 18 11:27:53 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533891714 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.2533891714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2342198444 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 790840271 ps |
| CPU time | 11.55 seconds |
| Started | Sep 18 11:22:50 AM UTC 24 |
| Finished | Sep 18 11:23:03 AM UTC 24 |
| Peak memory | 235796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2342198444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _throughput_w_partial_write.2342198444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.569003223 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 28283711296 ps |
| CPU time | 819.44 seconds |
| Started | Sep 18 10:03:10 AM UTC 24 |
| Finished | Sep 18 10:16:59 AM UTC 24 |
| Peak memory | 387612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569003223 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during _key_req.569003223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.644900634 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 25673100 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 10:03:58 AM UTC 24 |
| Finished | Sep 18 10:04:00 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644900634 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.644900634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3475439413 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 115038789311 ps |
| CPU time | 2609.99 seconds |
| Started | Sep 18 10:02:36 AM UTC 24 |
| Finished | Sep 18 10:46:33 AM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475439413 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3475439413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.2403202780 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 34431958650 ps |
| CPU time | 637.38 seconds |
| Started | Sep 18 10:03:14 AM UTC 24 |
| Finished | Sep 18 10:13:59 AM UTC 24 |
| Peak memory | 367072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403202780 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.2403202780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1226977796 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 24847290611 ps |
| CPU time | 103.35 seconds |
| Started | Sep 18 10:03:08 AM UTC 24 |
| Finished | Sep 18 10:04:54 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226977796 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.1226977796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3346723985 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 774063811 ps |
| CPU time | 70.68 seconds |
| Started | Sep 18 10:02:44 AM UTC 24 |
| Finished | Sep 18 10:03:56 AM UTC 24 |
| Peak memory | 336280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3346723985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m ax_throughput.3346723985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2785585986 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 7090801791 ps |
| CPU time | 183.4 seconds |
| Started | Sep 18 10:03:35 AM UTC 24 |
| Finished | Sep 18 10:06:41 AM UTC 24 |
| Peak memory | 222604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785585986 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.2785585986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3939030938 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6917522030 ps |
| CPU time | 191.84 seconds |
| Started | Sep 18 10:03:29 AM UTC 24 |
| Finished | Sep 18 10:06:45 AM UTC 24 |
| Peak memory | 222592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939030938 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.3939030938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1503208882 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4279089343 ps |
| CPU time | 286.06 seconds |
| Started | Sep 18 10:02:36 AM UTC 24 |
| Finished | Sep 18 10:07:25 AM UTC 24 |
| Peak memory | 362896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503208882 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.1503208882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2507996569 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 778541631 ps |
| CPU time | 29.23 seconds |
| Started | Sep 18 10:02:39 AM UTC 24 |
| Finished | Sep 18 10:03:09 AM UTC 24 |
| Peak memory | 280792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507996569 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.2507996569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.123925698 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 147898492534 ps |
| CPU time | 437.79 seconds |
| Started | Sep 18 10:02:43 AM UTC 24 |
| Finished | Sep 18 10:10:06 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123925698 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acc ess_b2b.123925698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1368621080 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1306774227 ps |
| CPU time | 5.95 seconds |
| Started | Sep 18 10:03:26 AM UTC 24 |
| Finished | Sep 18 10:03:33 AM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368621080 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1368621080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4165862969 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 11911586801 ps |
| CPU time | 613.03 seconds |
| Started | Sep 18 10:03:21 AM UTC 24 |
| Finished | Sep 18 10:13:41 AM UTC 24 |
| Peak memory | 387544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165862969 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.4165862969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.4062919679 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 100376356 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 10:03:57 AM UTC 24 |
| Finished | Sep 18 10:04:00 AM UTC 24 |
| Peak memory | 248188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062919679 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.4062919679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1840762970 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 770199604 ps |
| CPU time | 14.76 seconds |
| Started | Sep 18 10:02:35 AM UTC 24 |
| Finished | Sep 18 10:02:51 AM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840762970 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1840762970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2323125674 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1035940235962 ps |
| CPU time | 6237.29 seconds |
| Started | Sep 18 10:03:43 AM UTC 24 |
| Finished | Sep 18 11:48:46 AM UTC 24 |
| Peak memory | 393052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23231256 74 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.2323125674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1843821152 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1092800006 ps |
| CPU time | 37.56 seconds |
| Started | Sep 18 10:03:37 AM UTC 24 |
| Finished | Sep 18 10:04:16 AM UTC 24 |
| Peak memory | 222648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843821152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1843821152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3608184143 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 25019253004 ps |
| CPU time | 358.23 seconds |
| Started | Sep 18 10:02:38 AM UTC 24 |
| Finished | Sep 18 10:08:41 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608184143 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3608184143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1436567084 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2796520037 ps |
| CPU time | 19.77 seconds |
| Started | Sep 18 10:02:52 AM UTC 24 |
| Finished | Sep 18 10:03:13 AM UTC 24 |
| Peak memory | 252176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1436567084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ throughput_w_partial_write.1436567084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1409168806 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 60026099217 ps |
| CPU time | 1133.28 seconds |
| Started | Sep 18 11:27:28 AM UTC 24 |
| Finished | Sep 18 11:46:33 AM UTC 24 |
| Peak memory | 391016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409168806 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri ng_key_req.1409168806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3316148958 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 54006213 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 11:28:06 AM UTC 24 |
| Finished | Sep 18 11:28:08 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316148958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3316148958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2181146795 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 505857558421 ps |
| CPU time | 2623.09 seconds |
| Started | Sep 18 11:24:53 AM UTC 24 |
| Finished | Sep 18 12:09:05 PM UTC 24 |
| Peak memory | 213944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181146795 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2181146795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.3216899235 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 13868260174 ps |
| CPU time | 779.97 seconds |
| Started | Sep 18 11:27:43 AM UTC 24 |
| Finished | Sep 18 11:40:51 AM UTC 24 |
| Peak memory | 387296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216899235 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.3216899235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.408947064 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 71379408643 ps |
| CPU time | 90.51 seconds |
| Started | Sep 18 11:27:21 AM UTC 24 |
| Finished | Sep 18 11:28:54 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408947064 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.408947064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1056843444 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 3122414237 ps |
| CPU time | 71.08 seconds |
| Started | Sep 18 11:26:49 AM UTC 24 |
| Finished | Sep 18 11:28:02 AM UTC 24 |
| Peak memory | 360732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1056843444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ max_throughput.1056843444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.4151270550 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 17313964797 ps |
| CPU time | 117.83 seconds |
| Started | Sep 18 11:28:03 AM UTC 24 |
| Finished | Sep 18 11:30:03 AM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151270550 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.4151270550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.2764039254 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 10335325874 ps |
| CPU time | 169.9 seconds |
| Started | Sep 18 11:27:55 AM UTC 24 |
| Finished | Sep 18 11:30:48 AM UTC 24 |
| Peak memory | 222588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764039254 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.2764039254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.551554923 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 7702483604 ps |
| CPU time | 104.54 seconds |
| Started | Sep 18 11:24:43 AM UTC 24 |
| Finished | Sep 18 11:26:30 AM UTC 24 |
| Peak memory | 321744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551554923 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.551554923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.378015748 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1489999247 ps |
| CPU time | 38.69 seconds |
| Started | Sep 18 11:26:08 AM UTC 24 |
| Finished | Sep 18 11:26:48 AM UTC 24 |
| Peak memory | 295120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378015748 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.378015748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.93030852 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 16824048831 ps |
| CPU time | 417.3 seconds |
| Started | Sep 18 11:26:31 AM UTC 24 |
| Finished | Sep 18 11:33:34 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93030852 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acc ess_b2b.93030852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.513172595 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 345922751 ps |
| CPU time | 5.91 seconds |
| Started | Sep 18 11:27:55 AM UTC 24 |
| Finished | Sep 18 11:28:02 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513172595 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.513172595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.2296378153 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5190118767 ps |
| CPU time | 150.13 seconds |
| Started | Sep 18 11:27:54 AM UTC 24 |
| Finished | Sep 18 11:30:26 AM UTC 24 |
| Peak memory | 385236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296378153 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2296378153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.768020490 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8513321227 ps |
| CPU time | 38.98 seconds |
| Started | Sep 18 11:24:38 AM UTC 24 |
| Finished | Sep 18 11:25:19 AM UTC 24 |
| Peak memory | 301328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768020490 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.768020490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.4228516739 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 142054111434 ps |
| CPU time | 3206.69 seconds |
| Started | Sep 18 11:28:06 AM UTC 24 |
| Finished | Sep 18 12:22:06 PM UTC 24 |
| Peak memory | 395168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42285167 39 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_a ll.4228516739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1894947091 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4910520715 ps |
| CPU time | 108.82 seconds |
| Started | Sep 18 11:28:03 AM UTC 24 |
| Finished | Sep 18 11:29:54 AM UTC 24 |
| Peak memory | 373008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894947091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1894947091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2795809223 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 5756395596 ps |
| CPU time | 189.4 seconds |
| Started | Sep 18 11:25:19 AM UTC 24 |
| Finished | Sep 18 11:28:32 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795809223 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.2795809223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.996974791 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 676304157 ps |
| CPU time | 7.05 seconds |
| Started | Sep 18 11:27:18 AM UTC 24 |
| Finished | Sep 18 11:27:26 AM UTC 24 |
| Peak memory | 222808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =996974791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ throughput_w_partial_write.996974791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.407162434 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 9483045333 ps |
| CPU time | 468.31 seconds |
| Started | Sep 18 11:29:45 AM UTC 24 |
| Finished | Sep 18 11:37:40 AM UTC 24 |
| Peak memory | 383516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407162434 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_durin g_key_req.407162434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2657338051 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 15611107 ps |
| CPU time | 1 seconds |
| Started | Sep 18 11:30:35 AM UTC 24 |
| Finished | Sep 18 11:30:37 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657338051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2657338051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.4188100355 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 61114008545 ps |
| CPU time | 1071.45 seconds |
| Started | Sep 18 11:28:41 AM UTC 24 |
| Finished | Sep 18 11:46:45 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188100355 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.4188100355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.865520679 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 8678607390 ps |
| CPU time | 735.42 seconds |
| Started | Sep 18 11:29:47 AM UTC 24 |
| Finished | Sep 18 11:42:11 AM UTC 24 |
| Peak memory | 383232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865520679 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.865520679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.80256656 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 6371425083 ps |
| CPU time | 66.07 seconds |
| Started | Sep 18 11:29:32 AM UTC 24 |
| Finished | Sep 18 11:30:40 AM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80256656 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.80256656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2944166965 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2811601561 ps |
| CPU time | 34.2 seconds |
| Started | Sep 18 11:28:56 AM UTC 24 |
| Finished | Sep 18 11:29:32 AM UTC 24 |
| Peak memory | 321796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2944166965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ max_throughput.2944166965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3364527121 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 10098263358 ps |
| CPU time | 170.76 seconds |
| Started | Sep 18 11:30:18 AM UTC 24 |
| Finished | Sep 18 11:33:12 AM UTC 24 |
| Peak memory | 222684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364527121 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.3364527121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4092724105 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2040211039 ps |
| CPU time | 120.37 seconds |
| Started | Sep 18 11:30:11 AM UTC 24 |
| Finished | Sep 18 11:32:14 AM UTC 24 |
| Peak memory | 222592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092724105 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.4092724105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2958275290 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 19511404390 ps |
| CPU time | 713.88 seconds |
| Started | Sep 18 11:28:33 AM UTC 24 |
| Finished | Sep 18 11:40:34 AM UTC 24 |
| Peak memory | 389396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958275290 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.2958275290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2191662892 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 5951809076 ps |
| CPU time | 21.89 seconds |
| Started | Sep 18 11:28:52 AM UTC 24 |
| Finished | Sep 18 11:29:15 AM UTC 24 |
| Peak memory | 212580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191662892 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.2191662892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.17666479 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 15586618810 ps |
| CPU time | 432.21 seconds |
| Started | Sep 18 11:28:55 AM UTC 24 |
| Finished | Sep 18 11:36:13 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17666479 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc ess_b2b.17666479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.4199799532 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1350472797 ps |
| CPU time | 5.15 seconds |
| Started | Sep 18 11:30:04 AM UTC 24 |
| Finished | Sep 18 11:30:10 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199799532 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.4199799532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.932646285 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 66966920564 ps |
| CPU time | 507.22 seconds |
| Started | Sep 18 11:29:55 AM UTC 24 |
| Finished | Sep 18 11:38:28 AM UTC 24 |
| Peak memory | 389324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932646285 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.932646285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.1527562889 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 6276573045 ps |
| CPU time | 34.21 seconds |
| Started | Sep 18 11:28:09 AM UTC 24 |
| Finished | Sep 18 11:28:45 AM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527562889 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1527562889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.4035488700 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 967290394590 ps |
| CPU time | 5995.24 seconds |
| Started | Sep 18 11:30:34 AM UTC 24 |
| Finished | Sep 18 01:11:34 PM UTC 24 |
| Peak memory | 390932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40354887 00 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_a ll.4035488700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1543194490 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3740968332 ps |
| CPU time | 65.32 seconds |
| Started | Sep 18 11:30:27 AM UTC 24 |
| Finished | Sep 18 11:31:34 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543194490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1543194490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1940750139 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2602154520 ps |
| CPU time | 223.68 seconds |
| Started | Sep 18 11:28:46 AM UTC 24 |
| Finished | Sep 18 11:32:33 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940750139 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.1940750139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3664686879 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 794755388 ps |
| CPU time | 77.1 seconds |
| Started | Sep 18 11:29:16 AM UTC 24 |
| Finished | Sep 18 11:30:35 AM UTC 24 |
| Peak memory | 381332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3664686879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _throughput_w_partial_write.3664686879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2582580234 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 64368646839 ps |
| CPU time | 1096.37 seconds |
| Started | Sep 18 11:32:38 AM UTC 24 |
| Finished | Sep 18 11:51:07 AM UTC 24 |
| Peak memory | 389400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582580234 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_duri ng_key_req.2582580234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.237296284 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 13507814 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 11:34:27 AM UTC 24 |
| Finished | Sep 18 11:34:29 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237296284 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.237296284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2097353129 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 16411426890 ps |
| CPU time | 641.76 seconds |
| Started | Sep 18 11:30:49 AM UTC 24 |
| Finished | Sep 18 11:41:39 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097353129 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.2097353129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3320235031 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 26139648543 ps |
| CPU time | 434.84 seconds |
| Started | Sep 18 11:32:38 AM UTC 24 |
| Finished | Sep 18 11:39:58 AM UTC 24 |
| Peak memory | 385236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320235031 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.3320235031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.856116101 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 46747247857 ps |
| CPU time | 109.77 seconds |
| Started | Sep 18 11:32:33 AM UTC 24 |
| Finished | Sep 18 11:34:25 AM UTC 24 |
| Peak memory | 226732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856116101 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.856116101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3797263713 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1519367282 ps |
| CPU time | 29.43 seconds |
| Started | Sep 18 11:32:15 AM UTC 24 |
| Finished | Sep 18 11:32:46 AM UTC 24 |
| Peak memory | 288912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3797263713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ max_throughput.3797263713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3850920029 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2457411576 ps |
| CPU time | 143.15 seconds |
| Started | Sep 18 11:33:34 AM UTC 24 |
| Finished | Sep 18 11:36:00 AM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850920029 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.3850920029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3329324739 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 4153358118 ps |
| CPU time | 354.91 seconds |
| Started | Sep 18 11:33:21 AM UTC 24 |
| Finished | Sep 18 11:39:21 AM UTC 24 |
| Peak memory | 222624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329324739 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.3329324739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.183300474 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 22361644495 ps |
| CPU time | 461.45 seconds |
| Started | Sep 18 11:30:41 AM UTC 24 |
| Finished | Sep 18 11:38:29 AM UTC 24 |
| Peak memory | 379156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183300474 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.183300474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.308069593 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2945389980 ps |
| CPU time | 41.61 seconds |
| Started | Sep 18 11:31:36 AM UTC 24 |
| Finished | Sep 18 11:32:19 AM UTC 24 |
| Peak memory | 295108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308069593 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.308069593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3531074364 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 78716630375 ps |
| CPU time | 493.71 seconds |
| Started | Sep 18 11:32:14 AM UTC 24 |
| Finished | Sep 18 11:40:35 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531074364 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_a ccess_b2b.3531074364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.4183330158 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 694072848 ps |
| CPU time | 5.82 seconds |
| Started | Sep 18 11:33:13 AM UTC 24 |
| Finished | Sep 18 11:33:20 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183330158 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.4183330158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3864176896 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 43103641997 ps |
| CPU time | 694.25 seconds |
| Started | Sep 18 11:32:47 AM UTC 24 |
| Finished | Sep 18 11:44:29 AM UTC 24 |
| Peak memory | 387280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864176896 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3864176896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.4235557403 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3267347221 ps |
| CPU time | 35.25 seconds |
| Started | Sep 18 11:30:38 AM UTC 24 |
| Finished | Sep 18 11:31:15 AM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235557403 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.4235557403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.107381785 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 181321796967 ps |
| CPU time | 3774.78 seconds |
| Started | Sep 18 11:34:20 AM UTC 24 |
| Finished | Sep 18 12:37:55 PM UTC 24 |
| Peak memory | 390924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10738178 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.107381785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.891044987 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 6880039296 ps |
| CPU time | 119.24 seconds |
| Started | Sep 18 11:33:52 AM UTC 24 |
| Finished | Sep 18 11:35:54 AM UTC 24 |
| Peak memory | 248352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891044987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.891044987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1320526467 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 4988041030 ps |
| CPU time | 394.06 seconds |
| Started | Sep 18 11:31:16 AM UTC 24 |
| Finished | Sep 18 11:37:55 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320526467 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.1320526467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2118082427 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2978348169 ps |
| CPU time | 15.61 seconds |
| Started | Sep 18 11:32:20 AM UTC 24 |
| Finished | Sep 18 11:32:37 AM UTC 24 |
| Peak memory | 233880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2118082427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _throughput_w_partial_write.2118082427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.886372523 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 75945506270 ps |
| CPU time | 1109.54 seconds |
| Started | Sep 18 11:37:56 AM UTC 24 |
| Finished | Sep 18 11:56:38 AM UTC 24 |
| Peak memory | 389492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886372523 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_durin g_key_req.886372523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3278809284 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 42519357 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 11:39:19 AM UTC 24 |
| Finished | Sep 18 11:39:21 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278809284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3278809284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.3906674588 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 28301356377 ps |
| CPU time | 1982.37 seconds |
| Started | Sep 18 11:34:56 AM UTC 24 |
| Finished | Sep 18 12:08:23 PM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906674588 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.3906674588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.678939502 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 86888672318 ps |
| CPU time | 1206.18 seconds |
| Started | Sep 18 11:38:07 AM UTC 24 |
| Finished | Sep 18 11:58:27 AM UTC 24 |
| Peak memory | 379244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678939502 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.678939502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3881041309 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 6040280055 ps |
| CPU time | 41.8 seconds |
| Started | Sep 18 11:37:54 AM UTC 24 |
| Finished | Sep 18 11:38:37 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881041309 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.3881041309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3569881588 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2823160801 ps |
| CPU time | 107.11 seconds |
| Started | Sep 18 11:36:17 AM UTC 24 |
| Finished | Sep 18 11:38:06 AM UTC 24 |
| Peak memory | 379164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3569881588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ max_throughput.3569881588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1848066284 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5566539152 ps |
| CPU time | 107.18 seconds |
| Started | Sep 18 11:38:38 AM UTC 24 |
| Finished | Sep 18 11:40:27 AM UTC 24 |
| Peak memory | 222608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848066284 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.1848066284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3334473607 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 10394260919 ps |
| CPU time | 176.02 seconds |
| Started | Sep 18 11:38:29 AM UTC 24 |
| Finished | Sep 18 11:41:29 AM UTC 24 |
| Peak memory | 222580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334473607 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.3334473607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.5972951 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 20185939842 ps |
| CPU time | 672.43 seconds |
| Started | Sep 18 11:34:47 AM UTC 24 |
| Finished | Sep 18 11:46:07 AM UTC 24 |
| Peak memory | 385228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5972951 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.5972951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1942729221 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 951110485 ps |
| CPU time | 14.7 seconds |
| Started | Sep 18 11:36:01 AM UTC 24 |
| Finished | Sep 18 11:36:16 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942729221 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1942729221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.582454682 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 43748964461 ps |
| CPU time | 445.57 seconds |
| Started | Sep 18 11:36:14 AM UTC 24 |
| Finished | Sep 18 11:43:45 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582454682 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_ac cess_b2b.582454682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.1471678963 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1405336151 ps |
| CPU time | 6.7 seconds |
| Started | Sep 18 11:38:29 AM UTC 24 |
| Finished | Sep 18 11:38:37 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471678963 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1471678963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.2943860270 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 29329902688 ps |
| CPU time | 974.49 seconds |
| Started | Sep 18 11:38:19 AM UTC 24 |
| Finished | Sep 18 11:54:44 AM UTC 24 |
| Peak memory | 387284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943860270 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2943860270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1835366129 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1774256218 ps |
| CPU time | 23.9 seconds |
| Started | Sep 18 11:34:30 AM UTC 24 |
| Finished | Sep 18 11:34:55 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835366129 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1835366129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.21469948 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 460427864771 ps |
| CPU time | 3776.94 seconds |
| Started | Sep 18 11:39:14 AM UTC 24 |
| Finished | Sep 18 12:42:48 PM UTC 24 |
| Peak memory | 390944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21469948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.21469948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1573636196 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2993216649 ps |
| CPU time | 78.71 seconds |
| Started | Sep 18 11:38:38 AM UTC 24 |
| Finished | Sep 18 11:39:58 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573636196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1573636196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1152823572 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 17166261421 ps |
| CPU time | 239.42 seconds |
| Started | Sep 18 11:35:56 AM UTC 24 |
| Finished | Sep 18 11:39:59 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152823572 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.1152823572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3440962646 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 5173576495 ps |
| CPU time | 10.71 seconds |
| Started | Sep 18 11:37:40 AM UTC 24 |
| Finished | Sep 18 11:37:52 AM UTC 24 |
| Peak memory | 222880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3440962646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _throughput_w_partial_write.3440962646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2703111476 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 22052642453 ps |
| CPU time | 472.12 seconds |
| Started | Sep 18 11:40:36 AM UTC 24 |
| Finished | Sep 18 11:48:35 AM UTC 24 |
| Peak memory | 379084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703111476 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_duri ng_key_req.2703111476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1419274402 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 12585751 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 11:41:42 AM UTC 24 |
| Finished | Sep 18 11:41:44 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419274402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1419274402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.2789471814 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 192482769306 ps |
| CPU time | 952.79 seconds |
| Started | Sep 18 11:39:42 AM UTC 24 |
| Finished | Sep 18 11:55:46 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789471814 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.2789471814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1960524912 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 58991692315 ps |
| CPU time | 934.34 seconds |
| Started | Sep 18 11:40:36 AM UTC 24 |
| Finished | Sep 18 11:56:22 AM UTC 24 |
| Peak memory | 379172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960524912 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.1960524912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2494781623 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 8136332380 ps |
| CPU time | 71.14 seconds |
| Started | Sep 18 11:40:28 AM UTC 24 |
| Finished | Sep 18 11:41:41 AM UTC 24 |
| Peak memory | 222896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494781623 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.2494781623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3832657381 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1490107602 ps |
| CPU time | 77.13 seconds |
| Started | Sep 18 11:40:00 AM UTC 24 |
| Finished | Sep 18 11:41:19 AM UTC 24 |
| Peak memory | 348308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3832657381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ max_throughput.3832657381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1346229458 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4477622213 ps |
| CPU time | 199.46 seconds |
| Started | Sep 18 11:41:20 AM UTC 24 |
| Finished | Sep 18 11:44:43 AM UTC 24 |
| Peak memory | 222836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346229458 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.1346229458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2370800572 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 54474040998 ps |
| CPU time | 170.05 seconds |
| Started | Sep 18 11:41:02 AM UTC 24 |
| Finished | Sep 18 11:43:55 AM UTC 24 |
| Peak memory | 222620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370800572 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.2370800572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.735584445 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 22789364836 ps |
| CPU time | 823.59 seconds |
| Started | Sep 18 11:39:22 AM UTC 24 |
| Finished | Sep 18 11:53:15 AM UTC 24 |
| Peak memory | 377044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735584445 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.735584445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2190920910 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 5268026891 ps |
| CPU time | 11.01 seconds |
| Started | Sep 18 11:39:59 AM UTC 24 |
| Finished | Sep 18 11:40:11 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190920910 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.2190920910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1083548160 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 6842329763 ps |
| CPU time | 410.55 seconds |
| Started | Sep 18 11:39:59 AM UTC 24 |
| Finished | Sep 18 11:46:55 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083548160 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_a ccess_b2b.1083548160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1720872144 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 680425716 ps |
| CPU time | 5.74 seconds |
| Started | Sep 18 11:40:54 AM UTC 24 |
| Finished | Sep 18 11:41:01 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720872144 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1720872144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.2902731154 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 60918137671 ps |
| CPU time | 1049.76 seconds |
| Started | Sep 18 11:40:52 AM UTC 24 |
| Finished | Sep 18 11:58:34 AM UTC 24 |
| Peak memory | 389328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902731154 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2902731154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.3657175404 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2887978409 ps |
| CPU time | 18.34 seconds |
| Started | Sep 18 11:39:22 AM UTC 24 |
| Finished | Sep 18 11:39:42 AM UTC 24 |
| Peak memory | 248280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657175404 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3657175404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3791734697 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 32773072971 ps |
| CPU time | 1667.46 seconds |
| Started | Sep 18 11:41:40 AM UTC 24 |
| Finished | Sep 18 12:09:46 PM UTC 24 |
| Peak memory | 390932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37917346 97 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_a ll.3791734697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3277921426 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 682141820 ps |
| CPU time | 45.92 seconds |
| Started | Sep 18 11:41:29 AM UTC 24 |
| Finished | Sep 18 11:42:17 AM UTC 24 |
| Peak memory | 224692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277921426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3277921426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.1692330247 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 12692118643 ps |
| CPU time | 227.5 seconds |
| Started | Sep 18 11:39:52 AM UTC 24 |
| Finished | Sep 18 11:43:43 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692330247 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.1692330247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2998826020 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2901362520 ps |
| CPU time | 39.66 seconds |
| Started | Sep 18 11:40:12 AM UTC 24 |
| Finished | Sep 18 11:40:53 AM UTC 24 |
| Peak memory | 342220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2998826020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _throughput_w_partial_write.2998826020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3107001943 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 15071178264 ps |
| CPU time | 246 seconds |
| Started | Sep 18 11:44:01 AM UTC 24 |
| Finished | Sep 18 11:48:11 AM UTC 24 |
| Peak memory | 356548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107001943 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_duri ng_key_req.3107001943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.958548372 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 14732020 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 11:45:31 AM UTC 24 |
| Finished | Sep 18 11:45:33 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958548372 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.958548372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.2321414783 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 143870374990 ps |
| CPU time | 2038.15 seconds |
| Started | Sep 18 11:42:18 AM UTC 24 |
| Finished | Sep 18 12:16:40 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321414783 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.2321414783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1758686913 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 11043907902 ps |
| CPU time | 495.11 seconds |
| Started | Sep 18 11:44:02 AM UTC 24 |
| Finished | Sep 18 11:52:23 AM UTC 24 |
| Peak memory | 387276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758686913 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.1758686913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.630620323 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4802335200 ps |
| CPU time | 26.75 seconds |
| Started | Sep 18 11:43:59 AM UTC 24 |
| Finished | Sep 18 11:44:27 AM UTC 24 |
| Peak memory | 222620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630620323 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.630620323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3201909204 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1402524912 ps |
| CPU time | 10.06 seconds |
| Started | Sep 18 11:43:46 AM UTC 24 |
| Finished | Sep 18 11:43:58 AM UTC 24 |
| Peak memory | 222624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3201909204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ max_throughput.3201909204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.274832891 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3457125152 ps |
| CPU time | 105.95 seconds |
| Started | Sep 18 11:44:39 AM UTC 24 |
| Finished | Sep 18 11:46:27 AM UTC 24 |
| Peak memory | 222572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274832891 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.274832891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.581207392 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 16435260766 ps |
| CPU time | 218.39 seconds |
| Started | Sep 18 11:44:36 AM UTC 24 |
| Finished | Sep 18 11:48:18 AM UTC 24 |
| Peak memory | 222664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581207392 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.581207392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3416542287 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 5741787926 ps |
| CPU time | 240.02 seconds |
| Started | Sep 18 11:42:12 AM UTC 24 |
| Finished | Sep 18 11:46:16 AM UTC 24 |
| Peak memory | 325828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416542287 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3416542287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.745265683 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 6227560385 ps |
| CPU time | 24.14 seconds |
| Started | Sep 18 11:43:34 AM UTC 24 |
| Finished | Sep 18 11:44:00 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745265683 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.745265683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1612912624 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 22160358739 ps |
| CPU time | 551.88 seconds |
| Started | Sep 18 11:43:43 AM UTC 24 |
| Finished | Sep 18 11:53:02 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612912624 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_a ccess_b2b.1612912624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.327546490 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 360080867 ps |
| CPU time | 4.65 seconds |
| Started | Sep 18 11:44:30 AM UTC 24 |
| Finished | Sep 18 11:44:36 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327546490 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.327546490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2011460635 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 26149606906 ps |
| CPU time | 884.42 seconds |
| Started | Sep 18 11:44:27 AM UTC 24 |
| Finished | Sep 18 11:59:22 AM UTC 24 |
| Peak memory | 389336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011460635 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2011460635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2407312728 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 18640027371 ps |
| CPU time | 106.35 seconds |
| Started | Sep 18 11:41:45 AM UTC 24 |
| Finished | Sep 18 11:43:33 AM UTC 24 |
| Peak memory | 366812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407312728 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2407312728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1032192319 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 272624223818 ps |
| CPU time | 3941.22 seconds |
| Started | Sep 18 11:45:24 AM UTC 24 |
| Finished | Sep 18 12:51:44 PM UTC 24 |
| Peak memory | 390948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10321923 19 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_a ll.1032192319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.857706476 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2395952141 ps |
| CPU time | 80.59 seconds |
| Started | Sep 18 11:44:44 AM UTC 24 |
| Finished | Sep 18 11:46:06 AM UTC 24 |
| Peak memory | 224960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857706476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.857706476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.2005450460 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 15448128830 ps |
| CPU time | 287.52 seconds |
| Started | Sep 18 11:42:55 AM UTC 24 |
| Finished | Sep 18 11:47:46 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005450460 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.2005450460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1457035512 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1570790280 ps |
| CPU time | 85.43 seconds |
| Started | Sep 18 11:43:56 AM UTC 24 |
| Finished | Sep 18 11:45:23 AM UTC 24 |
| Peak memory | 356564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1457035512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _throughput_w_partial_write.1457035512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1998228901 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 91772684035 ps |
| CPU time | 495.46 seconds |
| Started | Sep 18 11:46:55 AM UTC 24 |
| Finished | Sep 18 11:55:16 AM UTC 24 |
| Peak memory | 383260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998228901 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_duri ng_key_req.1998228901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3901087211 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 19050458 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 11:48:20 AM UTC 24 |
| Finished | Sep 18 11:48:22 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901087211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3901087211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.1761797939 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 982039666846 ps |
| CPU time | 3154.54 seconds |
| Started | Sep 18 11:45:45 AM UTC 24 |
| Finished | Sep 18 12:38:55 PM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761797939 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.1761797939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.670902601 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 17873053726 ps |
| CPU time | 591.76 seconds |
| Started | Sep 18 11:46:56 AM UTC 24 |
| Finished | Sep 18 11:56:55 AM UTC 24 |
| Peak memory | 389396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670902601 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.670902601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.76487413 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 19392482293 ps |
| CPU time | 58.69 seconds |
| Started | Sep 18 11:46:46 AM UTC 24 |
| Finished | Sep 18 11:47:47 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76487413 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.76487413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2301305358 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5475623286 ps |
| CPU time | 24.37 seconds |
| Started | Sep 18 11:46:28 AM UTC 24 |
| Finished | Sep 18 11:46:54 AM UTC 24 |
| Peak memory | 295124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2301305358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ max_throughput.2301305358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.637145768 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2527646721 ps |
| CPU time | 185.53 seconds |
| Started | Sep 18 11:47:54 AM UTC 24 |
| Finished | Sep 18 11:51:03 AM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637145768 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.637145768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1417310561 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2040094954 ps |
| CPU time | 163.33 seconds |
| Started | Sep 18 11:47:48 AM UTC 24 |
| Finished | Sep 18 11:50:34 AM UTC 24 |
| Peak memory | 222632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417310561 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.1417310561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.225484956 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 38973456034 ps |
| CPU time | 1201.06 seconds |
| Started | Sep 18 11:45:44 AM UTC 24 |
| Finished | Sep 18 12:05:58 PM UTC 24 |
| Peak memory | 385304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225484956 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.225484956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1741410036 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4362966008 ps |
| CPU time | 55.3 seconds |
| Started | Sep 18 11:46:09 AM UTC 24 |
| Finished | Sep 18 11:47:06 AM UTC 24 |
| Peak memory | 319696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741410036 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.1741410036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.4152122499 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3932468009 ps |
| CPU time | 299.25 seconds |
| Started | Sep 18 11:46:17 AM UTC 24 |
| Finished | Sep 18 11:51:21 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152122499 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_a ccess_b2b.4152122499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.429527981 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1405152239 ps |
| CPU time | 5.32 seconds |
| Started | Sep 18 11:47:47 AM UTC 24 |
| Finished | Sep 18 11:47:54 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429527981 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.429527981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.356451274 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2950598202 ps |
| CPU time | 765.04 seconds |
| Started | Sep 18 11:47:07 AM UTC 24 |
| Finished | Sep 18 12:00:01 PM UTC 24 |
| Peak memory | 385288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356451274 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.356451274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.792908837 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1736048794 ps |
| CPU time | 8.79 seconds |
| Started | Sep 18 11:45:34 AM UTC 24 |
| Finished | Sep 18 11:45:44 AM UTC 24 |
| Peak memory | 219156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792908837 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.792908837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1175359864 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 428987752053 ps |
| CPU time | 3047.67 seconds |
| Started | Sep 18 11:48:12 AM UTC 24 |
| Finished | Sep 18 12:39:32 PM UTC 24 |
| Peak memory | 395292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11753598 64 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_a ll.1175359864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2120055691 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 866894660 ps |
| CPU time | 33.22 seconds |
| Started | Sep 18 11:48:10 AM UTC 24 |
| Finished | Sep 18 11:48:45 AM UTC 24 |
| Peak memory | 222780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120055691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2120055691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.2005903782 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 5258535017 ps |
| CPU time | 381.78 seconds |
| Started | Sep 18 11:46:08 AM UTC 24 |
| Finished | Sep 18 11:52:35 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005903782 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.2005903782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.850308352 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 912854182 ps |
| CPU time | 94.18 seconds |
| Started | Sep 18 11:46:33 AM UTC 24 |
| Finished | Sep 18 11:48:09 AM UTC 24 |
| Peak memory | 381136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =850308352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ throughput_w_partial_write.850308352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2786803529 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 10512225920 ps |
| CPU time | 196.68 seconds |
| Started | Sep 18 11:51:17 AM UTC 24 |
| Finished | Sep 18 11:54:37 AM UTC 24 |
| Peak memory | 387360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786803529 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_duri ng_key_req.2786803529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2394846622 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 40158435 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 11:53:03 AM UTC 24 |
| Finished | Sep 18 11:53:05 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394846622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.2394846622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1657304696 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 443527412567 ps |
| CPU time | 2971 seconds |
| Started | Sep 18 11:48:38 AM UTC 24 |
| Finished | Sep 18 12:38:42 PM UTC 24 |
| Peak memory | 214000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657304696 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.1657304696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2883893793 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5062012858 ps |
| CPU time | 547.65 seconds |
| Started | Sep 18 11:51:21 AM UTC 24 |
| Finished | Sep 18 12:00:36 PM UTC 24 |
| Peak memory | 387360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883893793 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.2883893793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3292060197 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 23025552981 ps |
| CPU time | 74.65 seconds |
| Started | Sep 18 11:51:08 AM UTC 24 |
| Finished | Sep 18 11:52:24 AM UTC 24 |
| Peak memory | 222568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292060197 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.3292060197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.329584933 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3114348977 ps |
| CPU time | 75.13 seconds |
| Started | Sep 18 11:50:35 AM UTC 24 |
| Finished | Sep 18 11:51:52 AM UTC 24 |
| Peak memory | 352464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 329584933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_m ax_throughput.329584933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1101810143 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 11426090191 ps |
| CPU time | 93.52 seconds |
| Started | Sep 18 11:52:30 AM UTC 24 |
| Finished | Sep 18 11:54:06 AM UTC 24 |
| Peak memory | 222868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101810143 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1101810143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1709708724 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 7159953874 ps |
| CPU time | 210.91 seconds |
| Started | Sep 18 11:52:25 AM UTC 24 |
| Finished | Sep 18 11:56:00 AM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709708724 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.1709708724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2148729386 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 37127329762 ps |
| CPU time | 793.52 seconds |
| Started | Sep 18 11:48:35 AM UTC 24 |
| Finished | Sep 18 12:01:57 PM UTC 24 |
| Peak memory | 389320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148729386 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.2148729386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3082035653 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2768519321 ps |
| CPU time | 66.82 seconds |
| Started | Sep 18 11:48:48 AM UTC 24 |
| Finished | Sep 18 11:49:56 AM UTC 24 |
| Peak memory | 336348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082035653 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3082035653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.217153746 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 13042556542 ps |
| CPU time | 370.08 seconds |
| Started | Sep 18 11:49:57 AM UTC 24 |
| Finished | Sep 18 11:56:12 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217153746 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_ac cess_b2b.217153746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1684692881 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1397199209 ps |
| CPU time | 5.73 seconds |
| Started | Sep 18 11:52:25 AM UTC 24 |
| Finished | Sep 18 11:52:32 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684692881 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1684692881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.3164823735 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1969801920 ps |
| CPU time | 591.29 seconds |
| Started | Sep 18 11:51:54 AM UTC 24 |
| Finished | Sep 18 12:01:52 PM UTC 24 |
| Peak memory | 389508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164823735 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3164823735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.47225997 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 437698418 ps |
| CPU time | 13.26 seconds |
| Started | Sep 18 11:48:23 AM UTC 24 |
| Finished | Sep 18 11:48:37 AM UTC 24 |
| Peak memory | 212404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47225997 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.47225997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3648558902 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 340512291165 ps |
| CPU time | 5547.91 seconds |
| Started | Sep 18 11:52:36 AM UTC 24 |
| Finished | Sep 18 01:26:03 PM UTC 24 |
| Peak memory | 391204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36485589 02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_a ll.3648558902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2050048658 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1187733288 ps |
| CPU time | 46.1 seconds |
| Started | Sep 18 11:52:32 AM UTC 24 |
| Finished | Sep 18 11:53:20 AM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050048658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2050048658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.717673352 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3987119540 ps |
| CPU time | 268.59 seconds |
| Started | Sep 18 11:48:46 AM UTC 24 |
| Finished | Sep 18 11:53:19 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717673352 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.717673352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3128711127 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3199231448 ps |
| CPU time | 84.13 seconds |
| Started | Sep 18 11:51:04 AM UTC 24 |
| Finished | Sep 18 11:52:30 AM UTC 24 |
| Peak memory | 358604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3128711127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _throughput_w_partial_write.3128711127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.923147103 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 177066592644 ps |
| CPU time | 904.48 seconds |
| Started | Sep 18 11:54:52 AM UTC 24 |
| Finished | Sep 18 12:10:06 PM UTC 24 |
| Peak memory | 387292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923147103 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_durin g_key_req.923147103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3282467016 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 12148043 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 11:56:23 AM UTC 24 |
| Finished | Sep 18 11:56:25 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282467016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3282467016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2478794119 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 230027982310 ps |
| CPU time | 2684.91 seconds |
| Started | Sep 18 11:53:16 AM UTC 24 |
| Finished | Sep 18 12:38:30 PM UTC 24 |
| Peak memory | 214016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478794119 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.2478794119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.4086113783 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 34941539553 ps |
| CPU time | 1325.34 seconds |
| Started | Sep 18 11:55:10 AM UTC 24 |
| Finished | Sep 18 12:17:30 PM UTC 24 |
| Peak memory | 391216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086113783 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.4086113783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3294872439 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3210229509 ps |
| CPU time | 22.9 seconds |
| Started | Sep 18 11:54:45 AM UTC 24 |
| Finished | Sep 18 11:55:09 AM UTC 24 |
| Peak memory | 212404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294872439 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.3294872439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2737950318 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 797135647 ps |
| CPU time | 88.08 seconds |
| Started | Sep 18 11:54:06 AM UTC 24 |
| Finished | Sep 18 11:55:36 AM UTC 24 |
| Peak memory | 381344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2737950318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ max_throughput.2737950318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3780084401 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 20727824081 ps |
| CPU time | 168.94 seconds |
| Started | Sep 18 11:55:47 AM UTC 24 |
| Finished | Sep 18 11:58:39 AM UTC 24 |
| Peak memory | 222628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780084401 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.3780084401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2162437224 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3945457696 ps |
| CPU time | 252.54 seconds |
| Started | Sep 18 11:55:46 AM UTC 24 |
| Finished | Sep 18 12:00:02 PM UTC 24 |
| Peak memory | 222700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162437224 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.2162437224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3434714928 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 56517772249 ps |
| CPU time | 573.45 seconds |
| Started | Sep 18 11:53:15 AM UTC 24 |
| Finished | Sep 18 12:02:56 PM UTC 24 |
| Peak memory | 374972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434714928 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.3434714928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2638573092 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1874811220 ps |
| CPU time | 41.71 seconds |
| Started | Sep 18 11:53:21 AM UTC 24 |
| Finished | Sep 18 11:54:04 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638573092 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.2638573092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1757511467 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 8469519604 ps |
| CPU time | 401.14 seconds |
| Started | Sep 18 11:54:05 AM UTC 24 |
| Finished | Sep 18 12:00:52 PM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757511467 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_a ccess_b2b.1757511467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1151740427 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 871810314 ps |
| CPU time | 6 seconds |
| Started | Sep 18 11:55:38 AM UTC 24 |
| Finished | Sep 18 11:55:45 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151740427 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1151740427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.770087814 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 15975966709 ps |
| CPU time | 601.5 seconds |
| Started | Sep 18 11:55:16 AM UTC 24 |
| Finished | Sep 18 12:05:25 PM UTC 24 |
| Peak memory | 383180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770087814 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.770087814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.113579481 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2143778640 ps |
| CPU time | 6.67 seconds |
| Started | Sep 18 11:53:06 AM UTC 24 |
| Finished | Sep 18 11:53:14 AM UTC 24 |
| Peak memory | 212576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113579481 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.113579481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.163948918 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 213968919103 ps |
| CPU time | 4364.26 seconds |
| Started | Sep 18 11:56:13 AM UTC 24 |
| Finished | Sep 18 01:09:42 PM UTC 24 |
| Peak memory | 388876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16394891 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.163948918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1657465551 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1641021326 ps |
| CPU time | 55.63 seconds |
| Started | Sep 18 11:56:00 AM UTC 24 |
| Finished | Sep 18 11:56:57 AM UTC 24 |
| Peak memory | 229592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657465551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1657465551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.22092593 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 10473839131 ps |
| CPU time | 235.93 seconds |
| Started | Sep 18 11:53:20 AM UTC 24 |
| Finished | Sep 18 11:57:19 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22092593 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.22092593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1936130946 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2118528041 ps |
| CPU time | 12.42 seconds |
| Started | Sep 18 11:54:38 AM UTC 24 |
| Finished | Sep 18 11:54:51 AM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1936130946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _throughput_w_partial_write.1936130946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3659234955 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 55563326972 ps |
| CPU time | 734.82 seconds |
| Started | Sep 18 11:58:11 AM UTC 24 |
| Finished | Sep 18 12:10:34 PM UTC 24 |
| Peak memory | 387292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659234955 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri ng_key_req.3659234955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2849567997 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 15469568 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 11:58:39 AM UTC 24 |
| Finished | Sep 18 11:58:41 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849567997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2849567997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.5443191 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 88843365727 ps |
| CPU time | 1739.33 seconds |
| Started | Sep 18 11:56:40 AM UTC 24 |
| Finished | Sep 18 12:25:59 PM UTC 24 |
| Peak memory | 214008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5443191 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.5443191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3550111130 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 30226766364 ps |
| CPU time | 1416.45 seconds |
| Started | Sep 18 11:58:26 AM UTC 24 |
| Finished | Sep 18 12:22:18 PM UTC 24 |
| Peak memory | 388912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550111130 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.3550111130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2259356232 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 6315514234 ps |
| CPU time | 72.18 seconds |
| Started | Sep 18 11:57:37 AM UTC 24 |
| Finished | Sep 18 11:58:51 AM UTC 24 |
| Peak memory | 222568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259356232 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2259356232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1063043419 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 790513139 ps |
| CPU time | 80.13 seconds |
| Started | Sep 18 11:57:13 AM UTC 24 |
| Finished | Sep 18 11:58:35 AM UTC 24 |
| Peak memory | 369056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1063043419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ max_throughput.1063043419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1782913675 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1474012943 ps |
| CPU time | 78.91 seconds |
| Started | Sep 18 11:58:35 AM UTC 24 |
| Finished | Sep 18 11:59:55 AM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782913675 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.1782913675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.4071306035 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 35913333846 ps |
| CPU time | 172.9 seconds |
| Started | Sep 18 11:58:29 AM UTC 24 |
| Finished | Sep 18 12:01:25 PM UTC 24 |
| Peak memory | 222692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071306035 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.4071306035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.462790898 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 6201212170 ps |
| CPU time | 106.4 seconds |
| Started | Sep 18 11:56:39 AM UTC 24 |
| Finished | Sep 18 11:58:27 AM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462790898 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.462790898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1529375716 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2034872924 ps |
| CPU time | 11.94 seconds |
| Started | Sep 18 11:56:59 AM UTC 24 |
| Finished | Sep 18 11:57:12 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529375716 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1529375716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.521019542 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 74007666788 ps |
| CPU time | 652.04 seconds |
| Started | Sep 18 11:57:12 AM UTC 24 |
| Finished | Sep 18 12:08:12 PM UTC 24 |
| Peak memory | 212404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521019542 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_ac cess_b2b.521019542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1707540911 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1605969588 ps |
| CPU time | 5.37 seconds |
| Started | Sep 18 11:58:28 AM UTC 24 |
| Finished | Sep 18 11:58:35 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707540911 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1707540911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.4053007247 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 14665180139 ps |
| CPU time | 1220.1 seconds |
| Started | Sep 18 11:58:28 AM UTC 24 |
| Finished | Sep 18 12:19:01 PM UTC 24 |
| Peak memory | 389328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053007247 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.4053007247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3826427438 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3039762782 ps |
| CPU time | 12.81 seconds |
| Started | Sep 18 11:56:26 AM UTC 24 |
| Finished | Sep 18 11:56:40 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826427438 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3826427438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1296261871 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 141021634504 ps |
| CPU time | 3162.78 seconds |
| Started | Sep 18 11:58:36 AM UTC 24 |
| Finished | Sep 18 12:51:52 PM UTC 24 |
| Peak memory | 390924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12962618 71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_a ll.1296261871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.77798442 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 35601969239 ps |
| CPU time | 270.43 seconds |
| Started | Sep 18 11:58:36 AM UTC 24 |
| Finished | Sep 18 12:03:10 PM UTC 24 |
| Peak memory | 393752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77798442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.77798442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.469187182 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 24454119508 ps |
| CPU time | 243.45 seconds |
| Started | Sep 18 11:56:55 AM UTC 24 |
| Finished | Sep 18 12:01:02 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469187182 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.469187182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1851849943 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1514468744 ps |
| CPU time | 66.23 seconds |
| Started | Sep 18 11:57:20 AM UTC 24 |
| Finished | Sep 18 11:58:28 AM UTC 24 |
| Peak memory | 338060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1851849943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _throughput_w_partial_write.1851849943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3326996906 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 24901646809 ps |
| CPU time | 290.33 seconds |
| Started | Sep 18 10:04:52 AM UTC 24 |
| Finished | Sep 18 10:09:46 AM UTC 24 |
| Peak memory | 385240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326996906 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin g_key_req.3326996906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2639679580 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 12756903 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 10:06:32 AM UTC 24 |
| Finished | Sep 18 10:06:34 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639679580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2639679580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.1328609031 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 110736258453 ps |
| CPU time | 1093.24 seconds |
| Started | Sep 18 10:04:01 AM UTC 24 |
| Finished | Sep 18 10:22:27 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328609031 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.1328609031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.414100732 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 27201433611 ps |
| CPU time | 386.8 seconds |
| Started | Sep 18 10:04:54 AM UTC 24 |
| Finished | Sep 18 10:11:26 AM UTC 24 |
| Peak memory | 360728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414100732 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.414100732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.867984223 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 14115288881 ps |
| CPU time | 37.34 seconds |
| Started | Sep 18 10:04:32 AM UTC 24 |
| Finished | Sep 18 10:05:10 AM UTC 24 |
| Peak memory | 278748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 867984223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ma x_throughput.867984223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2653782894 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 9349234940 ps |
| CPU time | 183.91 seconds |
| Started | Sep 18 10:05:27 AM UTC 24 |
| Finished | Sep 18 10:08:34 AM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653782894 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.2653782894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.175348592 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 71752755238 ps |
| CPU time | 381.56 seconds |
| Started | Sep 18 10:05:19 AM UTC 24 |
| Finished | Sep 18 10:11:46 AM UTC 24 |
| Peak memory | 222876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175348592 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.175348592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2116492930 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3839915390 ps |
| CPU time | 375.67 seconds |
| Started | Sep 18 10:04:01 AM UTC 24 |
| Finished | Sep 18 10:10:22 AM UTC 24 |
| Peak memory | 385300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116492930 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.2116492930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3305047860 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3207463258 ps |
| CPU time | 10.32 seconds |
| Started | Sep 18 10:04:16 AM UTC 24 |
| Finished | Sep 18 10:04:28 AM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305047860 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.3305047860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3823002241 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 10573020148 ps |
| CPU time | 151.75 seconds |
| Started | Sep 18 10:04:28 AM UTC 24 |
| Finished | Sep 18 10:07:03 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823002241 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_ac cess_b2b.3823002241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2995872824 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 720015067 ps |
| CPU time | 5.83 seconds |
| Started | Sep 18 10:05:11 AM UTC 24 |
| Finished | Sep 18 10:05:19 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995872824 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2995872824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.570552214 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 208172801 ps |
| CPU time | 3.77 seconds |
| Started | Sep 18 10:06:26 AM UTC 24 |
| Finished | Sep 18 10:06:30 AM UTC 24 |
| Peak memory | 248204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570552214 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.570552214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.142339009 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 14402744290 ps |
| CPU time | 54.88 seconds |
| Started | Sep 18 10:03:59 AM UTC 24 |
| Finished | Sep 18 10:04:56 AM UTC 24 |
| Peak memory | 305620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142339009 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.142339009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.847744991 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 72582974160 ps |
| CPU time | 2402.69 seconds |
| Started | Sep 18 10:05:48 AM UTC 24 |
| Finished | Sep 18 10:46:15 AM UTC 24 |
| Peak memory | 393052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84774499 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.847744991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1113618010 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2985044211 ps |
| CPU time | 62.45 seconds |
| Started | Sep 18 10:05:42 AM UTC 24 |
| Finished | Sep 18 10:06:46 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113618010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1113618010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.20188681 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 7257037427 ps |
| CPU time | 337.27 seconds |
| Started | Sep 18 10:04:09 AM UTC 24 |
| Finished | Sep 18 10:09:52 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20188681 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.20188681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3618016666 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2682456411 ps |
| CPU time | 13.22 seconds |
| Started | Sep 18 10:04:37 AM UTC 24 |
| Finished | Sep 18 10:04:51 AM UTC 24 |
| Peak memory | 222900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3618016666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ throughput_w_partial_write.3618016666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1555681452 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 84281427985 ps |
| CPU time | 1042.55 seconds |
| Started | Sep 18 12:00:26 PM UTC 24 |
| Finished | Sep 18 12:18:00 PM UTC 24 |
| Peak memory | 389380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555681452 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_duri ng_key_req.1555681452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.995059172 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 51307852 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 12:01:27 PM UTC 24 |
| Finished | Sep 18 12:01:29 PM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995059172 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.995059172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.1931167091 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 522064834072 ps |
| CPU time | 2086.34 seconds |
| Started | Sep 18 11:59:13 AM UTC 24 |
| Finished | Sep 18 12:34:23 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931167091 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.1931167091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.163822893 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 18869561271 ps |
| CPU time | 1047.6 seconds |
| Started | Sep 18 12:00:37 PM UTC 24 |
| Finished | Sep 18 12:18:17 PM UTC 24 |
| Peak memory | 385304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163822893 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.163822893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.183634200 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 36020928942 ps |
| CPU time | 50.95 seconds |
| Started | Sep 18 12:00:20 PM UTC 24 |
| Finished | Sep 18 12:01:13 PM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183634200 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.183634200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.1014436639 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 762463871 ps |
| CPU time | 62.87 seconds |
| Started | Sep 18 12:00:07 PM UTC 24 |
| Finished | Sep 18 12:01:11 PM UTC 24 |
| Peak memory | 362712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1014436639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ max_throughput.1014436639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.186358342 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 10180289038 ps |
| CPU time | 149.59 seconds |
| Started | Sep 18 12:01:04 PM UTC 24 |
| Finished | Sep 18 12:03:36 PM UTC 24 |
| Peak memory | 222636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186358342 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.186358342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2437125053 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 299773433780 ps |
| CPU time | 372.61 seconds |
| Started | Sep 18 12:01:02 PM UTC 24 |
| Finished | Sep 18 12:07:20 PM UTC 24 |
| Peak memory | 222620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437125053 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2437125053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.788548588 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 66205850529 ps |
| CPU time | 1159.07 seconds |
| Started | Sep 18 11:58:53 AM UTC 24 |
| Finished | Sep 18 12:18:25 PM UTC 24 |
| Peak memory | 387280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788548588 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.788548588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2046020725 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1394600074 ps |
| CPU time | 21.59 seconds |
| Started | Sep 18 11:59:56 AM UTC 24 |
| Finished | Sep 18 12:00:19 PM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046020725 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.2046020725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3433017656 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 7742249907 ps |
| CPU time | 492.86 seconds |
| Started | Sep 18 12:00:02 PM UTC 24 |
| Finished | Sep 18 12:08:25 PM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433017656 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_a ccess_b2b.3433017656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.31629195 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 352824235 ps |
| CPU time | 5.66 seconds |
| Started | Sep 18 12:00:54 PM UTC 24 |
| Finished | Sep 18 12:01:01 PM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31629195 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.31629195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2562524317 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 7699753509 ps |
| CPU time | 593.76 seconds |
| Started | Sep 18 12:00:53 PM UTC 24 |
| Finished | Sep 18 12:10:54 PM UTC 24 |
| Peak memory | 389392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562524317 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2562524317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.893626278 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1938503959 ps |
| CPU time | 28.36 seconds |
| Started | Sep 18 11:58:42 AM UTC 24 |
| Finished | Sep 18 11:59:12 AM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893626278 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.893626278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2440616602 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 33796626696 ps |
| CPU time | 2927.74 seconds |
| Started | Sep 18 12:01:14 PM UTC 24 |
| Finished | Sep 18 12:50:35 PM UTC 24 |
| Peak memory | 391264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24406166 02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_a ll.2440616602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.908749115 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 6915409608 ps |
| CPU time | 84.68 seconds |
| Started | Sep 18 12:01:12 PM UTC 24 |
| Finished | Sep 18 12:02:39 PM UTC 24 |
| Peak memory | 222704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908749115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.908749115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4148276744 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2944112806 ps |
| CPU time | 206.02 seconds |
| Started | Sep 18 11:59:23 AM UTC 24 |
| Finished | Sep 18 12:02:53 PM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148276744 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.4148276744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3483525184 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2884143013 ps |
| CPU time | 16.24 seconds |
| Started | Sep 18 12:00:08 PM UTC 24 |
| Finished | Sep 18 12:00:25 PM UTC 24 |
| Peak memory | 245964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3483525184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _throughput_w_partial_write.3483525184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2159594032 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 53112044347 ps |
| CPU time | 990.45 seconds |
| Started | Sep 18 12:03:14 PM UTC 24 |
| Finished | Sep 18 12:19:55 PM UTC 24 |
| Peak memory | 389596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159594032 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_duri ng_key_req.2159594032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.737752920 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 11877695 ps |
| CPU time | 1 seconds |
| Started | Sep 18 12:06:25 PM UTC 24 |
| Finished | Sep 18 12:06:27 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737752920 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.737752920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.3500776743 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 65716847691 ps |
| CPU time | 817.11 seconds |
| Started | Sep 18 12:01:53 PM UTC 24 |
| Finished | Sep 18 12:15:40 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500776743 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.3500776743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2348824807 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 33256078588 ps |
| CPU time | 394.02 seconds |
| Started | Sep 18 12:03:37 PM UTC 24 |
| Finished | Sep 18 12:10:17 PM UTC 24 |
| Peak memory | 381224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348824807 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.2348824807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.620589285 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 13891615078 ps |
| CPU time | 101.05 seconds |
| Started | Sep 18 12:03:12 PM UTC 24 |
| Finished | Sep 18 12:04:55 PM UTC 24 |
| Peak memory | 222884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620589285 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.620589285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1387224617 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 770954265 ps |
| CPU time | 47.52 seconds |
| Started | Sep 18 12:02:53 PM UTC 24 |
| Finished | Sep 18 12:03:42 PM UTC 24 |
| Peak memory | 317852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1387224617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ max_throughput.1387224617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.597482637 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2789647840 ps |
| CPU time | 104.38 seconds |
| Started | Sep 18 12:04:57 PM UTC 24 |
| Finished | Sep 18 12:06:43 PM UTC 24 |
| Peak memory | 222540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597482637 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.597482637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.3437666915 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 20691244287 ps |
| CPU time | 331.13 seconds |
| Started | Sep 18 12:03:59 PM UTC 24 |
| Finished | Sep 18 12:09:34 PM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437666915 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.3437666915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2237966559 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 16138826894 ps |
| CPU time | 623.93 seconds |
| Started | Sep 18 12:01:46 PM UTC 24 |
| Finished | Sep 18 12:12:18 PM UTC 24 |
| Peak memory | 360648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237966559 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2237966559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.820623771 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1638062050 ps |
| CPU time | 42.29 seconds |
| Started | Sep 18 12:02:29 PM UTC 24 |
| Finished | Sep 18 12:03:13 PM UTC 24 |
| Peak memory | 301264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820623771 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.820623771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1765153954 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 11108846923 ps |
| CPU time | 294.93 seconds |
| Started | Sep 18 12:02:40 PM UTC 24 |
| Finished | Sep 18 12:07:39 PM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765153954 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_a ccess_b2b.1765153954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4186435612 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2260526576 ps |
| CPU time | 5.66 seconds |
| Started | Sep 18 12:03:51 PM UTC 24 |
| Finished | Sep 18 12:03:58 PM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186435612 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4186435612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1762535124 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 8904517669 ps |
| CPU time | 840.07 seconds |
| Started | Sep 18 12:03:43 PM UTC 24 |
| Finished | Sep 18 12:17:54 PM UTC 24 |
| Peak memory | 379080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762535124 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1762535124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.510853732 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1446281506 ps |
| CPU time | 13.72 seconds |
| Started | Sep 18 12:01:30 PM UTC 24 |
| Finished | Sep 18 12:01:45 PM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510853732 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.510853732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.4181881100 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 108797214689 ps |
| CPU time | 2491.22 seconds |
| Started | Sep 18 12:05:59 PM UTC 24 |
| Finished | Sep 18 12:47:56 PM UTC 24 |
| Peak memory | 388892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41818811 00 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_a ll.4181881100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1482123817 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5105864323 ps |
| CPU time | 55.95 seconds |
| Started | Sep 18 12:05:26 PM UTC 24 |
| Finished | Sep 18 12:06:23 PM UTC 24 |
| Peak memory | 222708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482123817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1482123817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.278650417 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4391311546 ps |
| CPU time | 266.55 seconds |
| Started | Sep 18 12:01:59 PM UTC 24 |
| Finished | Sep 18 12:06:29 PM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278650417 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.278650417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.1340968735 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 763934341 ps |
| CPU time | 51.54 seconds |
| Started | Sep 18 12:02:56 PM UTC 24 |
| Finished | Sep 18 12:03:49 PM UTC 24 |
| Peak memory | 344276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1340968735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _throughput_w_partial_write.1340968735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1439538560 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 14482224024 ps |
| CPU time | 927.9 seconds |
| Started | Sep 18 12:08:14 PM UTC 24 |
| Finished | Sep 18 12:23:53 PM UTC 24 |
| Peak memory | 385224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439538560 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri ng_key_req.1439538560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2595344493 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 23631564 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 12:09:35 PM UTC 24 |
| Finished | Sep 18 12:09:38 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595344493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2595344493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1511900243 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 35595357196 ps |
| CPU time | 1103.47 seconds |
| Started | Sep 18 12:06:44 PM UTC 24 |
| Finished | Sep 18 12:25:20 PM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511900243 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.1511900243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.1100715313 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 25755179994 ps |
| CPU time | 954.23 seconds |
| Started | Sep 18 12:08:20 PM UTC 24 |
| Finished | Sep 18 12:24:25 PM UTC 24 |
| Peak memory | 389340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100715313 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.1100715313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1615302932 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 7840025185 ps |
| CPU time | 33.95 seconds |
| Started | Sep 18 12:08:13 PM UTC 24 |
| Finished | Sep 18 12:08:48 PM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615302932 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.1615302932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.870602655 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3154665944 ps |
| CPU time | 17.63 seconds |
| Started | Sep 18 12:07:40 PM UTC 24 |
| Finished | Sep 18 12:07:59 PM UTC 24 |
| Peak memory | 262428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 870602655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_m ax_throughput.870602655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3962950577 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2637214933 ps |
| CPU time | 99 seconds |
| Started | Sep 18 12:08:50 PM UTC 24 |
| Finished | Sep 18 12:10:31 PM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962950577 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.3962950577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.146219041 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 57919902342 ps |
| CPU time | 521.88 seconds |
| Started | Sep 18 12:08:33 PM UTC 24 |
| Finished | Sep 18 12:17:22 PM UTC 24 |
| Peak memory | 222628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146219041 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.146219041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2415808618 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 67201412239 ps |
| CPU time | 1363.74 seconds |
| Started | Sep 18 12:06:30 PM UTC 24 |
| Finished | Sep 18 12:29:29 PM UTC 24 |
| Peak memory | 383432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415808618 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.2415808618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.585953518 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3256530707 ps |
| CPU time | 48.91 seconds |
| Started | Sep 18 12:07:21 PM UTC 24 |
| Finished | Sep 18 12:08:11 PM UTC 24 |
| Peak memory | 330000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585953518 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.585953518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1641339161 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 37607878171 ps |
| CPU time | 648.8 seconds |
| Started | Sep 18 12:07:37 PM UTC 24 |
| Finished | Sep 18 12:18:34 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641339161 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_a ccess_b2b.1641339161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3183920692 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 358519169 ps |
| CPU time | 5.63 seconds |
| Started | Sep 18 12:08:26 PM UTC 24 |
| Finished | Sep 18 12:08:33 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183920692 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3183920692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2071830252 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 13297651830 ps |
| CPU time | 922.7 seconds |
| Started | Sep 18 12:08:24 PM UTC 24 |
| Finished | Sep 18 12:23:57 PM UTC 24 |
| Peak memory | 385300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071830252 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2071830252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4129538754 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 1196306763 ps |
| CPU time | 66.05 seconds |
| Started | Sep 18 12:06:28 PM UTC 24 |
| Finished | Sep 18 12:07:36 PM UTC 24 |
| Peak memory | 350352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129538754 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4129538754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.191434045 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 57367355319 ps |
| CPU time | 4304.56 seconds |
| Started | Sep 18 12:09:22 PM UTC 24 |
| Finished | Sep 18 01:21:54 PM UTC 24 |
| Peak memory | 391072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19143404 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.191434045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2975356878 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3106828493 ps |
| CPU time | 14.52 seconds |
| Started | Sep 18 12:09:06 PM UTC 24 |
| Finished | Sep 18 12:09:22 PM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975356878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2975356878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1823223611 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4879345047 ps |
| CPU time | 335.74 seconds |
| Started | Sep 18 12:07:15 PM UTC 24 |
| Finished | Sep 18 12:12:56 PM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823223611 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1823223611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1122398558 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3864149562 ps |
| CPU time | 17.56 seconds |
| Started | Sep 18 12:08:00 PM UTC 24 |
| Finished | Sep 18 12:08:19 PM UTC 24 |
| Peak memory | 248084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1122398558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl _throughput_w_partial_write.1122398558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.4050575346 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 13326480574 ps |
| CPU time | 565.56 seconds |
| Started | Sep 18 12:10:52 PM UTC 24 |
| Finished | Sep 18 12:20:25 PM UTC 24 |
| Peak memory | 385308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050575346 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_duri ng_key_req.4050575346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3299085349 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 16494216 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 12:14:13 PM UTC 24 |
| Finished | Sep 18 12:14:16 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299085349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3299085349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.390223254 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 168407894723 ps |
| CPU time | 863.99 seconds |
| Started | Sep 18 12:09:53 PM UTC 24 |
| Finished | Sep 18 12:24:27 PM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390223254 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.390223254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.2730976491 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 30970629666 ps |
| CPU time | 255.86 seconds |
| Started | Sep 18 12:10:55 PM UTC 24 |
| Finished | Sep 18 12:15:15 PM UTC 24 |
| Peak memory | 385316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730976491 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.2730976491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.3130803886 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 6498949067 ps |
| CPU time | 24.2 seconds |
| Started | Sep 18 12:10:45 PM UTC 24 |
| Finished | Sep 18 12:11:10 PM UTC 24 |
| Peak memory | 212404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130803886 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.3130803886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3861438807 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5498839669 ps |
| CPU time | 36.15 seconds |
| Started | Sep 18 12:10:32 PM UTC 24 |
| Finished | Sep 18 12:11:10 PM UTC 24 |
| Peak memory | 291024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3861438807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ max_throughput.3861438807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1135022969 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2689607019 ps |
| CPU time | 115.47 seconds |
| Started | Sep 18 12:12:20 PM UTC 24 |
| Finished | Sep 18 12:14:17 PM UTC 24 |
| Peak memory | 222704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135022969 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.1135022969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3436511724 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 6923245070 ps |
| CPU time | 171.04 seconds |
| Started | Sep 18 12:11:18 PM UTC 24 |
| Finished | Sep 18 12:14:12 PM UTC 24 |
| Peak memory | 222852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436511724 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3436511724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2804156705 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 29080443351 ps |
| CPU time | 416.08 seconds |
| Started | Sep 18 12:09:47 PM UTC 24 |
| Finished | Sep 18 12:16:48 PM UTC 24 |
| Peak memory | 389372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804156705 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.2804156705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2774557186 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 8127089155 ps |
| CPU time | 27.25 seconds |
| Started | Sep 18 12:10:16 PM UTC 24 |
| Finished | Sep 18 12:10:44 PM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774557186 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.2774557186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2934984149 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 33607488309 ps |
| CPU time | 420.18 seconds |
| Started | Sep 18 12:10:18 PM UTC 24 |
| Finished | Sep 18 12:17:23 PM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934984149 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_a ccess_b2b.2934984149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2439000115 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1689154572 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 12:11:12 PM UTC 24 |
| Finished | Sep 18 12:11:17 PM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439000115 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.2439000115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.2230856784 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 83578101946 ps |
| CPU time | 877.77 seconds |
| Started | Sep 18 12:11:10 PM UTC 24 |
| Finished | Sep 18 12:25:58 PM UTC 24 |
| Peak memory | 385300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230856784 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2230856784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1714409423 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4082347765 ps |
| CPU time | 12.12 seconds |
| Started | Sep 18 12:09:39 PM UTC 24 |
| Finished | Sep 18 12:09:52 PM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714409423 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1714409423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.4181447935 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 24937822393 ps |
| CPU time | 954.9 seconds |
| Started | Sep 18 12:13:54 PM UTC 24 |
| Finished | Sep 18 12:30:00 PM UTC 24 |
| Peak memory | 311504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41814479 35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_a ll.4181447935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.857430565 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 10252153249 ps |
| CPU time | 54.92 seconds |
| Started | Sep 18 12:12:57 PM UTC 24 |
| Finished | Sep 18 12:13:53 PM UTC 24 |
| Peak memory | 227064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857430565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.857430565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3939245696 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3417626635 ps |
| CPU time | 252.9 seconds |
| Started | Sep 18 12:10:06 PM UTC 24 |
| Finished | Sep 18 12:14:23 PM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939245696 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.3939245696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.841450972 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4537689900 ps |
| CPU time | 15.54 seconds |
| Started | Sep 18 12:10:34 PM UTC 24 |
| Finished | Sep 18 12:10:51 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =841450972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ throughput_w_partial_write.841450972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.162151993 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 27178544717 ps |
| CPU time | 775.04 seconds |
| Started | Sep 18 12:17:23 PM UTC 24 |
| Finished | Sep 18 12:30:28 PM UTC 24 |
| Peak memory | 385316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162151993 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_durin g_key_req.162151993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4271086930 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 31701985 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 12:18:04 PM UTC 24 |
| Finished | Sep 18 12:18:06 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271086930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.4271086930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.540264995 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 7189416319 ps |
| CPU time | 446.18 seconds |
| Started | Sep 18 12:14:24 PM UTC 24 |
| Finished | Sep 18 12:21:56 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540264995 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.540264995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.1526792607 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 39487270701 ps |
| CPU time | 334.74 seconds |
| Started | Sep 18 12:17:24 PM UTC 24 |
| Finished | Sep 18 12:23:04 PM UTC 24 |
| Peak memory | 385512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526792607 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.1526792607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2971605531 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 19371583270 ps |
| CPU time | 61.98 seconds |
| Started | Sep 18 12:16:59 PM UTC 24 |
| Finished | Sep 18 12:18:02 PM UTC 24 |
| Peak memory | 222832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971605531 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.2971605531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1866003940 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1538092477 ps |
| CPU time | 53.95 seconds |
| Started | Sep 18 12:16:40 PM UTC 24 |
| Finished | Sep 18 12:17:36 PM UTC 24 |
| Peak memory | 327896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1866003940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ max_throughput.1866003940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1223131610 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4925886380 ps |
| CPU time | 219.87 seconds |
| Started | Sep 18 12:17:54 PM UTC 24 |
| Finished | Sep 18 12:21:38 PM UTC 24 |
| Peak memory | 222812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223131610 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.1223131610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3128994146 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 20710821238 ps |
| CPU time | 464.29 seconds |
| Started | Sep 18 12:17:44 PM UTC 24 |
| Finished | Sep 18 12:25:35 PM UTC 24 |
| Peak memory | 222656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128994146 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.3128994146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.106287151 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 2633803003 ps |
| CPU time | 393.37 seconds |
| Started | Sep 18 12:14:19 PM UTC 24 |
| Finished | Sep 18 12:20:58 PM UTC 24 |
| Peak memory | 387220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106287151 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.106287151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1379770939 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 858931724 ps |
| CPU time | 98.36 seconds |
| Started | Sep 18 12:15:18 PM UTC 24 |
| Finished | Sep 18 12:16:58 PM UTC 24 |
| Peak memory | 366808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379770939 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.1379770939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.2904346229 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 62421505513 ps |
| CPU time | 482.93 seconds |
| Started | Sep 18 12:15:41 PM UTC 24 |
| Finished | Sep 18 12:23:50 PM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904346229 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_a ccess_b2b.2904346229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.913032661 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 595477871 ps |
| CPU time | 5.15 seconds |
| Started | Sep 18 12:17:37 PM UTC 24 |
| Finished | Sep 18 12:17:43 PM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913032661 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.913032661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3621903051 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 4721047081 ps |
| CPU time | 671.85 seconds |
| Started | Sep 18 12:17:31 PM UTC 24 |
| Finished | Sep 18 12:28:51 PM UTC 24 |
| Peak memory | 387352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621903051 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3621903051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.2939482719 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 767002385 ps |
| CPU time | 58.18 seconds |
| Started | Sep 18 12:14:17 PM UTC 24 |
| Finished | Sep 18 12:15:17 PM UTC 24 |
| Peak memory | 326040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939482719 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2939482719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1637622588 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 27154184995 ps |
| CPU time | 2008.09 seconds |
| Started | Sep 18 12:18:02 PM UTC 24 |
| Finished | Sep 18 12:51:50 PM UTC 24 |
| Peak memory | 399204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16376225 88 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a ll.1637622588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3432057653 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 215495001 ps |
| CPU time | 8.93 seconds |
| Started | Sep 18 12:17:54 PM UTC 24 |
| Finished | Sep 18 12:18:04 PM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432057653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3432057653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2842847019 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 20567912130 ps |
| CPU time | 373.81 seconds |
| Started | Sep 18 12:15:17 PM UTC 24 |
| Finished | Sep 18 12:21:35 PM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842847019 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.2842847019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2142791902 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1535278472 ps |
| CPU time | 62.14 seconds |
| Started | Sep 18 12:16:50 PM UTC 24 |
| Finished | Sep 18 12:17:53 PM UTC 24 |
| Peak memory | 336012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2142791902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _throughput_w_partial_write.2142791902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.828177791 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 20756835312 ps |
| CPU time | 553.76 seconds |
| Started | Sep 18 12:19:54 PM UTC 24 |
| Finished | Sep 18 12:29:14 PM UTC 24 |
| Peak memory | 389344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828177791 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_durin g_key_req.828177791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1177329152 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 16176812 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 12:21:55 PM UTC 24 |
| Finished | Sep 18 12:21:57 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177329152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1177329152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1369882173 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 7257707093 ps |
| CPU time | 558.64 seconds |
| Started | Sep 18 12:18:17 PM UTC 24 |
| Finished | Sep 18 12:27:43 PM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369882173 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.1369882173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3926725044 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 75034736573 ps |
| CPU time | 490.82 seconds |
| Started | Sep 18 12:19:56 PM UTC 24 |
| Finished | Sep 18 12:28:13 PM UTC 24 |
| Peak memory | 377320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926725044 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3926725044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2962134311 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 7771323041 ps |
| CPU time | 94.2 seconds |
| Started | Sep 18 12:19:14 PM UTC 24 |
| Finished | Sep 18 12:20:50 PM UTC 24 |
| Peak memory | 226640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962134311 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.2962134311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1048204292 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2078087210 ps |
| CPU time | 49.06 seconds |
| Started | Sep 18 12:19:02 PM UTC 24 |
| Finished | Sep 18 12:19:53 PM UTC 24 |
| Peak memory | 315612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1048204292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ max_throughput.1048204292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.789904992 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2952390397 ps |
| CPU time | 93.4 seconds |
| Started | Sep 18 12:21:00 PM UTC 24 |
| Finished | Sep 18 12:22:36 PM UTC 24 |
| Peak memory | 222596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789904992 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.789904992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2950844134 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 21337933093 ps |
| CPU time | 369.41 seconds |
| Started | Sep 18 12:20:59 PM UTC 24 |
| Finished | Sep 18 12:27:13 PM UTC 24 |
| Peak memory | 222640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950844134 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2950844134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1537933601 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 106691830532 ps |
| CPU time | 1171.16 seconds |
| Started | Sep 18 12:18:06 PM UTC 24 |
| Finished | Sep 18 12:37:51 PM UTC 24 |
| Peak memory | 389212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537933601 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.1537933601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2190604738 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3204993793 ps |
| CPU time | 26.26 seconds |
| Started | Sep 18 12:18:34 PM UTC 24 |
| Finished | Sep 18 12:19:01 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190604738 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.2190604738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2871562215 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 51351047509 ps |
| CPU time | 388.85 seconds |
| Started | Sep 18 12:18:35 PM UTC 24 |
| Finished | Sep 18 12:25:09 PM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871562215 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_a ccess_b2b.2871562215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1826438779 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 627140247 ps |
| CPU time | 5.98 seconds |
| Started | Sep 18 12:20:52 PM UTC 24 |
| Finished | Sep 18 12:20:59 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826438779 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1826438779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1332047527 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 32485194587 ps |
| CPU time | 359.93 seconds |
| Started | Sep 18 12:20:26 PM UTC 24 |
| Finished | Sep 18 12:26:31 PM UTC 24 |
| Peak memory | 358664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332047527 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1332047527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.3805306489 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2695457240 ps |
| CPU time | 26.57 seconds |
| Started | Sep 18 12:18:05 PM UTC 24 |
| Finished | Sep 18 12:18:33 PM UTC 24 |
| Peak memory | 288912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805306489 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3805306489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3813759801 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 429281135677 ps |
| CPU time | 5409.33 seconds |
| Started | Sep 18 12:21:39 PM UTC 24 |
| Finished | Sep 18 01:52:49 PM UTC 24 |
| Peak memory | 388888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38137598 01 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_a ll.3813759801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3511090185 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 245875685 ps |
| CPU time | 16.27 seconds |
| Started | Sep 18 12:21:36 PM UTC 24 |
| Finished | Sep 18 12:21:54 PM UTC 24 |
| Peak memory | 224956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511090185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3511090185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1356343982 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4027380669 ps |
| CPU time | 241.16 seconds |
| Started | Sep 18 12:18:27 PM UTC 24 |
| Finished | Sep 18 12:22:32 PM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356343982 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1356343982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.4222342134 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 680816404 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 12:19:03 PM UTC 24 |
| Finished | Sep 18 12:19:13 PM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4222342134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _throughput_w_partial_write.4222342134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.2104814599 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 59629111743 ps |
| CPU time | 1074.33 seconds |
| Started | Sep 18 12:23:44 PM UTC 24 |
| Finished | Sep 18 12:41:50 PM UTC 24 |
| Peak memory | 389824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104814599 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_duri ng_key_req.2104814599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2026521913 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 37218946 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 12:24:37 PM UTC 24 |
| Finished | Sep 18 12:24:39 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026521913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2026521913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.1223364987 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 424809714423 ps |
| CPU time | 1876.87 seconds |
| Started | Sep 18 12:22:06 PM UTC 24 |
| Finished | Sep 18 12:53:45 PM UTC 24 |
| Peak memory | 214004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223364987 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.1223364987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3938510540 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 18840140184 ps |
| CPU time | 972.58 seconds |
| Started | Sep 18 12:23:52 PM UTC 24 |
| Finished | Sep 18 12:40:15 PM UTC 24 |
| Peak memory | 387368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938510540 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.3938510540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.129118141 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 8101785822 ps |
| CPU time | 53.47 seconds |
| Started | Sep 18 12:23:08 PM UTC 24 |
| Finished | Sep 18 12:24:03 PM UTC 24 |
| Peak memory | 222692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129118141 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.129118141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.4248108801 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 791059692 ps |
| CPU time | 96.12 seconds |
| Started | Sep 18 12:22:58 PM UTC 24 |
| Finished | Sep 18 12:24:36 PM UTC 24 |
| Peak memory | 381080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4248108801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ max_throughput.4248108801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1852333970 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 9121836972 ps |
| CPU time | 174.63 seconds |
| Started | Sep 18 12:24:06 PM UTC 24 |
| Finished | Sep 18 12:27:03 PM UTC 24 |
| Peak memory | 222876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852333970 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.1852333970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4228218364 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 38518388097 ps |
| CPU time | 150.71 seconds |
| Started | Sep 18 12:24:04 PM UTC 24 |
| Finished | Sep 18 12:26:38 PM UTC 24 |
| Peak memory | 222912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228218364 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.4228218364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.183638481 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 14973528322 ps |
| CPU time | 1029.39 seconds |
| Started | Sep 18 12:21:57 PM UTC 24 |
| Finished | Sep 18 12:39:19 PM UTC 24 |
| Peak memory | 389488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183638481 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.183638481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3743377104 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 933604676 ps |
| CPU time | 32.83 seconds |
| Started | Sep 18 12:22:33 PM UTC 24 |
| Finished | Sep 18 12:23:07 PM UTC 24 |
| Peak memory | 299480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743377104 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.3743377104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2383517453 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 29555741667 ps |
| CPU time | 379.99 seconds |
| Started | Sep 18 12:22:37 PM UTC 24 |
| Finished | Sep 18 12:29:02 PM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383517453 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_a ccess_b2b.2383517453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4286234878 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1242826455 ps |
| CPU time | 5.17 seconds |
| Started | Sep 18 12:23:58 PM UTC 24 |
| Finished | Sep 18 12:24:04 PM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286234878 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.4286234878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3237771531 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 28192882334 ps |
| CPU time | 762.68 seconds |
| Started | Sep 18 12:23:54 PM UTC 24 |
| Finished | Sep 18 12:36:45 PM UTC 24 |
| Peak memory | 377108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237771531 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3237771531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1825266045 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 757776890 ps |
| CPU time | 58.32 seconds |
| Started | Sep 18 12:21:57 PM UTC 24 |
| Finished | Sep 18 12:22:57 PM UTC 24 |
| Peak memory | 346336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825266045 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1825266045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.652089937 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 64432393996 ps |
| CPU time | 3434.69 seconds |
| Started | Sep 18 12:24:28 PM UTC 24 |
| Finished | Sep 18 01:22:21 PM UTC 24 |
| Peak memory | 349980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65208993 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.652089937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2294224204 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 461481247 ps |
| CPU time | 20.78 seconds |
| Started | Sep 18 12:24:26 PM UTC 24 |
| Finished | Sep 18 12:24:48 PM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294224204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2294224204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2071132507 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3248065471 ps |
| CPU time | 288.36 seconds |
| Started | Sep 18 12:22:19 PM UTC 24 |
| Finished | Sep 18 12:27:12 PM UTC 24 |
| Peak memory | 212340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071132507 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.2071132507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2986202841 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 751291080 ps |
| CPU time | 36.25 seconds |
| Started | Sep 18 12:23:05 PM UTC 24 |
| Finished | Sep 18 12:23:43 PM UTC 24 |
| Peak memory | 295056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2986202841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _throughput_w_partial_write.2986202841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3081330040 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 74280966711 ps |
| CPU time | 237.8 seconds |
| Started | Sep 18 12:26:00 PM UTC 24 |
| Finished | Sep 18 12:30:02 PM UTC 24 |
| Peak memory | 350612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081330040 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_duri ng_key_req.3081330040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2249759432 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 17704712 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 12:27:14 PM UTC 24 |
| Finished | Sep 18 12:27:16 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249759432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2249759432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.2667435466 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 132471489330 ps |
| CPU time | 2425.87 seconds |
| Started | Sep 18 12:25:10 PM UTC 24 |
| Finished | Sep 18 01:06:03 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667435466 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.2667435466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2905517317 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 5971276530 ps |
| CPU time | 185.27 seconds |
| Started | Sep 18 12:26:17 PM UTC 24 |
| Finished | Sep 18 12:29:25 PM UTC 24 |
| Peak memory | 375076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905517317 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.2905517317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.791145072 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 8487892459 ps |
| CPU time | 106.11 seconds |
| Started | Sep 18 12:25:58 PM UTC 24 |
| Finished | Sep 18 12:27:46 PM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791145072 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.791145072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1415358927 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 1412486517 ps |
| CPU time | 24.2 seconds |
| Started | Sep 18 12:25:57 PM UTC 24 |
| Finished | Sep 18 12:26:22 PM UTC 24 |
| Peak memory | 280856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1415358927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ max_throughput.1415358927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2476996782 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2484225180 ps |
| CPU time | 173.66 seconds |
| Started | Sep 18 12:26:40 PM UTC 24 |
| Finished | Sep 18 12:29:37 PM UTC 24 |
| Peak memory | 222640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476996782 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.2476996782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2493421153 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 18155418171 ps |
| CPU time | 339.97 seconds |
| Started | Sep 18 12:26:39 PM UTC 24 |
| Finished | Sep 18 12:32:23 PM UTC 24 |
| Peak memory | 222888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493421153 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.2493421153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.959906071 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 3060088589 ps |
| CPU time | 194.46 seconds |
| Started | Sep 18 12:24:49 PM UTC 24 |
| Finished | Sep 18 12:28:07 PM UTC 24 |
| Peak memory | 334028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959906071 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.959906071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.1785208953 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 928735118 ps |
| CPU time | 19.75 seconds |
| Started | Sep 18 12:25:35 PM UTC 24 |
| Finished | Sep 18 12:25:56 PM UTC 24 |
| Peak memory | 212336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785208953 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.1785208953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2226891326 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 9531299218 ps |
| CPU time | 237.06 seconds |
| Started | Sep 18 12:25:50 PM UTC 24 |
| Finished | Sep 18 12:29:50 PM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226891326 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_a ccess_b2b.2226891326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.803776757 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3350731625 ps |
| CPU time | 5.64 seconds |
| Started | Sep 18 12:26:32 PM UTC 24 |
| Finished | Sep 18 12:26:39 PM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803776757 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.803776757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3329814454 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 11400439750 ps |
| CPU time | 725.71 seconds |
| Started | Sep 18 12:26:24 PM UTC 24 |
| Finished | Sep 18 12:38:40 PM UTC 24 |
| Peak memory | 389328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329814454 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3329814454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.646593154 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3789991463 ps |
| CPU time | 65.75 seconds |
| Started | Sep 18 12:24:41 PM UTC 24 |
| Finished | Sep 18 12:25:49 PM UTC 24 |
| Peak memory | 354772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646593154 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.646593154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.978691083 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 19554947309 ps |
| CPU time | 1493.6 seconds |
| Started | Sep 18 12:27:12 PM UTC 24 |
| Finished | Sep 18 12:52:22 PM UTC 24 |
| Peak memory | 390940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97869108 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.978691083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.772061105 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 245685930 ps |
| CPU time | 12.35 seconds |
| Started | Sep 18 12:27:04 PM UTC 24 |
| Finished | Sep 18 12:27:18 PM UTC 24 |
| Peak memory | 222584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772061105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.772061105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1151400418 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 13793471446 ps |
| CPU time | 242.08 seconds |
| Started | Sep 18 12:25:20 PM UTC 24 |
| Finished | Sep 18 12:29:26 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151400418 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.1151400418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.353391837 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2995220754 ps |
| CPU time | 18 seconds |
| Started | Sep 18 12:25:57 PM UTC 24 |
| Finished | Sep 18 12:26:16 PM UTC 24 |
| Peak memory | 286992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =353391837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ throughput_w_partial_write.353391837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4059460364 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 9584074362 ps |
| CPU time | 483.73 seconds |
| Started | Sep 18 12:28:52 PM UTC 24 |
| Finished | Sep 18 12:37:02 PM UTC 24 |
| Peak memory | 383240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059460364 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_duri ng_key_req.4059460364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1282818511 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 44514189 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 12:29:37 PM UTC 24 |
| Finished | Sep 18 12:29:40 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282818511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1282818511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.4077689151 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 73050163968 ps |
| CPU time | 988.87 seconds |
| Started | Sep 18 12:27:40 PM UTC 24 |
| Finished | Sep 18 12:44:21 PM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077689151 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.4077689151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.62156149 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 311759208377 ps |
| CPU time | 1349.2 seconds |
| Started | Sep 18 12:28:57 PM UTC 24 |
| Finished | Sep 18 12:51:42 PM UTC 24 |
| Peak memory | 390948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62156149 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.62156149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1060382090 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 26127360087 ps |
| CPU time | 141.01 seconds |
| Started | Sep 18 12:28:27 PM UTC 24 |
| Finished | Sep 18 12:30:51 PM UTC 24 |
| Peak memory | 222832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060382090 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.1060382090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.139982287 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4788967147 ps |
| CPU time | 11.21 seconds |
| Started | Sep 18 12:28:14 PM UTC 24 |
| Finished | Sep 18 12:28:27 PM UTC 24 |
| Peak memory | 226748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 139982287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_m ax_throughput.139982287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2483245075 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 9630006224 ps |
| CPU time | 91 seconds |
| Started | Sep 18 12:29:26 PM UTC 24 |
| Finished | Sep 18 12:30:59 PM UTC 24 |
| Peak memory | 222680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483245075 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2483245075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1163763742 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 10963622368 ps |
| CPU time | 145.94 seconds |
| Started | Sep 18 12:29:25 PM UTC 24 |
| Finished | Sep 18 12:31:53 PM UTC 24 |
| Peak memory | 222584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163763742 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.1163763742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1410952786 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 93586059956 ps |
| CPU time | 740.83 seconds |
| Started | Sep 18 12:27:19 PM UTC 24 |
| Finished | Sep 18 12:39:48 PM UTC 24 |
| Peak memory | 387532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410952786 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.1410952786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2510833032 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 14502640684 ps |
| CPU time | 37.49 seconds |
| Started | Sep 18 12:27:47 PM UTC 24 |
| Finished | Sep 18 12:28:27 PM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510833032 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.2510833032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1689020340 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 100410345230 ps |
| CPU time | 281.47 seconds |
| Started | Sep 18 12:28:08 PM UTC 24 |
| Finished | Sep 18 12:32:54 PM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689020340 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_a ccess_b2b.1689020340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.472023425 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2102682324 ps |
| CPU time | 6.94 seconds |
| Started | Sep 18 12:29:15 PM UTC 24 |
| Finished | Sep 18 12:29:24 PM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472023425 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.472023425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.3845961173 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 35939421565 ps |
| CPU time | 499.6 seconds |
| Started | Sep 18 12:29:02 PM UTC 24 |
| Finished | Sep 18 12:37:28 PM UTC 24 |
| Peak memory | 387356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845961173 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3845961173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.51771769 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 994670606 ps |
| CPU time | 20.51 seconds |
| Started | Sep 18 12:27:18 PM UTC 24 |
| Finished | Sep 18 12:27:39 PM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51771769 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.51771769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.356757910 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 1038774735845 ps |
| CPU time | 4671.83 seconds |
| Started | Sep 18 12:29:30 PM UTC 24 |
| Finished | Sep 18 01:48:14 PM UTC 24 |
| Peak memory | 315492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35675791 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.356757910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2823743825 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7190272796 ps |
| CPU time | 56.74 seconds |
| Started | Sep 18 12:29:27 PM UTC 24 |
| Finished | Sep 18 12:30:25 PM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823743825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2823743825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3123713383 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 13477263488 ps |
| CPU time | 349.42 seconds |
| Started | Sep 18 12:27:44 PM UTC 24 |
| Finished | Sep 18 12:33:39 PM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123713383 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.3123713383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.326554974 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 13831282527 ps |
| CPU time | 27.65 seconds |
| Started | Sep 18 12:28:27 PM UTC 24 |
| Finished | Sep 18 12:28:56 PM UTC 24 |
| Peak memory | 248080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =326554974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ throughput_w_partial_write.326554974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3331397746 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 11584670231 ps |
| CPU time | 247.46 seconds |
| Started | Sep 18 12:31:00 PM UTC 24 |
| Finished | Sep 18 12:35:12 PM UTC 24 |
| Peak memory | 385312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331397746 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_duri ng_key_req.3331397746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.367606618 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 15610711 ps |
| CPU time | 1 seconds |
| Started | Sep 18 12:33:38 PM UTC 24 |
| Finished | Sep 18 12:33:40 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367606618 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.367606618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.1587067122 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 165251062484 ps |
| CPU time | 2599.09 seconds |
| Started | Sep 18 12:30:01 PM UTC 24 |
| Finished | Sep 18 01:13:49 PM UTC 24 |
| Peak memory | 214008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587067122 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.1587067122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1310946121 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 23529093270 ps |
| CPU time | 906.4 seconds |
| Started | Sep 18 12:31:08 PM UTC 24 |
| Finished | Sep 18 12:46:25 PM UTC 24 |
| Peak memory | 389600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310946121 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1310946121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.351390617 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 59515389676 ps |
| CPU time | 220.01 seconds |
| Started | Sep 18 12:30:53 PM UTC 24 |
| Finished | Sep 18 12:34:36 PM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351390617 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.351390617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3809030551 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 790625659 ps |
| CPU time | 51.07 seconds |
| Started | Sep 18 12:30:29 PM UTC 24 |
| Finished | Sep 18 12:31:22 PM UTC 24 |
| Peak memory | 334296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3809030551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ max_throughput.3809030551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3682246059 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 5154946544 ps |
| CPU time | 153.32 seconds |
| Started | Sep 18 12:31:54 PM UTC 24 |
| Finished | Sep 18 12:34:30 PM UTC 24 |
| Peak memory | 222568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682246059 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.3682246059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.930627609 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 7893761789 ps |
| CPU time | 155.09 seconds |
| Started | Sep 18 12:31:31 PM UTC 24 |
| Finished | Sep 18 12:34:09 PM UTC 24 |
| Peak memory | 222588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930627609 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.930627609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1010664468 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 98379367680 ps |
| CPU time | 503.1 seconds |
| Started | Sep 18 12:29:51 PM UTC 24 |
| Finished | Sep 18 12:38:21 PM UTC 24 |
| Peak memory | 389388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010664468 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.1010664468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.952069489 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 817512963 ps |
| CPU time | 65.52 seconds |
| Started | Sep 18 12:30:06 PM UTC 24 |
| Finished | Sep 18 12:31:13 PM UTC 24 |
| Peak memory | 329848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952069489 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.952069489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.272942273 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 44976380791 ps |
| CPU time | 373.73 seconds |
| Started | Sep 18 12:30:27 PM UTC 24 |
| Finished | Sep 18 12:36:46 PM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272942273 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_ac cess_b2b.272942273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3634726447 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 343975810 ps |
| CPU time | 5.79 seconds |
| Started | Sep 18 12:31:23 PM UTC 24 |
| Finished | Sep 18 12:31:30 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634726447 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3634726447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2597045087 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 30802110497 ps |
| CPU time | 1072.58 seconds |
| Started | Sep 18 12:31:13 PM UTC 24 |
| Finished | Sep 18 12:49:18 PM UTC 24 |
| Peak memory | 387352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597045087 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2597045087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2664018470 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1721641601 ps |
| CPU time | 22.55 seconds |
| Started | Sep 18 12:29:41 PM UTC 24 |
| Finished | Sep 18 12:30:05 PM UTC 24 |
| Peak memory | 212608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664018470 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2664018470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1650631274 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 230108067046 ps |
| CPU time | 3233.32 seconds |
| Started | Sep 18 12:32:55 PM UTC 24 |
| Finished | Sep 18 01:27:23 PM UTC 24 |
| Peak memory | 390932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16506312 74 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_a ll.1650631274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1855235160 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2476483382 ps |
| CPU time | 70.65 seconds |
| Started | Sep 18 12:32:24 PM UTC 24 |
| Finished | Sep 18 12:33:37 PM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855235160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1855235160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3799215375 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 16626647121 ps |
| CPU time | 348.41 seconds |
| Started | Sep 18 12:30:02 PM UTC 24 |
| Finished | Sep 18 12:35:56 PM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799215375 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.3799215375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.924402449 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 730876934 ps |
| CPU time | 14.26 seconds |
| Started | Sep 18 12:30:52 PM UTC 24 |
| Finished | Sep 18 12:31:07 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =924402449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ throughput_w_partial_write.924402449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1849593592 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 15690189131 ps |
| CPU time | 898.25 seconds |
| Started | Sep 18 10:07:44 AM UTC 24 |
| Finished | Sep 18 10:22:52 AM UTC 24 |
| Peak memory | 385308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849593592 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin g_key_req.1849593592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3003458321 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 13156138 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 10:08:35 AM UTC 24 |
| Finished | Sep 18 10:08:37 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003458321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3003458321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.855882927 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 166423118593 ps |
| CPU time | 959.82 seconds |
| Started | Sep 18 10:06:46 AM UTC 24 |
| Finished | Sep 18 10:22:57 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855882927 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.855882927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3794390618 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 70899233789 ps |
| CPU time | 883.79 seconds |
| Started | Sep 18 10:07:45 AM UTC 24 |
| Finished | Sep 18 10:22:38 AM UTC 24 |
| Peak memory | 389400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794390618 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.3794390618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3077637107 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 10398892892 ps |
| CPU time | 77.91 seconds |
| Started | Sep 18 10:07:39 AM UTC 24 |
| Finished | Sep 18 10:08:58 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077637107 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.3077637107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1509865840 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2823900979 ps |
| CPU time | 15.65 seconds |
| Started | Sep 18 10:07:26 AM UTC 24 |
| Finished | Sep 18 10:07:43 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1509865840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_m ax_throughput.1509865840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1897258032 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 19945502377 ps |
| CPU time | 154.25 seconds |
| Started | Sep 18 10:07:57 AM UTC 24 |
| Finished | Sep 18 10:10:34 AM UTC 24 |
| Peak memory | 222684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897258032 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1897258032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.247534190 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 41336426530 ps |
| CPU time | 193.37 seconds |
| Started | Sep 18 10:07:54 AM UTC 24 |
| Finished | Sep 18 10:11:10 AM UTC 24 |
| Peak memory | 222684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247534190 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.247534190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3598453820 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 296972733909 ps |
| CPU time | 1113.38 seconds |
| Started | Sep 18 10:06:43 AM UTC 24 |
| Finished | Sep 18 10:25:28 AM UTC 24 |
| Peak memory | 391372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598453820 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.3598453820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.111132742 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1529426678 ps |
| CPU time | 32.19 seconds |
| Started | Sep 18 10:07:03 AM UTC 24 |
| Finished | Sep 18 10:07:37 AM UTC 24 |
| Peak memory | 212340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111132742 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.111132742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.4013136983 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 20514695497 ps |
| CPU time | 356.2 seconds |
| Started | Sep 18 10:07:25 AM UTC 24 |
| Finished | Sep 18 10:13:26 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013136983 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_ac cess_b2b.4013136983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2743992749 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 410249999 ps |
| CPU time | 4.23 seconds |
| Started | Sep 18 10:07:51 AM UTC 24 |
| Finished | Sep 18 10:07:56 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743992749 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2743992749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.428033804 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 59196447965 ps |
| CPU time | 1259.39 seconds |
| Started | Sep 18 10:07:51 AM UTC 24 |
| Finished | Sep 18 10:29:05 AM UTC 24 |
| Peak memory | 387352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428033804 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.428033804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.24085956 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1832845939 ps |
| CPU time | 83.78 seconds |
| Started | Sep 18 10:06:35 AM UTC 24 |
| Finished | Sep 18 10:08:00 AM UTC 24 |
| Peak memory | 370824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24085956 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.24085956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2712335747 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 451396273322 ps |
| CPU time | 3268.07 seconds |
| Started | Sep 18 10:08:01 AM UTC 24 |
| Finished | Sep 18 11:03:02 AM UTC 24 |
| Peak memory | 399112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27123357 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.2712335747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2462678732 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 872453889 ps |
| CPU time | 35.12 seconds |
| Started | Sep 18 10:07:59 AM UTC 24 |
| Finished | Sep 18 10:08:36 AM UTC 24 |
| Peak memory | 222640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462678732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2462678732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1687815898 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 22950796330 ps |
| CPU time | 213.51 seconds |
| Started | Sep 18 10:06:47 AM UTC 24 |
| Finished | Sep 18 10:10:24 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687815898 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.1687815898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1241451840 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1392216717 ps |
| CPU time | 14.49 seconds |
| Started | Sep 18 10:07:37 AM UTC 24 |
| Finished | Sep 18 10:07:53 AM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1241451840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ throughput_w_partial_write.1241451840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1233669355 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 14251751437 ps |
| CPU time | 786.92 seconds |
| Started | Sep 18 10:09:52 AM UTC 24 |
| Finished | Sep 18 10:23:07 AM UTC 24 |
| Peak memory | 389600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233669355 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_durin g_key_req.1233669355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3262281914 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 15235914 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 10:10:27 AM UTC 24 |
| Finished | Sep 18 10:10:29 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262281914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3262281914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3607726437 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 102619752591 ps |
| CPU time | 1528.47 seconds |
| Started | Sep 18 10:08:40 AM UTC 24 |
| Finished | Sep 18 10:34:26 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607726437 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.3607726437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1562743711 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 8397796073 ps |
| CPU time | 1178.08 seconds |
| Started | Sep 18 10:09:55 AM UTC 24 |
| Finished | Sep 18 10:29:48 AM UTC 24 |
| Peak memory | 389336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562743711 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.1562743711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2892772355 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 8354470849 ps |
| CPU time | 36.99 seconds |
| Started | Sep 18 10:09:47 AM UTC 24 |
| Finished | Sep 18 10:10:26 AM UTC 24 |
| Peak memory | 222904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892772355 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2892772355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3687040293 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 8783727518 ps |
| CPU time | 27.37 seconds |
| Started | Sep 18 10:09:09 AM UTC 24 |
| Finished | Sep 18 10:09:38 AM UTC 24 |
| Peak memory | 278736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3687040293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m ax_throughput.3687040293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1389181150 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1956381115 ps |
| CPU time | 82.08 seconds |
| Started | Sep 18 10:10:22 AM UTC 24 |
| Finished | Sep 18 10:11:46 AM UTC 24 |
| Peak memory | 222572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389181150 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.1389181150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2579567017 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 8208989180 ps |
| CPU time | 232.19 seconds |
| Started | Sep 18 10:10:14 AM UTC 24 |
| Finished | Sep 18 10:14:09 AM UTC 24 |
| Peak memory | 222620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579567017 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.2579567017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1989095462 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 10737668114 ps |
| CPU time | 448.45 seconds |
| Started | Sep 18 10:08:38 AM UTC 24 |
| Finished | Sep 18 10:16:11 AM UTC 24 |
| Peak memory | 366784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989095462 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.1989095462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2382255851 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1197670043 ps |
| CPU time | 7.5 seconds |
| Started | Sep 18 10:08:59 AM UTC 24 |
| Finished | Sep 18 10:09:08 AM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382255851 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.2382255851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2288843277 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 47555171163 ps |
| CPU time | 584.13 seconds |
| Started | Sep 18 10:09:01 AM UTC 24 |
| Finished | Sep 18 10:18:53 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288843277 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_ac cess_b2b.2288843277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1745822202 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 680817476 ps |
| CPU time | 4.53 seconds |
| Started | Sep 18 10:10:08 AM UTC 24 |
| Finished | Sep 18 10:10:13 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745822202 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1745822202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1162602891 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 8326296006 ps |
| CPU time | 1088.34 seconds |
| Started | Sep 18 10:10:06 AM UTC 24 |
| Finished | Sep 18 10:28:28 AM UTC 24 |
| Peak memory | 387352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162602891 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1162602891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1108244619 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1988235906 ps |
| CPU time | 21.85 seconds |
| Started | Sep 18 10:08:36 AM UTC 24 |
| Finished | Sep 18 10:08:59 AM UTC 24 |
| Peak memory | 256216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108244619 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1108244619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.669609358 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 794430561028 ps |
| CPU time | 4856.8 seconds |
| Started | Sep 18 10:10:25 AM UTC 24 |
| Finished | Sep 18 11:32:15 AM UTC 24 |
| Peak memory | 392928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66960935 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.669609358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.204476976 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3846017366 ps |
| CPU time | 51.38 seconds |
| Started | Sep 18 10:10:23 AM UTC 24 |
| Finished | Sep 18 10:11:16 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204476976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.204476976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2651424341 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 25157065295 ps |
| CPU time | 426.44 seconds |
| Started | Sep 18 10:08:42 AM UTC 24 |
| Finished | Sep 18 10:15:54 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651424341 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.2651424341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.446860310 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 7772993035 ps |
| CPU time | 102.02 seconds |
| Started | Sep 18 10:09:39 AM UTC 24 |
| Finished | Sep 18 10:11:23 AM UTC 24 |
| Peak memory | 375060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =446860310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_t hroughput_w_partial_write.446860310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3678086660 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 53418153566 ps |
| CPU time | 491.88 seconds |
| Started | Sep 18 10:11:30 AM UTC 24 |
| Finished | Sep 18 10:19:47 AM UTC 24 |
| Peak memory | 387360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678086660 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin g_key_req.3678086660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2640786318 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 13524105 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 10:12:16 AM UTC 24 |
| Finished | Sep 18 10:12:19 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640786318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2640786318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.496545056 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 93118897309 ps |
| CPU time | 697.33 seconds |
| Started | Sep 18 10:10:34 AM UTC 24 |
| Finished | Sep 18 10:22:21 AM UTC 24 |
| Peak memory | 212576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496545056 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.496545056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3186750929 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 15703228738 ps |
| CPU time | 53.6 seconds |
| Started | Sep 18 10:11:27 AM UTC 24 |
| Finished | Sep 18 10:12:22 AM UTC 24 |
| Peak memory | 222580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186750929 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3186750929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1324084615 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3027328625 ps |
| CPU time | 51.64 seconds |
| Started | Sep 18 10:11:17 AM UTC 24 |
| Finished | Sep 18 10:12:10 AM UTC 24 |
| Peak memory | 311580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1324084615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m ax_throughput.1324084615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2266841927 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5578299918 ps |
| CPU time | 199.31 seconds |
| Started | Sep 18 10:12:00 AM UTC 24 |
| Finished | Sep 18 10:15:23 AM UTC 24 |
| Peak memory | 229656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266841927 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.2266841927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2360023954 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2744869267 ps |
| CPU time | 132.58 seconds |
| Started | Sep 18 10:11:54 AM UTC 24 |
| Finished | Sep 18 10:14:09 AM UTC 24 |
| Peak memory | 222664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360023954 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.2360023954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2504370697 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 34140503707 ps |
| CPU time | 210.88 seconds |
| Started | Sep 18 10:10:32 AM UTC 24 |
| Finished | Sep 18 10:14:06 AM UTC 24 |
| Peak memory | 366796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504370697 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.2504370697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.293660304 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5165308620 ps |
| CPU time | 29.54 seconds |
| Started | Sep 18 10:10:58 AM UTC 24 |
| Finished | Sep 18 10:11:29 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293660304 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.293660304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3498890267 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 25309643191 ps |
| CPU time | 494.62 seconds |
| Started | Sep 18 10:11:11 AM UTC 24 |
| Finished | Sep 18 10:19:33 AM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498890267 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_ac cess_b2b.3498890267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3597347289 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 743317878 ps |
| CPU time | 5.65 seconds |
| Started | Sep 18 10:11:47 AM UTC 24 |
| Finished | Sep 18 10:11:54 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597347289 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3597347289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.1856296537 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 9037011382 ps |
| CPU time | 766.2 seconds |
| Started | Sep 18 10:11:47 AM UTC 24 |
| Finished | Sep 18 10:24:42 AM UTC 24 |
| Peak memory | 387540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856296537 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1856296537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1477313854 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2071265152 ps |
| CPU time | 25.91 seconds |
| Started | Sep 18 10:10:30 AM UTC 24 |
| Finished | Sep 18 10:10:57 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477313854 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1477313854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4006266038 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 62403508280 ps |
| CPU time | 6289.51 seconds |
| Started | Sep 18 10:12:10 AM UTC 24 |
| Finished | Sep 18 11:58:09 AM UTC 24 |
| Peak memory | 390932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40062660 38 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.4006266038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1543868598 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 802268015 ps |
| CPU time | 11.83 seconds |
| Started | Sep 18 10:12:02 AM UTC 24 |
| Finished | Sep 18 10:12:15 AM UTC 24 |
| Peak memory | 224760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543868598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1543868598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1616653351 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3126547365 ps |
| CPU time | 232.11 seconds |
| Started | Sep 18 10:10:38 AM UTC 24 |
| Finished | Sep 18 10:14:34 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616653351 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.1616653351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3047073835 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 781869143 ps |
| CPU time | 35.02 seconds |
| Started | Sep 18 10:11:25 AM UTC 24 |
| Finished | Sep 18 10:12:01 AM UTC 24 |
| Peak memory | 287124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3047073835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ throughput_w_partial_write.3047073835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.302439909 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 25881852878 ps |
| CPU time | 524.14 seconds |
| Started | Sep 18 10:14:10 AM UTC 24 |
| Finished | Sep 18 10:23:01 AM UTC 24 |
| Peak memory | 352284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302439909 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during _key_req.302439909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4098408853 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 41689726 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 10:15:23 AM UTC 24 |
| Finished | Sep 18 10:15:26 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098408853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.4098408853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1287487221 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 64599697649 ps |
| CPU time | 1759.86 seconds |
| Started | Sep 18 10:12:33 AM UTC 24 |
| Finished | Sep 18 10:42:14 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287487221 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.1287487221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3918865914 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 107086731010 ps |
| CPU time | 1281.66 seconds |
| Started | Sep 18 10:14:10 AM UTC 24 |
| Finished | Sep 18 10:35:46 AM UTC 24 |
| Peak memory | 385448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918865914 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3918865914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1373015288 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 16613590606 ps |
| CPU time | 53.2 seconds |
| Started | Sep 18 10:14:06 AM UTC 24 |
| Finished | Sep 18 10:15:01 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373015288 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.1373015288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3054823043 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1473532101 ps |
| CPU time | 67.74 seconds |
| Started | Sep 18 10:13:57 AM UTC 24 |
| Finished | Sep 18 10:15:07 AM UTC 24 |
| Peak memory | 327824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3054823043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m ax_throughput.3054823043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2693725587 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 6373354894 ps |
| CPU time | 192.43 seconds |
| Started | Sep 18 10:15:02 AM UTC 24 |
| Finished | Sep 18 10:18:18 AM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693725587 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.2693725587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3679061756 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5977466366 ps |
| CPU time | 138.98 seconds |
| Started | Sep 18 10:14:42 AM UTC 24 |
| Finished | Sep 18 10:17:03 AM UTC 24 |
| Peak memory | 222600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679061756 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3679061756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.278802305 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 47174877386 ps |
| CPU time | 1510.58 seconds |
| Started | Sep 18 10:12:23 AM UTC 24 |
| Finished | Sep 18 10:37:49 AM UTC 24 |
| Peak memory | 389596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278802305 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.278802305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3153216945 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2779473980 ps |
| CPU time | 53.33 seconds |
| Started | Sep 18 10:13:27 AM UTC 24 |
| Finished | Sep 18 10:14:22 AM UTC 24 |
| Peak memory | 309452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153216945 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3153216945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.65651748 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 20946214228 ps |
| CPU time | 616.49 seconds |
| Started | Sep 18 10:13:42 AM UTC 24 |
| Finished | Sep 18 10:24:06 AM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65651748 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce ss_b2b.65651748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3834879972 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1410539805 ps |
| CPU time | 5.01 seconds |
| Started | Sep 18 10:14:35 AM UTC 24 |
| Finished | Sep 18 10:14:41 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834879972 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3834879972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.265324548 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11663053875 ps |
| CPU time | 369.85 seconds |
| Started | Sep 18 10:14:23 AM UTC 24 |
| Finished | Sep 18 10:20:37 AM UTC 24 |
| Peak memory | 375120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265324548 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.265324548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1671093107 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1753584263 ps |
| CPU time | 10.7 seconds |
| Started | Sep 18 10:12:20 AM UTC 24 |
| Finished | Sep 18 10:12:32 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671093107 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1671093107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.4013831773 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 93464524052 ps |
| CPU time | 2790.55 seconds |
| Started | Sep 18 10:15:08 AM UTC 24 |
| Finished | Sep 18 11:02:08 AM UTC 24 |
| Peak memory | 378684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40138317 73 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.4013831773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2112627468 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 456924620 ps |
| CPU time | 21.56 seconds |
| Started | Sep 18 10:15:04 AM UTC 24 |
| Finished | Sep 18 10:15:27 AM UTC 24 |
| Peak memory | 222640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112627468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2112627468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.604729387 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 10316517276 ps |
| CPU time | 314.26 seconds |
| Started | Sep 18 10:12:39 AM UTC 24 |
| Finished | Sep 18 10:17:58 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604729387 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.604729387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3918024223 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 785003358 ps |
| CPU time | 62.75 seconds |
| Started | Sep 18 10:13:59 AM UTC 24 |
| Finished | Sep 18 10:15:04 AM UTC 24 |
| Peak memory | 381136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3918024223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ throughput_w_partial_write.3918024223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2456271073 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 15139308983 ps |
| CPU time | 494.02 seconds |
| Started | Sep 18 10:17:15 AM UTC 24 |
| Finished | Sep 18 10:25:36 AM UTC 24 |
| Peak memory | 387288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456271073 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin g_key_req.2456271073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.138432928 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 34773136 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 10:19:28 AM UTC 24 |
| Finished | Sep 18 10:19:29 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138432928 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.138432928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3429310851 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 91173287055 ps |
| CPU time | 2136.38 seconds |
| Started | Sep 18 10:15:41 AM UTC 24 |
| Finished | Sep 18 10:51:41 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429310851 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.3429310851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.117771455 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 88070124099 ps |
| CPU time | 1037.22 seconds |
| Started | Sep 18 10:17:59 AM UTC 24 |
| Finished | Sep 18 10:35:28 AM UTC 24 |
| Peak memory | 387268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117771455 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.117771455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2483545560 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2953928794 ps |
| CPU time | 96.5 seconds |
| Started | Sep 18 10:16:26 AM UTC 24 |
| Finished | Sep 18 10:18:05 AM UTC 24 |
| Peak memory | 383236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2483545560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_m ax_throughput.2483545560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.758142093 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 19003303019 ps |
| CPU time | 140.99 seconds |
| Started | Sep 18 10:18:27 AM UTC 24 |
| Finished | Sep 18 10:20:51 AM UTC 24 |
| Peak memory | 222704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758142093 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.758142093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3936148294 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 10516593985 ps |
| CPU time | 164.01 seconds |
| Started | Sep 18 10:18:24 AM UTC 24 |
| Finished | Sep 18 10:21:11 AM UTC 24 |
| Peak memory | 222916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936148294 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.3936148294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3567702280 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 62983780585 ps |
| CPU time | 947.45 seconds |
| Started | Sep 18 10:15:27 AM UTC 24 |
| Finished | Sep 18 10:31:25 AM UTC 24 |
| Peak memory | 379088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567702280 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3567702280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1775439048 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1651411207 ps |
| CPU time | 12.03 seconds |
| Started | Sep 18 10:16:12 AM UTC 24 |
| Finished | Sep 18 10:16:25 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775439048 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.1775439048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1958286100 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 50464189901 ps |
| CPU time | 365.65 seconds |
| Started | Sep 18 10:16:12 AM UTC 24 |
| Finished | Sep 18 10:22:22 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958286100 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_ac cess_b2b.1958286100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3181318582 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1408578332 ps |
| CPU time | 6.59 seconds |
| Started | Sep 18 10:18:19 AM UTC 24 |
| Finished | Sep 18 10:18:27 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181318582 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3181318582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2852870832 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 47817403677 ps |
| CPU time | 393.47 seconds |
| Started | Sep 18 10:18:06 AM UTC 24 |
| Finished | Sep 18 10:24:44 AM UTC 24 |
| Peak memory | 383256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852870832 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2852870832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.3054361116 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1472793269 ps |
| CPU time | 12.27 seconds |
| Started | Sep 18 10:15:26 AM UTC 24 |
| Finished | Sep 18 10:15:40 AM UTC 24 |
| Peak memory | 212648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054361116 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3054361116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4027071539 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 2212455757597 ps |
| CPU time | 9740.42 seconds |
| Started | Sep 18 10:19:27 AM UTC 24 |
| Finished | Sep 18 01:03:31 PM UTC 24 |
| Peak memory | 390932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40270715 39 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.4027071539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1845718697 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3285763056 ps |
| CPU time | 30.94 seconds |
| Started | Sep 18 10:18:54 AM UTC 24 |
| Finished | Sep 18 10:19:27 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845718697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1845718697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3391123389 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 10609144570 ps |
| CPU time | 208.96 seconds |
| Started | Sep 18 10:15:55 AM UTC 24 |
| Finished | Sep 18 10:19:27 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391123389 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.3391123389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1769841796 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 11103812652 ps |
| CPU time | 13.73 seconds |
| Started | Sep 18 10:16:59 AM UTC 24 |
| Finished | Sep 18 10:17:14 AM UTC 24 |
| Peak memory | 222556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1769841796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ throughput_w_partial_write.1769841796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |