SRAM_CTRL/RET Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.432m	568.389us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.800s	13.374us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	14.500us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.760s	73.155us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	19.153us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.530s	48.164us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	14.500us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	19.153us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.020s	5.034ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.930s	239.196us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	28.614m	78.298ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.617m	8.975ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.270m	18.661ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.716m	11.904ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	19.510s	2.404ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.550m	10.564ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.252m	6.960ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.625m	78.223ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.026m	543.748us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.125m	166.071us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.600m	8.120ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.420s	44.414us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.351h	14.379ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.700s	12.988us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.690s	50.544us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.690s	50.544us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.800s	13.374us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	14.500us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	19.153us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	17.281us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.800s	13.374us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	14.500us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	19.153us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	17.281us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.250s	431.689us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.340s	334.266us	5	5	100.00
		sram_ctrl_tl_intg_err	2.600s	285.155us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.340s	334.266us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	285.155us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.600m	8.120ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	14.500us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.550m	10.564ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.550m	10.564ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.550m	10.564ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	19.510s	2.404ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.250s	431.689us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.432m	568.389us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.432m	568.389us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.550m	10.564ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.340s	334.266us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	19.510s	2.404ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.340s	334.266us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.340s	334.266us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.432m	568.389us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.340s	334.266us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.754h	10.556ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:

Test sram_ctrl_stress_all has 1 failures.

2.sram_ctrl_stress_all.3084229250
Line 376, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 428247999241 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x7c1e5545
  UVM_INFO @ 428247999241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sram_ctrl_executable has 1 failures.

5.sram_ctrl_executable.3917320508
Line 253, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest/run.log

  UVM_FATAL @ 28237860150 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x1d9722bb
  UVM_INFO @ 28237860150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 22.sram_ctrl_multiple_keys.1948082644
    Line 269, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 89584851088 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xbfe90de8
  UVM_INFO @ 89584851088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```