SRAM_CTRL/RET Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.872m	820.910us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	15.906us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.670s	12.973us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.840s	415.725us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	13.628us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.210s	43.614us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.670s	12.973us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	13.628us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.930s	2.735ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.050s	1.247ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	19.128m	26.287ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.902m	3.732ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.471m	13.297ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.417m	8.968ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.630s	942.747us	43	50	86.00
V2	executable	sram_ctrl_executable	30.889m	17.487ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.239m	666.017us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.315m	107.690ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.784m	537.795us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.109m	279.671us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.551m	19.166ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.410s	71.282us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.375h	379.690ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.730s	13.642us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.770s	478.072us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.770s	478.072us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	15.906us	5	5	100.00
		sram_ctrl_csr_rw	0.670s	12.973us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	13.628us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	88.009us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	15.906us	5	5	100.00
		sram_ctrl_csr_rw	0.670s	12.973us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	13.628us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	88.009us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	11.770s	7.591ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.120s	314.066us	5	5	100.00
		sram_ctrl_tl_intg_err	2.650s	1.051ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.120s	314.066us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.650s	1.051ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.551m	19.166ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.670s	12.973us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.889m	17.487ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.889m	17.487ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.889m	17.487ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.630s	942.747us	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	11.770s	7.591ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.872m	820.910us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.872m	820.910us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.889m	17.487ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.120s	314.066us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.630s	942.747us	43	50	86.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.120s	314.066us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.120s	314.066us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.872m	820.910us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.120s	314.066us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.569h	31.721ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1025	1040	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	100.00	98.13	100.00	100.00	99.71	99.70	100.00

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:369) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 13 failures:

Test sram_ctrl_stress_all has 6 failures.

2.sram_ctrl_stress_all.45595957515525737401305276074893308689559020666899884881259918248618910831791
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @  25528915 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @  25528915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.sram_ctrl_stress_all.42213511344218685874892992617307217736585768669714563507595552051025209674594
Line 332, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2485917230 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 2485917230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test sram_ctrl_lc_escalation has 7 failures.

18.sram_ctrl_lc_escalation.73540004156802433676712630344608900990943256221586267726353083007697497380618
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 505992629 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 505992629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sram_ctrl_lc_escalation.109225504032005843555363639813347885084958982845571642877229670631530807514829
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 306793881 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 306793881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 14.sram_ctrl_regwen.26799698297743501715252402988821937418834854354043752311593836751048497105925
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 49628546931 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x9a3dc1aa
  UVM_INFO @ 49628546931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 18.sram_ctrl_executable.53836713722491712107979064340609200811949027182901158854359881925905784076879
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 32745732371 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xd4beac77
  UVM_INFO @ 32745732371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```