Unified Coverage Report :: Module :: prim_ram_1p_adv

Module : prim_ram_1p_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	106	3	0	0.00
CONT_ASSIGN	113	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	117	1	0	0.00
CONT_ASSIGN	118	0	0
CONT_ASSIGN	210	1	0	0.00
CONT_ASSIGN	211	1	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	244	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	266	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
106	0	1
107	0	1
109	0	1
113	0	1
114	0	1
115	0	1
116	0	1
117	0	1
118		unreachable
210	0	1
211	0	1
213	0	1
217	0	1
241	0	1
242	0	1
243	0	1
244	0	1
245	0	1
263	0	1
264	0	1
266		unreachable

---

Cond Coverage for Module : prim_ram_1p_adv

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       109
 EXPRESSION (req_q & ((~write_q)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	106	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	106	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered