Unified Coverage Report :: Module :: prim_ram_1p_scr

Module : prim_ram_1p_scr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.94	0.00	0.00	95.76		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_addr_scr.u_prim_subst_perm	0.00	0.00
gen_diffuse_data[0].u_prim_subst_perm_dec	0.00	0.00
gen_diffuse_data[0].u_prim_subst_perm_enc	0.00	0.00
gen_par_scr[0].u_prim_prince	0.00			0.00
u_intg_error	0.00	0.00
u_prim_ram_1p_adv	0.00	0.00	0.00			0.00

Line Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		53	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	121	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	184	1	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	219	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	300	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
ALWAYS	315	10	0	0.00
ALWAYS	343	26	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	0	1
114	0	1
115	0	1
121	0	1
131	0	1
134	0	1
137	0	1
145	0	1
150	0	1
171	0	1
184	0	1
213	0	1
219	0	1
245	0	1
275	0	1
300	0	1
309	0	1
315	0	1
316	0	1
318	0	1
319	0	1
322	0	1
323	0	1
324	0	1
325	0	1
327	0	1
333	0	1
			==> MISSING_ELSE
343	0	1
344	0	1
345	0	1
346	0	1
347	0	1
348	0	1
349	0	1
350	0	1
351	0	1
352	0	1
353	0	1
354	0	1
356	0	1
357	0	1
358	0	1
359	0	1
360	0	1
362	0	1
363	0	1
			==> MISSING_ELSE
365	0	1
366	0	1
367	0	1
368	0	1
369	0	1
			==> MISSING_ELSE
371	0	1
372	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_ram_1p_scr

	Total	Covered	Percent
Conditions	47	0	0.00
Logical	47	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       114
 EXPRESSION (gnt_o & ((~write_i)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       115
 EXPRESSION (gnt_o & write_i)
             --1--   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       121
 EXPRESSION (read_en & (write_en_q | write_pending_q) & (addr_scr == waddr_scr_q))
             ---1---   ---------------2--------------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       121
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       121
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       131
 EXPRESSION (((~intg_error_w_q)) & ((~intg_error_buf)) & (read_en | write_en_q | write_pending_q))
             ---------1---------   ---------2---------   --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       131
 SUB-EXPRESSION (read_en | write_en_q | write_pending_q)
                 ---1---   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       134
 EXPRESSION ((write_en_q | write_pending_q) & ((~read_en)) & ((~intg_error_w_q)))
             ---------------1--------------   ------2-----   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       134
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       137
 EXPRESSION (write_en_q & read_en)
             -----1----   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (read_en ? addr_scr : waddr_scr_q)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       300
 EXPRESSION (macro_write ? 1'b0 : (rw_collision ? 1'b1 : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       300
 SUB-EXPRESSION (rw_collision ? 1'b1 : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 EXPRESSION (write_pending_q ? wdata_scr_q : wdata_scr_d)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (((!intg_error_r_q)) && rvalid_q)
             ---------1---------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		17	0	0.00
TERNARY	145	2	0	0.00
TERNARY	300	3	0	0.00
TERNARY	309	2	0	0.00
IF	318	3	0	0.00
IF	343	7	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	145	(read_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	300	(macro_write) ? 
-2-:	300	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	309	(write_pending_q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	318	if (((!intg_error_r_q) && rvalid_q))
-2-:	322	if (addr_collision_q)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	343	if ((!rst_ni))
-2-:	362	if (read_en)
-3-:	365	if (write_en_d)
-4-:	371	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	-	-	Not Covered
0	-	1	-	Not Covered
0	-	0	-	Not Covered
0	-	-	1	Not Covered
0	-	-	0	Not Covered

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		52	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	121	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	184	1	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	219	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	300	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
ALWAYS	315	9	0	0.00
ALWAYS	343	26	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	0	1
114	0	1
115	0	1
121	0	1
131	0	1
134	0	1
137	0	1
145	0	1
150	0	1
171	0	1
184	0	1
213	0	1
219	0	1
245	0	1
275	0	1
300	0	1
309	0	1
315	0	1
316	0	1
318	0	1
319	0	1
322	0	1
323	0	1
324	0	1
325	0	1
327		excluded
			Exclude Annotation: VC_COV_UNR
333	0	1
			==> MISSING_ELSE
343	0	1
344	0	1
345	0	1
346	0	1
347	0	1
348	0	1
349	0	1
350	0	1
351	0	1
352	0	1
353	0	1
354	0	1
356	0	1
357	0	1
358	0	1
359	0	1
360	0	1
362	0	1
363	0	1
			==> MISSING_ELSE
365	0	1
366	0	1
367	0	1
368	0	1
369	0	1
			==> MISSING_ELSE
371	0	1
372	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Total	Covered	Percent
Conditions	47	0	0.00
Logical	47	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       114
 EXPRESSION (gnt_o & ((~write_i)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       115
 EXPRESSION (gnt_o & write_i)
             --1--   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       121
 EXPRESSION (read_en & (write_en_q | write_pending_q) & (addr_scr == waddr_scr_q))
             ---1---   ---------------2--------------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       121
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       121
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       131
 EXPRESSION (((~intg_error_w_q)) & ((~intg_error_buf)) & (read_en | write_en_q | write_pending_q))
             ---------1---------   ---------2---------   --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       131
 SUB-EXPRESSION (read_en | write_en_q | write_pending_q)
                 ---1---   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       134
 EXPRESSION ((write_en_q | write_pending_q) & ((~read_en)) & ((~intg_error_w_q)))
             ---------------1--------------   ------2-----   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       134
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       137
 EXPRESSION (write_en_q & read_en)
             -----1----   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (read_en ? addr_scr : waddr_scr_q)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       300
 EXPRESSION (macro_write ? 1'b0 : (rw_collision ? 1'b1 : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       300
 SUB-EXPRESSION (rw_collision ? 1'b1 : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       309
 EXPRESSION (write_pending_q ? wdata_scr_q : wdata_scr_d)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (((!intg_error_r_q)) && rvalid_q)
             ---------1---------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		17	0	0.00
TERNARY	145	2	0	0.00
TERNARY	300	3	0	0.00
TERNARY	309	2	0	0.00
IF	318	3	0	0.00
IF	343	7	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	145	(read_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	300	(macro_write) ? 
-2-:	300	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	309	(write_pending_q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	318	if (((!intg_error_r_q) && rvalid_q))
-2-:	322	if (addr_collision_q)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	343	if ((!rst_ni))
-2-:	362	if (read_en)
-3-:	365	if (write_en_d)
-4-:	371	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	-	-	Not Covered
0	-	1	-	Not Covered
0	-	0	-	Not Covered
0	-	-	1	Not Covered
0	-	-	0	Not Covered