Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.94	0.00	0.00	95.76		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1238294	7963	0	0
ctrl_regwen_rd_A	1238294	1353	0	0
exec_rd_A	1238294	1216	0	0
exec_regwen_rd_A	1238294	1478	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1238294	7963	0	0
T1	8431	154	0	0
T2	3069	11	0	0
T3	1884	0	0	0
T4	3534	20	0	0
T5	1152	0	0	0
T6	26228	0	0	0
T9	6640	3	0	0
T10	1517	0	0	0
T11	1234	0	0	0
T12	0	19	0	0
T13	1232	0	0	0
T14	0	65	0	0
T16	0	261	0	0
T18	0	110	0	0
T19	0	66	0	0
T20	0	330	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1238294	1353	0	0
T2	3069	4	0	0
T3	1884	0	0	0
T4	3534	16	0	0
T5	1152	0	0	0
T6	26228	34	0	0
T8	0	78	0	0
T9	6640	0	0	0
T10	1517	0	0	0
T11	1234	0	0	0
T13	1232	28	0	0
T16	0	67	0	0
T21	2169	22	0	0
T22	0	5	0	0
T29	0	6	0	0
T51	0	104	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1238294	1216	0	0
T2	3069	6	0	0
T3	1884	0	0	0
T4	3534	37	0	0
T5	1152	0	0	0
T6	26228	34	0	0
T8	0	70	0	0
T9	6640	0	0	0
T10	1517	0	0	0
T11	1234	0	0	0
T13	1232	29	0	0
T16	0	38	0	0
T21	2169	23	0	0
T22	0	6	0	0
T29	0	2	0	0
T51	0	60	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1238294	1478	0	0
T2	3069	6	0	0
T3	1884	0	0	0
T4	3534	30	0	0
T5	1152	0	0	0
T6	26228	34	0	0
T8	0	80	0	0
T9	6640	0	0	0
T10	1517	0	0	0
T11	1234	0	0	0
T13	1232	38	0	0
T16	0	59	0	0
T21	2169	47	0	0
T22	0	8	0	0
T51	0	130	0	0
T52	0	3	0	0