Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
23.94	0.00	0.00	95.76		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	23.94	0.00	0.00	95.76		0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
23.94	0.00	0.00	95.76		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
42.64	25.95	32.17	70.74	0.00	28.53	98.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sram_ctrl_regs_csr_assert	100.00						100.00
tlul_assert_device_ram	32.28	0.00				0.00	96.85
tlul_assert_device_regs	33.33	0.00				0.00	100.00
u_lfsr	0.00			0.00
u_prim_alert_sender_parity	100.00			100.00
u_prim_count	0.00			0.00
u_prim_lc_sync	0.00	0.00				0.00
u_prim_ram_1p_scr	0.00	0.00	0.00	0.00		0.00
u_prim_sync_reqack_data	0.00	0.00	0.00			0.00
u_reg_regs	97.68	99.26	97.88	95.15		96.12	100.00
u_tlul_adapter_sram	18.15	0.00	0.00	90.74	0.00	0.00
u_tlul_data_integ_enc	0.00	0.00
u_tlul_lc_gate	0.00	0.00	0.00		0.00	0.00

Line Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
TOTAL		48	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
ALWAYS	218	3	0	0.00
CONT_ASSIGN	230	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	255	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	276	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	281	1	0	0.00
CONT_ASSIGN	282	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	287	1	0	0.00
ALWAYS	290	11	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	377	1	0	0.00
CONT_ASSIGN	479	1	0	0.00
CONT_ASSIGN	480	1	0	0.00
CONT_ASSIGN	481	1	0	0.00
CONT_ASSIGN	482	1	0	0.00
CONT_ASSIGN	483	1	0	0.00
CONT_ASSIGN	484	1	0	0.00
CONT_ASSIGN	485	1	0	0.00
CONT_ASSIGN	497	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	0	1
134	0	1
137	0	1
141	0	1
144	0	1
176	0	1
178	0	1
186	0	1
192	0	1
200	0	1
209	0	1
214	0	1
218	0	1
219	0	1
221	0	1
230	0	1
231	0	1
255	0	1
256	0	1
267	0	1
272	0	1
276	0	1
277	0	1
281	0	1
282	0	1
286	0	1
287	0	1
290	0	1
291	0	1
294	0	1
295	0	1
297	0	1
298	0	1
299	0	1
300	0	1
			==> MISSING_ELSE
305	0	1
306	0	1
307	0	1
			==> MISSING_ELSE
334	0	1
377	0	1
479	0	1
480	0	1
481	0	1
482	0	1
483	0	1
484	0	1
485	0	1
497	0	1

---

Cond Coverage for Module : sram_ctrl

	Total	Covered	Percent
Conditions	95	0	0.00
Logical	95	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       144
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       186
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       192
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       209
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       214
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       214
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       230
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       255
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       256
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       267
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       272
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       272
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       276
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       277
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       281
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       281
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       286
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       479
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       480
 EXPRESSION (sram_gnt & ((~init_req)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       481
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       482
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       483
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       484
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       485
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       497
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       497
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       497
 SUB-EXPRESSION (tl_gate_resp_pending & tlul_we)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	60	53	88.33
Total Bits	1226	1174	95.76
Total Bits 0->1	613	587	95.76
Total Bits 1->0	613	587	95.76

Ports	60	53	88.33
Port Bits	1226	1174	95.76
Port Bits 0->1	613	587	95.76
Port Bits 1->0	613	587	95.76

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T4	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T5	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	OUTPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
lc_hw_debug_en_i[3:0]	No	No		No		INPUT
otp_en_sram_ifetch_i[7:0]	No	No		No		INPUT
sram_otp_key_o.req	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T6,T7	Yes	T2,T4,T6	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T2,T6,T7	Yes	T6,T7,T12	INPUT
sram_otp_key_i.ack	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
Branches		24	0	0.00
TERNARY	214	3	0	0.00
TERNARY	272	3	0	0.00
TERNARY	281	2	0	0.00
TERNARY	483	2	0	0.00
TERNARY	484	2	0	0.00
TERNARY	485	2	0	0.00
TERNARY	497	3	0	0.00
IF	218	2	0	0.00
IF	290	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	214	(init_done) ? 
-2-:	214	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	272	(key_req) ? 
-2-:	272	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	281	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	483	(init_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	484	(init_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	485	(init_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	497	(key_req_pending_q) ? 
-2-:	497	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	218	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	290	if ((!rst_ni))
-2-:	298	if (key_ack)
-3-:	305	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		48	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
ALWAYS	218	3	0	0.00
CONT_ASSIGN	230	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	255	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	276	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	281	1	0	0.00
CONT_ASSIGN	282	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	287	1	0	0.00
ALWAYS	290	11	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	377	1	0	0.00
CONT_ASSIGN	479	1	0	0.00
CONT_ASSIGN	480	1	0	0.00
CONT_ASSIGN	481	1	0	0.00
CONT_ASSIGN	482	1	0	0.00
CONT_ASSIGN	483	1	0	0.00
CONT_ASSIGN	484	1	0	0.00
CONT_ASSIGN	485	1	0	0.00
CONT_ASSIGN	497	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	0	1
134	0	1
137	0	1
141	0	1
144	0	1
176	0	1
178	0	1
186	0	1
192	0	1
200	0	1
209	0	1
214	0	1
218	0	1
219	0	1
221	0	1
230	0	1
231	0	1
255	0	1
256	0	1
267	0	1
272	0	1
276	0	1
277	0	1
281	0	1
282	0	1
286	0	1
287	0	1
290	0	1
291	0	1
294	0	1
295	0	1
297	0	1
298	0	1
299	0	1
300	0	1
			==> MISSING_ELSE
305	0	1
306	0	1
307	0	1
			==> MISSING_ELSE
334	0	1
377	0	1
479	0	1
480	0	1
481	0	1
482	0	1
483	0	1
484	0	1
485	0	1
497	0	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	93	0	0.00
Logical	93	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       144
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       186
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       192
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       209
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       214
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       214
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       230
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       255
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Excluded		[LOWRISK] we don't issue a new init when there is a unfinished init
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       256
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       267
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       272
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       272
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       276
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Excluded		[UNSUPPORTED] ACK can't come without REQ
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       277
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       281
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       281
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       286
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       479
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       480
 EXPRESSION (sram_gnt & ((~init_req)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       481
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       482
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       483
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       484
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       485
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       497
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       497
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       497
 SUB-EXPRESSION (tl_gate_resp_pending & tlul_we)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	60	53	88.33
Total Bits	1226	1174	95.76
Total Bits 0->1	613	587	95.76
Total Bits 1->0	613	587	95.76

Ports	60	53	88.33
Port Bits	1226	1174	95.76
Port Bits 0->1	613	587	95.76
Port Bits 1->0	613	587	95.76

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T4	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T5	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	OUTPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
lc_hw_debug_en_i[3:0]	No	No		No		INPUT
otp_en_sram_ifetch_i[7:0]	No	No		No		INPUT
sram_otp_key_o.req	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T6,T7	Yes	T2,T4,T6	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T2,T6,T7	Yes	T6,T7,T12	INPUT
sram_otp_key_i.ack	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		24	0	0.00
TERNARY	214	3	0	0.00
TERNARY	272	3	0	0.00
TERNARY	281	2	0	0.00
TERNARY	483	2	0	0.00
TERNARY	484	2	0	0.00
TERNARY	485	2	0	0.00
TERNARY	497	3	0	0.00
IF	218	2	0	0.00
IF	290	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	214	(init_done) ? 
-2-:	214	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	272	(key_req) ? 
-2-:	272	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	281	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	483	(init_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	484	(init_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	485	(init_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	497	(key_req_pending_q) ? 
-2-:	497	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	218	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	290	if ((!rst_ni))
-2-:	298	if (key_ack)
-3-:	305	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered