SRAM_CTRL/RET Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.734m	638.222us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	33.757us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	14.561us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.190s	123.813us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	23.678us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.380s	159.738us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	14.561us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	23.678us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.640s	1.359ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.990s	903.808us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	28.187m	55.610ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.006m	59.502ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.383m	19.978ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.742m	9.115ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.260s	16.641ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.410m	31.109ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.802m	1.614ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.655m	87.369ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.483m	519.713us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.685m	299.846us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.384m	97.977ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.820s	71.515us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.943h	70.512ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.720s	119.942us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.630s	310.326us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.630s	310.326us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	33.757us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	14.561us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	23.678us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	238.287us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	33.757us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	14.561us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	23.678us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	238.287us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.050s	797.014us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.840s	462.338us	5	5	100.00
		sram_ctrl_tl_intg_err	3.430s	2.812ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.840s	462.338us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.430s	2.812ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.384m	97.977ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	14.561us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.410m	31.109ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.410m	31.109ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.410m	31.109ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.260s	16.641ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.050s	797.014us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.734m	638.222us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.734m	638.222us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.410m	31.109ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.840s	462.338us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.260s	16.641ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.840s	462.338us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.840s	462.338us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.734m	638.222us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.840s	462.338us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.273m	9.793ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1029	1040	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 7.sram_ctrl_stress_all_with_rand_reset.23198732640905012176093037952637587823595647427959041014172122731768430958715
    Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2558576645 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2558576645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_stress_all_with_rand_reset.86184608279861993344634863284291338150142659429833717603026739076826752957879
    Line 374, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8933411527 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8933411527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))'

has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

14.sram_ctrl_stress_all.77824136663400409386579639031962768972512382573384270845912839039584139334925
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 155776184 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 155776184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.sram_ctrl_stress_all.19304805151269353949021360787655860974425515828510369190445848876921871550932
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1083383626 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1083383626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.48857499644325246277296432259787099289583224040935639138977256701126765352625
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 161352508 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 161352508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```