SRAM_CTRL/RET Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.648m	856.824us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	17.936us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	15.130us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.860s	187.905us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	16.790us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.260s	62.814us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	15.130us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	16.790us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.910s	2.620ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.720s	330.976us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	29.004m	86.637ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.133m	8.795ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.413m	51.696ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.150m	13.113ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.570s	3.444ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.744m	30.714ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.351m	2.852ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.746m	99.149ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.671m	268.228us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.720m	671.048us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.909m	26.302ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.830s	205.799us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.411h	296.754ms	42	50	84.00
V2	alert_test	sram_ctrl_alert_test	0.700s	26.743us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.060s	158.042us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.060s	158.042us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	17.936us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	15.130us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	16.790us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	81.347us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	17.936us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	15.130us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	16.790us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	81.347us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.710s	4.500ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.220s	902.037us	5	5	100.00
		sram_ctrl_tl_intg_err	2.780s	1.641ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.220s	902.037us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	1.641ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.909m	26.302ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	15.130us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.744m	30.714ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.744m	30.714ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.744m	30.714ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.570s	3.444ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.710s	4.500ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.648m	856.824us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.648m	856.824us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.744m	30.714ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.220s	902.037us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.570s	3.444ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.220s	902.037us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.220s	902.037us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.648m	856.824us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.220s	902.037us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.850m	1.318ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.58	99.70	98.52

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 7 failures:

Test sram_ctrl_stress_all has 7 failures.

11.sram_ctrl_stress_all.92538044323783041362311748885892815746436065807674718274687904776624613961345
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  16994445 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  16994445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.sram_ctrl_stress_all.43586645959764953537537503830874292071120990407386054529406426390331238913267
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  15637332 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  15637332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 5 failures.
  - 10.sram_ctrl_stress_all_with_rand_reset.9368302377811020621720671936868439529195898242321901727072375324125363078435
    Line 365, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1188937999 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1188937999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.sram_ctrl_stress_all_with_rand_reset.4049238003473070004649751373071999998426423066752880087108142825961751785623
    Line 390, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12742906144 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12742906144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 2 failures.
  - 15.sram_ctrl_multiple_keys.90891818310182769808342173341332603594813707579792137938478233157403177312353
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 10236009156 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x81012987
  UVM_INFO @ 10236009156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.sram_ctrl_multiple_keys.108328235968834142153512294809070871470649358389035286210688467156330877852630
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 119883806471 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x4b02e50
  UVM_INFO @ 119883806471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.31200786328530121842693206211747723396587084785188905371129446290900220558290
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 100578768 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 100578768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 22.sram_ctrl_stress_all.103512586395612278389620405403007567516714772873492458657482427074060965720800
    Line 318, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 105347398088 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xe595c35e
  UVM_INFO @ 105347398088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```