SRAM_CTRL/RET Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.274m 665.678us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.750s 27.313us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.700s 20.256us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.400s 708.524us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 25.398us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.180s 208.711us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.700s 20.256us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 25.398us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 10.940s 2.734ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.960s 3.244ms 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 26.196m 22.979ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.361m 17.971ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.247m 4.763ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.645m 10.904ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.330s 1.203ms 50 50 100.00
V2 executable sram_ctrl_executable 24.661m 50.998ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.132m 2.473ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.623m 56.788ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.236m 535.929us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.211m 1.237ms 50 50 100.00
V2 regwen sram_ctrl_regwen 41.956m 22.119ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 0.820s 45.286us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.433h 359.261ms 44 50 88.00
V2 alert_test sram_ctrl_alert_test 0.730s 108.902us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.410s 292.354us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.410s 292.354us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.750s 27.313us 5 5 100.00
sram_ctrl_csr_rw 0.700s 20.256us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 25.398us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.810s 26.412us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.750s 27.313us 5 5 100.00
sram_ctrl_csr_rw 0.700s 20.256us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 25.398us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.810s 26.412us 20 20 100.00
V2 TOTAL 732 740 98.92
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.900s 830.172us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.160s 229.630us 5 5 100.00
sram_ctrl_tl_intg_err 2.980s 454.637us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.160s 229.630us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.980s 454.637us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 41.956m 22.119ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.700s 20.256us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 24.661m 50.998ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 24.661m 50.998ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 24.661m 50.998ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.330s 1.203ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.900s 830.172us 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.274m 665.678us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.274m 665.678us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 24.661m 50.998ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.160s 229.630us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.330s 1.203ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.160s 229.630us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.160s 229.630us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.274m 665.678us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.160s 229.630us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 15.681m 2.488ms 43 50 86.00
V3 TOTAL 43 50 86.00
TOTAL 1023 1040 98.37

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.09 99.81 97.02 100.00 100.00 98.58 99.70 98.52

Failure Buckets

Past Results