SRAM_CTRL/RET Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.772m 659.239us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 17.609us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.690s 22.206us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.120s 337.251us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.740s 44.069us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.430s 153.351us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.690s 22.206us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 44.069us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.010s 7.305ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.560s 311.115us 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 43.140m 19.114ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.448m 9.021ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.431m 20.689ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 42.633m 44.116ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.500s 981.527us 50 50 100.00
V2 executable sram_ctrl_executable 33.580m 14.210ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.451m 702.803us 50 50 100.00
sram_ctrl_partial_access_b2b 9.989m 82.357ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.417m 134.108us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.649m 314.132us 50 50 100.00
V2 regwen sram_ctrl_regwen 37.995m 17.629ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 0.940s 94.442us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.713h 80.869ms 44 50 88.00
V2 alert_test sram_ctrl_alert_test 0.750s 18.912us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.950s 559.637us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.950s 559.637us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 17.609us 5 5 100.00
sram_ctrl_csr_rw 0.690s 22.206us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 44.069us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.800s 22.827us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 17.609us 5 5 100.00
sram_ctrl_csr_rw 0.690s 22.206us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 44.069us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.800s 22.827us 20 20 100.00
V2 TOTAL 732 740 98.92
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.330s 448.603us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.300s 474.123us 5 5 100.00
sram_ctrl_tl_intg_err 2.830s 423.049us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.300s 474.123us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.830s 423.049us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 37.995m 17.629ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.690s 22.206us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 33.580m 14.210ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 33.580m 14.210ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 33.580m 14.210ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.500s 981.527us 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.330s 448.603us 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.772m 659.239us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.772m 659.239us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 33.580m 14.210ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.300s 474.123us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.500s 981.527us 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.300s 474.123us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.300s 474.123us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.772m 659.239us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.300s 474.123us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 15.610m 8.524ms 43 50 86.00
V3 TOTAL 43 50 86.00
TOTAL 1023 1040 98.37

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52

Failure Buckets

Past Results