ae68723071
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | sram_ctrl_smoke | 2.772m | 659.239us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.700s | 17.609us | 5 | 5 | 100.00 |
V1 | csr_rw | sram_ctrl_csr_rw | 0.690s | 22.206us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.120s | 337.251us | 5 | 5 | 100.00 |
V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.740s | 44.069us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 2.430s | 153.351us | 18 | 20 | 90.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.690s | 22.206us | 20 | 20 | 100.00 |
sram_ctrl_csr_aliasing | 0.740s | 44.069us | 5 | 5 | 100.00 | ||
V1 | mem_walk | sram_ctrl_mem_walk | 12.010s | 7.305ms | 50 | 50 | 100.00 |
V1 | mem_partial_access | sram_ctrl_mem_partial_access | 5.560s | 311.115us | 50 | 50 | 100.00 |
V1 | TOTAL | 203 | 205 | 99.02 | |||
V2 | multiple_keys | sram_ctrl_multiple_keys | 43.140m | 19.114ms | 50 | 50 | 100.00 |
V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.448m | 9.021ms | 50 | 50 | 100.00 |
V2 | bijection | sram_ctrl_bijection | 1.431m | 20.689ms | 50 | 50 | 100.00 |
V2 | access_during_key_req | sram_ctrl_access_during_key_req | 42.633m | 44.116ms | 50 | 50 | 100.00 |
V2 | lc_escalation | sram_ctrl_lc_escalation | 10.500s | 981.527us | 50 | 50 | 100.00 |
V2 | executable | sram_ctrl_executable | 33.580m | 14.210ms | 49 | 50 | 98.00 |
V2 | partial_access | sram_ctrl_partial_access | 2.451m | 702.803us | 50 | 50 | 100.00 |
sram_ctrl_partial_access_b2b | 9.989m | 82.357ms | 50 | 50 | 100.00 | ||
V2 | max_throughput | sram_ctrl_max_throughput | 2.417m | 134.108us | 50 | 50 | 100.00 |
sram_ctrl_throughput_w_partial_write | 2.649m | 314.132us | 50 | 50 | 100.00 | ||
V2 | regwen | sram_ctrl_regwen | 37.995m | 17.629ms | 49 | 50 | 98.00 |
V2 | ram_cfg | sram_ctrl_ram_cfg | 0.940s | 94.442us | 50 | 50 | 100.00 |
V2 | stress_all | sram_ctrl_stress_all | 1.713h | 80.869ms | 44 | 50 | 88.00 |
V2 | alert_test | sram_ctrl_alert_test | 0.750s | 18.912us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.950s | 559.637us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.950s | 559.637us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.700s | 17.609us | 5 | 5 | 100.00 |
sram_ctrl_csr_rw | 0.690s | 22.206us | 20 | 20 | 100.00 | ||
sram_ctrl_csr_aliasing | 0.740s | 44.069us | 5 | 5 | 100.00 | ||
sram_ctrl_same_csr_outstanding | 0.800s | 22.827us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.700s | 17.609us | 5 | 5 | 100.00 |
sram_ctrl_csr_rw | 0.690s | 22.206us | 20 | 20 | 100.00 | ||
sram_ctrl_csr_aliasing | 0.740s | 44.069us | 5 | 5 | 100.00 | ||
sram_ctrl_same_csr_outstanding | 0.800s | 22.827us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 732 | 740 | 98.92 | |||
V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 3.330s | 448.603us | 20 | 20 | 100.00 |
V2S | tl_intg_err | sram_ctrl_sec_cm | 3.300s | 474.123us | 5 | 5 | 100.00 |
sram_ctrl_tl_intg_err | 2.830s | 423.049us | 20 | 20 | 100.00 | ||
V2S | prim_count_check | sram_ctrl_sec_cm | 3.300s | 474.123us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.830s | 423.049us | 20 | 20 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 37.995m | 17.629ms | 49 | 50 | 98.00 |
V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.690s | 22.206us | 20 | 20 | 100.00 |
V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 33.580m | 14.210ms | 49 | 50 | 98.00 |
V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 33.580m | 14.210ms | 49 | 50 | 98.00 |
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 33.580m | 14.210ms | 49 | 50 | 98.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 10.500s | 981.527us | 50 | 50 | 100.00 |
V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 3.330s | 448.603us | 20 | 20 | 100.00 |
V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.772m | 659.239us | 50 | 50 | 100.00 |
V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.772m | 659.239us | 50 | 50 | 100.00 |
V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 33.580m | 14.210ms | 49 | 50 | 98.00 |
V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.300s | 474.123us | 5 | 5 | 100.00 |
V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 10.500s | 981.527us | 50 | 50 | 100.00 |
V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.300s | 474.123us | 5 | 5 | 100.00 |
V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.300s | 474.123us | 5 | 5 | 100.00 |
V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.772m | 659.239us | 50 | 50 | 100.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.300s | 474.123us | 5 | 5 | 100.00 |
V2S | TOTAL | 45 | 45 | 100.00 | |||
V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 15.610m | 8.524ms | 43 | 50 | 86.00 |
V3 | TOTAL | 43 | 50 | 86.00 | |||
TOTAL | 1023 | 1040 | 98.37 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.08 | 99.81 | 96.99 | 100.00 | 100.00 | 98.57 | 99.70 | 98.52 |
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 7 failures:
24.sram_ctrl_stress_all_with_rand_reset.60064672377913898185381121128006610897128520327603315562531506454671741911788
Line 307, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5059943764 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5059943764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sram_ctrl_stress_all_with_rand_reset.111482346753121224592135152532327905706483284129248802139821200282605005314649
Line 347, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24678329619 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24678329619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))'
has 5 failures:
2.sram_ctrl_stress_all.59473816834219469193487015824457967949670008272520359952868799182091256957650
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 49549372 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 49549372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.sram_ctrl_stress_all.109683138210149991837245854427537608225714578618558139395828255958665018591321
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 150242698 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 150242698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=*
has 2 failures:
Test sram_ctrl_stress_all has 1 failures.
33.sram_ctrl_stress_all.68205135788441128678275167584395584821552562054020466117042595439209697951148
Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 39151832399 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xc2cad16c
UVM_INFO @ 39151832399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_executable has 1 failures.
36.sram_ctrl_executable.101651532768096363621412503217445723473220460121272156125173730954968816840456
Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest/run.log
UVM_FATAL @ 41981102583 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x251d6b79
UVM_INFO @ 41981102583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *
has 1 failures:
2.sram_ctrl_csr_mem_rw_with_rand_reset.352165636700123272328176861187378329982151460446655697758945500452076670834
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 103152434 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 103152434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=*
has 1 failures:
4.sram_ctrl_regwen.75026506425281219567668040349360524410939201609431571303759097824742434152070
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 10298778472 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x7e4ceeaf
UVM_INFO @ 10298778472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
has 1 failures:
7.sram_ctrl_csr_mem_rw_with_rand_reset.47756497162290658085866231264005814807558434467731209448820848452747709149100
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 25791157 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 25791157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---