SRAM_CTRL/RET Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.101m	1.082ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	54.612us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.760s	23.682us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.330s	599.498us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	13.499us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.450s	566.826us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.760s	23.682us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	13.499us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.590s	681.849us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.580s	302.608us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	35.751m	22.613ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.933m	4.937ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.394m	30.998ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.826m	4.188ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.700s	1.123ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.365m	12.498ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.476m	225.926us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.572m	23.679ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.090m	139.158us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.420m	142.771us	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.236m	78.642ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.870s	49.811us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.809h	84.419ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.730s	28.715us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.060s	499.239us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.060s	499.239us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	54.612us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	23.682us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	13.499us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	28.595us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	54.612us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	23.682us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	13.499us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	28.595us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	7.290s	1.790ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.410s	440.623us	5	5	100.00
		sram_ctrl_tl_intg_err	2.690s	388.860us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.410s	440.623us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.690s	388.860us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.236m	78.642ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.760s	23.682us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.365m	12.498ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.365m	12.498ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.365m	12.498ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.700s	1.123ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	7.290s	1.790ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.101m	1.082ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.101m	1.082ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.365m	12.498ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.410s	440.623us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.700s	1.123ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.410s	440.623us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.410s	440.623us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.101m	1.082ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.410s	440.623us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.622m	2.984ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 3 failures.

    • 24.sram_ctrl_stress_all_with_rand_reset.13620083309433362101189970610888370278288366272399287525526595316805171359708
      Line 446, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24657838203 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24657838203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.sram_ctrl_stress_all_with_rand_reset.82830393525816478562526513508972448805164350606780865592156689248604192851237
      Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6218028088 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6218028088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 2.sram_ctrl_executable.34500988930138514619962765415991498352314676667554003960647133173333026127094
      Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 33390906764 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xf8631aaf
        UVM_INFO @ 33390906764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 16.sram_ctrl_csr_mem_rw_with_rand_reset.40630600648033188694342042241778642201340817262664295949679536976206614013905
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  30574865 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @  30574865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.22_07.41.29
• 2024.04.19_05.22.22
• 2024.04.17_05.29.39
• 2024.04.16_04.25.40
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