SRAM_CTRL/RET Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.007m 693.244us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.730s 16.380us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.690s 21.103us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.030s 608.994us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 21.036us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 1.630s 130.695us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.690s 21.103us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 21.036us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 11.970s 10.846ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.530s 2.264ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 32.313m 38.550ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 5.925m 14.931ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.376m 25.940ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 21.163m 20.901ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.030s 1.323ms 50 50 100.00
V2 executable sram_ctrl_executable 32.654m 110.008ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.435m 1.350ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.335m 99.403ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.058m 274.794us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.343m 316.886us 50 50 100.00
V2 regwen sram_ctrl_regwen 31.147m 104.260ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.910s 86.335us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.572h 128.676ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.670s 25.796us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.610s 932.377us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.610s 932.377us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.730s 16.380us 5 5 100.00
sram_ctrl_csr_rw 0.690s 21.103us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 21.036us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 26.374us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.730s 16.380us 5 5 100.00
sram_ctrl_csr_rw 0.690s 21.103us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 21.036us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 26.374us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.310s 4.500ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.580s 3.211ms 5 5 100.00
sram_ctrl_tl_intg_err 2.520s 1.908ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.580s 3.211ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.520s 1.908ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 31.147m 104.260ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.690s 21.103us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 32.654m 110.008ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 32.654m 110.008ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 32.654m 110.008ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.030s 1.323ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.310s 4.500ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.007m 693.244us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.007m 693.244us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 32.654m 110.008ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.580s 3.211ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.030s 1.323ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.580s 3.211ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.580s 3.211ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.007m 693.244us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.580s 3.211ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 17.442m 11.061ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 1033 1040 99.33

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52

Failure Buckets

Past Results