18c8953cf1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.470m | 141.259us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.670s | 23.238us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.670s | 32.131us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.130s | 163.298us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.730s | 159.192us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 1.710s | 118.237us | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.670s | 32.131us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.730s | 159.192us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 10.760s | 2.278ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 5.360s | 293.395us | 50 | 50 | 100.00 |
| V1 | TOTAL | 202 | 205 | 98.54 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 33.873m | 108.753ms | 50 | 50 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.564m | 17.351ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.411m | 5.654ms | 50 | 50 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 25.879m | 21.475ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 10.820s | 2.036ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 37.918m | 26.199ms | 50 | 50 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.754m | 896.579us | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 10.180m | 106.286ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.522m | 138.018us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.251m | 1.319ms | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 24.673m | 2.966ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.830s | 50.729us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.913h | 71.237ms | 37 | 50 | 74.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.710s | 41.815us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.580s | 509.235us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.580s | 509.235us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.670s | 23.238us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.670s | 32.131us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.730s | 159.192us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.820s | 24.402us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.670s | 23.238us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.670s | 32.131us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.730s | 159.192us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.820s | 24.402us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 727 | 740 | 98.24 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 4.120s | 2.964ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.220s | 781.853us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 3.230s | 1.441ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.220s | 781.853us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 3.230s | 1.441ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 24.673m | 2.966ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.670s | 32.131us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 37.918m | 26.199ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 37.918m | 26.199ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 37.918m | 26.199ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 10.820s | 2.036ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 4.120s | 2.964ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.470m | 141.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.470m | 141.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 37.918m | 26.199ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.220s | 781.853us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 10.820s | 2.036ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.220s | 781.853us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.220s | 781.853us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.470m | 141.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.220s | 781.853us | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 16.835m | 1.831ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 1019 | 1040 | 97.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 15 | 93.75 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.06 | 99.81 | 96.99 | 100.00 | 100.00 | 98.57 | 99.70 | 98.33 |
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 10 failures:
2.sram_ctrl_stress_all.57527452670262731631606687053913830895983755777348244484545567038899641575324
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 46857670 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 46857670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.sram_ctrl_stress_all.5537413579526961856546737455599839064764222035955326994787803976302673005166
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 75405914 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 75405914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
3.sram_ctrl_stress_all_with_rand_reset.106122748209768781082428720090688007103288729336758294198444549719037150452528
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 719593094 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 719593094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.sram_ctrl_stress_all_with_rand_reset.35664894394981968846338642799154404898703871007788450434830744392117179421685
Line 317, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7394313166 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7394313166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '(!$isunknown(rdata_o))' has 3 failures:
7.sram_ctrl_stress_all.75268760662888685940865620679033712684079267287991282919032461631234942407880
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 87511299 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 87511299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.sram_ctrl_stress_all.6817377118353309126788046274116396767983225946169850162743773387933436879114
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 46604695 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 46604695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
0.sram_ctrl_csr_mem_rw_with_rand_reset.110707900435073875666738404965744521272242360400743473238988575865158156619584
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 104471268 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 104471268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
3.sram_ctrl_csr_mem_rw_with_rand_reset.89809456750126705527072397502778933487489079066618202198050894568240021417739
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 85822292 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 85822292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
9.sram_ctrl_csr_mem_rw_with_rand_reset.72810393532866834806176919316834258304760892644606537115869931172075364862964
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 90370487 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 90370487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---