SRAM_CTRL/RET Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.535m	1.736ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	14.774us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	30.450us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.020s	121.320us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	40.827us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.510s	41.528us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	30.450us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	40.827us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.770s	1.312ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.390s	1.593ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	31.636m	70.849ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.514m	4.616ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.415m	9.794ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.264m	7.423ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.300s	3.784ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.412m	85.526ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.442m	1.075ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.587m	64.729ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.518m	134.841us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.997m	158.049us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.443m	40.371ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.880s	28.201us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.736h	116.418ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.690s	17.062us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.990s	174.224us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.990s	174.224us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	14.774us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	30.450us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	40.827us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	27.587us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	14.774us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	30.450us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	40.827us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	27.587us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.060s	741.916us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.240s	541.114us	5	5	100.00
		sram_ctrl_tl_intg_err	2.890s	411.023us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.240s	541.114us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.890s	411.023us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.443m	40.371ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	30.450us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.412m	85.526ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.412m	85.526ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.412m	85.526ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.300s	3.784ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.060s	741.916us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.535m	1.736ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.535m	1.736ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.412m	85.526ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.240s	541.114us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.300s	3.784ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.240s	541.114us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.240s	541.114us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.535m	1.736ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.240s	541.114us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.722m	2.081ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1026	1040	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.sram_ctrl_stress_all_with_rand_reset.48403842856848824916414281569071417790951928434321696164255164584636290408221
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3250162593 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3250162593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.sram_ctrl_stress_all_with_rand_reset.48602140197292912086900820202907752611307580069063054989089146558747836904182
    Line 344, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1112210174 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1112210174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

4.sram_ctrl_stress_all.17507463412634930703008218723577130764037313216874379720623606962021313951983
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 558346479 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 558346479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.sram_ctrl_stress_all.77025918556003627369344937667229557579009298417928665054158699256860423806148
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 632562005 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 632562005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.74144677616710832897090677690286294550287522899672992582300474551642863494290
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  95028140 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  95028140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 16.sram_ctrl_csr_mem_rw_with_rand_reset.113017528602469643390788229073610533603688296267436274075393007114415463203225
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  92698852 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  92698852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 17.sram_ctrl_regwen.25895199339586454940156787838561101131792425645199298871805266222099415202613
    Line 300, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 57534488010 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x8e718ddb
  UVM_INFO @ 57534488010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 47.sram_ctrl_stress_all.27564489732965192274989627126586508473453219323460243097758703026766282082885
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 127338631 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 127338631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```