SRAM_CTRL/RET Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.073m	3.582ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	29.698us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	18.653us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.430s	966.001us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	23.272us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.340s	81.642us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	18.653us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	23.272us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.500s	3.647ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.500s	153.475us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	31.972m	53.395ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.407m	8.997ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.330m	4.494ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.812m	5.849ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.500s	2.368ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.645m	4.699ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.931m	782.085us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.720m	48.155ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.866m	617.520us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.947m	1.348ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	43.191m	221.861ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.820s	29.332us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.201h	82.325ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.700s	44.967us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.500s	690.759us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.500s	690.759us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	29.698us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	18.653us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	23.272us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	22.457us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	29.698us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	18.653us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	23.272us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	22.457us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.770s	6.081ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.420s	545.371us	5	5	100.00
		sram_ctrl_tl_intg_err	2.660s	887.978us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.420s	545.371us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.660s	887.978us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	43.191m	221.861ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	18.653us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.645m	4.699ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.645m	4.699ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.645m	4.699ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.500s	2.368ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.770s	6.081ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.073m	3.582ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.073m	3.582ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.645m	4.699ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.420s	545.371us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.500s	2.368ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.420s	545.371us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.420s	545.371us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.073m	3.582ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.420s	545.371us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.518m	6.553ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1028	1040	98.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.81	96.99	100.00	100.00	98.57	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 6.sram_ctrl_stress_all_with_rand_reset.91255487373275017588755354662292953238736186748991288970654613858482033696514
    Line 326, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1338073437 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1338073437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_stress_all_with_rand_reset.1181642495345576330950065936610523854552365566542805520078975704821218074916
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 608534880 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 608534880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

11.sram_ctrl_stress_all.99327811752344543539924912947701527631853368486392453934217819431892461565193
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  57197810 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  57197810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.sram_ctrl_stress_all.79686476786896131837899047167051315902514597598855609751726439013369203339471
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 332430086 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 332430086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 1 failures.
  - 41.sram_ctrl_executable.59145203154626619243233906626713459616151539124031621770285267645899040967552
    Line 324, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 163170398368 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xdcc1d7d8
  UVM_INFO @ 163170398368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 48.sram_ctrl_stress_all.2653375512576942028487472960121132952045518196481303003900736926106527035518
    Line 287, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 179352838507 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x3f74d17d
  UVM_INFO @ 179352838507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 16.sram_ctrl_csr_mem_rw_with_rand_reset.42836371872275067972556666239367507261388117324632903977010997508545689697305
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48053373 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  48053373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 28.sram_ctrl_multiple_keys.92251452691677645122341051575547490750802546796995472271839892302855107409697
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 13101216125 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x73eaf052
  UVM_INFO @ 13101216125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```