302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.571m | 3.359ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.700s | 55.396us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.700s | 50.354us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.340s | 176.629us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.740s | 43.030us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 1.780s | 447.451us | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.700s | 50.354us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.740s | 43.030us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 12.890s | 658.294us | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 6.310s | 660.581us | 50 | 50 | 100.00 |
| V1 | TOTAL | 202 | 205 | 98.54 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 39.298m | 4.986ms | 50 | 50 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 8.842m | 10.700ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.495m | 9.216ms | 50 | 50 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 31.484m | 3.918ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 10.020s | 4.532ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 31.697m | 26.862ms | 49 | 50 | 98.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.629m | 670.394us | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 9.941m | 27.316ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.874m | 531.605us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.666m | 161.001us | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 36.068m | 21.112ms | 49 | 50 | 98.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.910s | 151.803us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.558h | 163.709ms | 45 | 50 | 90.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.720s | 35.089us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.540s | 242.449us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.540s | 242.449us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.700s | 55.396us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.700s | 50.354us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.740s | 43.030us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 37.198us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.700s | 55.396us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.700s | 50.354us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.740s | 43.030us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 37.198us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 733 | 740 | 99.05 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 4.450s | 4.246ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0.760s | 27.577us | 0 | 5 | 0.00 |
| sram_ctrl_tl_intg_err | 2.910s | 1.845ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0.760s | 27.577us | 0 | 5 | 0.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.910s | 1.845ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 36.068m | 21.112ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.700s | 50.354us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 31.697m | 26.862ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 31.697m | 26.862ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 31.697m | 26.862ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 10.020s | 4.532ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 4.450s | 4.246ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 2.571m | 3.359ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.571m | 3.359ms | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.571m | 3.359ms | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 31.697m | 26.862ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0.760s | 27.577us | 0 | 5 | 0.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 10.020s | 4.532ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0.760s | 27.577us | 0 | 5 | 0.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0.760s | 27.577us | 0 | 5 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.571m | 3.359ms | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0.760s | 27.577us | 0 | 5 | 0.00 |
| V2S | TOTAL | 39 | 45 | 86.67 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 14.693m | 4.654ms | 41 | 50 | 82.00 |
| V3 | TOTAL | 41 | 50 | 82.00 | |||
| TOTAL | 1015 | 1040 | 97.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 13 | 81.25 |
| V2S | 3 | 3 | 1 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.36 | 98.99 | 92.48 | 99.31 | 100.00 | 95.26 | 98.38 | 97.07 |
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
18.sram_ctrl_stress_all_with_rand_reset.41069185255027376490949521663034301076105243214483832963582786025597402090706
Line 475, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1322890076 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1322890076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.sram_ctrl_stress_all_with_rand_reset.46179164309750759388162888408370623652164634970813817966579697601579618565494
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2396099403 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2396099403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:
0.sram_ctrl_stress_all.2061605637329622862011283435383706175448163234470783947493001776124574600638
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 21112785 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 21112785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_stress_all.95433323619360574408964191282635061080350735688692176499278492994604650250738
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 15138816 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 15138816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:
0.sram_ctrl_sec_cm.95401972230109583212833721607540663038245230586802326158548925530053396454950
Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 4438749 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4438749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.sram_ctrl_sec_cm.9865629878725771939444292467180218778450003561355189666721961914716224118281
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 6979651 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6979651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!$isunknown(rdata_o))' has 1 failures:
1.sram_ctrl_sec_cm.23230995327660328126921137797178386491871918724199267204158903483012556154924
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 22093331 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 22093331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(tl_o.d_valid))' has 1 failures:
3.sram_ctrl_sec_cm.63868604944181091974163623151375688890736021082045959934395300768066252302131
Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(tl_o.d_valid))'
UVM_ERROR @ 27576665 ps: (tlul_adapter_sram.sv:679) [ASSERT FAILED] TlOutValidKnown_A
UVM_INFO @ 27576665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
4.sram_ctrl_passthru_mem_tl_intg_err.28353223309692832509495546590646123081804299723696231759479921177480428434307
Line 340, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_ERROR @ 767518727 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 767518727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
5.sram_ctrl_csr_mem_rw_with_rand_reset.40643677261097959848072583448035752672008805120703015926423459817414986051497
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 109707739 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 109707739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
6.sram_ctrl_csr_mem_rw_with_rand_reset.73151483281511832621809748141595108287739891004779189634150364560380977491903
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 226071303 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 226071303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
8.sram_ctrl_regwen.57521478319673895452939533211400089892307067836693203809228017814456950270683
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 42149721001 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x2fa68a3c
UVM_INFO @ 42149721001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
14.sram_ctrl_csr_mem_rw_with_rand_reset.24038685301509054400025204679206445477384082812102981035473223807098039962031
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 113201373 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 113201373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job sram_ctrl_ret-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
20.sram_ctrl_executable.99495647867703780416557192158241894093386246963586052232591332961700628373977
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest/run.log
Job ID: smart:2807c568-61bd-44d3-84e2-e6ee93aa1b34