SRAM_CTRL/RET Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.638m	2.401ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	17.524us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	35.315us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.240s	325.043us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	19.875us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.030s	65.898us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	35.315us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	19.875us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.320s	4.376ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.540s	165.797us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	29.650m	20.043ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.626m	4.084ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.409m	18.080ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.124m	5.189ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.770s	2.276ms	50	50	100.00
V2	executable	sram_ctrl_executable	38.881m	27.228ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.499m	1.320ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.731m	22.734ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.296m	2.066ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.360m	668.473us	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.513m	73.064ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.860s	38.630us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.352h	56.174ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.730s	21.117us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.130s	121.628us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.130s	121.628us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	17.524us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	35.315us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	19.875us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	100.691us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	17.524us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	35.315us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	19.875us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	100.691us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.690s	7.679ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.840s	8.947us	0	5	0.00
		sram_ctrl_tl_intg_err	3.300s	502.409us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.840s	8.947us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.300s	502.409us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.513m	73.064ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	35.315us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	38.881m	27.228ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	38.881m	27.228ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	38.881m	27.228ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.770s	2.276ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.690s	7.679ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.638m	2.401ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.638m	2.401ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.638m	2.401ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	38.881m	27.228ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.840s	8.947us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.770s	2.276ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.840s	8.947us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.840s	8.947us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.638m	2.401ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.840s	8.947us	0	5	0.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.616m	1.822ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			1023	1040	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	98.99	92.48	99.31	100.00	95.26	98.38	97.26

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 6 failures:

Test sram_ctrl_stress_all has 6 failures.

6.sram_ctrl_stress_all.68542438413022155246571645693040742082831508956615157782880057164647658399226
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 224871790 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 224871790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.sram_ctrl_stress_all.8764692872334656513441924626675017951714820388953168186331307941725087309
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 116861345 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 116861345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 3 failures.
  - 35.sram_ctrl_stress_all_with_rand_reset.71307543335308052221390907283811999355033442411081661974922115974857945152566
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2326968311 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2326968311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.sram_ctrl_stress_all_with_rand_reset.18770337405993659248994770246191257897081533322093963291422782042651388273151
    Line 313, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1930626324 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1930626324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 1.sram_ctrl_sec_cm.38082643643496007870321351023424996385875783892401481544942734330616715636093
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  22400332 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  22400332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.sram_ctrl_sec_cm.83950743311107827552963329604930194430657673488526288765918462016749101357305
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   8946946 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8946946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 3.sram_ctrl_sec_cm.87207842027519419636510150818722401578456350948318822229509236924090143395390
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   1589496 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   1589496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.sram_ctrl_sec_cm.96674652443606403156949659383429885959547946461646064189106325240989211065899
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   3030182 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3030182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(tl_o.d_valid))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 0.sram_ctrl_sec_cm.23689821762282817261044319198283541743977823525146940174473593613252590668815
    Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(tl_o.d_valid))'
  UVM_ERROR @  25001060 ps: (tlul_adapter_sram.sv:679) [ASSERT FAILED] TlOutValidKnown_A
  UVM_INFO @  25001060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 3.sram_ctrl_stress_all.85562646948091481033311804026773871594059404512451018333571482949962155427385
    Line 395, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 353627150714 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x87a09540
  UVM_INFO @ 353627150714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.95350415098870155388010651333189105560056772461914800364606062696266786886146
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 136803628 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 136803628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 28.sram_ctrl_regwen.44627842935265248786205368824690847067990387093273777067592391326977211807455
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 16537286858 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x68f42687
  UVM_INFO @ 16537286858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```