| T90 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1844834076 |
|
|
Oct 15 03:30:56 AM UTC 24 |
Oct 15 03:31:01 AM UTC 24 |
301322574 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3018363913 |
|
|
Oct 15 03:30:55 AM UTC 24 |
Oct 15 03:31:03 AM UTC 24 |
186584698 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3097225008 |
|
|
Oct 15 03:31:01 AM UTC 24 |
Oct 15 03:31:04 AM UTC 24 |
107998773 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1184683169 |
|
|
Oct 15 03:31:05 AM UTC 24 |
Oct 15 03:31:07 AM UTC 24 |
38695481 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3346298847 |
|
|
Oct 15 03:25:50 AM UTC 24 |
Oct 15 03:31:22 AM UTC 24 |
20704029231 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.1497776415 |
|
|
Oct 15 03:30:00 AM UTC 24 |
Oct 15 03:31:25 AM UTC 24 |
982924620 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.211261665 |
|
|
Oct 15 03:22:24 AM UTC 24 |
Oct 15 03:31:28 AM UTC 24 |
72655489277 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3538447960 |
|
|
Oct 15 03:24:54 AM UTC 24 |
Oct 15 03:31:29 AM UTC 24 |
3636183113 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.2755002533 |
|
|
Oct 15 03:31:08 AM UTC 24 |
Oct 15 03:31:29 AM UTC 24 |
3659858535 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1514528546 |
|
|
Oct 15 03:23:09 AM UTC 24 |
Oct 15 03:31:34 AM UTC 24 |
4220966704 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.862979336 |
|
|
Oct 15 03:30:36 AM UTC 24 |
Oct 15 03:31:43 AM UTC 24 |
455706147 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1376223756 |
|
|
Oct 15 03:31:30 AM UTC 24 |
Oct 15 03:31:51 AM UTC 24 |
1583171165 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4138919430 |
|
|
Oct 15 03:31:51 AM UTC 24 |
Oct 15 03:32:01 AM UTC 24 |
1388212005 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.406153926 |
|
|
Oct 15 03:27:59 AM UTC 24 |
Oct 15 03:32:09 AM UTC 24 |
1589274371 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2458481088 |
|
|
Oct 15 03:30:49 AM UTC 24 |
Oct 15 03:32:23 AM UTC 24 |
6677140283 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2974830830 |
|
|
Oct 15 03:28:28 AM UTC 24 |
Oct 15 03:32:36 AM UTC 24 |
8451362249 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.413277020 |
|
|
Oct 15 03:31:44 AM UTC 24 |
Oct 15 03:32:37 AM UTC 24 |
111119538 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1463095258 |
|
|
Oct 15 03:32:37 AM UTC 24 |
Oct 15 03:32:39 AM UTC 24 |
26755720 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2307298304 |
|
|
Oct 15 03:13:02 AM UTC 24 |
Oct 15 03:32:41 AM UTC 24 |
32030560458 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_readback_err.3598817850 |
|
|
Oct 15 03:32:42 AM UTC 24 |
Oct 15 03:32:45 AM UTC 24 |
131918392 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3174005927 |
|
|
Oct 15 03:32:38 AM UTC 24 |
Oct 15 03:32:49 AM UTC 24 |
271153113 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.4182559671 |
|
|
Oct 15 03:31:25 AM UTC 24 |
Oct 15 03:32:49 AM UTC 24 |
5281629166 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.526790652 |
|
|
Oct 15 03:32:40 AM UTC 24 |
Oct 15 03:32:50 AM UTC 24 |
1841802783 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1128467501 |
|
|
Oct 15 03:32:51 AM UTC 24 |
Oct 15 03:32:53 AM UTC 24 |
61219602 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1565962967 |
|
|
Oct 15 03:31:35 AM UTC 24 |
Oct 15 03:32:58 AM UTC 24 |
131444369 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.1818473127 |
|
|
Oct 15 03:32:51 AM UTC 24 |
Oct 15 03:33:08 AM UTC 24 |
2254220062 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3571656658 |
|
|
Oct 15 03:30:45 AM UTC 24 |
Oct 15 03:33:09 AM UTC 24 |
3011409439 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.666511001 |
|
|
Oct 15 03:33:09 AM UTC 24 |
Oct 15 03:33:13 AM UTC 24 |
65484772 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.631448059 |
|
|
Oct 15 03:30:14 AM UTC 24 |
Oct 15 03:33:21 AM UTC 24 |
1734417754 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1083163802 |
|
|
Oct 15 03:27:41 AM UTC 24 |
Oct 15 03:33:25 AM UTC 24 |
1903688128 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.4116931367 |
|
|
Oct 15 03:33:22 AM UTC 24 |
Oct 15 03:33:25 AM UTC 24 |
39580086 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.881275511 |
|
|
Oct 15 03:32:59 AM UTC 24 |
Oct 15 03:33:32 AM UTC 24 |
1883504037 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.208001140 |
|
|
Oct 15 03:33:26 AM UTC 24 |
Oct 15 03:33:37 AM UTC 24 |
3065550429 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.270292123 |
|
|
Oct 15 03:20:25 AM UTC 24 |
Oct 15 03:34:16 AM UTC 24 |
12426471844 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3028670467 |
|
|
Oct 15 03:34:39 AM UTC 24 |
Oct 15 03:34:42 AM UTC 24 |
40297816 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.21996963 |
|
|
Oct 15 03:33:26 AM UTC 24 |
Oct 15 03:34:43 AM UTC 24 |
150074830 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1552158465 |
|
|
Oct 15 03:34:45 AM UTC 24 |
Oct 15 03:34:53 AM UTC 24 |
173963880 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3086777408 |
|
|
Oct 15 03:34:43 AM UTC 24 |
Oct 15 03:34:53 AM UTC 24 |
1367016660 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_readback_err.2813095285 |
|
|
Oct 15 03:34:54 AM UTC 24 |
Oct 15 03:34:56 AM UTC 24 |
32842500 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3933586129 |
|
|
Oct 15 03:31:28 AM UTC 24 |
Oct 15 03:35:17 AM UTC 24 |
12510148747 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1393626383 |
|
|
Oct 15 03:35:18 AM UTC 24 |
Oct 15 03:35:20 AM UTC 24 |
22346721 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1791401280 |
|
|
Oct 15 03:23:20 AM UTC 24 |
Oct 15 03:35:27 AM UTC 24 |
10932163014 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.226281435 |
|
|
Oct 15 03:31:02 AM UTC 24 |
Oct 15 03:35:32 AM UTC 24 |
5130472669 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3218662778 |
|
|
Oct 15 03:20:31 AM UTC 24 |
Oct 15 03:35:36 AM UTC 24 |
26162316157 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.238240046 |
|
|
Oct 15 03:35:21 AM UTC 24 |
Oct 15 03:35:38 AM UTC 24 |
1009954843 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.729674498 |
|
|
Oct 15 03:26:42 AM UTC 24 |
Oct 15 03:35:38 AM UTC 24 |
2723274987 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2532378794 |
|
|
Oct 15 03:18:12 AM UTC 24 |
Oct 15 03:35:42 AM UTC 24 |
7382442964 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3044326594 |
|
|
Oct 15 03:29:08 AM UTC 24 |
Oct 15 03:35:42 AM UTC 24 |
3373421297 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2924019915 |
|
|
Oct 15 03:35:38 AM UTC 24 |
Oct 15 03:35:58 AM UTC 24 |
2376106244 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1281153072 |
|
|
Oct 15 03:35:59 AM UTC 24 |
Oct 15 03:36:02 AM UTC 24 |
169019581 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1124362340 |
|
|
Oct 15 03:31:30 AM UTC 24 |
Oct 15 03:36:11 AM UTC 24 |
8088741517 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1465022673 |
|
|
Oct 15 03:35:43 AM UTC 24 |
Oct 15 03:36:23 AM UTC 24 |
193470559 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3358548650 |
|
|
Oct 15 03:18:54 AM UTC 24 |
Oct 15 03:36:37 AM UTC 24 |
10970188654 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2774331320 |
|
|
Oct 15 03:36:37 AM UTC 24 |
Oct 15 03:36:39 AM UTC 24 |
252120448 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1623433586 |
|
|
Oct 15 03:35:43 AM UTC 24 |
Oct 15 03:36:45 AM UTC 24 |
121204967 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2836131359 |
|
|
Oct 15 03:36:40 AM UTC 24 |
Oct 15 03:36:48 AM UTC 24 |
362563923 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.918051359 |
|
|
Oct 15 03:36:45 AM UTC 24 |
Oct 15 03:36:50 AM UTC 24 |
75191203 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_readback_err.65658475 |
|
|
Oct 15 03:36:49 AM UTC 24 |
Oct 15 03:36:51 AM UTC 24 |
32283756 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2007654562 |
|
|
Oct 15 03:35:33 AM UTC 24 |
Oct 15 03:36:55 AM UTC 24 |
3613248217 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2351859162 |
|
|
Oct 15 03:36:55 AM UTC 24 |
Oct 15 03:36:57 AM UTC 24 |
22269680 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.3731212222 |
|
|
Oct 15 03:27:43 AM UTC 24 |
Oct 15 03:37:05 AM UTC 24 |
7812597605 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.1542867893 |
|
|
Oct 15 03:21:26 AM UTC 24 |
Oct 15 03:37:12 AM UTC 24 |
48365527009 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.997260133 |
|
|
Oct 15 03:28:39 AM UTC 24 |
Oct 15 03:37:26 AM UTC 24 |
69970838669 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3086513828 |
|
|
Oct 15 03:27:20 AM UTC 24 |
Oct 15 03:37:26 AM UTC 24 |
74852856397 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.284355422 |
|
|
Oct 15 03:33:08 AM UTC 24 |
Oct 15 03:37:32 AM UTC 24 |
13894921935 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3206733531 |
|
|
Oct 15 03:37:50 AM UTC 24 |
Oct 15 03:37:53 AM UTC 24 |
150093976 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2868918262 |
|
|
Oct 15 03:37:28 AM UTC 24 |
Oct 15 03:37:55 AM UTC 24 |
1004984997 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2505639430 |
|
|
Oct 15 03:37:12 AM UTC 24 |
Oct 15 03:38:00 AM UTC 24 |
2602999666 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.2969809748 |
|
|
Oct 15 03:37:56 AM UTC 24 |
Oct 15 03:38:01 AM UTC 24 |
293466995 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1096680812 |
|
|
Oct 15 03:37:54 AM UTC 24 |
Oct 15 03:38:07 AM UTC 24 |
274594544 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3729410614 |
|
|
Oct 15 03:36:03 AM UTC 24 |
Oct 15 03:38:11 AM UTC 24 |
2195019680 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3779890363 |
|
|
Oct 15 03:38:12 AM UTC 24 |
Oct 15 03:38:14 AM UTC 24 |
43743266 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3329100979 |
|
|
Oct 15 03:38:15 AM UTC 24 |
Oct 15 03:38:23 AM UTC 24 |
81456921 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_readback_err.1847316108 |
|
|
Oct 15 03:38:24 AM UTC 24 |
Oct 15 03:38:26 AM UTC 24 |
30800268 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3804053484 |
|
|
Oct 15 03:38:22 AM UTC 24 |
Oct 15 03:38:27 AM UTC 24 |
65355746 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2326196662 |
|
|
Oct 15 03:33:13 AM UTC 24 |
Oct 15 03:38:35 AM UTC 24 |
32040226900 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.157018053 |
|
|
Oct 15 03:36:58 AM UTC 24 |
Oct 15 03:38:35 AM UTC 24 |
1440748788 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1419284337 |
|
|
Oct 15 03:38:36 AM UTC 24 |
Oct 15 03:38:38 AM UTC 24 |
16990136 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.3466583821 |
|
|
Oct 15 03:38:36 AM UTC 24 |
Oct 15 03:38:39 AM UTC 24 |
42308926 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.343592116 |
|
|
Oct 15 03:32:24 AM UTC 24 |
Oct 15 03:38:40 AM UTC 24 |
9482469913 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2709205593 |
|
|
Oct 15 03:31:23 AM UTC 24 |
Oct 15 03:39:02 AM UTC 24 |
31197187594 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3789566104 |
|
|
Oct 15 03:38:40 AM UTC 24 |
Oct 15 03:39:04 AM UTC 24 |
1045503766 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2243375804 |
|
|
Oct 15 03:39:03 AM UTC 24 |
Oct 15 03:39:07 AM UTC 24 |
475904212 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3147352094 |
|
|
Oct 15 03:26:07 AM UTC 24 |
Oct 15 03:39:10 AM UTC 24 |
26337930234 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.845024881 |
|
|
Oct 15 03:28:23 AM UTC 24 |
Oct 15 03:39:14 AM UTC 24 |
4207439564 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1295479525 |
|
|
Oct 15 03:39:15 AM UTC 24 |
Oct 15 03:39:21 AM UTC 24 |
711212983 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2380580869 |
|
|
Oct 15 03:32:02 AM UTC 24 |
Oct 15 03:39:24 AM UTC 24 |
1858319666 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1235889636 |
|
|
Oct 15 03:22:39 AM UTC 24 |
Oct 15 03:39:49 AM UTC 24 |
6347661722 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.385165969 |
|
|
Oct 15 03:20:38 AM UTC 24 |
Oct 15 03:40:03 AM UTC 24 |
13054737697 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3864199293 |
|
|
Oct 15 03:40:03 AM UTC 24 |
Oct 15 03:40:06 AM UTC 24 |
29791514 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.952269807 |
|
|
Oct 15 03:40:07 AM UTC 24 |
Oct 15 03:40:16 AM UTC 24 |
1736801887 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.4033729051 |
|
|
Oct 15 03:40:12 AM UTC 24 |
Oct 15 03:40:17 AM UTC 24 |
159453283 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_readback_err.2983586549 |
|
|
Oct 15 03:40:16 AM UTC 24 |
Oct 15 03:40:18 AM UTC 24 |
50523149 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1445866114 |
|
|
Oct 15 03:39:07 AM UTC 24 |
Oct 15 03:40:23 AM UTC 24 |
124309681 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.764058750 |
|
|
Oct 15 03:40:23 AM UTC 24 |
Oct 15 03:40:25 AM UTC 24 |
27146859 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.3126453548 |
|
|
Oct 15 03:40:27 AM UTC 24 |
Oct 15 03:40:30 AM UTC 24 |
76678731 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2061546238 |
|
|
Oct 15 03:35:39 AM UTC 24 |
Oct 15 03:40:37 AM UTC 24 |
14512261612 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2175594681 |
|
|
Oct 15 03:39:10 AM UTC 24 |
Oct 15 03:40:51 AM UTC 24 |
159190465 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3008523457 |
|
|
Oct 15 03:39:22 AM UTC 24 |
Oct 15 03:40:53 AM UTC 24 |
1191447322 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1841306138 |
|
|
Oct 15 03:35:37 AM UTC 24 |
Oct 15 03:40:56 AM UTC 24 |
28734844927 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2212334937 |
|
|
Oct 15 03:40:38 AM UTC 24 |
Oct 15 03:41:07 AM UTC 24 |
1382864672 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.459322253 |
|
|
Oct 15 03:37:27 AM UTC 24 |
Oct 15 03:41:10 AM UTC 24 |
4399700065 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3728964516 |
|
|
Oct 15 03:19:06 AM UTC 24 |
Oct 15 03:41:12 AM UTC 24 |
66658163235 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3402774273 |
|
|
Oct 15 03:41:11 AM UTC 24 |
Oct 15 03:41:18 AM UTC 24 |
738457686 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3004089740 |
|
|
Oct 15 03:40:56 AM UTC 24 |
Oct 15 03:41:42 AM UTC 24 |
468339505 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1418479898 |
|
|
Oct 15 03:30:36 AM UTC 24 |
Oct 15 03:41:45 AM UTC 24 |
335049731166 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2970628539 |
|
|
Oct 15 03:41:46 AM UTC 24 |
Oct 15 03:41:48 AM UTC 24 |
50300908 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.28108616 |
|
|
Oct 15 03:24:34 AM UTC 24 |
Oct 15 03:41:54 AM UTC 24 |
4213765336 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1484888984 |
|
|
Oct 15 03:41:55 AM UTC 24 |
Oct 15 03:42:01 AM UTC 24 |
90755720 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1087957611 |
|
|
Oct 15 03:41:49 AM UTC 24 |
Oct 15 03:42:02 AM UTC 24 |
1194404975 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_readback_err.262786850 |
|
|
Oct 15 03:42:02 AM UTC 24 |
Oct 15 03:42:04 AM UTC 24 |
53698695 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.3962264333 |
|
|
Oct 15 03:40:52 AM UTC 24 |
Oct 15 03:42:09 AM UTC 24 |
2701016597 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2016070971 |
|
|
Oct 15 03:42:10 AM UTC 24 |
Oct 15 03:42:12 AM UTC 24 |
13999731 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1679797967 |
|
|
Oct 15 03:32:10 AM UTC 24 |
Oct 15 03:42:13 AM UTC 24 |
2556637314 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.955215222 |
|
|
Oct 15 03:37:06 AM UTC 24 |
Oct 15 03:42:16 AM UTC 24 |
1236403883 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.3471625880 |
|
|
Oct 15 03:42:14 AM UTC 24 |
Oct 15 03:42:19 AM UTC 24 |
153855230 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2466570610 |
|
|
Oct 15 03:42:03 AM UTC 24 |
Oct 15 03:42:19 AM UTC 24 |
648763157 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.3009874088 |
|
|
Oct 15 03:33:38 AM UTC 24 |
Oct 15 03:42:26 AM UTC 24 |
6708985151 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.1464248388 |
|
|
Oct 15 03:39:25 AM UTC 24 |
Oct 15 03:42:27 AM UTC 24 |
7054803609 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1264689140 |
|
|
Oct 15 03:41:09 AM UTC 24 |
Oct 15 03:42:35 AM UTC 24 |
1057211497 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3316455689 |
|
|
Oct 15 03:38:01 AM UTC 24 |
Oct 15 03:42:36 AM UTC 24 |
6535364129 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2078432634 |
|
|
Oct 15 03:42:20 AM UTC 24 |
Oct 15 03:42:40 AM UTC 24 |
612941276 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.583704593 |
|
|
Oct 15 03:42:37 AM UTC 24 |
Oct 15 03:42:41 AM UTC 24 |
152538530 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.2456515701 |
|
|
Oct 15 03:42:17 AM UTC 24 |
Oct 15 03:42:45 AM UTC 24 |
25371663698 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2624338379 |
|
|
Oct 15 03:42:37 AM UTC 24 |
Oct 15 03:42:46 AM UTC 24 |
4310853122 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3501469105 |
|
|
Oct 15 03:29:54 AM UTC 24 |
Oct 15 03:42:46 AM UTC 24 |
3633476539 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.2941261960 |
|
|
Oct 15 03:42:47 AM UTC 24 |
Oct 15 03:42:50 AM UTC 24 |
83108716 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.4288481739 |
|
|
Oct 15 03:25:04 AM UTC 24 |
Oct 15 03:42:51 AM UTC 24 |
32452407427 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.1889688731 |
|
|
Oct 15 03:22:45 AM UTC 24 |
Oct 15 03:42:52 AM UTC 24 |
88740687652 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.391708363 |
|
|
Oct 15 03:42:29 AM UTC 24 |
Oct 15 03:42:54 AM UTC 24 |
310279569 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_readback_err.109598871 |
|
|
Oct 15 03:42:52 AM UTC 24 |
Oct 15 03:42:54 AM UTC 24 |
29503218 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.550829327 |
|
|
Oct 15 03:42:55 AM UTC 24 |
Oct 15 03:42:57 AM UTC 24 |
47342333 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3864802699 |
|
|
Oct 15 03:42:47 AM UTC 24 |
Oct 15 03:42:58 AM UTC 24 |
1837731482 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.410641183 |
|
|
Oct 15 03:42:58 AM UTC 24 |
Oct 15 03:43:17 AM UTC 24 |
779295794 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1849011647 |
|
|
Oct 15 03:42:51 AM UTC 24 |
Oct 15 03:42:59 AM UTC 24 |
155922902 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.274918832 |
|
|
Oct 15 03:33:33 AM UTC 24 |
Oct 15 03:43:13 AM UTC 24 |
7011169358 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.601003713 |
|
|
Oct 15 03:29:00 AM UTC 24 |
Oct 15 03:43:17 AM UTC 24 |
17751275949 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.828901170 |
|
|
Oct 15 03:40:42 AM UTC 24 |
Oct 15 03:43:25 AM UTC 24 |
2826875985 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3295604914 |
|
|
Oct 15 03:42:14 AM UTC 24 |
Oct 15 03:43:33 AM UTC 24 |
3964575662 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.321817247 |
|
|
Oct 15 03:43:18 AM UTC 24 |
Oct 15 03:43:42 AM UTC 24 |
1200291563 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.3088000370 |
|
|
Oct 15 03:43:00 AM UTC 24 |
Oct 15 03:43:43 AM UTC 24 |
8139075690 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.870805686 |
|
|
Oct 15 03:43:34 AM UTC 24 |
Oct 15 03:43:43 AM UTC 24 |
240117854 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.682930118 |
|
|
Oct 15 03:43:27 AM UTC 24 |
Oct 15 03:43:44 AM UTC 24 |
203651035 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2316843434 |
|
|
Oct 15 03:43:43 AM UTC 24 |
Oct 15 03:43:51 AM UTC 24 |
1175618731 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2657453755 |
|
|
Oct 15 03:43:52 AM UTC 24 |
Oct 15 03:43:54 AM UTC 24 |
30242720 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.833623803 |
|
|
Oct 15 03:26:02 AM UTC 24 |
Oct 15 03:43:56 AM UTC 24 |
3753186683 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3734350334 |
|
|
Oct 15 03:43:57 AM UTC 24 |
Oct 15 03:44:03 AM UTC 24 |
121151044 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_readback_err.3770847162 |
|
|
Oct 15 03:44:04 AM UTC 24 |
Oct 15 03:44:06 AM UTC 24 |
320097074 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2469024694 |
|
|
Oct 15 03:43:55 AM UTC 24 |
Oct 15 03:44:07 AM UTC 24 |
1165719860 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3686364679 |
|
|
Oct 15 03:44:27 AM UTC 24 |
Oct 15 03:44:29 AM UTC 24 |
52452401 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3372277824 |
|
|
Oct 15 03:34:17 AM UTC 24 |
Oct 15 03:44:33 AM UTC 24 |
4475308006 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.740066131 |
|
|
Oct 15 03:27:46 AM UTC 24 |
Oct 15 03:44:33 AM UTC 24 |
94755765525 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2156403407 |
|
|
Oct 15 03:38:42 AM UTC 24 |
Oct 15 03:44:35 AM UTC 24 |
45627738709 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3808531239 |
|
|
Oct 15 03:44:07 AM UTC 24 |
Oct 15 03:44:36 AM UTC 24 |
500143513 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.3910473856 |
|
|
Oct 15 03:44:37 AM UTC 24 |
Oct 15 03:44:40 AM UTC 24 |
152195576 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.3027017080 |
|
|
Oct 15 03:49:09 AM UTC 24 |
Oct 15 03:49:36 AM UTC 24 |
369489606 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.421005180 |
|
|
Oct 15 03:44:30 AM UTC 24 |
Oct 15 03:44:48 AM UTC 24 |
787982884 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1615999605 |
|
|
Oct 15 03:44:48 AM UTC 24 |
Oct 15 03:44:54 AM UTC 24 |
314972028 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3253684663 |
|
|
Oct 15 03:44:48 AM UTC 24 |
Oct 15 03:44:56 AM UTC 24 |
321700256 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2833125310 |
|
|
Oct 15 03:39:05 AM UTC 24 |
Oct 15 03:44:58 AM UTC 24 |
11608639624 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3885434735 |
|
|
Oct 15 03:40:53 AM UTC 24 |
Oct 15 03:45:03 AM UTC 24 |
51832232085 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2062740794 |
|
|
Oct 15 03:44:56 AM UTC 24 |
Oct 15 03:45:03 AM UTC 24 |
416811979 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2569227531 |
|
|
Oct 15 03:45:04 AM UTC 24 |
Oct 15 03:45:06 AM UTC 24 |
28782466 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.298847098 |
|
|
Oct 15 03:37:33 AM UTC 24 |
Oct 15 03:45:13 AM UTC 24 |
54348064517 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2267115707 |
|
|
Oct 15 03:45:15 AM UTC 24 |
Oct 15 03:45:19 AM UTC 24 |
671502606 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2292423359 |
|
|
Oct 15 03:45:07 AM UTC 24 |
Oct 15 03:45:22 AM UTC 24 |
549286578 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3510368822 |
|
|
Oct 15 03:45:21 AM UTC 24 |
Oct 15 03:45:23 AM UTC 24 |
94898312 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.654932023 |
|
|
Oct 15 03:44:34 AM UTC 24 |
Oct 15 03:45:25 AM UTC 24 |
5122370406 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.4294225330 |
|
|
Oct 15 03:45:26 AM UTC 24 |
Oct 15 03:45:28 AM UTC 24 |
18226927 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1454149328 |
|
|
Oct 15 03:34:54 AM UTC 24 |
Oct 15 03:45:32 AM UTC 24 |
24418609359 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2212221314 |
|
|
Oct 15 03:42:20 AM UTC 24 |
Oct 15 03:45:35 AM UTC 24 |
1951662646 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1173168294 |
|
|
Oct 15 03:41:43 AM UTC 24 |
Oct 15 03:45:50 AM UTC 24 |
10447387358 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1898752596 |
|
|
Oct 15 03:40:31 AM UTC 24 |
Oct 15 03:45:57 AM UTC 24 |
22941224269 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.4226468434 |
|
|
Oct 15 03:36:24 AM UTC 24 |
Oct 15 03:46:00 AM UTC 24 |
2217321032 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3288926525 |
|
|
Oct 15 03:38:39 AM UTC 24 |
Oct 15 03:46:06 AM UTC 24 |
15772981172 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1242363920 |
|
|
Oct 15 03:46:06 AM UTC 24 |
Oct 15 03:46:15 AM UTC 24 |
558119112 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3277750977 |
|
|
Oct 15 03:45:58 AM UTC 24 |
Oct 15 03:46:26 AM UTC 24 |
616536421 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3221755874 |
|
|
Oct 15 03:46:28 AM UTC 24 |
Oct 15 03:46:34 AM UTC 24 |
263509035 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2278595130 |
|
|
Oct 15 03:45:29 AM UTC 24 |
Oct 15 03:46:41 AM UTC 24 |
563803939 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1107197489 |
|
|
Oct 15 03:45:36 AM UTC 24 |
Oct 15 03:47:01 AM UTC 24 |
8439557623 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1641909008 |
|
|
Oct 15 03:47:04 AM UTC 24 |
Oct 15 03:47:06 AM UTC 24 |
48458176 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1740120029 |
|
|
Oct 15 03:38:02 AM UTC 24 |
Oct 15 03:47:12 AM UTC 24 |
1954166292 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1986775001 |
|
|
Oct 15 03:47:07 AM UTC 24 |
Oct 15 03:47:14 AM UTC 24 |
154996053 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_readback_err.497587600 |
|
|
Oct 15 03:47:13 AM UTC 24 |
Oct 15 03:47:16 AM UTC 24 |
28483588 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4071627792 |
|
|
Oct 15 03:47:13 AM UTC 24 |
Oct 15 03:47:18 AM UTC 24 |
136572077 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2356760768 |
|
|
Oct 15 03:47:19 AM UTC 24 |
Oct 15 03:47:21 AM UTC 24 |
13817133 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1288198512 |
|
|
Oct 15 03:47:14 AM UTC 24 |
Oct 15 03:47:28 AM UTC 24 |
332899118 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.572930881 |
|
|
Oct 15 03:47:22 AM UTC 24 |
Oct 15 03:47:40 AM UTC 24 |
1265787013 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3642269433 |
|
|
Oct 15 03:44:36 AM UTC 24 |
Oct 15 03:47:55 AM UTC 24 |
7997534010 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2961712117 |
|
|
Oct 15 03:46:16 AM UTC 24 |
Oct 15 03:48:00 AM UTC 24 |
287408758 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2492460971 |
|
|
Oct 15 03:42:26 AM UTC 24 |
Oct 15 03:48:24 AM UTC 24 |
18869331462 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.4251148815 |
|
|
Oct 15 03:48:02 AM UTC 24 |
Oct 15 03:48:32 AM UTC 24 |
3508174926 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3747643315 |
|
|
Oct 15 03:35:28 AM UTC 24 |
Oct 15 03:48:35 AM UTC 24 |
29116295838 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3384252799 |
|
|
Oct 15 03:47:41 AM UTC 24 |
Oct 15 03:48:48 AM UTC 24 |
8127977945 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.292615574 |
|
|
Oct 15 03:44:33 AM UTC 24 |
Oct 15 03:48:52 AM UTC 24 |
15942924776 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.209583675 |
|
|
Oct 15 03:48:36 AM UTC 24 |
Oct 15 03:48:53 AM UTC 24 |
321975526 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2883347645 |
|
|
Oct 15 03:43:18 AM UTC 24 |
Oct 15 03:48:53 AM UTC 24 |
3394435102 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2782121744 |
|
|
Oct 15 03:48:33 AM UTC 24 |
Oct 15 03:48:55 AM UTC 24 |
157196042 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3011005552 |
|
|
Oct 15 03:48:55 AM UTC 24 |
Oct 15 03:48:57 AM UTC 24 |
43634956 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1593020450 |
|
|
Oct 15 03:48:48 AM UTC 24 |
Oct 15 03:49:00 AM UTC 24 |
1418306043 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2988462110 |
|
|
Oct 15 03:32:54 AM UTC 24 |
Oct 15 03:49:01 AM UTC 24 |
23421719464 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_readback_err.2369779514 |
|
|
Oct 15 03:49:02 AM UTC 24 |
Oct 15 03:49:04 AM UTC 24 |
79785179 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.3081481695 |
|
|
Oct 15 03:39:50 AM UTC 24 |
Oct 15 03:49:06 AM UTC 24 |
6517491137 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2343432092 |
|
|
Oct 15 03:49:02 AM UTC 24 |
Oct 15 03:49:07 AM UTC 24 |
99445236 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.131828274 |
|
|
Oct 15 03:48:58 AM UTC 24 |
Oct 15 03:49:08 AM UTC 24 |
244889784 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.4193442208 |
|
|
Oct 15 03:49:08 AM UTC 24 |
Oct 15 03:49:11 AM UTC 24 |
22347984 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.4083175753 |
|
|
Oct 15 03:45:51 AM UTC 24 |
Oct 15 03:49:13 AM UTC 24 |
1635176760 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2551347881 |
|
|
Oct 15 03:38:28 AM UTC 24 |
Oct 15 03:49:25 AM UTC 24 |
10431015003 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1959900279 |
|
|
Oct 15 03:42:46 AM UTC 24 |
Oct 15 03:49:27 AM UTC 24 |
9284943280 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.156264674 |
|
|
Oct 15 03:49:28 AM UTC 24 |
Oct 15 03:49:40 AM UTC 24 |
387469562 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1659641720 |
|
|
Oct 15 03:44:41 AM UTC 24 |
Oct 15 03:49:51 AM UTC 24 |
49709863877 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3403105577 |
|
|
Oct 15 03:46:01 AM UTC 24 |
Oct 15 03:49:55 AM UTC 24 |
5964015375 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.911348258 |
|
|
Oct 15 03:42:41 AM UTC 24 |
Oct 15 03:49:59 AM UTC 24 |
12975145190 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.805107548 |
|
|
Oct 15 03:49:55 AM UTC 24 |
Oct 15 03:49:59 AM UTC 24 |
114868808 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2170893310 |
|
|
Oct 15 03:49:41 AM UTC 24 |
Oct 15 03:49:59 AM UTC 24 |
287632695 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.596637955 |
|
|
Oct 15 03:46:35 AM UTC 24 |
Oct 15 03:50:10 AM UTC 24 |
834427524 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2737187576 |
|
|
Oct 15 03:50:11 AM UTC 24 |
Oct 15 03:50:13 AM UTC 24 |
30407899 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1836261253 |
|
|
Oct 15 03:43:14 AM UTC 24 |
Oct 15 03:50:26 AM UTC 24 |
13863765642 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1650331022 |
|
|
Oct 15 03:49:06 AM UTC 24 |
Oct 15 03:50:27 AM UTC 24 |
2957895596 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1022750592 |
|
|
Oct 15 03:48:54 AM UTC 24 |
Oct 15 03:50:28 AM UTC 24 |
960360947 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.4009375374 |
|
|
Oct 15 03:50:14 AM UTC 24 |
Oct 15 03:50:30 AM UTC 24 |
457077438 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_readback_err.3909605864 |
|
|
Oct 15 03:50:28 AM UTC 24 |
Oct 15 03:50:30 AM UTC 24 |
55617299 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.765066187 |
|
|
Oct 15 03:49:14 AM UTC 24 |
Oct 15 03:50:30 AM UTC 24 |
4015310820 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.233231060 |
|
|
Oct 15 03:50:31 AM UTC 24 |
Oct 15 03:50:33 AM UTC 24 |
15621850 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3289419212 |
|
|
Oct 15 03:50:28 AM UTC 24 |
Oct 15 03:50:33 AM UTC 24 |
115251109 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.205972807 |
|
|
Oct 15 03:38:08 AM UTC 24 |
Oct 15 03:50:37 AM UTC 24 |
34606019090 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1162622545 |
|
|
Oct 15 03:50:31 AM UTC 24 |
Oct 15 03:50:51 AM UTC 24 |
231621094 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2778952873 |
|
|
Oct 15 03:49:52 AM UTC 24 |
Oct 15 03:51:10 AM UTC 24 |
136928838 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2114954229 |
|
|
Oct 15 03:50:52 AM UTC 24 |
Oct 15 03:51:13 AM UTC 24 |
260911368 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1034567202 |
|
|
Oct 15 03:21:09 AM UTC 24 |
Oct 15 03:51:15 AM UTC 24 |
15508096350 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.95457652 |
|
|
Oct 15 03:24:31 AM UTC 24 |
Oct 15 03:51:16 AM UTC 24 |
15300289199 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.476143058 |
|
|
Oct 15 03:51:16 AM UTC 24 |
Oct 15 03:51:25 AM UTC 24 |
966152351 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3901384742 |
|
|
Oct 15 03:51:16 AM UTC 24 |
Oct 15 03:52:11 AM UTC 24 |
155094811 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.359129502 |
|
|
Oct 15 03:41:13 AM UTC 24 |
Oct 15 03:52:13 AM UTC 24 |
7222350761 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1078992853 |
|
|
Oct 15 03:50:34 AM UTC 24 |
Oct 15 03:52:16 AM UTC 24 |
3972834328 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1630066874 |
|
|
Oct 15 03:52:14 AM UTC 24 |
Oct 15 03:52:16 AM UTC 24 |
36742562 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3344705356 |
|
|
Oct 15 03:52:17 AM UTC 24 |
Oct 15 03:52:25 AM UTC 24 |
97994056 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_readback_err.1330648573 |
|
|
Oct 15 03:52:26 AM UTC 24 |
Oct 15 03:52:29 AM UTC 24 |
71508464 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.3052799587 |
|
|
Oct 15 03:45:04 AM UTC 24 |
Oct 15 03:52:31 AM UTC 24 |
52848755761 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1177016 |
|
|
Oct 15 03:52:17 AM UTC 24 |
Oct 15 03:52:32 AM UTC 24 |
1842651613 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1829796995 |
|
|
Oct 15 03:52:34 AM UTC 24 |
Oct 15 03:52:36 AM UTC 24 |
36667060 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.1756146349 |
|
|
Oct 15 03:52:37 AM UTC 24 |
Oct 15 03:52:53 AM UTC 24 |
1801395442 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.182131139 |
|
|
Oct 15 03:48:26 AM UTC 24 |
Oct 15 03:53:07 AM UTC 24 |
38647811565 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2799415954 |
|
|
Oct 15 03:52:30 AM UTC 24 |
Oct 15 03:53:13 AM UTC 24 |
3685426657 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3398376704 |
|
|
Oct 15 03:49:37 AM UTC 24 |
Oct 15 03:53:22 AM UTC 24 |
12479556273 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.2483683675 |
|
|
Oct 15 03:50:37 AM UTC 24 |
Oct 15 03:53:26 AM UTC 24 |
3106381986 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2598673480 |
|
|
Oct 15 03:42:59 AM UTC 24 |
Oct 15 03:53:33 AM UTC 24 |
8982949455 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.4215872430 |
|
|
Oct 15 03:51:14 AM UTC 24 |
Oct 15 03:53:35 AM UTC 24 |
2598133427 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2509743269 |
|
|
Oct 15 03:30:50 AM UTC 24 |
Oct 15 03:53:36 AM UTC 24 |
35321904186 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1417131813 |
|
|
Oct 15 03:53:22 AM UTC 24 |
Oct 15 03:53:39 AM UTC 24 |
102004848 ps |