| T305 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1165952970 |
|
|
Feb 08 11:56:19 AM UTC 25 |
Feb 08 11:56:37 AM UTC 25 |
2288488940 ps |
| T306 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2008735449 |
|
|
Feb 08 11:52:26 AM UTC 25 |
Feb 08 11:56:45 AM UTC 25 |
2693367697 ps |
| T307 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1196468447 |
|
|
Feb 08 11:56:45 AM UTC 25 |
Feb 08 11:56:49 AM UTC 25 |
82526729 ps |
| T308 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3944452928 |
|
|
Feb 08 11:56:50 AM UTC 25 |
Feb 08 11:57:01 AM UTC 25 |
1526434341 ps |
| T309 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.661086409 |
|
|
Feb 08 11:49:40 AM UTC 25 |
Feb 08 11:57:06 AM UTC 25 |
23992355444 ps |
| T310 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3744070517 |
|
|
Feb 08 11:50:52 AM UTC 25 |
Feb 08 11:57:10 AM UTC 25 |
49584643275 ps |
| T311 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3452533893 |
|
|
Feb 08 11:57:22 AM UTC 25 |
Feb 08 11:57:24 AM UTC 25 |
181404884 ps |
| T312 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2135444583 |
|
|
Feb 08 11:55:21 AM UTC 25 |
Feb 08 11:57:28 AM UTC 25 |
586146592 ps |
| T313 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4248238009 |
|
|
Feb 08 11:57:25 AM UTC 25 |
Feb 08 11:57:33 AM UTC 25 |
230657780 ps |
| T314 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.4060564958 |
|
|
Feb 08 11:57:29 AM UTC 25 |
Feb 08 11:57:34 AM UTC 25 |
185003565 ps |
| T315 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.3666758824 |
|
|
Feb 08 11:56:16 AM UTC 25 |
Feb 08 11:57:41 AM UTC 25 |
2095438080 ps |
| T316 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.4010093110 |
|
|
Feb 08 11:57:42 AM UTC 25 |
Feb 08 11:57:45 AM UTC 25 |
85100946 ps |
| T317 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2149416353 |
|
|
Feb 08 11:53:45 AM UTC 25 |
Feb 08 11:57:45 AM UTC 25 |
16332850633 ps |
| T318 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.1170218132 |
|
|
Feb 08 11:50:05 AM UTC 25 |
Feb 08 11:57:50 AM UTC 25 |
18806663468 ps |
| T319 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2557757506 |
|
|
Feb 08 11:54:57 AM UTC 25 |
Feb 08 11:57:58 AM UTC 25 |
6105648688 ps |
| T320 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.718382856 |
|
|
Feb 08 11:57:45 AM UTC 25 |
Feb 08 11:58:02 AM UTC 25 |
938027150 ps |
| T321 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3066372370 |
|
|
Feb 08 11:58:04 AM UTC 25 |
Feb 08 11:58:09 AM UTC 25 |
131527452 ps |
| T322 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3991619882 |
|
|
Feb 08 11:53:03 AM UTC 25 |
Feb 08 11:58:12 AM UTC 25 |
1139655868 ps |
| T323 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2281124 |
|
|
Feb 08 11:44:05 AM UTC 25 |
Feb 08 11:58:19 AM UTC 25 |
11865661294 ps |
| T324 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.688017993 |
|
|
Feb 08 11:57:51 AM UTC 25 |
Feb 08 11:58:19 AM UTC 25 |
1809729591 ps |
| T325 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3389166815 |
|
|
Feb 08 11:56:37 AM UTC 25 |
Feb 08 11:58:25 AM UTC 25 |
138425138 ps |
| T326 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3208832498 |
|
|
Feb 08 11:58:20 AM UTC 25 |
Feb 08 11:58:28 AM UTC 25 |
3001186599 ps |
| T327 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1500061643 |
|
|
Feb 08 11:37:58 AM UTC 25 |
Feb 08 11:58:33 AM UTC 25 |
11421798847 ps |
| T328 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1684354893 |
|
|
Feb 08 11:45:21 AM UTC 25 |
Feb 08 11:58:37 AM UTC 25 |
24353053239 ps |
| T329 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2758949705 |
|
|
Feb 08 11:58:38 AM UTC 25 |
Feb 08 11:58:41 AM UTC 25 |
48310343 ps |
| T330 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.1115623103 |
|
|
Feb 08 11:48:08 AM UTC 25 |
Feb 08 11:58:52 AM UTC 25 |
3452656422 ps |
| T331 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2992783681 |
|
|
Feb 08 11:58:41 AM UTC 25 |
Feb 08 11:58:53 AM UTC 25 |
531290724 ps |
| T332 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3548950925 |
|
|
Feb 08 11:58:53 AM UTC 25 |
Feb 08 11:59:03 AM UTC 25 |
253095221 ps |
| T333 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3516516554 |
|
|
Feb 08 11:41:16 AM UTC 25 |
Feb 08 11:59:04 AM UTC 25 |
12922282642 ps |
| T334 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.14677995 |
|
|
Feb 08 11:59:06 AM UTC 25 |
Feb 08 11:59:08 AM UTC 25 |
16371723 ps |
| T335 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.3607988941 |
|
|
Feb 08 11:59:09 AM UTC 25 |
Feb 08 11:59:29 AM UTC 25 |
313371951 ps |
| T336 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1185624515 |
|
|
Feb 08 11:56:13 AM UTC 25 |
Feb 08 11:59:30 AM UTC 25 |
1306473279 ps |
| T337 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2516082200 |
|
|
Feb 08 11:58:13 AM UTC 25 |
Feb 08 11:59:35 AM UTC 25 |
392297510 ps |
| T338 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2031500904 |
|
|
Feb 08 11:58:20 AM UTC 25 |
Feb 08 12:00:02 PM UTC 25 |
142801167 ps |
| T339 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2347509375 |
|
|
Feb 08 11:54:45 AM UTC 25 |
Feb 08 12:00:11 PM UTC 25 |
8019442627 ps |
| T340 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3489490217 |
|
|
Feb 08 11:45:13 AM UTC 25 |
Feb 08 12:00:16 PM UTC 25 |
9012499445 ps |
| T341 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1132876269 |
|
|
Feb 08 11:52:37 AM UTC 25 |
Feb 08 12:00:22 PM UTC 25 |
113834819242 ps |
| T342 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2758847417 |
|
|
Feb 08 11:59:31 AM UTC 25 |
Feb 08 12:00:33 PM UTC 25 |
3817682325 ps |
| T343 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.2298561275 |
|
|
Feb 08 11:50:27 AM UTC 25 |
Feb 08 12:00:39 PM UTC 25 |
11637472133 ps |
| T344 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.4096501028 |
|
|
Feb 08 12:00:30 PM UTC 25 |
Feb 08 12:00:47 PM UTC 25 |
141322417 ps |
| T345 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1435506411 |
|
|
Feb 08 12:00:34 PM UTC 25 |
Feb 08 12:00:48 PM UTC 25 |
2515714003 ps |
| T346 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2448949553 |
|
|
Feb 08 12:00:22 PM UTC 25 |
Feb 08 12:00:52 PM UTC 25 |
477634911 ps |
| T347 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.298580419 |
|
|
Feb 08 12:00:53 PM UTC 25 |
Feb 08 12:00:56 PM UTC 25 |
83728449 ps |
| T348 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.889591115 |
|
|
Feb 08 12:00:30 PM UTC 25 |
Feb 08 12:01:05 PM UTC 25 |
177537230 ps |
| T137 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.3237586891 |
|
|
Feb 08 11:49:11 AM UTC 25 |
Feb 08 12:01:14 PM UTC 25 |
77923702317 ps |
| T349 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2479930816 |
|
|
Feb 08 12:00:56 PM UTC 25 |
Feb 08 12:01:14 PM UTC 25 |
850592328 ps |
| T350 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2911512530 |
|
|
Feb 08 11:49:04 AM UTC 25 |
Feb 08 12:01:14 PM UTC 25 |
62516724654 ps |
| T351 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.4153700965 |
|
|
Feb 08 12:01:05 PM UTC 25 |
Feb 08 12:01:15 PM UTC 25 |
202597225 ps |
| T352 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1851252720 |
|
|
Feb 08 11:56:24 AM UTC 25 |
Feb 08 12:01:16 PM UTC 25 |
51043759604 ps |
| T353 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1055870431 |
|
|
Feb 08 12:01:16 PM UTC 25 |
Feb 08 12:01:18 PM UTC 25 |
12859804 ps |
| T354 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2161259565 |
|
|
Feb 08 11:44:33 AM UTC 25 |
Feb 08 12:01:19 PM UTC 25 |
14614714064 ps |
| T355 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2047869238 |
|
|
Feb 08 11:57:59 AM UTC 25 |
Feb 08 12:01:26 PM UTC 25 |
1696185226 ps |
| T356 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.522964924 |
|
|
Feb 08 11:58:53 AM UTC 25 |
Feb 08 12:01:27 PM UTC 25 |
1087679409 ps |
| T357 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3593167486 |
|
|
Feb 08 11:48:34 AM UTC 25 |
Feb 08 12:01:36 PM UTC 25 |
7370460757 ps |
| T358 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.637758079 |
|
|
Feb 08 11:56:18 AM UTC 25 |
Feb 08 12:01:42 PM UTC 25 |
13429036207 ps |
| T359 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.767774335 |
|
|
Feb 08 12:01:27 PM UTC 25 |
Feb 08 12:01:43 PM UTC 25 |
1249683804 ps |
| T360 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2585869852 |
|
|
Feb 08 12:01:43 PM UTC 25 |
Feb 08 12:01:53 PM UTC 25 |
593678721 ps |
| T361 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.174656312 |
|
|
Feb 08 11:53:46 AM UTC 25 |
Feb 08 12:01:55 PM UTC 25 |
68704380379 ps |
| T362 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.4168111439 |
|
|
Feb 08 11:53:42 AM UTC 25 |
Feb 08 12:02:08 PM UTC 25 |
5600016970 ps |
| T363 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.884541791 |
|
|
Feb 08 11:53:08 AM UTC 25 |
Feb 08 12:02:11 PM UTC 25 |
11377429114 ps |
| T364 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3186895212 |
|
|
Feb 08 12:02:09 PM UTC 25 |
Feb 08 12:02:11 PM UTC 25 |
88847992 ps |
| T365 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3734890472 |
|
|
Feb 08 11:55:10 AM UTC 25 |
Feb 08 12:02:15 PM UTC 25 |
12419885064 ps |
| T366 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.20851190 |
|
|
Feb 08 12:02:13 PM UTC 25 |
Feb 08 12:02:19 PM UTC 25 |
245303400 ps |
| T146 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.2921278693 |
|
|
Feb 08 11:37:19 AM UTC 25 |
Feb 08 12:02:23 PM UTC 25 |
40089299861 ps |
| T367 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2997751439 |
|
|
Feb 08 12:02:24 PM UTC 25 |
Feb 08 12:02:26 PM UTC 25 |
23786878 ps |
| T147 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1396619905 |
|
|
Feb 08 11:47:07 AM UTC 25 |
Feb 08 12:02:27 PM UTC 25 |
15239537139 ps |
| T368 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.1107846234 |
|
|
Feb 08 12:02:12 PM UTC 25 |
Feb 08 12:02:28 PM UTC 25 |
2220717909 ps |
| T369 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3207274056 |
|
|
Feb 08 11:42:01 AM UTC 25 |
Feb 08 12:02:35 PM UTC 25 |
10103074895 ps |
| T370 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3583881884 |
|
|
Feb 08 12:01:37 PM UTC 25 |
Feb 08 12:02:37 PM UTC 25 |
408749359 ps |
| T371 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2254348637 |
|
|
Feb 08 12:02:38 PM UTC 25 |
Feb 08 12:02:49 PM UTC 25 |
1238096283 ps |
| T372 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.1554896199 |
|
|
Feb 08 12:02:28 PM UTC 25 |
Feb 08 12:02:49 PM UTC 25 |
233504208 ps |
| T373 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.5644891 |
|
|
Feb 08 12:02:50 PM UTC 25 |
Feb 08 12:02:53 PM UTC 25 |
372628726 ps |
| T136 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.4190177507 |
|
|
Feb 08 12:00:49 PM UTC 25 |
Feb 08 12:02:54 PM UTC 25 |
914396738 ps |
| T374 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3777642582 |
|
|
Feb 08 11:59:36 AM UTC 25 |
Feb 08 12:02:57 PM UTC 25 |
4253465704 ps |
| T375 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.1878561376 |
|
|
Feb 08 12:01:19 PM UTC 25 |
Feb 08 12:03:02 PM UTC 25 |
16717190026 ps |
| T376 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2128831404 |
|
|
Feb 08 12:01:16 PM UTC 25 |
Feb 08 12:03:03 PM UTC 25 |
572265585 ps |
| T377 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.2145213642 |
|
|
Feb 08 12:02:55 PM UTC 25 |
Feb 08 12:03:06 PM UTC 25 |
1821558528 ps |
| T378 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.409281974 |
|
|
Feb 08 11:46:57 AM UTC 25 |
Feb 08 12:03:08 PM UTC 25 |
5092651030 ps |
| T379 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.440624586 |
|
|
Feb 08 12:03:06 PM UTC 25 |
Feb 08 12:03:09 PM UTC 25 |
43253011 ps |
| T380 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.245188237 |
|
|
Feb 08 12:01:43 PM UTC 25 |
Feb 08 12:03:17 PM UTC 25 |
2716183254 ps |
| T381 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3551873536 |
|
|
Feb 08 12:03:11 PM UTC 25 |
Feb 08 12:03:19 PM UTC 25 |
315729477 ps |
| T382 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1018555366 |
|
|
Feb 08 12:03:09 PM UTC 25 |
Feb 08 12:03:24 PM UTC 25 |
3403755115 ps |
| T383 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3942097210 |
|
|
Feb 08 12:03:26 PM UTC 25 |
Feb 08 12:03:28 PM UTC 25 |
54996386 ps |
| T384 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2272434191 |
|
|
Feb 08 12:02:54 PM UTC 25 |
Feb 08 12:03:31 PM UTC 25 |
134959748 ps |
| T385 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.641663005 |
|
|
Feb 08 11:49:32 AM UTC 25 |
Feb 08 12:03:32 PM UTC 25 |
3158655418 ps |
| T386 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.1380554786 |
|
|
Feb 08 12:03:30 PM UTC 25 |
Feb 08 12:03:50 PM UTC 25 |
992616614 ps |
| T387 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3415622173 |
|
|
Feb 08 12:03:51 PM UTC 25 |
Feb 08 12:03:56 PM UTC 25 |
51210396 ps |
| T388 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.2904340862 |
|
|
Feb 08 12:02:27 PM UTC 25 |
Feb 08 12:04:18 PM UTC 25 |
143544258 ps |
| T389 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1032770522 |
|
|
Feb 08 11:57:02 AM UTC 25 |
Feb 08 12:04:22 PM UTC 25 |
6268259212 ps |
| T390 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.599422725 |
|
|
Feb 08 12:04:18 PM UTC 25 |
Feb 08 12:04:26 PM UTC 25 |
205350321 ps |
| T391 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2105924948 |
|
|
Feb 08 11:51:12 AM UTC 25 |
Feb 08 12:04:29 PM UTC 25 |
3140289234 ps |
| T392 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.4287652316 |
|
|
Feb 08 12:04:22 PM UTC 25 |
Feb 08 12:04:30 PM UTC 25 |
57332380 ps |
| T393 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3559647249 |
|
|
Feb 08 12:04:27 PM UTC 25 |
Feb 08 12:04:34 PM UTC 25 |
496260719 ps |
| T394 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1292184657 |
|
|
Feb 08 12:03:20 PM UTC 25 |
Feb 08 12:04:48 PM UTC 25 |
5088930695 ps |
| T395 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.2643885954 |
|
|
Feb 08 12:04:49 PM UTC 25 |
Feb 08 12:04:52 PM UTC 25 |
217910958 ps |
| T396 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1089995200 |
|
|
Feb 08 11:42:45 AM UTC 25 |
Feb 08 12:04:54 PM UTC 25 |
65532552618 ps |
| T397 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.276511363 |
|
|
Feb 08 12:04:52 PM UTC 25 |
Feb 08 12:05:00 PM UTC 25 |
236275691 ps |
| T398 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3347260241 |
|
|
Feb 08 12:04:55 PM UTC 25 |
Feb 08 12:05:01 PM UTC 25 |
108707312 ps |
| T399 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1942413023 |
|
|
Feb 08 11:57:45 AM UTC 25 |
Feb 08 12:05:04 PM UTC 25 |
8549514846 ps |
| T400 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2476583678 |
|
|
Feb 08 11:58:10 AM UTC 25 |
Feb 08 12:05:05 PM UTC 25 |
23348052836 ps |
| T401 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1711837146 |
|
|
Feb 08 12:05:05 PM UTC 25 |
Feb 08 12:05:08 PM UTC 25 |
15741986 ps |
| T402 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3626631864 |
|
|
Feb 08 12:03:34 PM UTC 25 |
Feb 08 12:05:11 PM UTC 25 |
3639763479 ps |
| T403 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2400858713 |
|
|
Feb 08 11:55:26 AM UTC 25 |
Feb 08 12:05:12 PM UTC 25 |
4585893104 ps |
| T404 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.1041088712 |
|
|
Feb 08 11:47:28 AM UTC 25 |
Feb 08 12:05:16 PM UTC 25 |
18050425897 ps |
| T405 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2581626645 |
|
|
Feb 08 12:02:16 PM UTC 25 |
Feb 08 12:05:18 PM UTC 25 |
4237534714 ps |
| T406 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.666256980 |
|
|
Feb 08 12:05:18 PM UTC 25 |
Feb 08 12:05:28 PM UTC 25 |
1287726311 ps |
| T407 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.349985153 |
|
|
Feb 08 12:05:05 PM UTC 25 |
Feb 08 12:05:42 PM UTC 25 |
1533354243 ps |
| T408 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.759587133 |
|
|
Feb 08 12:05:09 PM UTC 25 |
Feb 08 12:05:43 PM UTC 25 |
832243501 ps |
| T409 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.4022096773 |
|
|
Feb 08 12:01:28 PM UTC 25 |
Feb 08 12:05:46 PM UTC 25 |
38096455888 ps |
| T50 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3397825464 |
|
|
Feb 08 12:05:01 PM UTC 25 |
Feb 08 12:05:51 PM UTC 25 |
4220743454 ps |
| T410 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.7813378 |
|
|
Feb 08 12:01:20 PM UTC 25 |
Feb 08 12:05:52 PM UTC 25 |
2788798216 ps |
| T411 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1229438683 |
|
|
Feb 08 12:05:43 PM UTC 25 |
Feb 08 12:05:54 PM UTC 25 |
3049485853 ps |
| T412 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.594299627 |
|
|
Feb 08 12:05:54 PM UTC 25 |
Feb 08 12:05:57 PM UTC 25 |
288704093 ps |
| T413 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2139053516 |
|
|
Feb 08 12:05:29 PM UTC 25 |
Feb 08 12:05:57 PM UTC 25 |
93581929 ps |
| T414 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1087873549 |
|
|
Feb 08 11:53:07 AM UTC 25 |
Feb 08 12:06:01 PM UTC 25 |
9607749711 ps |
| T415 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3062256789 |
|
|
Feb 08 12:05:58 PM UTC 25 |
Feb 08 12:06:07 PM UTC 25 |
229608926 ps |
| T416 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.1646535079 |
|
|
Feb 08 12:05:59 PM UTC 25 |
Feb 08 12:06:09 PM UTC 25 |
369766422 ps |
| T417 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3249164630 |
|
|
Feb 08 12:06:08 PM UTC 25 |
Feb 08 12:06:10 PM UTC 25 |
28257494 ps |
| T418 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.1091767289 |
|
|
Feb 08 12:05:13 PM UTC 25 |
Feb 08 12:06:20 PM UTC 25 |
1015934335 ps |
| T419 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1988074667 |
|
|
Feb 08 12:05:43 PM UTC 25 |
Feb 08 12:06:34 PM UTC 25 |
208924707 ps |
| T420 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1582612166 |
|
|
Feb 08 11:41:43 AM UTC 25 |
Feb 08 12:06:48 PM UTC 25 |
35995773627 ps |
| T421 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.855872578 |
|
|
Feb 08 11:43:22 AM UTC 25 |
Feb 08 12:06:58 PM UTC 25 |
33320964866 ps |
| T422 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2312583323 |
|
|
Feb 08 12:06:48 PM UTC 25 |
Feb 08 12:07:14 PM UTC 25 |
153467118 ps |
| T423 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1437563346 |
|
|
Feb 08 12:06:21 PM UTC 25 |
Feb 08 12:07:16 PM UTC 25 |
2230260683 ps |
| T424 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2085301555 |
|
|
Feb 08 12:07:18 PM UTC 25 |
Feb 08 12:07:27 PM UTC 25 |
571241048 ps |
| T425 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3481810705 |
|
|
Feb 08 12:00:29 PM UTC 25 |
Feb 08 12:07:37 PM UTC 25 |
25879634720 ps |
| T426 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1613187331 |
|
|
Feb 08 12:03:48 PM UTC 25 |
Feb 08 12:08:04 PM UTC 25 |
22044077137 ps |
| T427 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3192569593 |
|
|
Feb 08 11:50:04 AM UTC 25 |
Feb 08 12:08:06 PM UTC 25 |
39190350619 ps |
| T428 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2053890043 |
|
|
Feb 08 12:08:07 PM UTC 25 |
Feb 08 12:08:10 PM UTC 25 |
45897682 ps |
| T429 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.933137361 |
|
|
Feb 08 12:06:09 PM UTC 25 |
Feb 08 12:08:18 PM UTC 25 |
926679658 ps |
| T430 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1885452845 |
|
|
Feb 08 12:08:10 PM UTC 25 |
Feb 08 12:08:20 PM UTC 25 |
606998769 ps |
| T431 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3836956878 |
|
|
Feb 08 12:02:35 PM UTC 25 |
Feb 08 12:08:20 PM UTC 25 |
13725104209 ps |
| T432 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4063823318 |
|
|
Feb 08 12:01:15 PM UTC 25 |
Feb 08 12:08:27 PM UTC 25 |
5666727349 ps |
| T433 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3883623348 |
|
|
Feb 08 12:08:19 PM UTC 25 |
Feb 08 12:08:28 PM UTC 25 |
667124733 ps |
| T434 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2788237587 |
|
|
Feb 08 12:08:29 PM UTC 25 |
Feb 08 12:08:31 PM UTC 25 |
46805622 ps |
| T435 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.3578948415 |
|
|
Feb 08 11:51:23 AM UTC 25 |
Feb 08 12:08:32 PM UTC 25 |
17723415997 ps |
| T436 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3923316199 |
|
|
Feb 08 12:02:50 PM UTC 25 |
Feb 08 12:08:41 PM UTC 25 |
4154259521 ps |
| T437 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.958329878 |
|
|
Feb 08 12:00:48 PM UTC 25 |
Feb 08 12:08:43 PM UTC 25 |
3207801859 ps |
| T438 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2039603434 |
|
|
Feb 08 11:54:19 AM UTC 25 |
Feb 08 12:08:52 PM UTC 25 |
28702785761 ps |
| T439 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.147192150 |
|
|
Feb 08 12:08:04 PM UTC 25 |
Feb 08 12:08:53 PM UTC 25 |
3799510676 ps |
| T440 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1209207980 |
|
|
Feb 08 12:07:17 PM UTC 25 |
Feb 08 12:08:55 PM UTC 25 |
450583848 ps |
| T441 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2632573379 |
|
|
Feb 08 12:03:32 PM UTC 25 |
Feb 08 12:08:56 PM UTC 25 |
3449138479 ps |
| T442 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.2768879909 |
|
|
Feb 08 12:08:57 PM UTC 25 |
Feb 08 12:09:04 PM UTC 25 |
282610059 ps |
| T443 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.233074002 |
|
|
Feb 08 12:07:15 PM UTC 25 |
Feb 08 12:09:15 PM UTC 25 |
139488176 ps |
| T444 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3220244202 |
|
|
Feb 08 11:53:34 AM UTC 25 |
Feb 08 12:09:18 PM UTC 25 |
68710203718 ps |
| T445 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.1335911710 |
|
|
Feb 08 12:06:11 PM UTC 25 |
Feb 08 12:09:20 PM UTC 25 |
2184509148 ps |
| T446 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2277748359 |
|
|
Feb 08 12:09:21 PM UTC 25 |
Feb 08 12:09:23 PM UTC 25 |
31040230 ps |
| T447 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1615193711 |
|
|
Feb 08 12:09:24 PM UTC 25 |
Feb 08 12:09:31 PM UTC 25 |
254652556 ps |
| T448 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.4167389950 |
|
|
Feb 08 12:08:33 PM UTC 25 |
Feb 08 12:09:31 PM UTC 25 |
6938636760 ps |
| T449 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1959570412 |
|
|
Feb 08 12:08:56 PM UTC 25 |
Feb 08 12:09:39 PM UTC 25 |
413368412 ps |
| T450 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.965462283 |
|
|
Feb 08 12:09:32 PM UTC 25 |
Feb 08 12:09:41 PM UTC 25 |
611176971 ps |
| T451 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.839432264 |
|
|
Feb 08 11:45:45 AM UTC 25 |
Feb 08 12:09:41 PM UTC 25 |
52172896315 ps |
| T452 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.3958526024 |
|
|
Feb 08 12:09:41 PM UTC 25 |
Feb 08 12:09:44 PM UTC 25 |
13698422 ps |
| T453 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.3464318778 |
|
|
Feb 08 11:57:07 AM UTC 25 |
Feb 08 12:09:49 PM UTC 25 |
51991213773 ps |
| T454 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2332012030 |
|
|
Feb 08 12:01:16 PM UTC 25 |
Feb 08 12:09:59 PM UTC 25 |
3953019838 ps |
| T455 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2373504729 |
|
|
Feb 08 12:07:00 PM UTC 25 |
Feb 08 12:10:00 PM UTC 25 |
6734944992 ps |
| T456 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3880966712 |
|
|
Feb 08 12:09:50 PM UTC 25 |
Feb 08 12:10:17 PM UTC 25 |
6769231787 ps |
| T457 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.609428620 |
|
|
Feb 08 12:09:42 PM UTC 25 |
Feb 08 12:10:19 PM UTC 25 |
1080382566 ps |
| T458 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.307285273 |
|
|
Feb 08 11:58:25 AM UTC 25 |
Feb 08 12:10:21 PM UTC 25 |
10640998430 ps |
| T459 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.1926924050 |
|
|
Feb 08 12:10:01 PM UTC 25 |
Feb 08 12:10:22 PM UTC 25 |
464344719 ps |
| T460 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1728706221 |
|
|
Feb 08 12:02:58 PM UTC 25 |
Feb 08 12:10:25 PM UTC 25 |
4758023535 ps |
| T461 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2869974720 |
|
|
Feb 08 12:05:13 PM UTC 25 |
Feb 08 12:10:28 PM UTC 25 |
28370957957 ps |
| T462 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2097994870 |
|
|
Feb 08 12:10:23 PM UTC 25 |
Feb 08 12:10:31 PM UTC 25 |
1713766808 ps |
| T463 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1843601409 |
|
|
Feb 08 12:08:29 PM UTC 25 |
Feb 08 12:10:36 PM UTC 25 |
901629214 ps |
| T464 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4194045667 |
|
|
Feb 08 12:08:54 PM UTC 25 |
Feb 08 12:10:36 PM UTC 25 |
510791174 ps |
| T107 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2829748253 |
|
|
Feb 08 12:08:21 PM UTC 25 |
Feb 08 12:10:38 PM UTC 25 |
4819326083 ps |
| T465 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2731879110 |
|
|
Feb 08 12:10:36 PM UTC 25 |
Feb 08 12:10:39 PM UTC 25 |
85436624 ps |
| T466 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3537601708 |
|
|
Feb 08 12:10:40 PM UTC 25 |
Feb 08 12:10:44 PM UTC 25 |
46468664 ps |
| T467 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1091859667 |
|
|
Feb 08 12:03:57 PM UTC 25 |
Feb 08 12:10:45 PM UTC 25 |
16240093553 ps |
| T468 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3423580935 |
|
|
Feb 08 12:10:38 PM UTC 25 |
Feb 08 12:10:46 PM UTC 25 |
238080882 ps |
| T469 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.4272800525 |
|
|
Feb 08 12:10:46 PM UTC 25 |
Feb 08 12:10:48 PM UTC 25 |
47816063 ps |
| T470 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2000736442 |
|
|
Feb 08 12:09:32 PM UTC 25 |
Feb 08 12:10:52 PM UTC 25 |
2887718416 ps |
| T471 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1200267890 |
|
|
Feb 08 11:55:40 AM UTC 25 |
Feb 08 12:10:59 PM UTC 25 |
49731981906 ps |
| T472 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.79695519 |
|
|
Feb 08 12:08:44 PM UTC 25 |
Feb 08 12:11:03 PM UTC 25 |
782614726 ps |
| T473 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3917798338 |
|
|
Feb 08 12:04:30 PM UTC 25 |
Feb 08 12:11:04 PM UTC 25 |
22377393671 ps |
| T474 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.645708436 |
|
|
Feb 08 12:10:20 PM UTC 25 |
Feb 08 12:11:10 PM UTC 25 |
112145009 ps |
| T475 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3560888107 |
|
|
Feb 08 12:10:22 PM UTC 25 |
Feb 08 12:11:11 PM UTC 25 |
424648009 ps |
| T476 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1237244602 |
|
|
Feb 08 11:58:34 AM UTC 25 |
Feb 08 12:11:11 PM UTC 25 |
11202616665 ps |
| T477 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.182994878 |
|
|
Feb 08 11:36:48 AM UTC 25 |
Feb 08 12:11:12 PM UTC 25 |
32188150636 ps |
| T478 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.129276083 |
|
|
Feb 08 12:11:10 PM UTC 25 |
Feb 08 12:11:16 PM UTC 25 |
167183827 ps |
| T479 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.4247960663 |
|
|
Feb 08 12:11:12 PM UTC 25 |
Feb 08 12:11:20 PM UTC 25 |
1443910357 ps |
| T480 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1347587924 |
|
|
Feb 08 12:09:19 PM UTC 25 |
Feb 08 12:11:20 PM UTC 25 |
489818524 ps |
| T481 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2739407674 |
|
|
Feb 08 11:47:08 AM UTC 25 |
Feb 08 12:11:21 PM UTC 25 |
4634720739 ps |
| T482 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.119327741 |
|
|
Feb 08 12:11:04 PM UTC 25 |
Feb 08 12:11:23 PM UTC 25 |
460344641 ps |
| T483 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.586253146 |
|
|
Feb 08 12:11:21 PM UTC 25 |
Feb 08 12:11:24 PM UTC 25 |
51452818 ps |
| T484 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1310900613 |
|
|
Feb 08 12:11:22 PM UTC 25 |
Feb 08 12:11:29 PM UTC 25 |
114670112 ps |
| T485 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3409676329 |
|
|
Feb 08 11:57:34 AM UTC 25 |
Feb 08 12:11:30 PM UTC 25 |
11058685501 ps |
| T486 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.2808237458 |
|
|
Feb 08 12:10:47 PM UTC 25 |
Feb 08 12:11:30 PM UTC 25 |
92173687 ps |
| T487 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2768069414 |
|
|
Feb 08 12:11:31 PM UTC 25 |
Feb 08 12:11:33 PM UTC 25 |
21171014 ps |
| T488 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3021854163 |
|
|
Feb 08 12:11:24 PM UTC 25 |
Feb 08 12:11:33 PM UTC 25 |
1425104651 ps |
| T489 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1189153414 |
|
|
Feb 08 12:04:35 PM UTC 25 |
Feb 08 12:11:42 PM UTC 25 |
5214207803 ps |
| T490 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.229250997 |
|
|
Feb 08 12:10:53 PM UTC 25 |
Feb 08 12:12:00 PM UTC 25 |
877338336 ps |
| T491 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.3750260946 |
|
|
Feb 08 12:03:03 PM UTC 25 |
Feb 08 12:12:06 PM UTC 25 |
18567316457 ps |
| T492 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2364830564 |
|
|
Feb 08 11:48:28 AM UTC 25 |
Feb 08 12:12:08 PM UTC 25 |
25510690527 ps |
| T493 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.4189126195 |
|
|
Feb 08 12:11:12 PM UTC 25 |
Feb 08 12:12:15 PM UTC 25 |
869269154 ps |
| T494 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.3350368125 |
|
|
Feb 08 12:11:34 PM UTC 25 |
Feb 08 12:12:16 PM UTC 25 |
10835758228 ps |
| T495 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.2440465219 |
|
|
Feb 08 11:57:11 AM UTC 25 |
Feb 08 12:12:20 PM UTC 25 |
11508596084 ps |
| T496 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2582089209 |
|
|
Feb 08 12:12:17 PM UTC 25 |
Feb 08 12:12:25 PM UTC 25 |
208167715 ps |
| T497 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1406227434 |
|
|
Feb 08 12:12:00 PM UTC 25 |
Feb 08 12:12:26 PM UTC 25 |
1012256247 ps |
| T498 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1543383306 |
|
|
Feb 08 12:12:17 PM UTC 25 |
Feb 08 12:12:27 PM UTC 25 |
2931492927 ps |
| T499 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.4193533294 |
|
|
Feb 08 12:12:28 PM UTC 25 |
Feb 08 12:12:31 PM UTC 25 |
80639770 ps |
| T500 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3153569238 |
|
|
Feb 08 12:05:19 PM UTC 25 |
Feb 08 12:12:32 PM UTC 25 |
57034340152 ps |
| T501 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.2569351259 |
|
|
Feb 08 12:02:27 PM UTC 25 |
Feb 08 12:12:37 PM UTC 25 |
6408133470 ps |
| T502 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2065172895 |
|
|
Feb 08 12:12:34 PM UTC 25 |
Feb 08 12:12:39 PM UTC 25 |
164647648 ps |
| T503 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.4071237672 |
|
|
Feb 08 12:12:31 PM UTC 25 |
Feb 08 12:12:41 PM UTC 25 |
338710069 ps |
| T504 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2974230161 |
|
|
Feb 08 12:10:00 PM UTC 25 |
Feb 08 12:12:44 PM UTC 25 |
8136631311 ps |
| T505 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.169073934 |
|
|
Feb 08 12:12:42 PM UTC 25 |
Feb 08 12:12:44 PM UTC 25 |
22432214 ps |
| T506 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.3428678040 |
|
|
Feb 08 12:12:45 PM UTC 25 |
Feb 08 12:12:48 PM UTC 25 |
39280152 ps |
| T507 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1252965487 |
|
|
Feb 08 12:06:34 PM UTC 25 |
Feb 08 12:13:00 PM UTC 25 |
13252228849 ps |
| T508 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.857524117 |
|
|
Feb 08 12:11:31 PM UTC 25 |
Feb 08 12:13:19 PM UTC 25 |
2251755436 ps |
| T509 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3951388027 |
|
|
Feb 08 12:12:09 PM UTC 25 |
Feb 08 12:13:21 PM UTC 25 |
491512422 ps |
| T510 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.1693588020 |
|
|
Feb 08 12:07:38 PM UTC 25 |
Feb 08 12:13:50 PM UTC 25 |
53997185865 ps |
| T511 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3600983696 |
|
|
Feb 08 11:59:30 AM UTC 25 |
Feb 08 12:13:58 PM UTC 25 |
50056306617 ps |
| T512 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3280509737 |
|
|
Feb 08 12:11:00 PM UTC 25 |
Feb 08 12:14:03 PM UTC 25 |
1828590663 ps |
| T513 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3175304268 |
|
|
Feb 08 12:12:49 PM UTC 25 |
Feb 08 12:14:11 PM UTC 25 |
12281549295 ps |
| T514 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.897531613 |
|
|
Feb 08 12:08:53 PM UTC 25 |
Feb 08 12:14:12 PM UTC 25 |
64861554821 ps |
| T515 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2552829163 |
|
|
Feb 08 12:13:51 PM UTC 25 |
Feb 08 12:14:12 PM UTC 25 |
302675199 ps |
| T516 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.3213233672 |
|
|
Feb 08 12:03:03 PM UTC 25 |
Feb 08 12:14:13 PM UTC 25 |
5483407253 ps |
| T517 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1078077995 |
|
|
Feb 08 12:14:04 PM UTC 25 |
Feb 08 12:14:17 PM UTC 25 |
3185999599 ps |
| T518 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.568103523 |
|
|
Feb 08 12:14:14 PM UTC 25 |
Feb 08 12:14:17 PM UTC 25 |
29408299 ps |
| T519 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2457339036 |
|
|
Feb 08 12:14:18 PM UTC 25 |
Feb 08 12:14:23 PM UTC 25 |
310889609 ps |
| T520 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2697573661 |
|
|
Feb 08 12:08:42 PM UTC 25 |
Feb 08 12:14:25 PM UTC 25 |
3247424831 ps |
| T521 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3627181892 |
|
|
Feb 08 12:14:18 PM UTC 25 |
Feb 08 12:14:30 PM UTC 25 |
377357007 ps |
| T522 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.4089050972 |
|
|
Feb 08 12:13:59 PM UTC 25 |
Feb 08 12:14:31 PM UTC 25 |
98880634 ps |
| T523 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1136446488 |
|
|
Feb 08 12:14:31 PM UTC 25 |
Feb 08 12:14:33 PM UTC 25 |
40726940 ps |
| T524 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.1240971969 |
|
|
Feb 08 12:01:44 PM UTC 25 |
Feb 08 12:14:39 PM UTC 25 |
8740812736 ps |
| T525 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1085423858 |
|
|
Feb 08 12:11:25 PM UTC 25 |
Feb 08 12:14:41 PM UTC 25 |
1149494657 ps |
| T526 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.2881944009 |
|
|
Feb 08 12:14:32 PM UTC 25 |
Feb 08 12:14:50 PM UTC 25 |
1109896598 ps |
| T527 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.685000023 |
|
|
Feb 08 12:13:19 PM UTC 25 |
Feb 08 12:14:50 PM UTC 25 |
580046713 ps |
| T528 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1188700642 |
|
|
Feb 08 12:06:02 PM UTC 25 |
Feb 08 12:14:56 PM UTC 25 |
4891724616 ps |
| T529 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.2449926551 |
|
|
Feb 08 12:09:17 PM UTC 25 |
Feb 08 12:15:02 PM UTC 25 |
3540398469 ps |
| T530 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2753664571 |
|
|
Feb 08 12:14:40 PM UTC 25 |
Feb 08 12:15:06 PM UTC 25 |
2250342530 ps |
| T531 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1058207126 |
|
|
Feb 08 12:19:15 PM UTC 25 |
Feb 08 12:19:32 PM UTC 25 |
70001888 ps |
| T532 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3277152179 |
|
|
Feb 08 12:14:58 PM UTC 25 |
Feb 08 12:15:15 PM UTC 25 |
229915605 ps |
| T533 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2821940559 |
|
|
Feb 08 12:10:49 PM UTC 25 |
Feb 08 12:15:19 PM UTC 25 |
12290897052 ps |
| T534 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2794881167 |
|
|
Feb 08 12:15:07 PM UTC 25 |
Feb 08 12:15:20 PM UTC 25 |
741503621 ps |
| T535 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2730355667 |
|
|
Feb 08 12:15:21 PM UTC 25 |
Feb 08 12:15:23 PM UTC 25 |
54546689 ps |
| T536 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.405249135 |
|
|
Feb 08 12:15:24 PM UTC 25 |
Feb 08 12:15:32 PM UTC 25 |
236118892 ps |
| T537 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1691255345 |
|
|
Feb 08 12:12:21 PM UTC 25 |
Feb 08 12:15:32 PM UTC 25 |
1969246618 ps |
| T85 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.590729614 |
|
|
Feb 08 12:15:33 PM UTC 25 |
Feb 08 12:15:40 PM UTC 25 |
619227041 ps |
| T538 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1894487341 |
|
|
Feb 08 12:10:40 PM UTC 25 |
Feb 08 12:15:43 PM UTC 25 |
2678166135 ps |
| T539 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3981335745 |
|
|
Feb 08 12:15:44 PM UTC 25 |
Feb 08 12:15:47 PM UTC 25 |
12243151 ps |
| T540 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3632459871 |
|
|
Feb 08 12:15:03 PM UTC 25 |
Feb 08 12:15:48 PM UTC 25 |
422287147 ps |
| T541 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.306986247 |
|
|
Feb 08 12:11:42 PM UTC 25 |
Feb 08 12:15:49 PM UTC 25 |
2517317516 ps |
| T542 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2501070624 |
|
|
Feb 08 12:10:18 PM UTC 25 |
Feb 08 12:16:17 PM UTC 25 |
4566377892 ps |
| T543 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.2500602873 |
|
|
Feb 08 12:01:56 PM UTC 25 |
Feb 08 12:16:28 PM UTC 25 |
36106586799 ps |
| T544 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.648098620 |
|
|
Feb 08 11:51:13 AM UTC 25 |
Feb 08 12:16:31 PM UTC 25 |
113099181431 ps |
| T545 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3968240997 |
|
|
Feb 08 12:13:01 PM UTC 25 |
Feb 08 12:16:45 PM UTC 25 |
36403782234 ps |
| T546 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3316848987 |
|
|
Feb 08 12:16:29 PM UTC 25 |
Feb 08 12:16:48 PM UTC 25 |
8083068491 ps |
| T547 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.60246637 |
|
|
Feb 08 12:15:50 PM UTC 25 |
Feb 08 12:16:58 PM UTC 25 |
4894788813 ps |