| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2199038025 |
|
|
Oct 15 03:49:27 AM UTC 24 |
Oct 15 03:53:41 AM UTC 24 |
3368012869 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1039462197 |
|
|
Oct 15 03:53:37 AM UTC 24 |
Oct 15 03:53:42 AM UTC 24 |
783525918 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3124964325 |
|
|
Oct 15 03:47:56 AM UTC 24 |
Oct 15 03:53:43 AM UTC 24 |
3137075007 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2349489376 |
|
|
Oct 15 03:53:34 AM UTC 24 |
Oct 15 03:53:44 AM UTC 24 |
242497723 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1179920757 |
|
|
Oct 15 03:53:44 AM UTC 24 |
Oct 15 03:53:47 AM UTC 24 |
29279702 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1149952888 |
|
|
Oct 15 03:53:48 AM UTC 24 |
Oct 15 03:53:53 AM UTC 24 |
347748805 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.4196302356 |
|
|
Oct 15 03:53:44 AM UTC 24 |
Oct 15 03:53:54 AM UTC 24 |
849803777 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1414233091 |
|
|
Oct 15 03:53:54 AM UTC 24 |
Oct 15 03:53:57 AM UTC 24 |
103637850 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.605000892 |
|
|
Oct 15 03:53:36 AM UTC 24 |
Oct 15 03:54:03 AM UTC 24 |
92064014 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.267651090 |
|
|
Oct 15 03:54:04 AM UTC 24 |
Oct 15 03:54:06 AM UTC 24 |
12109710 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3264156078 |
|
|
Oct 15 03:53:08 AM UTC 24 |
Oct 15 03:54:09 AM UTC 24 |
10897145637 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1781552510 |
|
|
Oct 15 03:53:56 AM UTC 24 |
Oct 15 03:54:12 AM UTC 24 |
181474547 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.4125425082 |
|
|
Oct 15 03:41:19 AM UTC 24 |
Oct 15 03:54:23 AM UTC 24 |
39219441538 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3253800578 |
|
|
Oct 15 03:54:07 AM UTC 24 |
Oct 15 03:54:26 AM UTC 24 |
1035795764 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3589603607 |
|
|
Oct 15 03:42:41 AM UTC 24 |
Oct 15 03:54:34 AM UTC 24 |
14684838939 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1386239365 |
|
|
Oct 15 03:18:48 AM UTC 24 |
Oct 15 03:54:48 AM UTC 24 |
20788231017 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.4244325577 |
|
|
Oct 15 03:15:53 AM UTC 24 |
Oct 15 03:54:48 AM UTC 24 |
36157743300 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.3391587646 |
|
|
Oct 15 03:54:13 AM UTC 24 |
Oct 15 03:54:49 AM UTC 24 |
1711572113 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3654835616 |
|
|
Oct 15 03:54:27 AM UTC 24 |
Oct 15 03:54:50 AM UTC 24 |
2407428661 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2871321576 |
|
|
Oct 15 03:54:50 AM UTC 24 |
Oct 15 03:54:59 AM UTC 24 |
2130761170 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3353236848 |
|
|
Oct 15 03:50:00 AM UTC 24 |
Oct 15 03:55:11 AM UTC 24 |
2691120001 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3859014182 |
|
|
Oct 15 03:54:50 AM UTC 24 |
Oct 15 03:55:12 AM UTC 24 |
418099974 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2278552254 |
|
|
Oct 15 03:55:13 AM UTC 24 |
Oct 15 03:55:15 AM UTC 24 |
29729541 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3893550881 |
|
|
Oct 15 03:43:45 AM UTC 24 |
Oct 15 03:55:19 AM UTC 24 |
5992207299 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3428461594 |
|
|
Oct 15 03:53:42 AM UTC 24 |
Oct 15 03:55:23 AM UTC 24 |
931131920 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2745723221 |
|
|
Oct 15 03:55:20 AM UTC 24 |
Oct 15 03:55:25 AM UTC 24 |
126250344 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_readback_err.1080254855 |
|
|
Oct 15 03:55:24 AM UTC 24 |
Oct 15 03:55:26 AM UTC 24 |
59149524 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3182735443 |
|
|
Oct 15 03:55:16 AM UTC 24 |
Oct 15 03:55:29 AM UTC 24 |
181976452 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2884967754 |
|
|
Oct 15 03:55:30 AM UTC 24 |
Oct 15 03:55:32 AM UTC 24 |
56238611 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3884754307 |
|
|
Oct 15 03:51:12 AM UTC 24 |
Oct 15 03:55:43 AM UTC 24 |
3008411460 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2117295458 |
|
|
Oct 15 03:55:33 AM UTC 24 |
Oct 15 03:55:50 AM UTC 24 |
754241606 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.125460194 |
|
|
Oct 15 03:36:12 AM UTC 24 |
Oct 15 03:55:50 AM UTC 24 |
67998996656 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.777227238 |
|
|
Oct 15 03:50:29 AM UTC 24 |
Oct 15 03:56:01 AM UTC 24 |
7464442666 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.3342701741 |
|
|
Oct 15 03:47:17 AM UTC 24 |
Oct 15 03:56:05 AM UTC 24 |
5208574059 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2765919091 |
|
|
Oct 15 03:55:01 AM UTC 24 |
Oct 15 03:56:16 AM UTC 24 |
2758619504 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1676547071 |
|
|
Oct 15 03:56:02 AM UTC 24 |
Oct 15 03:56:16 AM UTC 24 |
738208480 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3951648665 |
|
|
Oct 15 03:54:48 AM UTC 24 |
Oct 15 03:56:23 AM UTC 24 |
225273728 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2452564446 |
|
|
Oct 15 03:44:59 AM UTC 24 |
Oct 15 03:56:29 AM UTC 24 |
36405075075 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.1464169154 |
|
|
Oct 15 03:56:24 AM UTC 24 |
Oct 15 03:56:38 AM UTC 24 |
1494483387 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3713246268 |
|
|
Oct 15 03:55:50 AM UTC 24 |
Oct 15 03:56:45 AM UTC 24 |
673607814 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.4049253288 |
|
|
Oct 15 03:56:16 AM UTC 24 |
Oct 15 03:56:50 AM UTC 24 |
343404844 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3216508249 |
|
|
Oct 15 03:54:24 AM UTC 24 |
Oct 15 03:56:52 AM UTC 24 |
2518026744 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3731485983 |
|
|
Oct 15 03:56:51 AM UTC 24 |
Oct 15 03:56:53 AM UTC 24 |
190474255 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2725181756 |
|
|
Oct 15 03:53:14 AM UTC 24 |
Oct 15 03:56:56 AM UTC 24 |
13997682939 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_readback_err.220892990 |
|
|
Oct 15 03:56:57 AM UTC 24 |
Oct 15 03:57:00 AM UTC 24 |
30611834 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1685423819 |
|
|
Oct 15 03:44:08 AM UTC 24 |
Oct 15 03:57:01 AM UTC 24 |
10746694717 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1392920591 |
|
|
Oct 15 03:56:54 AM UTC 24 |
Oct 15 03:57:02 AM UTC 24 |
93052073 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.1636132171 |
|
|
Oct 15 03:57:03 AM UTC 24 |
Oct 15 03:57:05 AM UTC 24 |
12873136 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2073063145 |
|
|
Oct 15 03:56:53 AM UTC 24 |
Oct 15 03:57:05 AM UTC 24 |
253802323 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1632630549 |
|
|
Oct 15 03:53:26 AM UTC 24 |
Oct 15 03:57:07 AM UTC 24 |
23477236059 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1032500584 |
|
|
Oct 15 03:49:11 AM UTC 24 |
Oct 15 03:57:09 AM UTC 24 |
1342684520 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.40529524 |
|
|
Oct 15 03:57:06 AM UTC 24 |
Oct 15 03:57:13 AM UTC 24 |
247510590 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1005510408 |
|
|
Oct 15 03:57:13 AM UTC 24 |
Oct 15 03:57:26 AM UTC 24 |
1647966230 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2965655212 |
|
|
Oct 15 03:56:16 AM UTC 24 |
Oct 15 03:57:42 AM UTC 24 |
678044131 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.3366971873 |
|
|
Oct 15 03:57:07 AM UTC 24 |
Oct 15 03:57:44 AM UTC 24 |
2068847733 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3209727295 |
|
|
Oct 15 03:44:57 AM UTC 24 |
Oct 15 03:57:46 AM UTC 24 |
12219511159 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1569660704 |
|
|
Oct 15 03:57:43 AM UTC 24 |
Oct 15 03:57:48 AM UTC 24 |
249751053 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3652079661 |
|
|
Oct 15 03:57:33 AM UTC 24 |
Oct 15 03:57:53 AM UTC 24 |
87886956 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2820864343 |
|
|
Oct 15 03:57:54 AM UTC 24 |
Oct 15 03:57:56 AM UTC 24 |
53295717 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2145580659 |
|
|
Oct 15 03:57:57 AM UTC 24 |
Oct 15 03:58:05 AM UTC 24 |
338077995 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2892424679 |
|
|
Oct 15 03:58:06 AM UTC 24 |
Oct 15 03:58:14 AM UTC 24 |
155182284 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1680737100 |
|
|
Oct 15 03:57:39 AM UTC 24 |
Oct 15 03:58:16 AM UTC 24 |
230027019 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3475891442 |
|
|
Oct 15 03:58:14 AM UTC 24 |
Oct 15 03:58:17 AM UTC 24 |
32424408 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3621995587 |
|
|
Oct 15 03:55:52 AM UTC 24 |
Oct 15 03:59:16 AM UTC 24 |
6163309578 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2006000110 |
|
|
Oct 15 03:59:17 AM UTC 24 |
Oct 15 03:59:19 AM UTC 24 |
36339270 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1271010136 |
|
|
Oct 15 03:31:05 AM UTC 24 |
Oct 15 03:59:42 AM UTC 24 |
23147903455 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.3708969119 |
|
|
Oct 15 03:57:50 AM UTC 24 |
Oct 15 04:00:06 AM UTC 24 |
2652795397 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2660445484 |
|
|
Oct 15 03:13:29 AM UTC 24 |
Oct 15 04:00:26 AM UTC 24 |
46056598122 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1288345646 |
|
|
Oct 15 03:59:20 AM UTC 24 |
Oct 15 04:00:30 AM UTC 24 |
4122254284 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.309058241 |
|
|
Oct 15 03:58:16 AM UTC 24 |
Oct 15 04:00:36 AM UTC 24 |
411344702 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2351545362 |
|
|
Oct 15 04:00:07 AM UTC 24 |
Oct 15 04:00:48 AM UTC 24 |
8158660683 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1091929355 |
|
|
Oct 15 04:00:31 AM UTC 24 |
Oct 15 04:00:54 AM UTC 24 |
1246654762 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1469396843 |
|
|
Oct 15 04:00:49 AM UTC 24 |
Oct 15 04:01:20 AM UTC 24 |
202524753 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2837732240 |
|
|
Oct 15 04:01:21 AM UTC 24 |
Oct 15 04:01:29 AM UTC 24 |
2177788661 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.905914022 |
|
|
Oct 15 04:00:54 AM UTC 24 |
Oct 15 04:01:32 AM UTC 24 |
220655859 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1935170066 |
|
|
Oct 15 03:40:19 AM UTC 24 |
Oct 15 04:01:35 AM UTC 24 |
7327834206 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1351690339 |
|
|
Oct 15 03:55:44 AM UTC 24 |
Oct 15 04:01:35 AM UTC 24 |
7647975794 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3686654150 |
|
|
Oct 15 04:01:36 AM UTC 24 |
Oct 15 04:01:38 AM UTC 24 |
178187479 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.251968354 |
|
|
Oct 15 03:57:01 AM UTC 24 |
Oct 15 04:01:38 AM UTC 24 |
1869242552 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.779689170 |
|
|
Oct 15 03:52:54 AM UTC 24 |
Oct 15 04:01:40 AM UTC 24 |
6874005049 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_readback_err.2398629764 |
|
|
Oct 15 04:01:42 AM UTC 24 |
Oct 15 04:01:44 AM UTC 24 |
61329242 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1161960041 |
|
|
Oct 15 04:01:39 AM UTC 24 |
Oct 15 04:01:45 AM UTC 24 |
133590434 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.229074846 |
|
|
Oct 15 04:01:39 AM UTC 24 |
Oct 15 04:01:46 AM UTC 24 |
96386600 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2344916325 |
|
|
Oct 15 04:01:47 AM UTC 24 |
Oct 15 04:01:49 AM UTC 24 |
35419334 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2202854823 |
|
|
Oct 15 03:57:10 AM UTC 24 |
Oct 15 04:01:56 AM UTC 24 |
2378566473 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.295371943 |
|
|
Oct 15 04:01:50 AM UTC 24 |
Oct 15 04:02:07 AM UTC 24 |
657177363 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1699212087 |
|
|
Oct 15 03:54:35 AM UTC 24 |
Oct 15 04:02:29 AM UTC 24 |
5984450208 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.1056327485 |
|
|
Oct 15 03:48:54 AM UTC 24 |
Oct 15 04:02:30 AM UTC 24 |
69932322249 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1138360467 |
|
|
Oct 15 03:57:06 AM UTC 24 |
Oct 15 04:02:41 AM UTC 24 |
23421450673 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4257723317 |
|
|
Oct 15 03:53:40 AM UTC 24 |
Oct 15 04:02:49 AM UTC 24 |
5613704237 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3737603627 |
|
|
Oct 15 03:54:52 AM UTC 24 |
Oct 15 04:02:50 AM UTC 24 |
5992937934 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.4179352604 |
|
|
Oct 15 04:02:51 AM UTC 24 |
Oct 15 04:02:55 AM UTC 24 |
76548117 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1265035148 |
|
|
Oct 15 04:02:08 AM UTC 24 |
Oct 15 04:03:04 AM UTC 24 |
2704402822 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2900818677 |
|
|
Oct 15 04:02:56 AM UTC 24 |
Oct 15 04:03:06 AM UTC 24 |
598698101 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3359624821 |
|
|
Oct 15 04:02:31 AM UTC 24 |
Oct 15 04:03:09 AM UTC 24 |
723877801 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.988854029 |
|
|
Oct 15 04:00:27 AM UTC 24 |
Oct 15 04:03:26 AM UTC 24 |
6795515130 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3580664544 |
|
|
Oct 15 04:03:26 AM UTC 24 |
Oct 15 04:03:28 AM UTC 24 |
29084009 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1911987708 |
|
|
Oct 15 04:02:50 AM UTC 24 |
Oct 15 04:03:33 AM UTC 24 |
459375269 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_readback_err.369753287 |
|
|
Oct 15 04:03:34 AM UTC 24 |
Oct 15 04:03:36 AM UTC 24 |
51162271 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1235811408 |
|
|
Oct 15 04:01:45 AM UTC 24 |
Oct 15 04:03:38 AM UTC 24 |
8287909593 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1480670103 |
|
|
Oct 15 03:55:27 AM UTC 24 |
Oct 15 04:03:39 AM UTC 24 |
15244001548 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.765668818 |
|
|
Oct 15 04:03:39 AM UTC 24 |
Oct 15 04:03:41 AM UTC 24 |
12559416 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2659333557 |
|
|
Oct 15 04:03:33 AM UTC 24 |
Oct 15 04:03:42 AM UTC 24 |
1059027276 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.4132895283 |
|
|
Oct 15 03:46:42 AM UTC 24 |
Oct 15 04:03:43 AM UTC 24 |
14868634725 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1167939815 |
|
|
Oct 15 04:03:29 AM UTC 24 |
Oct 15 04:03:43 AM UTC 24 |
3094748936 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.1683125383 |
|
|
Oct 15 04:03:43 AM UTC 24 |
Oct 15 04:04:03 AM UTC 24 |
1401899465 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2140688834 |
|
|
Oct 15 04:01:33 AM UTC 24 |
Oct 15 04:04:04 AM UTC 24 |
2090541411 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1838669365 |
|
|
Oct 15 03:56:30 AM UTC 24 |
Oct 15 04:04:10 AM UTC 24 |
9606908238 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3579400779 |
|
|
Oct 15 04:04:05 AM UTC 24 |
Oct 15 04:04:11 AM UTC 24 |
295788895 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.3316696084 |
|
|
Oct 15 03:52:13 AM UTC 24 |
Oct 15 04:04:18 AM UTC 24 |
61344948379 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.3377227534 |
|
|
Oct 15 04:03:44 AM UTC 24 |
Oct 15 04:04:19 AM UTC 24 |
2372830366 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.938719096 |
|
|
Oct 15 03:45:33 AM UTC 24 |
Oct 15 04:04:19 AM UTC 24 |
9405080159 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1192459998 |
|
|
Oct 15 03:56:06 AM UTC 24 |
Oct 15 04:04:23 AM UTC 24 |
17548398022 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.2281642872 |
|
|
Oct 15 03:47:02 AM UTC 24 |
Oct 15 04:04:25 AM UTC 24 |
10907416222 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.612542016 |
|
|
Oct 15 04:03:37 AM UTC 24 |
Oct 15 04:04:26 AM UTC 24 |
2366541432 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.1037114692 |
|
|
Oct 15 04:18:13 AM UTC 24 |
Oct 15 04:18:44 AM UTC 24 |
13332895317 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3909799821 |
|
|
Oct 15 04:04:19 AM UTC 24 |
Oct 15 04:04:26 AM UTC 24 |
1739792100 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2140925785 |
|
|
Oct 15 04:04:25 AM UTC 24 |
Oct 15 04:04:28 AM UTC 24 |
296261089 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1205768745 |
|
|
Oct 15 03:56:39 AM UTC 24 |
Oct 15 04:04:31 AM UTC 24 |
3254986185 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_readback_err.3368990904 |
|
|
Oct 15 04:04:29 AM UTC 24 |
Oct 15 04:04:31 AM UTC 24 |
450473317 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3149511148 |
|
|
Oct 15 04:04:28 AM UTC 24 |
Oct 15 04:04:36 AM UTC 24 |
630856651 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3036750761 |
|
|
Oct 15 04:03:44 AM UTC 24 |
Oct 15 04:04:38 AM UTC 24 |
2120456980 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1168087602 |
|
|
Oct 15 04:04:37 AM UTC 24 |
Oct 15 04:04:39 AM UTC 24 |
11868471 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2610771970 |
|
|
Oct 15 04:04:28 AM UTC 24 |
Oct 15 04:04:45 AM UTC 24 |
906672169 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.220449765 |
|
|
Oct 15 03:57:27 AM UTC 24 |
Oct 15 04:04:52 AM UTC 24 |
5086143906 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.424515848 |
|
|
Oct 15 04:04:38 AM UTC 24 |
Oct 15 04:04:55 AM UTC 24 |
2579989114 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.3025602631 |
|
|
Oct 15 03:55:12 AM UTC 24 |
Oct 15 04:05:19 AM UTC 24 |
48313315581 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2599620530 |
|
|
Oct 15 04:04:11 AM UTC 24 |
Oct 15 04:05:22 AM UTC 24 |
603399688 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.191144747 |
|
|
Oct 15 04:04:56 AM UTC 24 |
Oct 15 04:05:22 AM UTC 24 |
6453830803 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2262915228 |
|
|
Oct 15 04:02:30 AM UTC 24 |
Oct 15 04:05:40 AM UTC 24 |
8221625061 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.364047981 |
|
|
Oct 15 03:28:00 AM UTC 24 |
Oct 15 04:05:45 AM UTC 24 |
10512909719 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.636436755 |
|
|
Oct 15 04:05:41 AM UTC 24 |
Oct 15 04:05:54 AM UTC 24 |
815550579 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1433909332 |
|
|
Oct 15 04:04:12 AM UTC 24 |
Oct 15 04:05:57 AM UTC 24 |
586630396 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3094940615 |
|
|
Oct 15 03:47:29 AM UTC 24 |
Oct 15 04:06:04 AM UTC 24 |
201098818998 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2721188300 |
|
|
Oct 15 04:04:46 AM UTC 24 |
Oct 15 04:06:05 AM UTC 24 |
3081658095 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1270873994 |
|
|
Oct 15 04:06:05 AM UTC 24 |
Oct 15 04:06:08 AM UTC 24 |
109039601 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3827214981 |
|
|
Oct 15 04:05:22 AM UTC 24 |
Oct 15 04:06:12 AM UTC 24 |
111980636 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.31259490 |
|
|
Oct 15 04:06:09 AM UTC 24 |
Oct 15 04:06:14 AM UTC 24 |
61577353 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2972758920 |
|
|
Oct 15 04:06:05 AM UTC 24 |
Oct 15 04:06:14 AM UTC 24 |
175146663 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_readback_err.1841211107 |
|
|
Oct 15 04:06:13 AM UTC 24 |
Oct 15 04:06:15 AM UTC 24 |
161455010 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3806507160 |
|
|
Oct 15 04:06:16 AM UTC 24 |
Oct 15 04:06:18 AM UTC 24 |
173797119 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.3726028835 |
|
|
Oct 15 04:06:19 AM UTC 24 |
Oct 15 04:06:29 AM UTC 24 |
388636791 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.892347805 |
|
|
Oct 15 03:42:05 AM UTC 24 |
Oct 15 04:06:50 AM UTC 24 |
91997840538 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.322719233 |
|
|
Oct 15 04:00:37 AM UTC 24 |
Oct 15 04:06:54 AM UTC 24 |
17738488965 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1350753310 |
|
|
Oct 15 04:04:32 AM UTC 24 |
Oct 15 04:06:59 AM UTC 24 |
6141410639 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1668627663 |
|
|
Oct 15 04:06:51 AM UTC 24 |
Oct 15 04:07:09 AM UTC 24 |
1544701176 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3421207409 |
|
|
Oct 15 04:07:00 AM UTC 24 |
Oct 15 04:07:15 AM UTC 24 |
205071570 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3338876732 |
|
|
Oct 15 04:05:23 AM UTC 24 |
Oct 15 04:07:20 AM UTC 24 |
285134231 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.4085415045 |
|
|
Oct 15 03:59:42 AM UTC 24 |
Oct 15 04:07:20 AM UTC 24 |
2091004432 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.215280387 |
|
|
Oct 15 04:07:21 AM UTC 24 |
Oct 15 04:07:26 AM UTC 24 |
225987140 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1208419502 |
|
|
Oct 15 04:07:16 AM UTC 24 |
Oct 15 04:07:48 AM UTC 24 |
782374645 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2485895166 |
|
|
Oct 15 04:06:15 AM UTC 24 |
Oct 15 04:08:06 AM UTC 24 |
6385733361 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.543272575 |
|
|
Oct 15 03:50:00 AM UTC 24 |
Oct 15 04:08:20 AM UTC 24 |
16975644364 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2030974205 |
|
|
Oct 15 04:08:20 AM UTC 24 |
Oct 15 04:08:22 AM UTC 24 |
106032968 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.4291567555 |
|
|
Oct 15 04:03:44 AM UTC 24 |
Oct 15 04:08:39 AM UTC 24 |
8352501155 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.474744412 |
|
|
Oct 15 03:57:46 AM UTC 24 |
Oct 15 04:08:39 AM UTC 24 |
35489781235 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3310453022 |
|
|
Oct 15 04:08:23 AM UTC 24 |
Oct 15 04:08:40 AM UTC 24 |
7259872195 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1950152385 |
|
|
Oct 15 04:07:21 AM UTC 24 |
Oct 15 04:08:43 AM UTC 24 |
524448535 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_readback_err.1968901951 |
|
|
Oct 15 04:08:41 AM UTC 24 |
Oct 15 04:08:43 AM UTC 24 |
37223741 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1902773315 |
|
|
Oct 15 04:08:40 AM UTC 24 |
Oct 15 04:08:45 AM UTC 24 |
287324035 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2253210157 |
|
|
Oct 15 04:08:44 AM UTC 24 |
Oct 15 04:08:46 AM UTC 24 |
15307377 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.3747048099 |
|
|
Oct 15 04:08:45 AM UTC 24 |
Oct 15 04:08:56 AM UTC 24 |
1733477383 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.1674836077 |
|
|
Oct 15 03:56:46 AM UTC 24 |
Oct 15 04:09:03 AM UTC 24 |
4290909944 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.359495926 |
|
|
Oct 15 04:08:57 AM UTC 24 |
Oct 15 04:09:16 AM UTC 24 |
258275721 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.4097206724 |
|
|
Oct 15 04:04:53 AM UTC 24 |
Oct 15 04:09:28 AM UTC 24 |
14606564205 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1706612801 |
|
|
Oct 15 04:09:17 AM UTC 24 |
Oct 15 04:09:33 AM UTC 24 |
2425199197 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.994284208 |
|
|
Oct 15 03:43:45 AM UTC 24 |
Oct 15 04:09:33 AM UTC 24 |
51895924605 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.779562960 |
|
|
Oct 15 03:48:54 AM UTC 24 |
Oct 15 04:09:46 AM UTC 24 |
90272278834 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1427484478 |
|
|
Oct 15 04:01:57 AM UTC 24 |
Oct 15 04:09:51 AM UTC 24 |
9122832961 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.37329930 |
|
|
Oct 15 04:09:46 AM UTC 24 |
Oct 15 04:09:57 AM UTC 24 |
1435151676 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.421329006 |
|
|
Oct 15 04:05:20 AM UTC 24 |
Oct 15 04:10:05 AM UTC 24 |
8130395533 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1018821807 |
|
|
Oct 15 04:09:34 AM UTC 24 |
Oct 15 04:10:16 AM UTC 24 |
136093729 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4248076367 |
|
|
Oct 15 04:10:17 AM UTC 24 |
Oct 15 04:10:19 AM UTC 24 |
377140061 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2480897537 |
|
|
Oct 15 03:57:45 AM UTC 24 |
Oct 15 04:10:21 AM UTC 24 |
15746979476 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2847547628 |
|
|
Oct 15 03:29:50 AM UTC 24 |
Oct 15 04:10:24 AM UTC 24 |
31391576141 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.451922631 |
|
|
Oct 15 04:06:15 AM UTC 24 |
Oct 15 04:10:27 AM UTC 24 |
6218717849 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_readback_err.3719441192 |
|
|
Oct 15 04:10:25 AM UTC 24 |
Oct 15 04:10:28 AM UTC 24 |
28187009 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1345419869 |
|
|
Oct 15 04:10:21 AM UTC 24 |
Oct 15 04:10:29 AM UTC 24 |
356996190 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1600280412 |
|
|
Oct 15 04:10:30 AM UTC 24 |
Oct 15 04:10:32 AM UTC 24 |
32426469 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2108260904 |
|
|
Oct 15 04:10:20 AM UTC 24 |
Oct 15 04:10:33 AM UTC 24 |
643172234 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2104129748 |
|
|
Oct 15 04:10:33 AM UTC 24 |
Oct 15 04:10:46 AM UTC 24 |
257270172 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.916037297 |
|
|
Oct 15 04:10:29 AM UTC 24 |
Oct 15 04:10:56 AM UTC 24 |
974766298 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.583665541 |
|
|
Oct 15 03:50:01 AM UTC 24 |
Oct 15 04:10:58 AM UTC 24 |
3487004681 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1052486330 |
|
|
Oct 15 04:02:42 AM UTC 24 |
Oct 15 04:11:02 AM UTC 24 |
83492751979 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.4037126216 |
|
|
Oct 15 04:09:34 AM UTC 24 |
Oct 15 04:11:07 AM UTC 24 |
141102095 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1050171118 |
|
|
Oct 15 04:11:08 AM UTC 24 |
Oct 15 04:11:10 AM UTC 24 |
111779706 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1564846411 |
|
|
Oct 15 03:51:27 AM UTC 24 |
Oct 15 04:11:21 AM UTC 24 |
14596694013 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2075186676 |
|
|
Oct 15 04:08:46 AM UTC 24 |
Oct 15 04:11:22 AM UTC 24 |
1764638845 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3806632545 |
|
|
Oct 15 04:11:22 AM UTC 24 |
Oct 15 04:11:33 AM UTC 24 |
1211244897 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.870294582 |
|
|
Oct 15 04:10:47 AM UTC 24 |
Oct 15 04:11:42 AM UTC 24 |
13580132409 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1291621226 |
|
|
Oct 15 04:10:06 AM UTC 24 |
Oct 15 04:11:44 AM UTC 24 |
1699453105 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3346794754 |
|
|
Oct 15 03:43:45 AM UTC 24 |
Oct 15 04:11:45 AM UTC 24 |
108282409964 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1751472094 |
|
|
Oct 15 04:11:45 AM UTC 24 |
Oct 15 04:11:47 AM UTC 24 |
76691765 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2812015816 |
|
|
Oct 15 04:11:48 AM UTC 24 |
Oct 15 04:11:52 AM UTC 24 |
678763838 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1955503066 |
|
|
Oct 15 04:11:46 AM UTC 24 |
Oct 15 04:11:53 AM UTC 24 |
71853177 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_readback_err.2763341470 |
|
|
Oct 15 04:11:53 AM UTC 24 |
Oct 15 04:11:56 AM UTC 24 |
95264718 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.52495933 |
|
|
Oct 15 04:03:05 AM UTC 24 |
Oct 15 04:11:56 AM UTC 24 |
10812112673 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2457626804 |
|
|
Oct 15 04:11:58 AM UTC 24 |
Oct 15 04:12:00 AM UTC 24 |
19579970 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.341452299 |
|
|
Oct 15 03:53:43 AM UTC 24 |
Oct 15 04:12:00 AM UTC 24 |
14576974291 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3593077741 |
|
|
Oct 15 04:10:59 AM UTC 24 |
Oct 15 04:12:09 AM UTC 24 |
2040185115 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.342396379 |
|
|
Oct 15 04:04:05 AM UTC 24 |
Oct 15 04:12:16 AM UTC 24 |
21343656478 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.432871115 |
|
|
Oct 15 04:11:11 AM UTC 24 |
Oct 15 04:12:37 AM UTC 24 |
279792337 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1219077537 |
|
|
Oct 15 04:12:10 AM UTC 24 |
Oct 15 04:13:00 AM UTC 24 |
2520382819 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2219126272 |
|
|
Oct 15 04:12:37 AM UTC 24 |
Oct 15 04:13:01 AM UTC 24 |
1625187652 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2159771048 |
|
|
Oct 15 04:08:41 AM UTC 24 |
Oct 15 04:13:16 AM UTC 24 |
2685910475 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.2068192603 |
|
|
Oct 15 04:12:01 AM UTC 24 |
Oct 15 04:13:32 AM UTC 24 |
637105657 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1980982437 |
|
|
Oct 15 04:13:33 AM UTC 24 |
Oct 15 04:13:46 AM UTC 24 |
2161040800 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1967135393 |
|
|
Oct 15 04:13:17 AM UTC 24 |
Oct 15 04:13:57 AM UTC 24 |
214263704 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2025194683 |
|
|
Oct 15 04:06:56 AM UTC 24 |
Oct 15 04:14:08 AM UTC 24 |
4036940897 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2704775174 |
|
|
Oct 15 04:14:09 AM UTC 24 |
Oct 15 04:14:11 AM UTC 24 |
29474326 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2414237980 |
|
|
Oct 15 04:14:12 AM UTC 24 |
Oct 15 04:14:21 AM UTC 24 |
939004750 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.930324503 |
|
|
Oct 15 04:07:10 AM UTC 24 |
Oct 15 04:14:22 AM UTC 24 |
20994047975 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_readback_err.2987328604 |
|
|
Oct 15 04:14:23 AM UTC 24 |
Oct 15 04:14:25 AM UTC 24 |
106074345 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1840447294 |
|
|
Oct 15 04:09:29 AM UTC 24 |
Oct 15 04:14:25 AM UTC 24 |
66853266408 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1282913401 |
|
|
Oct 15 04:14:22 AM UTC 24 |
Oct 15 04:14:27 AM UTC 24 |
370210272 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.3551000663 |
|
|
Oct 15 04:01:36 AM UTC 24 |
Oct 15 04:14:30 AM UTC 24 |
38199539184 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1379315298 |
|
|
Oct 15 04:14:29 AM UTC 24 |
Oct 15 04:14:30 AM UTC 24 |
51516569 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3653471734 |
|
|
Oct 15 04:13:03 AM UTC 24 |
Oct 15 04:14:35 AM UTC 24 |
449172146 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.12719207 |
|
|
Oct 15 04:09:05 AM UTC 24 |
Oct 15 04:14:37 AM UTC 24 |
11252750295 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.3374658162 |
|
|
Oct 15 04:14:31 AM UTC 24 |
Oct 15 04:14:43 AM UTC 24 |
652235397 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1634296298 |
|
|
Oct 15 04:14:26 AM UTC 24 |
Oct 15 04:14:45 AM UTC 24 |
1758857846 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2199084199 |
|
|
Oct 15 04:14:44 AM UTC 24 |
Oct 15 04:14:48 AM UTC 24 |
417369569 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1279628028 |
|
|
Oct 15 04:12:17 AM UTC 24 |
Oct 15 04:15:18 AM UTC 24 |
1467215142 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1192381467 |
|
|
Oct 15 03:34:57 AM UTC 24 |
Oct 15 04:15:22 AM UTC 24 |
20629853850 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.924184989 |
|
|
Oct 15 04:14:49 AM UTC 24 |
Oct 15 04:15:27 AM UTC 24 |
96956210 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2440908546 |
|
|
Oct 15 04:08:06 AM UTC 24 |
Oct 15 04:15:29 AM UTC 24 |
5797191452 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1283625344 |
|
|
Oct 15 04:15:23 AM UTC 24 |
Oct 15 04:15:29 AM UTC 24 |
4021887865 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2572105660 |
|
|
Oct 15 03:04:18 AM UTC 24 |
Oct 15 04:15:41 AM UTC 24 |
50631457946 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3553094892 |
|
|
Oct 15 04:15:41 AM UTC 24 |
Oct 15 04:15:43 AM UTC 24 |
30809660 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3050851680 |
|
|
Oct 15 04:10:57 AM UTC 24 |
Oct 15 04:15:48 AM UTC 24 |
23640204924 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2114392420 |
|
|
Oct 15 04:15:50 AM UTC 24 |
Oct 15 04:15:57 AM UTC 24 |
91304744 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.871244455 |
|
|
Oct 15 04:15:44 AM UTC 24 |
Oct 15 04:15:59 AM UTC 24 |
751760187 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_readback_err.2715280741 |
|
|
Oct 15 04:15:58 AM UTC 24 |
Oct 15 04:16:00 AM UTC 24 |
28507484 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2471861920 |
|
|
Oct 15 04:15:19 AM UTC 24 |
Oct 15 04:16:04 AM UTC 24 |
426719639 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.685011758 |
|
|
Oct 15 04:16:05 AM UTC 24 |
Oct 15 04:16:07 AM UTC 24 |
39957333 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1349179951 |
|
|
Oct 15 04:14:36 AM UTC 24 |
Oct 15 04:16:13 AM UTC 24 |
7254509691 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1455882559 |
|
|
Oct 15 04:05:46 AM UTC 24 |
Oct 15 04:16:15 AM UTC 24 |
3198914478 ps |
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/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.4284232409 |
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Oct 15 04:16:08 AM UTC 24 |
Oct 15 04:16:27 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2729406752 |
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Oct 15 04:11:43 AM UTC 24 |
Oct 15 04:16:40 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3797347201 |
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Oct 15 04:16:16 AM UTC 24 |
Oct 15 04:16:48 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.559651540 |
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Oct 15 04:14:38 AM UTC 24 |
Oct 15 04:16:56 AM UTC 24 |
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| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.3640969204 |
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Oct 15 04:04:20 AM UTC 24 |
Oct 15 04:17:05 AM UTC 24 |
6703748457 ps |
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/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3504127020 |
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Oct 15 04:03:08 AM UTC 24 |
Oct 15 04:17:07 AM UTC 24 |
2511864214 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.489517804 |
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Oct 15 04:17:06 AM UTC 24 |
Oct 15 04:17:08 AM UTC 24 |
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| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1375889082 |
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Oct 15 04:17:08 AM UTC 24 |
Oct 15 04:17:15 AM UTC 24 |
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| T792 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.636159773 |
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Oct 15 04:16:41 AM UTC 24 |
Oct 15 04:17:23 AM UTC 24 |
386051283 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1427182908 |
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Oct 15 04:16:00 AM UTC 24 |
Oct 15 04:17:24 AM UTC 24 |
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| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.624257925 |
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Oct 15 04:17:25 AM UTC 24 |
Oct 15 04:17:27 AM UTC 24 |
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| T795 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3511153463 |
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Oct 15 03:54:10 AM UTC 24 |
Oct 15 04:17:28 AM UTC 24 |
83987720097 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1315060352 |
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Oct 15 04:17:30 AM UTC 24 |
Oct 15 04:17:37 AM UTC 24 |
124885241 ps |