| T548 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2263975153 |
|
|
Feb 08 12:05:47 PM UTC 25 |
Feb 08 12:17:06 PM UTC 25 |
7579434882 ps |
| T549 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.849878018 |
|
|
Feb 08 12:16:59 PM UTC 25 |
Feb 08 12:17:10 PM UTC 25 |
3682250902 ps |
| T550 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2502789731 |
|
|
Feb 08 12:14:51 PM UTC 25 |
Feb 08 12:17:10 PM UTC 25 |
1198187885 ps |
| T551 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1995245378 |
|
|
Feb 08 12:12:06 PM UTC 25 |
Feb 08 12:17:11 PM UTC 25 |
4179480974 ps |
| T552 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1921608407 |
|
|
Feb 08 12:17:12 PM UTC 25 |
Feb 08 12:17:14 PM UTC 25 |
33611799 ps |
| T553 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2934413109 |
|
|
Feb 08 12:17:16 PM UTC 25 |
Feb 08 12:17:22 PM UTC 25 |
74208160 ps |
| T554 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3609766354 |
|
|
Feb 08 12:11:05 PM UTC 25 |
Feb 08 12:17:26 PM UTC 25 |
57364244981 ps |
| T555 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2065146085 |
|
|
Feb 08 12:16:46 PM UTC 25 |
Feb 08 12:17:28 PM UTC 25 |
807872687 ps |
| T556 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.177281863 |
|
|
Feb 08 12:17:24 PM UTC 25 |
Feb 08 12:17:30 PM UTC 25 |
454796606 ps |
| T557 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3461451729 |
|
|
Feb 08 12:17:31 PM UTC 25 |
Feb 08 12:17:33 PM UTC 25 |
46577548 ps |
| T558 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.459827485 |
|
|
Feb 08 12:16:49 PM UTC 25 |
Feb 08 12:17:34 PM UTC 25 |
489200353 ps |
| T559 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.3554192549 |
|
|
Feb 08 12:17:34 PM UTC 25 |
Feb 08 12:17:46 PM UTC 25 |
664364386 ps |
| T560 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2606837407 |
|
|
Feb 08 12:15:47 PM UTC 25 |
Feb 08 12:18:00 PM UTC 25 |
4116727399 ps |
| T561 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1507275582 |
|
|
Feb 08 11:47:22 AM UTC 25 |
Feb 08 12:18:04 PM UTC 25 |
65870240172 ps |
| T562 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.181712619 |
|
|
Feb 08 12:14:24 PM UTC 25 |
Feb 08 12:18:14 PM UTC 25 |
1281505794 ps |
| T563 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1381107032 |
|
|
Feb 08 12:14:52 PM UTC 25 |
Feb 08 12:18:18 PM UTC 25 |
29686422570 ps |
| T564 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.4106429573 |
|
|
Feb 08 12:18:05 PM UTC 25 |
Feb 08 12:18:25 PM UTC 25 |
1422856823 ps |
| T565 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3544470675 |
|
|
Feb 08 12:01:54 PM UTC 25 |
Feb 08 12:18:25 PM UTC 25 |
4039509431 ps |
| T566 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.28236021 |
|
|
Feb 08 12:17:47 PM UTC 25 |
Feb 08 12:18:27 PM UTC 25 |
5331515426 ps |
| T567 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.653173928 |
|
|
Feb 08 12:00:40 PM UTC 25 |
Feb 08 12:18:27 PM UTC 25 |
13001032909 ps |
| T568 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.323075696 |
|
|
Feb 08 12:18:26 PM UTC 25 |
Feb 08 12:18:40 PM UTC 25 |
861872600 ps |
| T569 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.156168443 |
|
|
Feb 08 12:14:41 PM UTC 25 |
Feb 08 12:18:44 PM UTC 25 |
13153609044 ps |
| T570 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2702682579 |
|
|
Feb 08 12:18:45 PM UTC 25 |
Feb 08 12:18:47 PM UTC 25 |
86215266 ps |
| T571 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2684915303 |
|
|
Feb 08 12:15:15 PM UTC 25 |
Feb 08 12:18:48 PM UTC 25 |
13848169919 ps |
| T572 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2818475887 |
|
|
Feb 08 12:18:48 PM UTC 25 |
Feb 08 12:18:57 PM UTC 25 |
179467243 ps |
| T573 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.827766434 |
|
|
Feb 08 12:18:48 PM UTC 25 |
Feb 08 12:18:57 PM UTC 25 |
337908988 ps |
| T574 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.965978759 |
|
|
Feb 08 12:15:49 PM UTC 25 |
Feb 08 12:19:10 PM UTC 25 |
1863332979 ps |
| T575 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4175118472 |
|
|
Feb 08 12:19:11 PM UTC 25 |
Feb 08 12:19:14 PM UTC 25 |
20061081 ps |
| T576 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.934124724 |
|
|
Feb 08 12:05:53 PM UTC 25 |
Feb 08 12:19:14 PM UTC 25 |
15528574942 ps |
| T577 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1656956880 |
|
|
Feb 08 12:15:34 PM UTC 25 |
Feb 08 12:19:15 PM UTC 25 |
3137786254 ps |
| T578 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2649579704 |
|
|
Feb 08 12:13:22 PM UTC 25 |
Feb 08 12:19:23 PM UTC 25 |
16515869314 ps |
| T579 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3606908519 |
|
|
Feb 08 12:18:19 PM UTC 25 |
Feb 08 12:19:25 PM UTC 25 |
422285575 ps |
| T580 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.889406411 |
|
|
Feb 08 12:16:18 PM UTC 25 |
Feb 08 12:19:32 PM UTC 25 |
1828791339 ps |
| T581 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2923115797 |
|
|
Feb 08 12:19:26 PM UTC 25 |
Feb 08 12:19:35 PM UTC 25 |
317741779 ps |
| T582 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1088537361 |
|
|
Feb 08 12:19:33 PM UTC 25 |
Feb 08 12:19:40 PM UTC 25 |
55049603 ps |
| T108 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1947777561 |
|
|
Feb 08 12:17:27 PM UTC 25 |
Feb 08 12:19:50 PM UTC 25 |
2744799870 ps |
| T583 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2873895590 |
|
|
Feb 08 12:19:41 PM UTC 25 |
Feb 08 12:19:54 PM UTC 25 |
791281679 ps |
| T584 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2704215690 |
|
|
Feb 08 12:19:35 PM UTC 25 |
Feb 08 12:19:58 PM UTC 25 |
163696470 ps |
| T585 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.550123944 |
|
|
Feb 08 12:18:25 PM UTC 25 |
Feb 08 12:20:00 PM UTC 25 |
146164770 ps |
| T586 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.892123609 |
|
|
Feb 08 12:20:01 PM UTC 25 |
Feb 08 12:20:04 PM UTC 25 |
48029931 ps |
| T587 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1472031712 |
|
|
Feb 08 11:51:48 AM UTC 25 |
Feb 08 12:20:04 PM UTC 25 |
5192049214 ps |
| T588 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3963883475 |
|
|
Feb 08 12:20:05 PM UTC 25 |
Feb 08 12:20:13 PM UTC 25 |
288880827 ps |
| T589 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1895922339 |
|
|
Feb 08 12:20:05 PM UTC 25 |
Feb 08 12:20:13 PM UTC 25 |
106797699 ps |
| T590 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2711147631 |
|
|
Feb 08 12:19:16 PM UTC 25 |
Feb 08 12:20:37 PM UTC 25 |
39546645877 ps |
| T109 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.4059551545 |
|
|
Feb 08 12:18:58 PM UTC 25 |
Feb 08 12:20:37 PM UTC 25 |
2886698034 ps |
| T591 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2579580086 |
|
|
Feb 08 12:20:37 PM UTC 25 |
Feb 08 12:20:40 PM UTC 25 |
23616846 ps |
| T592 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.4277120700 |
|
|
Feb 08 12:20:39 PM UTC 25 |
Feb 08 12:20:45 PM UTC 25 |
380687416 ps |
| T593 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.730321457 |
|
|
Feb 08 12:10:26 PM UTC 25 |
Feb 08 12:20:47 PM UTC 25 |
9128596058 ps |
| T594 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2539490345 |
|
|
Feb 08 12:07:28 PM UTC 25 |
Feb 08 12:20:59 PM UTC 25 |
2113092990 ps |
| T595 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.2780706728 |
|
|
Feb 08 12:10:29 PM UTC 25 |
Feb 08 12:21:05 PM UTC 25 |
48874922443 ps |
| T596 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1605071152 |
|
|
Feb 08 11:38:20 AM UTC 25 |
Feb 08 12:21:07 PM UTC 25 |
166173010209 ps |
| T597 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2188669001 |
|
|
Feb 08 12:21:00 PM UTC 25 |
Feb 08 12:21:15 PM UTC 25 |
161370154 ps |
| T598 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1556079568 |
|
|
Feb 08 12:20:14 PM UTC 25 |
Feb 08 12:21:39 PM UTC 25 |
4246018561 ps |
| T599 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1261478856 |
|
|
Feb 08 12:20:46 PM UTC 25 |
Feb 08 12:21:40 PM UTC 25 |
2688396025 ps |
| T600 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.2742407389 |
|
|
Feb 08 12:05:51 PM UTC 25 |
Feb 08 12:21:49 PM UTC 25 |
3487223781 ps |
| T601 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3606598664 |
|
|
Feb 08 12:21:41 PM UTC 25 |
Feb 08 12:21:49 PM UTC 25 |
858605021 ps |
| T602 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.3553548022 |
|
|
Feb 08 12:09:06 PM UTC 25 |
Feb 08 12:22:02 PM UTC 25 |
3150190828 ps |
| T603 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.4082520537 |
|
|
Feb 08 12:21:16 PM UTC 25 |
Feb 08 12:22:03 PM UTC 25 |
388687189 ps |
| T604 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.360578755 |
|
|
Feb 08 12:22:03 PM UTC 25 |
Feb 08 12:22:06 PM UTC 25 |
115094696 ps |
| T605 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.991191919 |
|
|
Feb 08 12:19:24 PM UTC 25 |
Feb 08 12:22:07 PM UTC 25 |
1517864201 ps |
| T606 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.142738605 |
|
|
Feb 08 12:22:06 PM UTC 25 |
Feb 08 12:22:14 PM UTC 25 |
269316335 ps |
| T607 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1199400148 |
|
|
Feb 08 12:18:01 PM UTC 25 |
Feb 08 12:22:16 PM UTC 25 |
9709497546 ps |
| T608 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2625538633 |
|
|
Feb 08 12:22:09 PM UTC 25 |
Feb 08 12:22:18 PM UTC 25 |
166120933 ps |
| T609 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3483527563 |
|
|
Feb 08 12:22:17 PM UTC 25 |
Feb 08 12:22:19 PM UTC 25 |
11909158 ps |
| T610 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1800024492 |
|
|
Feb 08 12:21:07 PM UTC 25 |
Feb 08 12:22:19 PM UTC 25 |
125245428 ps |
| T611 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3902925191 |
|
|
Feb 08 12:22:04 PM UTC 25 |
Feb 08 12:22:20 PM UTC 25 |
2355107813 ps |
| T612 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.1069312242 |
|
|
Feb 08 12:21:50 PM UTC 25 |
Feb 08 12:22:27 PM UTC 25 |
2076565689 ps |
| T613 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1799558742 |
|
|
Feb 08 12:19:52 PM UTC 25 |
Feb 08 12:22:36 PM UTC 25 |
31626545099 ps |
| T614 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2237173294 |
|
|
Feb 08 12:22:28 PM UTC 25 |
Feb 08 12:22:38 PM UTC 25 |
182622662 ps |
| T615 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.505966952 |
|
|
Feb 08 12:10:32 PM UTC 25 |
Feb 08 12:22:54 PM UTC 25 |
27564348700 ps |
| T616 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.3224751916 |
|
|
Feb 08 12:22:19 PM UTC 25 |
Feb 08 12:23:03 PM UTC 25 |
212165944 ps |
| T617 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2805154266 |
|
|
Feb 08 12:23:04 PM UTC 25 |
Feb 08 12:23:10 PM UTC 25 |
588018535 ps |
| T618 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1432782532 |
|
|
Feb 08 12:22:55 PM UTC 25 |
Feb 08 12:23:36 PM UTC 25 |
110490151 ps |
| T619 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1780352682 |
|
|
Feb 08 12:12:45 PM UTC 25 |
Feb 08 12:23:37 PM UTC 25 |
25841279362 ps |
| T620 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.1238423836 |
|
|
Feb 08 12:22:20 PM UTC 25 |
Feb 08 12:23:38 PM UTC 25 |
995376298 ps |
| T621 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3790577684 |
|
|
Feb 08 12:23:38 PM UTC 25 |
Feb 08 12:23:41 PM UTC 25 |
34274133 ps |
| T622 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3793996628 |
|
|
Feb 08 12:17:11 PM UTC 25 |
Feb 08 12:23:45 PM UTC 25 |
18908128751 ps |
| T623 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.169622973 |
|
|
Feb 08 12:23:47 PM UTC 25 |
Feb 08 12:23:54 PM UTC 25 |
78335333 ps |
| T624 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3890125527 |
|
|
Feb 08 12:23:42 PM UTC 25 |
Feb 08 12:23:55 PM UTC 25 |
501318150 ps |
| T625 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2231783763 |
|
|
Feb 08 12:19:32 PM UTC 25 |
Feb 08 12:23:59 PM UTC 25 |
20520225409 ps |
| T626 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.4087296491 |
|
|
Feb 08 12:24:00 PM UTC 25 |
Feb 08 12:24:02 PM UTC 25 |
43779849 ps |
| T627 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.379980752 |
|
|
Feb 08 12:09:44 PM UTC 25 |
Feb 08 12:24:06 PM UTC 25 |
13609207924 ps |
| T628 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1410217136 |
|
|
Feb 08 12:02:20 PM UTC 25 |
Feb 08 12:24:08 PM UTC 25 |
39665703455 ps |
| T629 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.4141802744 |
|
|
Feb 08 12:18:15 PM UTC 25 |
Feb 08 12:24:27 PM UTC 25 |
26459241889 ps |
| T630 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2701688039 |
|
|
Feb 08 11:37:29 AM UTC 25 |
Feb 08 12:24:34 PM UTC 25 |
76468974937 ps |
| T631 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.1344959526 |
|
|
Feb 08 12:12:26 PM UTC 25 |
Feb 08 12:24:36 PM UTC 25 |
52927522859 ps |
| T632 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1895343760 |
|
|
Feb 08 12:16:33 PM UTC 25 |
Feb 08 12:24:57 PM UTC 25 |
71301040070 ps |
| T633 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1410985318 |
|
|
Feb 08 12:24:35 PM UTC 25 |
Feb 08 12:25:06 PM UTC 25 |
2299363843 ps |
| T634 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2283426183 |
|
|
Feb 08 12:24:03 PM UTC 25 |
Feb 08 12:25:07 PM UTC 25 |
4388099922 ps |
| T635 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.4156807919 |
|
|
Feb 08 12:23:36 PM UTC 25 |
Feb 08 12:25:08 PM UTC 25 |
2407748864 ps |
| T636 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2711370268 |
|
|
Feb 08 12:22:39 PM UTC 25 |
Feb 08 12:25:10 PM UTC 25 |
139608923 ps |
| T637 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.3979485879 |
|
|
Feb 08 12:24:09 PM UTC 25 |
Feb 08 12:25:11 PM UTC 25 |
3271833865 ps |
| T638 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2079851287 |
|
|
Feb 08 12:25:07 PM UTC 25 |
Feb 08 12:25:15 PM UTC 25 |
320333518 ps |
| T639 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.4293480040 |
|
|
Feb 08 12:25:16 PM UTC 25 |
Feb 08 12:25:19 PM UTC 25 |
45359243 ps |
| T640 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.255531761 |
|
|
Feb 08 12:20:48 PM UTC 25 |
Feb 08 12:25:25 PM UTC 25 |
8617495172 ps |
| T641 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3787980970 |
|
|
Feb 08 12:25:07 PM UTC 25 |
Feb 08 12:25:26 PM UTC 25 |
325598308 ps |
| T642 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1470793738 |
|
|
Feb 08 12:25:20 PM UTC 25 |
Feb 08 12:25:32 PM UTC 25 |
3207279715 ps |
| T643 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2369878967 |
|
|
Feb 08 12:25:26 PM UTC 25 |
Feb 08 12:25:35 PM UTC 25 |
1182861306 ps |
| T644 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.19043905 |
|
|
Feb 08 12:25:36 PM UTC 25 |
Feb 08 12:25:38 PM UTC 25 |
44056514 ps |
| T645 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2099629219 |
|
|
Feb 08 12:19:55 PM UTC 25 |
Feb 08 12:25:39 PM UTC 25 |
1084836836 ps |
| T646 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.1559373451 |
|
|
Feb 08 12:12:26 PM UTC 25 |
Feb 08 12:25:45 PM UTC 25 |
16527421778 ps |
| T647 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.584411595 |
|
|
Feb 08 12:24:58 PM UTC 25 |
Feb 08 12:25:49 PM UTC 25 |
114581842 ps |
| T648 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.4196313038 |
|
|
Feb 08 12:25:39 PM UTC 25 |
Feb 08 12:26:07 PM UTC 25 |
1426768548 ps |
| T649 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1463520612 |
|
|
Feb 08 12:25:53 PM UTC 25 |
Feb 08 12:26:11 PM UTC 25 |
261775436 ps |
| T650 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1791256382 |
|
|
Feb 08 11:58:29 AM UTC 25 |
Feb 08 12:26:19 PM UTC 25 |
12125896766 ps |
| T651 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.198622541 |
|
|
Feb 08 12:26:20 PM UTC 25 |
Feb 08 12:26:24 PM UTC 25 |
44305415 ps |
| T652 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3645104488 |
|
|
Feb 08 12:26:25 PM UTC 25 |
Feb 08 12:26:28 PM UTC 25 |
188781592 ps |
| T110 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.531861282 |
|
|
Feb 08 12:25:28 PM UTC 25 |
Feb 08 12:26:47 PM UTC 25 |
4954556907 ps |
| T653 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1153191912 |
|
|
Feb 08 12:25:46 PM UTC 25 |
Feb 08 12:26:49 PM UTC 25 |
2997755006 ps |
| T654 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2320220888 |
|
|
Feb 08 12:20:41 PM UTC 25 |
Feb 08 12:26:59 PM UTC 25 |
5079689337 ps |
| T655 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2172822358 |
|
|
Feb 08 12:27:00 PM UTC 25 |
Feb 08 12:27:02 PM UTC 25 |
75894227 ps |
| T656 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1010717881 |
|
|
Feb 08 12:27:03 PM UTC 25 |
Feb 08 12:27:12 PM UTC 25 |
296822188 ps |
| T657 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3068614351 |
|
|
Feb 08 12:27:12 PM UTC 25 |
Feb 08 12:27:18 PM UTC 25 |
498828311 ps |
| T658 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2883717965 |
|
|
Feb 08 12:22:36 PM UTC 25 |
Feb 08 12:27:31 PM UTC 25 |
8160361079 ps |
| T659 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1220228093 |
|
|
Feb 08 12:17:10 PM UTC 25 |
Feb 08 12:27:35 PM UTC 25 |
58553720345 ps |
| T660 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1182196400 |
|
|
Feb 08 12:27:36 PM UTC 25 |
Feb 08 12:27:38 PM UTC 25 |
43875855 ps |
| T661 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3025519588 |
|
|
Feb 08 11:50:16 AM UTC 25 |
Feb 08 12:27:41 PM UTC 25 |
61166907941 ps |
| T662 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.1504034080 |
|
|
Feb 08 12:11:17 PM UTC 25 |
Feb 08 12:27:46 PM UTC 25 |
18039015739 ps |
| T663 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2110549199 |
|
|
Feb 08 12:27:39 PM UTC 25 |
Feb 08 12:27:54 PM UTC 25 |
912703197 ps |
| T664 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2590319560 |
|
|
Feb 08 12:26:12 PM UTC 25 |
Feb 08 12:28:10 PM UTC 25 |
265276785 ps |
| T665 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1212555669 |
|
|
Feb 08 12:28:11 PM UTC 25 |
Feb 08 12:28:18 PM UTC 25 |
155811971 ps |
| T666 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.4061761606 |
|
|
Feb 08 12:15:15 PM UTC 25 |
Feb 08 12:28:24 PM UTC 25 |
5237248824 ps |
| T667 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3833556732 |
|
|
Feb 08 12:04:31 PM UTC 25 |
Feb 08 12:28:48 PM UTC 25 |
51388291449 ps |
| T668 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.1663414255 |
|
|
Feb 08 12:27:47 PM UTC 25 |
Feb 08 12:28:52 PM UTC 25 |
2573847156 ps |
| T669 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1012472353 |
|
|
Feb 08 12:21:06 PM UTC 25 |
Feb 08 12:28:54 PM UTC 25 |
128079889036 ps |
| T670 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2881354930 |
|
|
Feb 08 12:21:41 PM UTC 25 |
Feb 08 12:28:55 PM UTC 25 |
4710933013 ps |
| T671 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.588874741 |
|
|
Feb 08 12:28:26 PM UTC 25 |
Feb 08 12:28:55 PM UTC 25 |
439026269 ps |
| T672 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2517224130 |
|
|
Feb 08 12:28:53 PM UTC 25 |
Feb 08 12:28:57 PM UTC 25 |
444550029 ps |
| T673 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1889503510 |
|
|
Feb 08 12:11:34 PM UTC 25 |
Feb 08 12:29:00 PM UTC 25 |
30664016379 ps |
| T674 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.430924023 |
|
|
Feb 08 12:24:27 PM UTC 25 |
Feb 08 12:29:01 PM UTC 25 |
10546066227 ps |
| T675 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1609781066 |
|
|
Feb 08 12:28:59 PM UTC 25 |
Feb 08 12:29:01 PM UTC 25 |
81798123 ps |
| T676 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.846454048 |
|
|
Feb 08 12:29:02 PM UTC 25 |
Feb 08 12:29:10 PM UTC 25 |
157114385 ps |
| T677 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2773846531 |
|
|
Feb 08 12:28:48 PM UTC 25 |
Feb 08 12:29:10 PM UTC 25 |
92063682 ps |
| T678 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1616228023 |
|
|
Feb 08 12:29:12 PM UTC 25 |
Feb 08 12:29:14 PM UTC 25 |
15087050 ps |
| T679 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.708311587 |
|
|
Feb 08 12:29:01 PM UTC 25 |
Feb 08 12:29:15 PM UTC 25 |
1471668964 ps |
| T680 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3860869918 |
|
|
Feb 08 12:22:21 PM UTC 25 |
Feb 08 12:29:22 PM UTC 25 |
3984982362 ps |
| T681 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3818552209 |
|
|
Feb 08 12:26:09 PM UTC 25 |
Feb 08 12:29:26 PM UTC 25 |
2809436957 ps |
| T682 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1667980593 |
|
|
Feb 08 12:17:35 PM UTC 25 |
Feb 08 12:29:35 PM UTC 25 |
14045063857 ps |
| T683 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.206927714 |
|
|
Feb 08 12:29:15 PM UTC 25 |
Feb 08 12:29:38 PM UTC 25 |
1034962098 ps |
| T684 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2928755215 |
|
|
Feb 08 11:57:35 AM UTC 25 |
Feb 08 12:29:40 PM UTC 25 |
143665255702 ps |
| T685 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.189725903 |
|
|
Feb 08 12:29:23 PM UTC 25 |
Feb 08 12:29:52 PM UTC 25 |
6001181935 ps |
| T686 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2367686040 |
|
|
Feb 08 12:29:37 PM UTC 25 |
Feb 08 12:29:54 PM UTC 25 |
263163911 ps |
| T687 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2099257171 |
|
|
Feb 08 12:29:55 PM UTC 25 |
Feb 08 12:30:02 PM UTC 25 |
412793303 ps |
| T688 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3447739435 |
|
|
Feb 08 12:25:50 PM UTC 25 |
Feb 08 12:30:26 PM UTC 25 |
2347847814 ps |
| T689 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.440654632 |
|
|
Feb 08 12:29:52 PM UTC 25 |
Feb 08 12:30:27 PM UTC 25 |
315188532 ps |
| T690 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.738709072 |
|
|
Feb 08 12:19:59 PM UTC 25 |
Feb 08 12:30:30 PM UTC 25 |
20253894352 ps |
| T691 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.818420694 |
|
|
Feb 08 12:30:28 PM UTC 25 |
Feb 08 12:30:31 PM UTC 25 |
29880481 ps |
| T692 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.3179150410 |
|
|
Feb 08 12:15:20 PM UTC 25 |
Feb 08 12:30:31 PM UTC 25 |
8426954492 ps |
| T693 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2385966478 |
|
|
Feb 08 12:01:17 PM UTC 25 |
Feb 08 12:30:37 PM UTC 25 |
61878922695 ps |
| T694 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2181027521 |
|
|
Feb 08 12:30:31 PM UTC 25 |
Feb 08 12:30:39 PM UTC 25 |
182765473 ps |
| T695 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2078992863 |
|
|
Feb 08 12:30:41 PM UTC 25 |
Feb 08 12:30:43 PM UTC 25 |
12743502 ps |
| T696 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.2197363175 |
|
|
Feb 08 12:30:31 PM UTC 25 |
Feb 08 12:30:47 PM UTC 25 |
1209359476 ps |
| T697 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1512795805 |
|
|
Feb 08 12:24:38 PM UTC 25 |
Feb 08 12:30:47 PM UTC 25 |
13343216179 ps |
| T698 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2541726264 |
|
|
Feb 08 12:29:42 PM UTC 25 |
Feb 08 12:30:51 PM UTC 25 |
472118071 ps |
| T699 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1023793307 |
|
|
Feb 08 12:11:13 PM UTC 25 |
Feb 08 12:31:17 PM UTC 25 |
4393310167 ps |
| T700 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1066430269 |
|
|
Feb 08 12:19:15 PM UTC 25 |
Feb 08 12:31:17 PM UTC 25 |
8097957673 ps |
| T701 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1073237115 |
|
|
Feb 08 12:26:29 PM UTC 25 |
Feb 08 12:31:31 PM UTC 25 |
1959176566 ps |
| T702 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.3607661155 |
|
|
Feb 08 12:30:48 PM UTC 25 |
Feb 08 12:31:32 PM UTC 25 |
1604670124 ps |
| T703 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.74059992 |
|
|
Feb 08 12:31:18 PM UTC 25 |
Feb 08 12:31:36 PM UTC 25 |
315518289 ps |
| T704 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3891509776 |
|
|
Feb 08 12:31:32 PM UTC 25 |
Feb 08 12:31:38 PM UTC 25 |
55103177 ps |
| T705 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.1430635943 |
|
|
Feb 08 12:18:27 PM UTC 25 |
Feb 08 12:31:40 PM UTC 25 |
3162536337 ps |
| T706 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2046833415 |
|
|
Feb 08 12:31:37 PM UTC 25 |
Feb 08 12:31:45 PM UTC 25 |
1020010793 ps |
| T707 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3134406270 |
|
|
Feb 08 12:30:44 PM UTC 25 |
Feb 08 12:32:03 PM UTC 25 |
617978035 ps |
| T708 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3754177192 |
|
|
Feb 08 12:32:04 PM UTC 25 |
Feb 08 12:32:06 PM UTC 25 |
45705755 ps |
| T709 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1506552502 |
|
|
Feb 08 12:23:11 PM UTC 25 |
Feb 08 12:32:17 PM UTC 25 |
1147431737 ps |
| T710 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.505082291 |
|
|
Feb 08 12:24:06 PM UTC 25 |
Feb 08 12:32:19 PM UTC 25 |
1343031704 ps |
| T711 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1666003817 |
|
|
Feb 08 12:32:17 PM UTC 25 |
Feb 08 12:32:22 PM UTC 25 |
382557081 ps |
| T712 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.3677256548 |
|
|
Feb 08 12:32:07 PM UTC 25 |
Feb 08 12:32:25 PM UTC 25 |
1854908934 ps |
| T713 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.1716708097 |
|
|
Feb 08 12:23:38 PM UTC 25 |
Feb 08 12:32:25 PM UTC 25 |
7354444676 ps |
| T714 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.4092673826 |
|
|
Feb 08 12:32:26 PM UTC 25 |
Feb 08 12:32:28 PM UTC 25 |
39605642 ps |
| T715 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.2274076787 |
|
|
Feb 08 12:08:32 PM UTC 25 |
Feb 08 12:32:34 PM UTC 25 |
45671235668 ps |
| T716 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1189683782 |
|
|
Feb 08 12:32:26 PM UTC 25 |
Feb 08 12:32:47 PM UTC 25 |
1328625106 ps |
| T717 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2808260160 |
|
|
Feb 08 12:14:11 PM UTC 25 |
Feb 08 12:33:17 PM UTC 25 |
15556819894 ps |
| T718 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.1929298232 |
|
|
Feb 08 12:14:13 PM UTC 25 |
Feb 08 12:33:30 PM UTC 25 |
11087102698 ps |
| T719 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1619799552 |
|
|
Feb 08 12:31:32 PM UTC 25 |
Feb 08 12:33:31 PM UTC 25 |
156129756 ps |
| T720 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1206159851 |
|
|
Feb 08 12:33:18 PM UTC 25 |
Feb 08 12:33:32 PM UTC 25 |
554505864 ps |
| T721 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3923926784 |
|
|
Feb 08 12:22:20 PM UTC 25 |
Feb 08 12:33:50 PM UTC 25 |
51597401070 ps |
| T722 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3022265911 |
|
|
Feb 08 12:33:50 PM UTC 25 |
Feb 08 12:33:56 PM UTC 25 |
316302729 ps |
| T723 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.713394901 |
|
|
Feb 08 12:32:34 PM UTC 25 |
Feb 08 12:34:01 PM UTC 25 |
10678666956 ps |
| T724 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2744775828 |
|
|
Feb 08 12:29:02 PM UTC 25 |
Feb 08 12:34:06 PM UTC 25 |
1031961482 ps |
| T725 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4206402002 |
|
|
Feb 08 12:33:33 PM UTC 25 |
Feb 08 12:34:17 PM UTC 25 |
215705685 ps |
| T726 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2973789557 |
|
|
Feb 08 12:34:18 PM UTC 25 |
Feb 08 12:34:20 PM UTC 25 |
69837722 ps |
| T727 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.4171789793 |
|
|
Feb 08 12:27:55 PM UTC 25 |
Feb 08 12:34:26 PM UTC 25 |
15665298572 ps |
| T728 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2884301407 |
|
|
Feb 08 12:34:21 PM UTC 25 |
Feb 08 12:34:27 PM UTC 25 |
277823450 ps |
| T729 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3077655931 |
|
|
Feb 08 12:29:26 PM UTC 25 |
Feb 08 12:34:28 PM UTC 25 |
6248628912 ps |
| T730 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.181955795 |
|
|
Feb 08 12:34:26 PM UTC 25 |
Feb 08 12:34:31 PM UTC 25 |
58862865 ps |
| T731 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.109886082 |
|
|
Feb 08 12:33:32 PM UTC 25 |
Feb 08 12:34:32 PM UTC 25 |
103327547 ps |
| T732 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1838322930 |
|
|
Feb 08 12:29:40 PM UTC 25 |
Feb 08 12:34:33 PM UTC 25 |
40245546926 ps |
| T733 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1363872217 |
|
|
Feb 08 12:34:32 PM UTC 25 |
Feb 08 12:34:34 PM UTC 25 |
19025642 ps |
| T734 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.4210925882 |
|
|
Feb 08 12:28:20 PM UTC 25 |
Feb 08 12:34:40 PM UTC 25 |
16952010573 ps |
| T735 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.611049521 |
|
|
Feb 08 12:32:21 PM UTC 25 |
Feb 08 12:34:41 PM UTC 25 |
1472180887 ps |
| T736 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.478238729 |
|
|
Feb 08 11:45:38 AM UTC 25 |
Feb 08 12:34:54 PM UTC 25 |
40287934371 ps |
| T737 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.363260876 |
|
|
Feb 08 12:34:33 PM UTC 25 |
Feb 08 12:34:56 PM UTC 25 |
208459305 ps |
| T738 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.996901639 |
|
|
Feb 08 12:30:51 PM UTC 25 |
Feb 08 12:35:01 PM UTC 25 |
8616443284 ps |
| T739 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3433696703 |
|
|
Feb 08 12:34:43 PM UTC 25 |
Feb 08 12:35:01 PM UTC 25 |
185664086 ps |
| T740 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1074511324 |
|
|
Feb 08 12:34:57 PM UTC 25 |
Feb 08 12:35:02 PM UTC 25 |
164138607 ps |
| T741 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.4051524440 |
|
|
Feb 08 12:11:20 PM UTC 25 |
Feb 08 12:35:11 PM UTC 25 |
19762181405 ps |
| T742 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3714463041 |
|
|
Feb 08 12:35:01 PM UTC 25 |
Feb 08 12:35:12 PM UTC 25 |
2370414436 ps |
| T743 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.981339464 |
|
|
Feb 08 12:32:48 PM UTC 25 |
Feb 08 12:35:13 PM UTC 25 |
3414301692 ps |
| T744 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2118150984 |
|
|
Feb 08 12:35:14 PM UTC 25 |
Feb 08 12:35:17 PM UTC 25 |
151771680 ps |
| T745 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3151332117 |
|
|
Feb 08 11:59:04 AM UTC 25 |
Feb 08 12:35:18 PM UTC 25 |
57192361587 ps |
| T746 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1672930663 |
|
|
Feb 08 12:35:18 PM UTC 25 |
Feb 08 12:35:24 PM UTC 25 |
90066846 ps |
| T747 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2118682181 |
|
|
Feb 08 12:35:17 PM UTC 25 |
Feb 08 12:35:26 PM UTC 25 |
193393465 ps |
| T748 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.2348473273 |
|
|
Feb 08 12:35:01 PM UTC 25 |
Feb 08 12:35:27 PM UTC 25 |
414749871 ps |
| T749 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2957601288 |
|
|
Feb 08 12:35:28 PM UTC 25 |
Feb 08 12:35:30 PM UTC 25 |
43776513 ps |
| T750 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.803113122 |
|
|
Feb 08 12:31:18 PM UTC 25 |
Feb 08 12:35:33 PM UTC 25 |
97026495977 ps |
| T751 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.2462334931 |
|
|
Feb 08 12:34:34 PM UTC 25 |
Feb 08 12:36:03 PM UTC 25 |
9293009450 ps |
| T752 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.1516136572 |
|
|
Feb 08 12:18:41 PM UTC 25 |
Feb 08 12:36:12 PM UTC 25 |
7386086609 ps |
| T753 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1381964658 |
|
|
Feb 08 12:03:20 PM UTC 25 |
Feb 08 12:36:23 PM UTC 25 |
17938239215 ps |
| T754 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.972367910 |
|
|
Feb 08 12:17:06 PM UTC 25 |
Feb 08 12:36:29 PM UTC 25 |
5183377208 ps |
| T755 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1983556679 |
|
|
Feb 08 12:14:34 PM UTC 25 |
Feb 08 12:36:29 PM UTC 25 |
12479185879 ps |
| T756 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3961916577 |
|
|
Feb 08 12:25:09 PM UTC 25 |
Feb 08 12:36:57 PM UTC 25 |
7402504317 ps |
| T757 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3280032882 |
|
|
Feb 08 12:35:31 PM UTC 25 |
Feb 08 12:37:00 PM UTC 25 |
481655674 ps |
| T758 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4257697285 |
|
|
Feb 08 12:35:26 PM UTC 25 |
Feb 08 12:37:00 PM UTC 25 |
1187264020 ps |
| T759 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3440533479 |
|
|
Feb 08 12:36:04 PM UTC 25 |
Feb 08 12:37:08 PM UTC 25 |
2476430605 ps |
| T760 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.587264726 |
|
|
Feb 08 12:37:02 PM UTC 25 |
Feb 08 12:37:10 PM UTC 25 |
1700465288 ps |
| T761 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.174434339 |
|
|
Feb 08 12:36:58 PM UTC 25 |
Feb 08 12:37:18 PM UTC 25 |
85252453 ps |
| T762 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3823342919 |
|
|
Feb 08 12:36:24 PM UTC 25 |
Feb 08 12:37:20 PM UTC 25 |
261218120 ps |
| T763 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3881069892 |
|
|
Feb 08 12:37:19 PM UTC 25 |
Feb 08 12:37:22 PM UTC 25 |
80170986 ps |
| T764 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.3301627088 |
|
|
Feb 08 12:29:16 PM UTC 25 |
Feb 08 12:37:22 PM UTC 25 |
5230349270 ps |
| T765 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1177056279 |
|
|
Feb 08 12:37:21 PM UTC 25 |
Feb 08 12:37:30 PM UTC 25 |
304999624 ps |
| T766 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1075571720 |
|
|
Feb 08 12:37:23 PM UTC 25 |
Feb 08 12:37:30 PM UTC 25 |
584209506 ps |
| T767 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1126169716 |
|
|
Feb 08 12:37:31 PM UTC 25 |
Feb 08 12:37:33 PM UTC 25 |
34733028 ps |
| T768 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3622953691 |
|
|
Feb 08 12:31:38 PM UTC 25 |
Feb 08 12:37:51 PM UTC 25 |
2937892514 ps |
| T769 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.381781196 |
|
|
Feb 08 12:37:34 PM UTC 25 |
Feb 08 12:37:52 PM UTC 25 |
235830960 ps |
| T770 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3727079877 |
|
|
Feb 08 12:36:30 PM UTC 25 |
Feb 08 12:37:53 PM UTC 25 |
268671676 ps |
| T771 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.4236819773 |
|
|
Feb 08 12:26:49 PM UTC 25 |
Feb 08 12:38:01 PM UTC 25 |
15197196302 ps |
| T772 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2644753365 |
|
|
Feb 08 12:38:02 PM UTC 25 |
Feb 08 12:38:06 PM UTC 25 |
148596745 ps |
| T773 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1426504484 |
|
|
Feb 08 12:33:32 PM UTC 25 |
Feb 08 12:38:17 PM UTC 25 |
3391304597 ps |
| T774 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.3477545888 |
|
|
Feb 08 12:30:27 PM UTC 25 |
Feb 08 12:38:24 PM UTC 25 |
4593915419 ps |
| T775 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.2654068015 |
|
|
Feb 08 12:28:56 PM UTC 25 |
Feb 08 12:38:25 PM UTC 25 |
21376533551 ps |
| T776 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1916427585 |
|
|
Feb 08 12:37:54 PM UTC 25 |
Feb 08 12:38:27 PM UTC 25 |
580150179 ps |
| T777 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1790192813 |
|
|
Feb 08 12:34:41 PM UTC 25 |
Feb 08 12:38:28 PM UTC 25 |
9976341709 ps |
| T778 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.3976075937 |
|
|
Feb 08 12:40:12 PM UTC 25 |
Feb 08 12:40:25 PM UTC 25 |
819258365 ps |
| T779 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.910520913 |
|
|
Feb 08 12:34:28 PM UTC 25 |
Feb 08 12:38:28 PM UTC 25 |
1551827576 ps |
| T780 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.552070895 |
|
|
Feb 08 12:25:33 PM UTC 25 |
Feb 08 12:40:29 PM UTC 25 |
10367676962 ps |
| T781 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.1983873727 |
|
|
Feb 08 12:14:13 PM UTC 25 |
Feb 08 12:38:31 PM UTC 25 |
18029743022 ps |
| T782 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3880150204 |
|
|
Feb 08 12:38:32 PM UTC 25 |
Feb 08 12:38:35 PM UTC 25 |
33950729 ps |
| T783 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2058830275 |
|
|
Feb 08 12:21:50 PM UTC 25 |
Feb 08 12:38:35 PM UTC 25 |
119532363436 ps |
| T784 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.3811481000 |
|
|
Feb 08 12:09:40 PM UTC 25 |
Feb 08 12:38:38 PM UTC 25 |
106925879316 ps |
| T785 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1851996324 |
|
|
Feb 08 12:38:18 PM UTC 25 |
Feb 08 12:38:40 PM UTC 25 |
81499632 ps |
| T786 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2884765293 |
|
|
Feb 08 12:38:36 PM UTC 25 |
Feb 08 12:38:41 PM UTC 25 |
113303577 ps |
| T787 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3972491787 |
|
|
Feb 08 12:38:26 PM UTC 25 |
Feb 08 12:38:42 PM UTC 25 |
1036075304 ps |
| T788 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.212539585 |
|
|
Feb 08 12:38:42 PM UTC 25 |
Feb 08 12:38:44 PM UTC 25 |
23579415 ps |
| T789 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.4016959852 |
|
|
Feb 08 12:34:55 PM UTC 25 |
Feb 08 12:38:44 PM UTC 25 |
10886213756 ps |
| T790 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1642428844 |
|
|
Feb 08 12:38:35 PM UTC 25 |
Feb 08 12:38:46 PM UTC 25 |
548730675 ps |
| T791 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.135473495 |
|
|
Feb 08 12:38:43 PM UTC 25 |
Feb 08 12:39:05 PM UTC 25 |
997976279 ps |
| T792 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1856113050 |
|
|
Feb 08 12:30:48 PM UTC 25 |
Feb 08 12:39:07 PM UTC 25 |
1771857896 ps |
| T793 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.15660900 |
|
|
Feb 08 12:38:25 PM UTC 25 |
Feb 08 12:39:16 PM UTC 25 |
220404505 ps |
| T794 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.436933285 |
|
|
Feb 08 12:39:06 PM UTC 25 |
Feb 08 12:39:23 PM UTC 25 |
885564028 ps |