| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 98.63 | 99.48 | 96.05 | 99.72 | 100.00 | 97.29 | 99.12 | 98.72 |
| T85 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2581724477 | Oct 15 12:42:21 AM UTC 24 | Oct 15 12:42:23 AM UTC 24 | 50635041 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3179077754 | Oct 15 12:42:22 AM UTC 24 | Oct 15 12:42:24 AM UTC 24 | 14476366 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2782108167 | Oct 15 12:42:21 AM UTC 24 | Oct 15 12:42:24 AM UTC 24 | 38726410 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.828836295 | Oct 15 12:42:20 AM UTC 24 | Oct 15 12:42:24 AM UTC 24 | 231117485 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2292977435 | Oct 15 12:42:21 AM UTC 24 | Oct 15 12:42:24 AM UTC 24 | 115310408 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2865534982 | Oct 15 12:42:21 AM UTC 24 | Oct 15 12:42:25 AM UTC 24 | 222478357 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3351372298 | Oct 15 12:42:23 AM UTC 24 | Oct 15 12:42:25 AM UTC 24 | 35897954 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3906059857 | Oct 15 12:42:23 AM UTC 24 | Oct 15 12:42:25 AM UTC 24 | 51332575 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1687798550 | Oct 15 12:42:22 AM UTC 24 | Oct 15 12:42:25 AM UTC 24 | 36508416 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.647413180 | Oct 15 12:42:21 AM UTC 24 | Oct 15 12:42:26 AM UTC 24 | 82685158 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3923825733 | Oct 15 12:42:20 AM UTC 24 | Oct 15 12:42:26 AM UTC 24 | 2143836821 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1590684484 | Oct 15 12:42:24 AM UTC 24 | Oct 15 12:42:26 AM UTC 24 | 16639077 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2029722469 | Oct 15 12:42:24 AM UTC 24 | Oct 15 12:42:27 AM UTC 24 | 92022716 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3644544360 | Oct 15 12:42:23 AM UTC 24 | Oct 15 12:42:27 AM UTC 24 | 321438599 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1213417562 | Oct 15 12:42:25 AM UTC 24 | Oct 15 12:42:28 AM UTC 24 | 14235187 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2809706724 | Oct 15 12:42:26 AM UTC 24 | Oct 15 12:42:28 AM UTC 24 | 14156400 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1175448259 | Oct 15 12:42:24 AM UTC 24 | Oct 15 12:42:28 AM UTC 24 | 1161686921 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3890256575 | Oct 15 12:42:26 AM UTC 24 | Oct 15 12:42:28 AM UTC 24 | 44216785 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.372066117 | Oct 15 12:42:27 AM UTC 24 | Oct 15 12:42:29 AM UTC 24 | 50460857 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4288639008 | Oct 15 12:42:24 AM UTC 24 | Oct 15 12:42:28 AM UTC 24 | 799048136 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1461756266 | Oct 15 12:42:26 AM UTC 24 | Oct 15 12:42:29 AM UTC 24 | 348446236 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1895459549 | Oct 15 12:42:27 AM UTC 24 | Oct 15 12:42:29 AM UTC 24 | 43982627 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1327409819 | Oct 15 12:42:27 AM UTC 24 | Oct 15 12:42:29 AM UTC 24 | 121928381 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2192917901 | Oct 15 12:42:28 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 22799039 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3923168948 | Oct 15 12:42:29 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 38597804 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1429320391 | Oct 15 12:42:27 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 74334793 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3453543347 | Oct 15 12:42:28 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 77410325 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1631493143 | Oct 15 12:42:26 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 122997786 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2925153333 | Oct 15 12:42:27 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 836605962 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1329694547 | Oct 15 12:42:26 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 2269388360 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.18918613 | Oct 15 12:42:28 AM UTC 24 | Oct 15 12:42:31 AM UTC 24 | 53845361 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2936525712 | Oct 15 12:42:24 AM UTC 24 | Oct 15 12:42:32 AM UTC 24 | 783435929 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2983838630 | Oct 15 12:42:30 AM UTC 24 | Oct 15 12:42:32 AM UTC 24 | 19628782 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1022904728 | Oct 15 12:42:27 AM UTC 24 | Oct 15 12:42:32 AM UTC 24 | 215674327 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2533151107 | Oct 15 12:42:30 AM UTC 24 | Oct 15 12:42:32 AM UTC 24 | 254699209 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.917317686 | Oct 15 12:42:31 AM UTC 24 | Oct 15 12:42:33 AM UTC 24 | 14000492 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3195214948 | Oct 15 12:42:31 AM UTC 24 | Oct 15 12:42:33 AM UTC 24 | 16279406 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2353518303 | Oct 15 12:42:29 AM UTC 24 | Oct 15 12:42:34 AM UTC 24 | 190432237 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1200821636 | Oct 15 12:42:30 AM UTC 24 | Oct 15 12:42:34 AM UTC 24 | 1565680294 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.690359835 | Oct 15 12:42:30 AM UTC 24 | Oct 15 12:42:34 AM UTC 24 | 200831500 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3028126366 | Oct 15 12:42:28 AM UTC 24 | Oct 15 12:42:35 AM UTC 24 | 5252411399 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.690510835 | Oct 15 12:42:31 AM UTC 24 | Oct 15 12:42:35 AM UTC 24 | 236493121 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1438683428 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:36 AM UTC 24 | 71228522 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.507428732 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:36 AM UTC 24 | 27863891 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3772430325 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:37 AM UTC 24 | 115278256 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2763284460 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:37 AM UTC 24 | 164872493 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2669215487 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:37 AM UTC 24 | 420558498 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.56116726 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:38 AM UTC 24 | 73033324 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3667200699 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:38 AM UTC 24 | 36902303 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3636683073 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:38 AM UTC 24 | 39079602 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2833875307 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:38 AM UTC 24 | 120494806 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1390421567 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:38 AM UTC 24 | 91418219 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2239157521 | Oct 15 12:42:34 AM UTC 24 | Oct 15 12:42:38 AM UTC 24 | 204395956 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1368149235 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:38 AM UTC 24 | 196990348 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2122377677 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:39 AM UTC 24 | 108528662 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3296500446 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:39 AM UTC 24 | 165037219 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1822381964 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:39 AM UTC 24 | 264323722 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2328526655 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:39 AM UTC 24 | 337605063 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1433909950 | Oct 15 12:42:37 AM UTC 24 | Oct 15 12:42:39 AM UTC 24 | 17440556 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1977352053 | Oct 15 12:42:37 AM UTC 24 | Oct 15 12:42:39 AM UTC 24 | 64268861 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1730372479 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:40 AM UTC 24 | 375139251 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1159531857 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:40 AM UTC 24 | 296786571 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4013449677 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:40 AM UTC 24 | 63080485 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1389636936 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:41 AM UTC 24 | 21262103 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3802486803 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:41 AM UTC 24 | 18141997 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3116290785 | Oct 15 12:42:37 AM UTC 24 | Oct 15 12:42:41 AM UTC 24 | 138657218 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2833990215 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:41 AM UTC 24 | 16229651 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2902612973 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:41 AM UTC 24 | 29858868 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.5947504 | Oct 15 12:42:38 AM UTC 24 | Oct 15 12:42:41 AM UTC 24 | 240883616 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2625954553 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:42 AM UTC 24 | 407587586 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.785767854 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:42 AM UTC 24 | 804566312 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3195555577 | Oct 15 12:42:40 AM UTC 24 | Oct 15 12:42:42 AM UTC 24 | 92779510 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3682130714 | Oct 15 12:42:36 AM UTC 24 | Oct 15 12:42:42 AM UTC 24 | 4383860569 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.703596413 | Oct 15 12:42:40 AM UTC 24 | Oct 15 12:42:43 AM UTC 24 | 35926648 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.194188528 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:43 AM UTC 24 | 3083821788 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1841879720 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:43 AM UTC 24 | 37396987 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3295380556 | Oct 15 12:42:39 AM UTC 24 | Oct 15 12:42:43 AM UTC 24 | 280772185 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3762405604 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 691313360 ps |
| CPU time | 10.24 seconds |
| Started | Oct 15 03:03:46 AM UTC 24 |
| Finished | Oct 15 03:03:58 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762405604 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.3762405604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1200060030 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1433392542 ps |
| CPU time | 42.49 seconds |
| Started | Oct 15 03:06:11 AM UTC 24 |
| Finished | Oct 15 03:06:55 AM UTC 24 |
| Peak memory | 269648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200060030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1200060030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1676035560 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 855801605 ps |
| CPU time | 16.7 seconds |
| Started | Oct 15 03:21:08 AM UTC 24 |
| Finished | Oct 15 03:21:26 AM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676035560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1676035560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.22092432 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 187221453869 ps |
| CPU time | 897.78 seconds |
| Started | Oct 15 03:03:46 AM UTC 24 |
| Finished | Oct 15 03:18:54 AM UTC 24 |
| Peak memory | 376016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22092432 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.22092432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.4083078564 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 293753678 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 03:06:13 AM UTC 24 |
| Finished | Oct 15 03:06:17 AM UTC 24 |
| Peak memory | 247624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083078564 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.4083078564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_readback_err.4086983346 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 122213181 ps |
| CPU time | 1.61 seconds |
| Started | Oct 15 03:04:11 AM UTC 24 |
| Finished | Oct 15 03:04:14 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086983346 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_readback_err.4086983346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1175448259 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1161686921 ps |
| CPU time | 2.74 seconds |
| Started | Oct 15 12:42:24 AM UTC 24 |
| Finished | Oct 15 12:42:28 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11754 48259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_in tg_err.1175448259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1278258187 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 6990277189 ps |
| CPU time | 238.05 seconds |
| Started | Oct 15 03:03:45 AM UTC 24 |
| Finished | Oct 15 03:07:47 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278258187 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce ss_b2b.1278258187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.491625071 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 128543185 ps |
| CPU time | 6.3 seconds |
| Started | Oct 15 03:03:47 AM UTC 24 |
| Finished | Oct 15 03:03:54 AM UTC 24 |
| Peak memory | 221048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491625071 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.491625071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1578063038 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1053076649 ps |
| CPU time | 6.06 seconds |
| Started | Oct 15 12:41:56 AM UTC 24 |
| Finished | Oct 15 12:42:03 AM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 78063038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa ssthru_mem_tl_intg_err.1578063038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.19719446 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 32816314999 ps |
| CPU time | 1456.5 seconds |
| Started | Oct 15 03:06:12 AM UTC 24 |
| Finished | Oct 15 03:30:44 AM UTC 24 |
| Peak memory | 382232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19719446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.19719446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3935914537 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 38240660 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 03:04:07 AM UTC 24 |
| Finished | Oct 15 03:04:09 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935914537 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3935914537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.2235421763 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 181502750292 ps |
| CPU time | 1327.41 seconds |
| Started | Oct 15 03:08:07 AM UTC 24 |
| Finished | Oct 15 03:30:29 AM UTC 24 |
| Peak memory | 382192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235421763 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.2235421763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3220071000 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 6379526330 ps |
| CPU time | 306.53 seconds |
| Started | Oct 15 03:13:29 AM UTC 24 |
| Finished | Oct 15 03:18:39 AM UTC 24 |
| Peak memory | 341348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220071000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3220071000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1288198512 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 332899118 ps |
| CPU time | 12.58 seconds |
| Started | Oct 15 03:47:14 AM UTC 24 |
| Finished | Oct 15 03:47:28 AM UTC 24 |
| Peak memory | 242976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288198512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.1288198512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2353518303 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 190432237 ps |
| CPU time | 4.03 seconds |
| Started | Oct 15 12:42:29 AM UTC 24 |
| Finished | Oct 15 12:42:34 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23535 18303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i ntg_err.2353518303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3453598811 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14499800 ps |
| CPU time | 1 seconds |
| Started | Oct 15 03:03:50 AM UTC 24 |
| Finished | Oct 15 03:03:52 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453598811 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3453598811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1634296298 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1758857846 ps |
| CPU time | 17.48 seconds |
| Started | Oct 15 04:14:26 AM UTC 24 |
| Finished | Oct 15 04:14:45 AM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634296298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1634296298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3482809342 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 169838261 ps |
| CPU time | 3.61 seconds |
| Started | Oct 15 12:42:16 AM UTC 24 |
| Finished | Oct 15 12:42:20 AM UTC 24 |
| Peak memory | 224144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34828 09342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in tg_err.3482809342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3693836917 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 46274423019 ps |
| CPU time | 762.94 seconds |
| Started | Oct 15 03:03:51 AM UTC 24 |
| Finished | Oct 15 03:16:42 AM UTC 24 |
| Peak memory | 380352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693836917 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.3693836917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1235889636 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6347661722 ps |
| CPU time | 1018.14 seconds |
| Started | Oct 15 03:22:39 AM UTC 24 |
| Finished | Oct 15 03:39:49 AM UTC 24 |
| Peak memory | 384152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235889636 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1235889636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2625954553 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 407587586 ps |
| CPU time | 1.76 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:42 AM UTC 24 |
| Peak memory | 222756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26259 54553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i ntg_err.2625954553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2572105660 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 50631457946 ps |
| CPU time | 4239.89 seconds |
| Started | Oct 15 03:04:18 AM UTC 24 |
| Finished | Oct 15 04:15:41 AM UTC 24 |
| Peak memory | 385836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257210566 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.2572105660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_readback_err.1484721549 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 221121997 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 03:03:47 AM UTC 24 |
| Finished | Oct 15 03:03:49 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484721549 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_readback_err.1484721549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1982833722 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 48963493303 ps |
| CPU time | 1395.62 seconds |
| Started | Oct 15 03:03:48 AM UTC 24 |
| Finished | Oct 15 03:27:20 AM UTC 24 |
| Peak memory | 384272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198283372 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.1982833722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4148850169 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 25071085 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:42:04 AM UTC 24 |
| Finished | Oct 15 12:42:06 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41488501 69 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alia sing.4148850169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1380696012 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 86021381 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 12:42:04 AM UTC 24 |
| Finished | Oct 15 12:42:06 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13806960 12 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_ bash.1380696012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.952151955 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 38154830 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 12:42:02 AM UTC 24 |
| Finished | Oct 15 12:42:04 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95215195 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_re set.952151955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2168543732 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 134720883 ps |
| CPU time | 2.21 seconds |
| Started | Oct 15 12:42:05 AM UTC 24 |
| Finished | Oct 15 12:42:08 AM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2168543732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2168543732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2106289782 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 172926696 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 12:42:04 AM UTC 24 |
| Finished | Oct 15 12:42:06 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106289782 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2106289782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2186718267 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 168336229 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 12:42:05 AM UTC 24 |
| Finished | Oct 15 12:42:07 AM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2186718267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c trl_same_csr_outstanding.2186718267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.89195727 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 130000043 ps |
| CPU time | 4 seconds |
| Started | Oct 15 12:41:58 AM UTC 24 |
| Finished | Oct 15 12:42:03 AM UTC 24 |
| Peak memory | 223952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89195727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.89195727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.818514860 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 488055499 ps |
| CPU time | 3.12 seconds |
| Started | Oct 15 12:42:00 AM UTC 24 |
| Finished | Oct 15 12:42:04 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81851 4860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_int g_err.818514860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4103068146 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 19682062 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 12:42:08 AM UTC 24 |
| Finished | Oct 15 12:42:10 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41030681 46 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alia sing.4103068146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.793268684 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 78643328 ps |
| CPU time | 2.69 seconds |
| Started | Oct 15 12:42:08 AM UTC 24 |
| Finished | Oct 15 12:42:12 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79326868 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_b ash.793268684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.363649256 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 93063802 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:42:07 AM UTC 24 |
| Finished | Oct 15 12:42:09 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36364925 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_re set.363649256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3710555463 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 126494290 ps |
| CPU time | 2.95 seconds |
| Started | Oct 15 12:42:08 AM UTC 24 |
| Finished | Oct 15 12:42:12 AM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3710555463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3710555463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4130873243 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 15328995 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 12:42:08 AM UTC 24 |
| Finished | Oct 15 12:42:10 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130873243 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.4130873243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3191480270 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2910225271 ps |
| CPU time | 3.22 seconds |
| Started | Oct 15 12:42:05 AM UTC 24 |
| Finished | Oct 15 12:42:10 AM UTC 24 |
| Peak memory | 213676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 91480270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pa ssthru_mem_tl_intg_err.3191480270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1423911711 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 63011205 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:42:08 AM UTC 24 |
| Finished | Oct 15 12:42:10 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1423911711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c trl_same_csr_outstanding.1423911711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2197264771 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 26349477 ps |
| CPU time | 3.33 seconds |
| Started | Oct 15 12:42:06 AM UTC 24 |
| Finished | Oct 15 12:42:11 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197264771 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.2197264771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1934306797 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 361567047 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 12:42:06 AM UTC 24 |
| Finished | Oct 15 12:42:10 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19343 06797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_in tg_err.1934306797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1327409819 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 121928381 ps |
| CPU time | 1.48 seconds |
| Started | Oct 15 12:42:27 AM UTC 24 |
| Finished | Oct 15 12:42:29 AM UTC 24 |
| Peak memory | 222636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1327409819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1327409819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2809706724 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 14156400 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 12:42:26 AM UTC 24 |
| Finished | Oct 15 12:42:28 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809706724 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2809706724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1329694547 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 2269388360 ps |
| CPU time | 4.49 seconds |
| Started | Oct 15 12:42:26 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 29694547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p assthru_mem_tl_intg_err.1329694547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1895459549 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 43982627 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 12:42:27 AM UTC 24 |
| Finished | Oct 15 12:42:29 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1895459549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ ctrl_same_csr_outstanding.1895459549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1631493143 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 122997786 ps |
| CPU time | 4.1 seconds |
| Started | Oct 15 12:42:26 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631493143 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.1631493143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1461756266 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 348446236 ps |
| CPU time | 2.39 seconds |
| Started | Oct 15 12:42:26 AM UTC 24 |
| Finished | Oct 15 12:42:29 AM UTC 24 |
| Peak memory | 223888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14617 56266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_i ntg_err.1461756266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3453543347 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 77410325 ps |
| CPU time | 1.49 seconds |
| Started | Oct 15 12:42:28 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 222892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3453543347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3453543347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.372066117 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 50460857 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 12:42:27 AM UTC 24 |
| Finished | Oct 15 12:42:29 AM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372066117 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.372066117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2925153333 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 836605962 ps |
| CPU time | 2.85 seconds |
| Started | Oct 15 12:42:27 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 25153333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p assthru_mem_tl_intg_err.2925153333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2192917901 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 22799039 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 12:42:28 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 212844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2192917901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ ctrl_same_csr_outstanding.2192917901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1429320391 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 74334793 ps |
| CPU time | 2.5 seconds |
| Started | Oct 15 12:42:27 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429320391 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.1429320391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1022904728 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 215674327 ps |
| CPU time | 3.77 seconds |
| Started | Oct 15 12:42:27 AM UTC 24 |
| Finished | Oct 15 12:42:32 AM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10229 04728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_i ntg_err.1022904728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3923168948 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 38597804 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 12:42:29 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923168948 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.3923168948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3028126366 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 5252411399 ps |
| CPU time | 5.2 seconds |
| Started | Oct 15 12:42:28 AM UTC 24 |
| Finished | Oct 15 12:42:35 AM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 28126366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p assthru_mem_tl_intg_err.3028126366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2983838630 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 19628782 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 12:42:30 AM UTC 24 |
| Finished | Oct 15 12:42:32 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2983838630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ ctrl_same_csr_outstanding.2983838630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.18918613 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 53845361 ps |
| CPU time | 1.88 seconds |
| Started | Oct 15 12:42:28 AM UTC 24 |
| Finished | Oct 15 12:42:31 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18918613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.18918613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.917317686 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 14000492 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 12:42:31 AM UTC 24 |
| Finished | Oct 15 12:42:33 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917317686 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.917317686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1200821636 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1565680294 ps |
| CPU time | 3.51 seconds |
| Started | Oct 15 12:42:30 AM UTC 24 |
| Finished | Oct 15 12:42:34 AM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12 00821636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p assthru_mem_tl_intg_err.1200821636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3195214948 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 16279406 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 12:42:31 AM UTC 24 |
| Finished | Oct 15 12:42:33 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3195214948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ ctrl_same_csr_outstanding.3195214948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.690359835 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 200831500 ps |
| CPU time | 3.45 seconds |
| Started | Oct 15 12:42:30 AM UTC 24 |
| Finished | Oct 15 12:42:34 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690359835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.690359835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2533151107 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 254699209 ps |
| CPU time | 1.45 seconds |
| Started | Oct 15 12:42:30 AM UTC 24 |
| Finished | Oct 15 12:42:32 AM UTC 24 |
| Peak memory | 222756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25331 51107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i ntg_err.2533151107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3772430325 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 115278256 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:37 AM UTC 24 |
| Peak memory | 222636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3772430325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3772430325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1438683428 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 71228522 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:36 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438683428 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.1438683428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.690510835 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 236493121 ps |
| CPU time | 2.73 seconds |
| Started | Oct 15 12:42:31 AM UTC 24 |
| Finished | Oct 15 12:42:35 AM UTC 24 |
| Peak memory | 213772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69 0510835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_pa ssthru_mem_tl_intg_err.690510835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.507428732 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 27863891 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:36 AM UTC 24 |
| Peak memory | 212572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=507428732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_c trl_same_csr_outstanding.507428732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1390421567 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 91418219 ps |
| CPU time | 2.77 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:38 AM UTC 24 |
| Peak memory | 222864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390421567 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.1390421567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2763284460 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 164872493 ps |
| CPU time | 1.89 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:37 AM UTC 24 |
| Peak memory | 221756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27632 84460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i ntg_err.2763284460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2122377677 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 108528662 ps |
| CPU time | 1.72 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:39 AM UTC 24 |
| Peak memory | 222120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2122377677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2122377677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3667200699 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 36902303 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:38 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667200699 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.3667200699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2239157521 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 204395956 ps |
| CPU time | 2.65 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:38 AM UTC 24 |
| Peak memory | 213688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 39157521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p assthru_mem_tl_intg_err.2239157521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.56116726 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 73033324 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:38 AM UTC 24 |
| Peak memory | 212760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=56116726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ct rl_same_csr_outstanding.56116726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2833875307 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 120494806 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:38 AM UTC 24 |
| Peak memory | 223952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833875307 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.2833875307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2669215487 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 420558498 ps |
| CPU time | 1.83 seconds |
| Started | Oct 15 12:42:34 AM UTC 24 |
| Finished | Oct 15 12:42:37 AM UTC 24 |
| Peak memory | 222756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26692 15487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i ntg_err.2669215487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1822381964 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 264323722 ps |
| CPU time | 1.97 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:39 AM UTC 24 |
| Peak memory | 222628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1822381964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1822381964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3636683073 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 39079602 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:38 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636683073 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.3636683073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1730372479 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 375139251 ps |
| CPU time | 3.1 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:40 AM UTC 24 |
| Peak memory | 213688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 30372479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p assthru_mem_tl_intg_err.1730372479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1368149235 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 196990348 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:38 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1368149235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ ctrl_same_csr_outstanding.1368149235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1159531857 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 296786571 ps |
| CPU time | 3.06 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:40 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159531857 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.1159531857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2328526655 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 337605063 ps |
| CPU time | 2.39 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:39 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23285 26655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i ntg_err.2328526655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3116290785 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 138657218 ps |
| CPU time | 2.42 seconds |
| Started | Oct 15 12:42:37 AM UTC 24 |
| Finished | Oct 15 12:42:41 AM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3116290785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3116290785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1433909950 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 17440556 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 12:42:37 AM UTC 24 |
| Finished | Oct 15 12:42:39 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433909950 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.1433909950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3682130714 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 4383860569 ps |
| CPU time | 5.24 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:42 AM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 82130714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_p assthru_mem_tl_intg_err.3682130714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1977352053 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 64268861 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 12:42:37 AM UTC 24 |
| Finished | Oct 15 12:42:39 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1977352053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ ctrl_same_csr_outstanding.1977352053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4013449677 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 63080485 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:40 AM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013449677 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.4013449677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3296500446 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 165037219 ps |
| CPU time | 1.72 seconds |
| Started | Oct 15 12:42:36 AM UTC 24 |
| Finished | Oct 15 12:42:39 AM UTC 24 |
| Peak memory | 224804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32965 00446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.3296500446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2902612973 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 29858868 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:41 AM UTC 24 |
| Peak memory | 222884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2902612973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2902612973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1389636936 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 21262103 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:41 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389636936 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1389636936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.5947504 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 240883616 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 12:42:38 AM UTC 24 |
| Finished | Oct 15 12:42:41 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59 47504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_pass thru_mem_tl_intg_err.5947504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3802486803 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 18141997 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:41 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3802486803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ ctrl_same_csr_outstanding.3802486803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1841879720 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 37396987 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:43 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841879720 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.1841879720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.194188528 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 3083821788 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:43 AM UTC 24 |
| Peak memory | 224152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19418 8528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_in tg_err.194188528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.703596413 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 35926648 ps |
| CPU time | 1.6 seconds |
| Started | Oct 15 12:42:40 AM UTC 24 |
| Finished | Oct 15 12:42:43 AM UTC 24 |
| Peak memory | 222640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=703596413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.703596413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2833990215 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 16229651 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:41 AM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833990215 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.2833990215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.785767854 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 804566312 ps |
| CPU time | 2.19 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:42 AM UTC 24 |
| Peak memory | 213700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78 5767854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_pa ssthru_mem_tl_intg_err.785767854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3195555577 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 92779510 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 12:42:40 AM UTC 24 |
| Finished | Oct 15 12:42:42 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3195555577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ ctrl_same_csr_outstanding.3195555577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3295380556 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 280772185 ps |
| CPU time | 3.4 seconds |
| Started | Oct 15 12:42:39 AM UTC 24 |
| Finished | Oct 15 12:42:43 AM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295380556 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.3295380556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.252481284 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 47153980 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:42:11 AM UTC 24 |
| Finished | Oct 15 12:42:13 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25248128 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alias ing.252481284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3649915872 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 28579147 ps |
| CPU time | 1.86 seconds |
| Started | Oct 15 12:42:11 AM UTC 24 |
| Finished | Oct 15 12:42:14 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36499158 72 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_ bash.3649915872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3056003679 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 14753740 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 12:42:11 AM UTC 24 |
| Finished | Oct 15 12:42:13 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30560036 79 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r eset.3056003679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3914173576 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 35104426 ps |
| CPU time | 1.5 seconds |
| Started | Oct 15 12:42:12 AM UTC 24 |
| Finished | Oct 15 12:42:15 AM UTC 24 |
| Peak memory | 222888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3914173576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3914173576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2700564088 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 25025166 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 12:42:11 AM UTC 24 |
| Finished | Oct 15 12:42:13 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700564088 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.2700564088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1649076052 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 302284365 ps |
| CPU time | 3.35 seconds |
| Started | Oct 15 12:42:09 AM UTC 24 |
| Finished | Oct 15 12:42:14 AM UTC 24 |
| Peak memory | 213692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 49076052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa ssthru_mem_tl_intg_err.1649076052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3294006067 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 36264959 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 12:42:11 AM UTC 24 |
| Finished | Oct 15 12:42:13 AM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3294006067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c trl_same_csr_outstanding.3294006067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3326269633 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 116428246 ps |
| CPU time | 6.33 seconds |
| Started | Oct 15 12:42:09 AM UTC 24 |
| Finished | Oct 15 12:42:17 AM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326269633 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.3326269633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1807145668 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 216218480 ps |
| CPU time | 1.85 seconds |
| Started | Oct 15 12:42:10 AM UTC 24 |
| Finished | Oct 15 12:42:13 AM UTC 24 |
| Peak memory | 222756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18071 45668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_in tg_err.1807145668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2117517974 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 35868929 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 12:42:13 AM UTC 24 |
| Finished | Oct 15 12:42:15 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21175179 74 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia sing.2117517974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3724871671 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 156729205 ps |
| CPU time | 2.47 seconds |
| Started | Oct 15 12:42:13 AM UTC 24 |
| Finished | Oct 15 12:42:17 AM UTC 24 |
| Peak memory | 213736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37248716 71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_ bash.3724871671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2257951891 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 21677543 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 12:42:13 AM UTC 24 |
| Finished | Oct 15 12:42:15 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22579518 91 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_r eset.2257951891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2150309652 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 35058739 ps |
| CPU time | 2.27 seconds |
| Started | Oct 15 12:42:15 AM UTC 24 |
| Finished | Oct 15 12:42:18 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2150309652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2150309652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.900962148 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 19441545 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 12:42:13 AM UTC 24 |
| Finished | Oct 15 12:42:15 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900962148 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.900962148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.903872278 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 201935506 ps |
| CPU time | 2.85 seconds |
| Started | Oct 15 12:42:12 AM UTC 24 |
| Finished | Oct 15 12:42:16 AM UTC 24 |
| Peak memory | 213708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90 3872278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pas sthru_mem_tl_intg_err.903872278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1093385554 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 24567518 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 12:42:15 AM UTC 24 |
| Finished | Oct 15 12:42:16 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1093385554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c trl_same_csr_outstanding.1093385554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2874633073 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 292781468 ps |
| CPU time | 7.44 seconds |
| Started | Oct 15 12:42:12 AM UTC 24 |
| Finished | Oct 15 12:42:21 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874633073 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.2874633073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4128967206 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 587638531 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 12:42:13 AM UTC 24 |
| Finished | Oct 15 12:42:17 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41289 67206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in tg_err.4128967206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.983244746 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 13184492 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 12:42:17 AM UTC 24 |
| Finished | Oct 15 12:42:19 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98324474 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alias ing.983244746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1243376367 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 715412855 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 12:42:16 AM UTC 24 |
| Finished | Oct 15 12:42:20 AM UTC 24 |
| Peak memory | 213736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12433763 67 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_ bash.1243376367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1438448216 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 19568144 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:42:16 AM UTC 24 |
| Finished | Oct 15 12:42:18 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14384482 16 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_r eset.1438448216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1652097382 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 57353389 ps |
| CPU time | 2.05 seconds |
| Started | Oct 15 12:42:17 AM UTC 24 |
| Finished | Oct 15 12:42:20 AM UTC 24 |
| Peak memory | 223928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1652097382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1652097382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2803084411 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 30329702 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 12:42:16 AM UTC 24 |
| Finished | Oct 15 12:42:18 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803084411 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.2803084411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.394283388 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 246178660 ps |
| CPU time | 3.4 seconds |
| Started | Oct 15 12:42:15 AM UTC 24 |
| Finished | Oct 15 12:42:19 AM UTC 24 |
| Peak memory | 213624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 4283388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pas sthru_mem_tl_intg_err.394283388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3608912883 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 13360442 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 12:42:17 AM UTC 24 |
| Finished | Oct 15 12:42:19 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3608912883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c trl_same_csr_outstanding.3608912883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3545771531 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 46674259 ps |
| CPU time | 4.48 seconds |
| Started | Oct 15 12:42:16 AM UTC 24 |
| Finished | Oct 15 12:42:21 AM UTC 24 |
| Peak memory | 213764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545771531 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.3545771531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1134793722 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 106097730 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 12:42:19 AM UTC 24 |
| Finished | Oct 15 12:42:22 AM UTC 24 |
| Peak memory | 224680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1134793722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1134793722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2902023121 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 38360865 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 12:42:19 AM UTC 24 |
| Finished | Oct 15 12:42:21 AM UTC 24 |
| Peak memory | 212844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902023121 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.2902023121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2626895695 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 922152376 ps |
| CPU time | 2.48 seconds |
| Started | Oct 15 12:42:17 AM UTC 24 |
| Finished | Oct 15 12:42:21 AM UTC 24 |
| Peak memory | 213696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 26895695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa ssthru_mem_tl_intg_err.2626895695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2423524950 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 93247560 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 12:42:19 AM UTC 24 |
| Finished | Oct 15 12:42:21 AM UTC 24 |
| Peak memory | 212508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2423524950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_c trl_same_csr_outstanding.2423524950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2155648348 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 88578622 ps |
| CPU time | 2.29 seconds |
| Started | Oct 15 12:42:17 AM UTC 24 |
| Finished | Oct 15 12:42:21 AM UTC 24 |
| Peak memory | 213756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155648348 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.2155648348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2647086324 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 92777076 ps |
| CPU time | 2.45 seconds |
| Started | Oct 15 12:42:18 AM UTC 24 |
| Finished | Oct 15 12:42:21 AM UTC 24 |
| Peak memory | 224108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26470 86324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in tg_err.2647086324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2782108167 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 38726410 ps |
| CPU time | 1.61 seconds |
| Started | Oct 15 12:42:21 AM UTC 24 |
| Finished | Oct 15 12:42:24 AM UTC 24 |
| Peak memory | 222632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2782108167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2782108167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3492384076 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 29537970 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 12:42:20 AM UTC 24 |
| Finished | Oct 15 12:42:22 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492384076 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.3492384076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3923825733 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2143836821 ps |
| CPU time | 5.35 seconds |
| Started | Oct 15 12:42:20 AM UTC 24 |
| Finished | Oct 15 12:42:26 AM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 23825733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa ssthru_mem_tl_intg_err.3923825733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.50633323 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 17448612 ps |
| CPU time | 1.03 seconds |
| Started | Oct 15 12:42:21 AM UTC 24 |
| Finished | Oct 15 12:42:23 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=50633323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctr l_same_csr_outstanding.50633323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.828836295 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 231117485 ps |
| CPU time | 3.13 seconds |
| Started | Oct 15 12:42:20 AM UTC 24 |
| Finished | Oct 15 12:42:24 AM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828836295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.828836295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3257634207 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 299724394 ps |
| CPU time | 2.14 seconds |
| Started | Oct 15 12:42:20 AM UTC 24 |
| Finished | Oct 15 12:42:23 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32576 34207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in tg_err.3257634207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1687798550 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 36508416 ps |
| CPU time | 2.79 seconds |
| Started | Oct 15 12:42:22 AM UTC 24 |
| Finished | Oct 15 12:42:25 AM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1687798550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1687798550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2581724477 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 50635041 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 12:42:21 AM UTC 24 |
| Finished | Oct 15 12:42:23 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581724477 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2581724477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2865534982 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 222478357 ps |
| CPU time | 2.53 seconds |
| Started | Oct 15 12:42:21 AM UTC 24 |
| Finished | Oct 15 12:42:25 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28 65534982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pa ssthru_mem_tl_intg_err.2865534982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3179077754 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 14476366 ps |
| CPU time | 1 seconds |
| Started | Oct 15 12:42:22 AM UTC 24 |
| Finished | Oct 15 12:42:24 AM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3179077754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_c trl_same_csr_outstanding.3179077754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.647413180 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 82685158 ps |
| CPU time | 3.57 seconds |
| Started | Oct 15 12:42:21 AM UTC 24 |
| Finished | Oct 15 12:42:26 AM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647413180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.647413180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2292977435 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 115310408 ps |
| CPU time | 1.73 seconds |
| Started | Oct 15 12:42:21 AM UTC 24 |
| Finished | Oct 15 12:42:24 AM UTC 24 |
| Peak memory | 222756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22929 77435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in tg_err.2292977435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2029722469 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 92022716 ps |
| CPU time | 2.04 seconds |
| Started | Oct 15 12:42:24 AM UTC 24 |
| Finished | Oct 15 12:42:27 AM UTC 24 |
| Peak memory | 223944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2029722469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2029722469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3351372298 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 35897954 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 12:42:23 AM UTC 24 |
| Finished | Oct 15 12:42:25 AM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351372298 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.3351372298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3644544360 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 321438599 ps |
| CPU time | 3.56 seconds |
| Started | Oct 15 12:42:23 AM UTC 24 |
| Finished | Oct 15 12:42:27 AM UTC 24 |
| Peak memory | 213696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 44544360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa ssthru_mem_tl_intg_err.3644544360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3906059857 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 51332575 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 12:42:23 AM UTC 24 |
| Finished | Oct 15 12:42:25 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3906059857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c trl_same_csr_outstanding.3906059857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3320668369 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 74211460 ps |
| CPU time | 1.8 seconds |
| Started | Oct 15 12:42:23 AM UTC 24 |
| Finished | Oct 15 12:42:26 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320668369 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.3320668369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1111028637 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 246505122 ps |
| CPU time | 2.1 seconds |
| Started | Oct 15 12:42:23 AM UTC 24 |
| Finished | Oct 15 12:42:26 AM UTC 24 |
| Peak memory | 223952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11110 28637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in tg_err.1111028637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3890256575 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 44216785 ps |
| CPU time | 1.8 seconds |
| Started | Oct 15 12:42:26 AM UTC 24 |
| Finished | Oct 15 12:42:28 AM UTC 24 |
| Peak memory | 222820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3890256575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3890256575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1590684484 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 16639077 ps |
| CPU time | 1.03 seconds |
| Started | Oct 15 12:42:24 AM UTC 24 |
| Finished | Oct 15 12:42:26 AM UTC 24 |
| Peak memory | 212776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590684484 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.1590684484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4288639008 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 799048136 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 12:42:24 AM UTC 24 |
| Finished | Oct 15 12:42:28 AM UTC 24 |
| Peak memory | 213688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 88639008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa ssthru_mem_tl_intg_err.4288639008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1213417562 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 14235187 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 12:42:25 AM UTC 24 |
| Finished | Oct 15 12:42:28 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1213417562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c trl_same_csr_outstanding.1213417562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2936525712 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 783435929 ps |
| CPU time | 6.51 seconds |
| Started | Oct 15 12:42:24 AM UTC 24 |
| Finished | Oct 15 12:42:32 AM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936525712 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.2936525712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2368771815 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8401718066 ps |
| CPU time | 521.16 seconds |
| Started | Oct 15 03:03:46 AM UTC 24 |
| Finished | Oct 15 03:12:34 AM UTC 24 |
| Peak memory | 378012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368771815 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_ key_req.2368771815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.239079542 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4569541952 ps |
| CPU time | 41 seconds |
| Started | Oct 15 03:03:45 AM UTC 24 |
| Finished | Oct 15 03:04:27 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239079542 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.239079542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.3359048649 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 9948674356 ps |
| CPU time | 853.69 seconds |
| Started | Oct 15 03:03:46 AM UTC 24 |
| Finished | Oct 15 03:18:10 AM UTC 24 |
| Peak memory | 384176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359048649 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.3359048649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2315784572 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 86424284 ps |
| CPU time | 21.84 seconds |
| Started | Oct 15 03:03:46 AM UTC 24 |
| Finished | Oct 15 03:04:09 AM UTC 24 |
| Peak memory | 283960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 315784572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max _throughput.2315784572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3228409698 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 292266743 ps |
| CPU time | 5.62 seconds |
| Started | Oct 15 03:03:47 AM UTC 24 |
| Finished | Oct 15 03:03:53 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228409698 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.3228409698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.786968638 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 16464819909 ps |
| CPU time | 936.86 seconds |
| Started | Oct 15 03:03:45 AM UTC 24 |
| Finished | Oct 15 03:19:33 AM UTC 24 |
| Peak memory | 380156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786968638 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.786968638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.775477252 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 743830131 ps |
| CPU time | 104.37 seconds |
| Started | Oct 15 03:03:45 AM UTC 24 |
| Finished | Oct 15 03:05:32 AM UTC 24 |
| Peak memory | 367800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775477252 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.775477252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.107765991 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 54058094 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 03:03:46 AM UTC 24 |
| Finished | Oct 15 03:03:49 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107765991 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.107765991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1065212670 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 387797660 ps |
| CPU time | 5.87 seconds |
| Started | Oct 15 03:03:49 AM UTC 24 |
| Finished | Oct 15 03:03:56 AM UTC 24 |
| Peak memory | 247636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065212670 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1065212670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.1147463649 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 489801029 ps |
| CPU time | 10.6 seconds |
| Started | Oct 15 03:03:45 AM UTC 24 |
| Finished | Oct 15 03:03:57 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147463649 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1147463649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3303719039 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 25758648344 ps |
| CPU time | 63.54 seconds |
| Started | Oct 15 03:03:48 AM UTC 24 |
| Finished | Oct 15 03:04:53 AM UTC 24 |
| Peak memory | 319056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303719039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3303719039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2171299145 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2959675971 ps |
| CPU time | 332.32 seconds |
| Started | Oct 15 03:03:45 AM UTC 24 |
| Finished | Oct 15 03:09:22 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171299145 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.2171299145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1328781148 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 292841964 ps |
| CPU time | 11.88 seconds |
| Started | Oct 15 03:03:46 AM UTC 24 |
| Finished | Oct 15 03:03:59 AM UTC 24 |
| Peak memory | 261500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1328781148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th roughput_w_partial_write.1328781148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3947376031 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 5517065970 ps |
| CPU time | 725.66 seconds |
| Started | Oct 15 03:04:00 AM UTC 24 |
| Finished | Oct 15 03:16:15 AM UTC 24 |
| Peak memory | 382252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947376031 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_ key_req.3947376031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2614041043 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 34434101 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:04:28 AM UTC 24 |
| Finished | Oct 15 03:04:30 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614041043 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2614041043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.2239025290 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2620988921 ps |
| CPU time | 40.99 seconds |
| Started | Oct 15 03:03:53 AM UTC 24 |
| Finished | Oct 15 03:04:36 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239025290 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.2239025290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.2057903290 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 889911769 ps |
| CPU time | 424.7 seconds |
| Started | Oct 15 03:04:02 AM UTC 24 |
| Finished | Oct 15 03:11:12 AM UTC 24 |
| Peak memory | 382264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057903290 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.2057903290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.2079682794 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 714945893 ps |
| CPU time | 4.15 seconds |
| Started | Oct 15 03:03:59 AM UTC 24 |
| Finished | Oct 15 03:04:04 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079682794 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.2079682794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.4261468421 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 120405677 ps |
| CPU time | 51.19 seconds |
| Started | Oct 15 03:03:57 AM UTC 24 |
| Finished | Oct 15 03:04:50 AM UTC 24 |
| Peak memory | 343352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 261468421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max _throughput.4261468421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2650872947 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 183070740 ps |
| CPU time | 9.24 seconds |
| Started | Oct 15 03:04:10 AM UTC 24 |
| Finished | Oct 15 03:04:20 AM UTC 24 |
| Peak memory | 221704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650872947 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.2650872947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1237018545 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 282766685 ps |
| CPU time | 6.39 seconds |
| Started | Oct 15 03:04:10 AM UTC 24 |
| Finished | Oct 15 03:04:17 AM UTC 24 |
| Peak memory | 221640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237018545 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.1237018545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.125948779 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1164059345 ps |
| CPU time | 9.73 seconds |
| Started | Oct 15 03:03:55 AM UTC 24 |
| Finished | Oct 15 03:04:06 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125948779 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.125948779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4045754630 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 13006976352 ps |
| CPU time | 313.25 seconds |
| Started | Oct 15 03:03:56 AM UTC 24 |
| Finished | Oct 15 03:09:14 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045754630 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce ss_b2b.4045754630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.226307835 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 19923586909 ps |
| CPU time | 719.83 seconds |
| Started | Oct 15 03:04:05 AM UTC 24 |
| Finished | Oct 15 03:16:13 AM UTC 24 |
| Peak memory | 382220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226307835 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.226307835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3644505507 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 288273175 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 03:04:21 AM UTC 24 |
| Finished | Oct 15 03:04:26 AM UTC 24 |
| Peak memory | 247600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644505507 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3644505507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.3572818781 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 948964499 ps |
| CPU time | 19.02 seconds |
| Started | Oct 15 03:03:50 AM UTC 24 |
| Finished | Oct 15 03:04:10 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572818781 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3572818781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.788424850 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2622941788 ps |
| CPU time | 321.08 seconds |
| Started | Oct 15 03:03:54 AM UTC 24 |
| Finished | Oct 15 03:09:20 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788424850 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.788424850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1202375767 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 250610100 ps |
| CPU time | 32.45 seconds |
| Started | Oct 15 03:03:59 AM UTC 24 |
| Finished | Oct 15 03:04:32 AM UTC 24 |
| Peak memory | 310584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1202375767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th roughput_w_partial_write.1202375767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3451837841 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1311120555 ps |
| CPU time | 302.73 seconds |
| Started | Oct 15 03:22:35 AM UTC 24 |
| Finished | Oct 15 03:27:42 AM UTC 24 |
| Peak memory | 378120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451837841 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during _key_req.3451837841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3095763933 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 55969509 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 03:23:14 AM UTC 24 |
| Finished | Oct 15 03:23:15 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095763933 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3095763933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.4045373128 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4113441316 ps |
| CPU time | 49.61 seconds |
| Started | Oct 15 03:21:53 AM UTC 24 |
| Finished | Oct 15 03:22:44 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045373128 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.4045373128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2080546283 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 259216375 ps |
| CPU time | 4.88 seconds |
| Started | Oct 15 03:22:32 AM UTC 24 |
| Finished | Oct 15 03:22:39 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080546283 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.2080546283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1885936530 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 142072446 ps |
| CPU time | 102.03 seconds |
| Started | Oct 15 03:22:26 AM UTC 24 |
| Finished | Oct 15 03:24:10 AM UTC 24 |
| Peak memory | 378044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 885936530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma x_throughput.1885936530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2521660613 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 98332348 ps |
| CPU time | 4.34 seconds |
| Started | Oct 15 03:23:02 AM UTC 24 |
| Finished | Oct 15 03:23:07 AM UTC 24 |
| Peak memory | 221620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521660613 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.2521660613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1281301475 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 176269710 ps |
| CPU time | 10.86 seconds |
| Started | Oct 15 03:22:57 AM UTC 24 |
| Finished | Oct 15 03:23:09 AM UTC 24 |
| Peak memory | 221536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281301475 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.1281301475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.1542867893 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 48365527009 ps |
| CPU time | 934.79 seconds |
| Started | Oct 15 03:21:26 AM UTC 24 |
| Finished | Oct 15 03:37:12 AM UTC 24 |
| Peak memory | 384156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542867893 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.1542867893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1458043165 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 152632340 ps |
| CPU time | 9.92 seconds |
| Started | Oct 15 03:22:24 AM UTC 24 |
| Finished | Oct 15 03:22:35 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458043165 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.1458043165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.211261665 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 72655489277 ps |
| CPU time | 536.4 seconds |
| Started | Oct 15 03:22:24 AM UTC 24 |
| Finished | Oct 15 03:31:28 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211261665 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acce ss_b2b.211261665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3026913566 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 27930825 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 03:22:54 AM UTC 24 |
| Finished | Oct 15 03:22:56 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026913566 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3026913566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_readback_err.4063967848 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 38253591 ps |
| CPU time | 1.62 seconds |
| Started | Oct 15 03:23:08 AM UTC 24 |
| Finished | Oct 15 03:23:11 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063967848 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_readback_err.4063967848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.1889688731 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 88740687652 ps |
| CPU time | 1194.79 seconds |
| Started | Oct 15 03:22:45 AM UTC 24 |
| Finished | Oct 15 03:42:52 AM UTC 24 |
| Peak memory | 378004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889688731 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1889688731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2239334286 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1794615481 ps |
| CPU time | 55.68 seconds |
| Started | Oct 15 03:21:25 AM UTC 24 |
| Finished | Oct 15 03:22:23 AM UTC 24 |
| Peak memory | 322764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239334286 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2239334286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3946434923 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1001652335085 ps |
| CPU time | 5686.47 seconds |
| Started | Oct 15 03:23:11 AM UTC 24 |
| Finished | Oct 15 04:58:53 AM UTC 24 |
| Peak memory | 385588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394643492 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.3946434923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1514528546 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4220966704 ps |
| CPU time | 498.93 seconds |
| Started | Oct 15 03:23:09 AM UTC 24 |
| Finished | Oct 15 03:31:34 AM UTC 24 |
| Peak memory | 382280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514528546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1514528546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3134317318 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 6389829083 ps |
| CPU time | 202.8 seconds |
| Started | Oct 15 03:22:23 AM UTC 24 |
| Finished | Oct 15 03:25:49 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134317318 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3134317318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2973067887 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 157358457 ps |
| CPU time | 85.25 seconds |
| Started | Oct 15 03:22:31 AM UTC 24 |
| Finished | Oct 15 03:23:58 AM UTC 24 |
| Peak memory | 378044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2973067887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t hroughput_w_partial_write.2973067887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1988946421 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 6548372532 ps |
| CPU time | 239.63 seconds |
| Started | Oct 15 03:24:24 AM UTC 24 |
| Finished | Oct 15 03:28:27 AM UTC 24 |
| Peak memory | 378084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988946421 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during _key_req.1988946421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2279091127 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 49600541 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:24:57 AM UTC 24 |
| Finished | Oct 15 03:24:59 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279091127 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2279091127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.108925790 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1155534585 ps |
| CPU time | 61.31 seconds |
| Started | Oct 15 03:23:30 AM UTC 24 |
| Finished | Oct 15 03:24:33 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108925790 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.108925790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.95457652 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 15300289199 ps |
| CPU time | 1586.98 seconds |
| Started | Oct 15 03:24:31 AM UTC 24 |
| Finished | Oct 15 03:51:16 AM UTC 24 |
| Peak memory | 382200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95457652 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.95457652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.4143152670 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1166088383 ps |
| CPU time | 9.73 seconds |
| Started | Oct 15 03:24:20 AM UTC 24 |
| Finished | Oct 15 03:24:31 AM UTC 24 |
| Peak memory | 221540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143152670 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.4143152670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.846689802 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 191191609 ps |
| CPU time | 105.68 seconds |
| Started | Oct 15 03:24:11 AM UTC 24 |
| Finished | Oct 15 03:25:59 AM UTC 24 |
| Peak memory | 377968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 46689802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_max _throughput.846689802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1261221682 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 108458431 ps |
| CPU time | 4.25 seconds |
| Started | Oct 15 03:24:45 AM UTC 24 |
| Finished | Oct 15 03:24:50 AM UTC 24 |
| Peak memory | 221540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261221682 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.1261221682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2522270858 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 543239480 ps |
| CPU time | 11.59 seconds |
| Started | Oct 15 03:24:44 AM UTC 24 |
| Finished | Oct 15 03:24:56 AM UTC 24 |
| Peak memory | 221840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522270858 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.2522270858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1791401280 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 10932163014 ps |
| CPU time | 719.24 seconds |
| Started | Oct 15 03:23:20 AM UTC 24 |
| Finished | Oct 15 03:35:27 AM UTC 24 |
| Peak memory | 382144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791401280 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.1791401280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.560214701 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 656631117 ps |
| CPU time | 55.07 seconds |
| Started | Oct 15 03:23:59 AM UTC 24 |
| Finished | Oct 15 03:24:56 AM UTC 24 |
| Peak memory | 316724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560214701 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.560214701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.151932399 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 36260564108 ps |
| CPU time | 387.05 seconds |
| Started | Oct 15 03:24:07 AM UTC 24 |
| Finished | Oct 15 03:30:40 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151932399 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acce ss_b2b.151932399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3258355728 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 130446717 ps |
| CPU time | 0.81 seconds |
| Started | Oct 15 03:24:43 AM UTC 24 |
| Finished | Oct 15 03:24:44 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258355728 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3258355728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_readback_err.180930490 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 81785472 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 03:24:51 AM UTC 24 |
| Finished | Oct 15 03:24:53 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180930490 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_readback_err.180930490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.28108616 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4213765336 ps |
| CPU time | 1029.51 seconds |
| Started | Oct 15 03:24:34 AM UTC 24 |
| Finished | Oct 15 03:41:54 AM UTC 24 |
| Peak memory | 382280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28108616 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.28108616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1948574238 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 387541663 ps |
| CPU time | 11.68 seconds |
| Started | Oct 15 03:23:17 AM UTC 24 |
| Finished | Oct 15 03:23:29 AM UTC 24 |
| Peak memory | 243024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948574238 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1948574238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.531444208 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 188113252640 ps |
| CPU time | 3544.34 seconds |
| Started | Oct 15 03:24:57 AM UTC 24 |
| Finished | Oct 15 04:24:37 AM UTC 24 |
| Peak memory | 385764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531444208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.531444208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3538447960 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3636183113 ps |
| CPU time | 389.52 seconds |
| Started | Oct 15 03:24:54 AM UTC 24 |
| Finished | Oct 15 03:31:29 AM UTC 24 |
| Peak memory | 368072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538447960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3538447960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3893508198 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2594507286 ps |
| CPU time | 296.52 seconds |
| Started | Oct 15 03:23:48 AM UTC 24 |
| Finished | Oct 15 03:28:49 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893508198 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.3893508198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1152183630 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 169433292 ps |
| CPU time | 77.58 seconds |
| Started | Oct 15 03:24:13 AM UTC 24 |
| Finished | Oct 15 03:25:32 AM UTC 24 |
| Peak memory | 378168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1152183630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t hroughput_w_partial_write.1152183630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2630022194 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 900851693 ps |
| CPU time | 155.13 seconds |
| Started | Oct 15 03:26:00 AM UTC 24 |
| Finished | Oct 15 03:28:38 AM UTC 24 |
| Peak memory | 382148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630022194 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during _key_req.2630022194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1126695500 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 17470761 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 03:26:28 AM UTC 24 |
| Finished | Oct 15 03:26:30 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126695500 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1126695500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.798750392 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 910498184 ps |
| CPU time | 28.99 seconds |
| Started | Oct 15 03:25:11 AM UTC 24 |
| Finished | Oct 15 03:25:41 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798750392 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.798750392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.833623803 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3753186683 ps |
| CPU time | 1064.1 seconds |
| Started | Oct 15 03:26:02 AM UTC 24 |
| Finished | Oct 15 03:43:56 AM UTC 24 |
| Peak memory | 384240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833623803 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.833623803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.4073476518 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1568995607 ps |
| CPU time | 6.91 seconds |
| Started | Oct 15 03:25:58 AM UTC 24 |
| Finished | Oct 15 03:26:06 AM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073476518 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.4073476518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3027861355 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 484324390 ps |
| CPU time | 58.19 seconds |
| Started | Oct 15 03:25:52 AM UTC 24 |
| Finished | Oct 15 03:26:52 AM UTC 24 |
| Peak memory | 357492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 027861355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma x_throughput.3027861355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2636856215 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 155789945 ps |
| CPU time | 7 seconds |
| Started | Oct 15 03:26:17 AM UTC 24 |
| Finished | Oct 15 03:26:25 AM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636856215 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2636856215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.3053697656 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 146382912 ps |
| CPU time | 9.83 seconds |
| Started | Oct 15 03:26:17 AM UTC 24 |
| Finished | Oct 15 03:26:28 AM UTC 24 |
| Peak memory | 221588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053697656 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.3053697656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.4288481739 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 32452407427 ps |
| CPU time | 1055.35 seconds |
| Started | Oct 15 03:25:04 AM UTC 24 |
| Finished | Oct 15 03:42:51 AM UTC 24 |
| Peak memory | 378228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288481739 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.4288481739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1452824584 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 338082183 ps |
| CPU time | 7.97 seconds |
| Started | Oct 15 03:25:42 AM UTC 24 |
| Finished | Oct 15 03:25:51 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452824584 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.1452824584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3346298847 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 20704029231 ps |
| CPU time | 327.46 seconds |
| Started | Oct 15 03:25:50 AM UTC 24 |
| Finished | Oct 15 03:31:22 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346298847 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acc ess_b2b.3346298847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.3337539392 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 121228569 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 03:26:14 AM UTC 24 |
| Finished | Oct 15 03:26:16 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337539392 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3337539392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_readback_err.1571343983 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 111626064 ps |
| CPU time | 1.35 seconds |
| Started | Oct 15 03:26:18 AM UTC 24 |
| Finished | Oct 15 03:26:20 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571343983 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_readback_err.1571343983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3147352094 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 26337930234 ps |
| CPU time | 774.11 seconds |
| Started | Oct 15 03:26:07 AM UTC 24 |
| Finished | Oct 15 03:39:10 AM UTC 24 |
| Peak memory | 378188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147352094 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3147352094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.3355479619 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 541826654 ps |
| CPU time | 2.29 seconds |
| Started | Oct 15 03:25:00 AM UTC 24 |
| Finished | Oct 15 03:25:04 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355479619 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3355479619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1343304993 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 604923849789 ps |
| CPU time | 4681.68 seconds |
| Started | Oct 15 03:26:26 AM UTC 24 |
| Finished | Oct 15 04:45:17 AM UTC 24 |
| Peak memory | 385908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134330499 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.1343304993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1736711730 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 7222642566 ps |
| CPU time | 256.71 seconds |
| Started | Oct 15 03:25:33 AM UTC 24 |
| Finished | Oct 15 03:29:54 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736711730 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.1736711730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4195761154 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 153689143 ps |
| CPU time | 1.5 seconds |
| Started | Oct 15 03:25:55 AM UTC 24 |
| Finished | Oct 15 03:25:58 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4195761154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t hroughput_w_partial_write.4195761154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1083163802 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1903688128 ps |
| CPU time | 339.39 seconds |
| Started | Oct 15 03:27:41 AM UTC 24 |
| Finished | Oct 15 03:33:25 AM UTC 24 |
| Peak memory | 361756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083163802 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during _key_req.1083163802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2230340428 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 31657470 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:28:00 AM UTC 24 |
| Finished | Oct 15 03:28:02 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230340428 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2230340428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.4157755256 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 698334575 ps |
| CPU time | 56.48 seconds |
| Started | Oct 15 03:26:47 AM UTC 24 |
| Finished | Oct 15 03:27:45 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157755256 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.4157755256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.3731212222 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 7812597605 ps |
| CPU time | 555.63 seconds |
| Started | Oct 15 03:27:43 AM UTC 24 |
| Finished | Oct 15 03:37:05 AM UTC 24 |
| Peak memory | 382264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731212222 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.3731212222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.992075168 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 127230628 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 03:27:38 AM UTC 24 |
| Finished | Oct 15 03:27:41 AM UTC 24 |
| Peak memory | 220292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992075168 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.992075168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1662907034 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 117036464 ps |
| CPU time | 61.38 seconds |
| Started | Oct 15 03:27:20 AM UTC 24 |
| Finished | Oct 15 03:28:23 AM UTC 24 |
| Peak memory | 353596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 662907034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ma x_throughput.1662907034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1280670951 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 172045735 ps |
| CPU time | 7.9 seconds |
| Started | Oct 15 03:27:50 AM UTC 24 |
| Finished | Oct 15 03:27:59 AM UTC 24 |
| Peak memory | 221792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280670951 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.1280670951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3363497917 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1248134010 ps |
| CPU time | 7.26 seconds |
| Started | Oct 15 03:27:47 AM UTC 24 |
| Finished | Oct 15 03:27:55 AM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363497917 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3363497917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.729674498 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2723274987 ps |
| CPU time | 529.31 seconds |
| Started | Oct 15 03:26:42 AM UTC 24 |
| Finished | Oct 15 03:35:38 AM UTC 24 |
| Peak memory | 368000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729674498 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.729674498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.147368639 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 144558499 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 03:27:14 AM UTC 24 |
| Finished | Oct 15 03:27:20 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147368639 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.147368639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3086513828 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 74852856397 ps |
| CPU time | 598.37 seconds |
| Started | Oct 15 03:27:20 AM UTC 24 |
| Finished | Oct 15 03:37:26 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086513828 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc ess_b2b.3086513828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.490331529 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 69386203 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 03:27:47 AM UTC 24 |
| Finished | Oct 15 03:27:49 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490331529 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.490331529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3644852932 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 32701349 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 03:27:56 AM UTC 24 |
| Finished | Oct 15 03:27:58 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644852932 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_readback_err.3644852932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.740066131 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 94755765525 ps |
| CPU time | 996.16 seconds |
| Started | Oct 15 03:27:46 AM UTC 24 |
| Finished | Oct 15 03:44:33 AM UTC 24 |
| Peak memory | 384464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740066131 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.740066131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2461119106 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1054045791 ps |
| CPU time | 107.78 seconds |
| Started | Oct 15 03:26:32 AM UTC 24 |
| Finished | Oct 15 03:28:21 AM UTC 24 |
| Peak memory | 376012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461119106 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2461119106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.364047981 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 10512909719 ps |
| CPU time | 2243.04 seconds |
| Started | Oct 15 03:28:00 AM UTC 24 |
| Finished | Oct 15 04:05:45 AM UTC 24 |
| Peak memory | 381812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364047981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.364047981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.406153926 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1589274371 ps |
| CPU time | 246 seconds |
| Started | Oct 15 03:27:59 AM UTC 24 |
| Finished | Oct 15 03:32:09 AM UTC 24 |
| Peak memory | 384332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406153926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.406153926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1137184642 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1714676829 ps |
| CPU time | 218.24 seconds |
| Started | Oct 15 03:26:53 AM UTC 24 |
| Finished | Oct 15 03:30:35 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137184642 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.1137184642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3718526514 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 64565129 ps |
| CPU time | 7.02 seconds |
| Started | Oct 15 03:27:38 AM UTC 24 |
| Finished | Oct 15 03:27:46 AM UTC 24 |
| Peak memory | 244996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3718526514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t hroughput_w_partial_write.3718526514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.794706659 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2026421712 ps |
| CPU time | 100.87 seconds |
| Started | Oct 15 03:28:52 AM UTC 24 |
| Finished | Oct 15 03:30:35 AM UTC 24 |
| Peak memory | 347260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794706659 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during_ key_req.794706659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2661814097 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 33880314 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 03:29:50 AM UTC 24 |
| Finished | Oct 15 03:29:52 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661814097 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.2661814097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.4250944016 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 5945588806 ps |
| CPU time | 25.36 seconds |
| Started | Oct 15 03:28:24 AM UTC 24 |
| Finished | Oct 15 03:28:50 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250944016 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.4250944016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.601003713 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 17751275949 ps |
| CPU time | 847.36 seconds |
| Started | Oct 15 03:29:00 AM UTC 24 |
| Finished | Oct 15 03:43:17 AM UTC 24 |
| Peak memory | 382188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601003713 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.601003713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.540767012 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 506407035 ps |
| CPU time | 8.08 seconds |
| Started | Oct 15 03:28:49 AM UTC 24 |
| Finished | Oct 15 03:28:59 AM UTC 24 |
| Peak memory | 221552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540767012 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.540767012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3627660463 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 42469597 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 03:28:42 AM UTC 24 |
| Finished | Oct 15 03:28:45 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 627660463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma x_throughput.3627660463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2688421355 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 209324040 ps |
| CPU time | 8.09 seconds |
| Started | Oct 15 03:29:36 AM UTC 24 |
| Finished | Oct 15 03:29:46 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688421355 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2688421355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2594675206 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 464098001 ps |
| CPU time | 8.29 seconds |
| Started | Oct 15 03:29:26 AM UTC 24 |
| Finished | Oct 15 03:29:36 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594675206 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2594675206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.845024881 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4207439564 ps |
| CPU time | 643.79 seconds |
| Started | Oct 15 03:28:23 AM UTC 24 |
| Finished | Oct 15 03:39:14 AM UTC 24 |
| Peak memory | 384088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845024881 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.845024881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3849557669 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 665340035 ps |
| CPU time | 8.59 seconds |
| Started | Oct 15 03:28:32 AM UTC 24 |
| Finished | Oct 15 03:28:42 AM UTC 24 |
| Peak memory | 240956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849557669 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.3849557669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.997260133 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 69970838669 ps |
| CPU time | 519.37 seconds |
| Started | Oct 15 03:28:39 AM UTC 24 |
| Finished | Oct 15 03:37:26 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997260133 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acce ss_b2b.997260133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3323757877 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 44662895 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 03:29:23 AM UTC 24 |
| Finished | Oct 15 03:29:25 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323757877 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3323757877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_readback_err.700173437 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 76149417 ps |
| CPU time | 1.55 seconds |
| Started | Oct 15 03:29:47 AM UTC 24 |
| Finished | Oct 15 03:29:49 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700173437 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_readback_err.700173437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3044326594 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3373421297 ps |
| CPU time | 389.89 seconds |
| Started | Oct 15 03:29:08 AM UTC 24 |
| Finished | Oct 15 03:35:42 AM UTC 24 |
| Peak memory | 376072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044326594 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3044326594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.22965151 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1051332304 ps |
| CPU time | 26.16 seconds |
| Started | Oct 15 03:28:03 AM UTC 24 |
| Finished | Oct 15 03:28:31 AM UTC 24 |
| Peak memory | 285856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22965151 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.22965151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2847547628 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 31391576141 ps |
| CPU time | 2409.86 seconds |
| Started | Oct 15 03:29:50 AM UTC 24 |
| Finished | Oct 15 04:10:24 AM UTC 24 |
| Peak memory | 387856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284754762 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.2847547628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1655193679 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 185031038 ps |
| CPU time | 23.13 seconds |
| Started | Oct 15 03:29:48 AM UTC 24 |
| Finished | Oct 15 03:30:12 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655193679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1655193679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2974830830 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 8451362249 ps |
| CPU time | 243.9 seconds |
| Started | Oct 15 03:28:28 AM UTC 24 |
| Finished | Oct 15 03:32:36 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974830830 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.2974830830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.790688695 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 472007286 ps |
| CPU time | 62.12 seconds |
| Started | Oct 15 03:28:45 AM UTC 24 |
| Finished | Oct 15 03:29:49 AM UTC 24 |
| Peak memory | 330936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 790688695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_th roughput_w_partial_write.790688695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3571656658 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3011409439 ps |
| CPU time | 141.26 seconds |
| Started | Oct 15 03:30:45 AM UTC 24 |
| Finished | Oct 15 03:33:09 AM UTC 24 |
| Peak memory | 339300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571656658 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during _key_req.3571656658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1184683169 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 38695481 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 03:31:05 AM UTC 24 |
| Finished | Oct 15 03:31:07 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184683169 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1184683169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.1497776415 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 982924620 ps |
| CPU time | 82.27 seconds |
| Started | Oct 15 03:30:00 AM UTC 24 |
| Finished | Oct 15 03:31:25 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497776415 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.1497776415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2458481088 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 6677140283 ps |
| CPU time | 91.56 seconds |
| Started | Oct 15 03:30:49 AM UTC 24 |
| Finished | Oct 15 03:32:23 AM UTC 24 |
| Peak memory | 326840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458481088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.2458481088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1819360695 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 6255876455 ps |
| CPU time | 8.8 seconds |
| Started | Oct 15 03:30:41 AM UTC 24 |
| Finished | Oct 15 03:30:51 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819360695 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.1819360695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.862979336 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 455706147 ps |
| CPU time | 65.53 seconds |
| Started | Oct 15 03:30:36 AM UTC 24 |
| Finished | Oct 15 03:31:43 AM UTC 24 |
| Peak memory | 355504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 62979336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_max _throughput.862979336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1844834076 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 301322574 ps |
| CPU time | 3.94 seconds |
| Started | Oct 15 03:30:56 AM UTC 24 |
| Finished | Oct 15 03:31:01 AM UTC 24 |
| Peak memory | 221576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844834076 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.1844834076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3018363913 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 186584698 ps |
| CPU time | 7.13 seconds |
| Started | Oct 15 03:30:55 AM UTC 24 |
| Finished | Oct 15 03:31:03 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018363913 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.3018363913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3501469105 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3633476539 ps |
| CPU time | 762.48 seconds |
| Started | Oct 15 03:29:54 AM UTC 24 |
| Finished | Oct 15 03:42:46 AM UTC 24 |
| Peak memory | 384352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501469105 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.3501469105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.4065942099 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1093428472 ps |
| CPU time | 8.21 seconds |
| Started | Oct 15 03:30:31 AM UTC 24 |
| Finished | Oct 15 03:30:40 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065942099 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.4065942099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1418479898 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 335049731166 ps |
| CPU time | 660.43 seconds |
| Started | Oct 15 03:30:36 AM UTC 24 |
| Finished | Oct 15 03:41:45 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418479898 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acc ess_b2b.1418479898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3931642698 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 28347792 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 03:30:52 AM UTC 24 |
| Finished | Oct 15 03:30:54 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931642698 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3931642698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3097225008 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 107998773 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 03:31:01 AM UTC 24 |
| Finished | Oct 15 03:31:04 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097225008 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_readback_err.3097225008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2509743269 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 35321904186 ps |
| CPU time | 1349.97 seconds |
| Started | Oct 15 03:30:50 AM UTC 24 |
| Finished | Oct 15 03:53:36 AM UTC 24 |
| Peak memory | 378120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509743269 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2509743269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2926198576 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 299360998 ps |
| CPU time | 4.93 seconds |
| Started | Oct 15 03:29:53 AM UTC 24 |
| Finished | Oct 15 03:29:59 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926198576 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2926198576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1271010136 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 23147903455 ps |
| CPU time | 1699.62 seconds |
| Started | Oct 15 03:31:05 AM UTC 24 |
| Finished | Oct 15 03:59:42 AM UTC 24 |
| Peak memory | 392300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127101013 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.1271010136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.226281435 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5130472669 ps |
| CPU time | 265.02 seconds |
| Started | Oct 15 03:31:02 AM UTC 24 |
| Finished | Oct 15 03:35:32 AM UTC 24 |
| Peak memory | 361868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226281435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.226281435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.631448059 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1734417754 ps |
| CPU time | 183.9 seconds |
| Started | Oct 15 03:30:14 AM UTC 24 |
| Finished | Oct 15 03:33:21 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631448059 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.631448059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1072238962 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 83609689 ps |
| CPU time | 5.46 seconds |
| Started | Oct 15 03:30:41 AM UTC 24 |
| Finished | Oct 15 03:30:48 AM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1072238962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.1072238962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2380580869 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1858319666 ps |
| CPU time | 436.77 seconds |
| Started | Oct 15 03:32:02 AM UTC 24 |
| Finished | Oct 15 03:39:24 AM UTC 24 |
| Peak memory | 376100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380580869 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during _key_req.2380580869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1128467501 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 61219602 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 03:32:51 AM UTC 24 |
| Finished | Oct 15 03:32:53 AM UTC 24 |
| Peak memory | 209356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128467501 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1128467501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.4182559671 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5281629166 ps |
| CPU time | 81.96 seconds |
| Started | Oct 15 03:31:25 AM UTC 24 |
| Finished | Oct 15 03:32:49 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182559671 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.4182559671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1679797967 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2556637314 ps |
| CPU time | 596 seconds |
| Started | Oct 15 03:32:10 AM UTC 24 |
| Finished | Oct 15 03:42:13 AM UTC 24 |
| Peak memory | 384176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679797967 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.1679797967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4138919430 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1388212005 ps |
| CPU time | 9.3 seconds |
| Started | Oct 15 03:31:51 AM UTC 24 |
| Finished | Oct 15 03:32:01 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138919430 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.4138919430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1565962967 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 131444369 ps |
| CPU time | 81.48 seconds |
| Started | Oct 15 03:31:35 AM UTC 24 |
| Finished | Oct 15 03:32:58 AM UTC 24 |
| Peak memory | 374068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 565962967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ma x_throughput.1565962967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.526790652 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1841802783 ps |
| CPU time | 8.41 seconds |
| Started | Oct 15 03:32:40 AM UTC 24 |
| Finished | Oct 15 03:32:50 AM UTC 24 |
| Peak memory | 221708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526790652 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.526790652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3174005927 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 271153113 ps |
| CPU time | 10.18 seconds |
| Started | Oct 15 03:32:38 AM UTC 24 |
| Finished | Oct 15 03:32:49 AM UTC 24 |
| Peak memory | 221840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174005927 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.3174005927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2709205593 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 31197187594 ps |
| CPU time | 452.88 seconds |
| Started | Oct 15 03:31:23 AM UTC 24 |
| Finished | Oct 15 03:39:02 AM UTC 24 |
| Peak memory | 371928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709205593 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.2709205593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1376223756 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1583171165 ps |
| CPU time | 19.38 seconds |
| Started | Oct 15 03:31:30 AM UTC 24 |
| Finished | Oct 15 03:31:51 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376223756 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.1376223756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1124362340 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 8088741517 ps |
| CPU time | 277.44 seconds |
| Started | Oct 15 03:31:30 AM UTC 24 |
| Finished | Oct 15 03:36:11 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124362340 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acc ess_b2b.1124362340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1463095258 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 26755720 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 03:32:37 AM UTC 24 |
| Finished | Oct 15 03:32:39 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463095258 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1463095258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_readback_err.3598817850 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 131918392 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 03:32:42 AM UTC 24 |
| Finished | Oct 15 03:32:45 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598817850 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_readback_err.3598817850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.343592116 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 9482469913 ps |
| CPU time | 371.8 seconds |
| Started | Oct 15 03:32:24 AM UTC 24 |
| Finished | Oct 15 03:38:40 AM UTC 24 |
| Peak memory | 376276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343592116 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.343592116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.2755002533 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3659858535 ps |
| CPU time | 19.88 seconds |
| Started | Oct 15 03:31:08 AM UTC 24 |
| Finished | Oct 15 03:31:29 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755002533 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2755002533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1584581791 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 128830532836 ps |
| CPU time | 5954.65 seconds |
| Started | Oct 15 03:32:51 AM UTC 24 |
| Finished | Oct 15 05:13:04 AM UTC 24 |
| Peak memory | 385184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158458179 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.1584581791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3933586129 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 12510148747 ps |
| CPU time | 225.59 seconds |
| Started | Oct 15 03:31:28 AM UTC 24 |
| Finished | Oct 15 03:35:17 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933586129 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.3933586129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.413277020 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 111119538 ps |
| CPU time | 51.17 seconds |
| Started | Oct 15 03:31:44 AM UTC 24 |
| Finished | Oct 15 03:32:37 AM UTC 24 |
| Peak memory | 310384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 413277020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_th roughput_w_partial_write.413277020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.274918832 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 7011169358 ps |
| CPU time | 573.08 seconds |
| Started | Oct 15 03:33:33 AM UTC 24 |
| Finished | Oct 15 03:43:13 AM UTC 24 |
| Peak memory | 374004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274918832 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_ key_req.274918832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1393626383 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 22346721 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 03:35:18 AM UTC 24 |
| Finished | Oct 15 03:35:20 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393626383 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1393626383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.881275511 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1883504037 ps |
| CPU time | 32.16 seconds |
| Started | Oct 15 03:32:59 AM UTC 24 |
| Finished | Oct 15 03:33:32 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881275511 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.881275511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.3009874088 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6708985151 ps |
| CPU time | 521.31 seconds |
| Started | Oct 15 03:33:38 AM UTC 24 |
| Finished | Oct 15 03:42:26 AM UTC 24 |
| Peak memory | 378036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009874088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.3009874088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.208001140 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3065550429 ps |
| CPU time | 10.19 seconds |
| Started | Oct 15 03:33:26 AM UTC 24 |
| Finished | Oct 15 03:33:37 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208001140 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.208001140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.4116931367 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 39580086 ps |
| CPU time | 2.58 seconds |
| Started | Oct 15 03:33:22 AM UTC 24 |
| Finished | Oct 15 03:33:25 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 116931367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma x_throughput.4116931367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1552158465 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 173963880 ps |
| CPU time | 6.94 seconds |
| Started | Oct 15 03:34:45 AM UTC 24 |
| Finished | Oct 15 03:34:53 AM UTC 24 |
| Peak memory | 221676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552158465 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.1552158465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3086777408 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1367016660 ps |
| CPU time | 9.3 seconds |
| Started | Oct 15 03:34:43 AM UTC 24 |
| Finished | Oct 15 03:34:53 AM UTC 24 |
| Peak memory | 221536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086777408 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.3086777408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2988462110 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 23421719464 ps |
| CPU time | 955.97 seconds |
| Started | Oct 15 03:32:54 AM UTC 24 |
| Finished | Oct 15 03:49:01 AM UTC 24 |
| Peak memory | 382140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988462110 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.2988462110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.666511001 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 65484772 ps |
| CPU time | 2.28 seconds |
| Started | Oct 15 03:33:09 AM UTC 24 |
| Finished | Oct 15 03:33:13 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666511001 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.666511001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2326196662 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 32040226900 ps |
| CPU time | 317.07 seconds |
| Started | Oct 15 03:33:13 AM UTC 24 |
| Finished | Oct 15 03:38:35 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326196662 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acc ess_b2b.2326196662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3028670467 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 40297816 ps |
| CPU time | 1.29 seconds |
| Started | Oct 15 03:34:39 AM UTC 24 |
| Finished | Oct 15 03:34:42 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028670467 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3028670467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_readback_err.2813095285 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 32842500 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 03:34:54 AM UTC 24 |
| Finished | Oct 15 03:34:56 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813095285 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_readback_err.2813095285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3372277824 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 4475308006 ps |
| CPU time | 608.86 seconds |
| Started | Oct 15 03:34:17 AM UTC 24 |
| Finished | Oct 15 03:44:33 AM UTC 24 |
| Peak memory | 382140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372277824 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3372277824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.1818473127 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2254220062 ps |
| CPU time | 15.87 seconds |
| Started | Oct 15 03:32:51 AM UTC 24 |
| Finished | Oct 15 03:33:08 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818473127 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1818473127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1192381467 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 20629853850 ps |
| CPU time | 2399.16 seconds |
| Started | Oct 15 03:34:57 AM UTC 24 |
| Finished | Oct 15 04:15:22 AM UTC 24 |
| Peak memory | 381944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119238146 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.1192381467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1454149328 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 24418609359 ps |
| CPU time | 631.17 seconds |
| Started | Oct 15 03:34:54 AM UTC 24 |
| Finished | Oct 15 03:45:32 AM UTC 24 |
| Peak memory | 388496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454149328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1454149328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.284355422 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 13894921935 ps |
| CPU time | 260.02 seconds |
| Started | Oct 15 03:33:08 AM UTC 24 |
| Finished | Oct 15 03:37:32 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284355422 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.284355422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.21996963 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 150074830 ps |
| CPU time | 76.05 seconds |
| Started | Oct 15 03:33:26 AM UTC 24 |
| Finished | Oct 15 03:34:43 AM UTC 24 |
| Peak memory | 371896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 21996963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_thr oughput_w_partial_write.21996963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3729410614 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2195019680 ps |
| CPU time | 126.32 seconds |
| Started | Oct 15 03:36:03 AM UTC 24 |
| Finished | Oct 15 03:38:11 AM UTC 24 |
| Peak memory | 371896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729410614 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during _key_req.3729410614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2351859162 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 22269680 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 03:36:55 AM UTC 24 |
| Finished | Oct 15 03:36:57 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351859162 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2351859162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2007654562 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3613248217 ps |
| CPU time | 79.73 seconds |
| Started | Oct 15 03:35:33 AM UTC 24 |
| Finished | Oct 15 03:36:55 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007654562 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.2007654562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.125460194 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 67998996656 ps |
| CPU time | 1165.09 seconds |
| Started | Oct 15 03:36:12 AM UTC 24 |
| Finished | Oct 15 03:55:50 AM UTC 24 |
| Peak memory | 382132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125460194 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.125460194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1281153072 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 169019581 ps |
| CPU time | 2.42 seconds |
| Started | Oct 15 03:35:59 AM UTC 24 |
| Finished | Oct 15 03:36:02 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281153072 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.1281153072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1623433586 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 121204967 ps |
| CPU time | 59.49 seconds |
| Started | Oct 15 03:35:43 AM UTC 24 |
| Finished | Oct 15 03:36:45 AM UTC 24 |
| Peak memory | 353392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 623433586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ma x_throughput.1623433586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.918051359 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 75191203 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 03:36:45 AM UTC 24 |
| Finished | Oct 15 03:36:50 AM UTC 24 |
| Peak memory | 221704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918051359 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.918051359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2836131359 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 362563923 ps |
| CPU time | 6.55 seconds |
| Started | Oct 15 03:36:40 AM UTC 24 |
| Finished | Oct 15 03:36:48 AM UTC 24 |
| Peak memory | 221644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836131359 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.2836131359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3747643315 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 29116295838 ps |
| CPU time | 777.71 seconds |
| Started | Oct 15 03:35:28 AM UTC 24 |
| Finished | Oct 15 03:48:35 AM UTC 24 |
| Peak memory | 384248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747643315 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.3747643315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2924019915 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2376106244 ps |
| CPU time | 18.69 seconds |
| Started | Oct 15 03:35:38 AM UTC 24 |
| Finished | Oct 15 03:35:58 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924019915 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.2924019915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2061546238 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 14512261612 ps |
| CPU time | 293.87 seconds |
| Started | Oct 15 03:35:39 AM UTC 24 |
| Finished | Oct 15 03:40:37 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061546238 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc ess_b2b.2061546238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2774331320 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 252120448 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 03:36:37 AM UTC 24 |
| Finished | Oct 15 03:36:39 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774331320 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2774331320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_readback_err.65658475 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 32283756 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 03:36:49 AM UTC 24 |
| Finished | Oct 15 03:36:51 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65658475 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_readback_err.65658475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.4226468434 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2217321032 ps |
| CPU time | 569.05 seconds |
| Started | Oct 15 03:36:24 AM UTC 24 |
| Finished | Oct 15 03:46:00 AM UTC 24 |
| Peak memory | 382344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226468434 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.4226468434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.238240046 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1009954843 ps |
| CPU time | 15.1 seconds |
| Started | Oct 15 03:35:21 AM UTC 24 |
| Finished | Oct 15 03:35:38 AM UTC 24 |
| Peak memory | 273544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238240046 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.238240046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2112793690 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 414690997095 ps |
| CPU time | 4934.34 seconds |
| Started | Oct 15 03:36:52 AM UTC 24 |
| Finished | Oct 15 05:00:00 AM UTC 24 |
| Peak memory | 386032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211279369 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.2112793690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1841306138 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 28734844927 ps |
| CPU time | 314 seconds |
| Started | Oct 15 03:35:37 AM UTC 24 |
| Finished | Oct 15 03:40:56 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841306138 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.1841306138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1465022673 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 193470559 ps |
| CPU time | 37.99 seconds |
| Started | Oct 15 03:35:43 AM UTC 24 |
| Finished | Oct 15 03:36:23 AM UTC 24 |
| Peak memory | 298112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1465022673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t hroughput_w_partial_write.1465022673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3316455689 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 6535364129 ps |
| CPU time | 271.29 seconds |
| Started | Oct 15 03:38:01 AM UTC 24 |
| Finished | Oct 15 03:42:36 AM UTC 24 |
| Peak memory | 376204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316455689 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during _key_req.3316455689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1419284337 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 16990136 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 03:38:36 AM UTC 24 |
| Finished | Oct 15 03:38:38 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419284337 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1419284337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2505639430 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2602999666 ps |
| CPU time | 45.86 seconds |
| Started | Oct 15 03:37:12 AM UTC 24 |
| Finished | Oct 15 03:38:00 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505639430 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.2505639430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1740120029 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1954166292 ps |
| CPU time | 543.89 seconds |
| Started | Oct 15 03:38:02 AM UTC 24 |
| Finished | Oct 15 03:47:12 AM UTC 24 |
| Peak memory | 365712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740120029 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.1740120029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.2969809748 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 293466995 ps |
| CPU time | 4.11 seconds |
| Started | Oct 15 03:37:56 AM UTC 24 |
| Finished | Oct 15 03:38:01 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969809748 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.2969809748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3206733531 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 150093976 ps |
| CPU time | 2.19 seconds |
| Started | Oct 15 03:37:50 AM UTC 24 |
| Finished | Oct 15 03:37:53 AM UTC 24 |
| Peak memory | 227728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 206733531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma x_throughput.3206733531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3804053484 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 65355746 ps |
| CPU time | 4.71 seconds |
| Started | Oct 15 03:38:22 AM UTC 24 |
| Finished | Oct 15 03:38:27 AM UTC 24 |
| Peak memory | 221600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804053484 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.3804053484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3329100979 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 81456921 ps |
| CPU time | 6.35 seconds |
| Started | Oct 15 03:38:15 AM UTC 24 |
| Finished | Oct 15 03:38:23 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329100979 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.3329100979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.955215222 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1236403883 ps |
| CPU time | 305.81 seconds |
| Started | Oct 15 03:37:06 AM UTC 24 |
| Finished | Oct 15 03:42:16 AM UTC 24 |
| Peak memory | 382260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955215222 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.955215222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2868918262 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1004984997 ps |
| CPU time | 25.39 seconds |
| Started | Oct 15 03:37:28 AM UTC 24 |
| Finished | Oct 15 03:37:55 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868918262 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.2868918262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.298847098 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 54348064517 ps |
| CPU time | 454.17 seconds |
| Started | Oct 15 03:37:33 AM UTC 24 |
| Finished | Oct 15 03:45:13 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298847098 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acce ss_b2b.298847098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3779890363 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 43743266 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 03:38:12 AM UTC 24 |
| Finished | Oct 15 03:38:14 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779890363 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3779890363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_readback_err.1847316108 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 30800268 ps |
| CPU time | 1.42 seconds |
| Started | Oct 15 03:38:24 AM UTC 24 |
| Finished | Oct 15 03:38:26 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847316108 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_readback_err.1847316108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.205972807 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 34606019090 ps |
| CPU time | 740.45 seconds |
| Started | Oct 15 03:38:08 AM UTC 24 |
| Finished | Oct 15 03:50:37 AM UTC 24 |
| Peak memory | 382340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205972807 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.205972807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.157018053 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1440748788 ps |
| CPU time | 95.31 seconds |
| Started | Oct 15 03:36:58 AM UTC 24 |
| Finished | Oct 15 03:38:35 AM UTC 24 |
| Peak memory | 376012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157018053 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.157018053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2551347881 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 10431015003 ps |
| CPU time | 649.89 seconds |
| Started | Oct 15 03:38:28 AM UTC 24 |
| Finished | Oct 15 03:49:25 AM UTC 24 |
| Peak memory | 382156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255134788 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.2551347881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.459322253 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4399700065 ps |
| CPU time | 219.66 seconds |
| Started | Oct 15 03:37:27 AM UTC 24 |
| Finished | Oct 15 03:41:10 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459322253 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.459322253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1096680812 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 274594544 ps |
| CPU time | 11.19 seconds |
| Started | Oct 15 03:37:54 AM UTC 24 |
| Finished | Oct 15 03:38:07 AM UTC 24 |
| Peak memory | 261272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1096680812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_t hroughput_w_partial_write.1096680812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1251981301 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1446240043 ps |
| CPU time | 429.1 seconds |
| Started | Oct 15 03:05:21 AM UTC 24 |
| Finished | Oct 15 03:12:37 AM UTC 24 |
| Peak memory | 382076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251981301 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_ key_req.1251981301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3055320514 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 16360852 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 03:06:18 AM UTC 24 |
| Finished | Oct 15 03:06:21 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055320514 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3055320514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.4261897728 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2475881522 ps |
| CPU time | 83.76 seconds |
| Started | Oct 15 03:04:33 AM UTC 24 |
| Finished | Oct 15 03:05:59 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261897728 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.4261897728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.940615819 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 13923934946 ps |
| CPU time | 1102.97 seconds |
| Started | Oct 15 03:05:33 AM UTC 24 |
| Finished | Oct 15 03:24:07 AM UTC 24 |
| Peak memory | 376072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940615819 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.940615819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3899609123 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 281996865 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 03:05:17 AM UTC 24 |
| Finished | Oct 15 03:05:21 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899609123 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.3899609123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2490153473 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 178856249 ps |
| CPU time | 4.44 seconds |
| Started | Oct 15 03:05:01 AM UTC 24 |
| Finished | Oct 15 03:05:07 AM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 490153473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max _throughput.2490153473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2405242231 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 985614788 ps |
| CPU time | 7.01 seconds |
| Started | Oct 15 03:06:04 AM UTC 24 |
| Finished | Oct 15 03:06:12 AM UTC 24 |
| Peak memory | 221768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405242231 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.2405242231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.868399994 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 575704917 ps |
| CPU time | 8.21 seconds |
| Started | Oct 15 03:06:01 AM UTC 24 |
| Finished | Oct 15 03:06:11 AM UTC 24 |
| Peak memory | 221584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868399994 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.868399994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2922603801 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 29650430817 ps |
| CPU time | 328.65 seconds |
| Started | Oct 15 03:04:31 AM UTC 24 |
| Finished | Oct 15 03:10:04 AM UTC 24 |
| Peak memory | 384248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922603801 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.2922603801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2891505512 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 372940544 ps |
| CPU time | 8.15 seconds |
| Started | Oct 15 03:04:51 AM UTC 24 |
| Finished | Oct 15 03:05:00 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891505512 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.2891505512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3917162099 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 99102394822 ps |
| CPU time | 564.65 seconds |
| Started | Oct 15 03:04:54 AM UTC 24 |
| Finished | Oct 15 03:14:26 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917162099 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce ss_b2b.3917162099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1295351167 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 28411898 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:06:00 AM UTC 24 |
| Finished | Oct 15 03:06:03 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295351167 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1295351167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_readback_err.367163301 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 101131877 ps |
| CPU time | 1.58 seconds |
| Started | Oct 15 03:06:09 AM UTC 24 |
| Finished | Oct 15 03:06:12 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367163301 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_readback_err.367163301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.3328439282 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1444077087 ps |
| CPU time | 227.58 seconds |
| Started | Oct 15 03:05:34 AM UTC 24 |
| Finished | Oct 15 03:09:25 AM UTC 24 |
| Peak memory | 320640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328439282 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3328439282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.617646843 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1446436514 ps |
| CPU time | 97.11 seconds |
| Started | Oct 15 03:04:29 AM UTC 24 |
| Finished | Oct 15 03:06:08 AM UTC 24 |
| Peak memory | 376012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617646843 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.617646843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.817612492 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 36969953215 ps |
| CPU time | 213.95 seconds |
| Started | Oct 15 03:04:37 AM UTC 24 |
| Finished | Oct 15 03:08:14 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817612492 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.817612492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2469503547 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 363010607 ps |
| CPU time | 24.48 seconds |
| Started | Oct 15 03:05:07 AM UTC 24 |
| Finished | Oct 15 03:05:33 AM UTC 24 |
| Peak memory | 285808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2469503547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th roughput_w_partial_write.2469503547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3008523457 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1191447322 ps |
| CPU time | 88.67 seconds |
| Started | Oct 15 03:39:22 AM UTC 24 |
| Finished | Oct 15 03:40:53 AM UTC 24 |
| Peak memory | 337096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008523457 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during _key_req.3008523457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.764058750 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 27146859 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 03:40:23 AM UTC 24 |
| Finished | Oct 15 03:40:25 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764058750 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.764058750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3789566104 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1045503766 ps |
| CPU time | 23.44 seconds |
| Started | Oct 15 03:38:40 AM UTC 24 |
| Finished | Oct 15 03:39:04 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789566104 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3789566104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.1464248388 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 7054803609 ps |
| CPU time | 178.91 seconds |
| Started | Oct 15 03:39:25 AM UTC 24 |
| Finished | Oct 15 03:42:27 AM UTC 24 |
| Peak memory | 376256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464248388 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.1464248388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1295479525 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 711212983 ps |
| CPU time | 5.11 seconds |
| Started | Oct 15 03:39:15 AM UTC 24 |
| Finished | Oct 15 03:39:21 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295479525 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.1295479525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1445866114 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 124309681 ps |
| CPU time | 73.04 seconds |
| Started | Oct 15 03:39:07 AM UTC 24 |
| Finished | Oct 15 03:40:23 AM UTC 24 |
| Peak memory | 347320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 445866114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ma x_throughput.1445866114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.4033729051 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 159453283 ps |
| CPU time | 4.09 seconds |
| Started | Oct 15 03:40:12 AM UTC 24 |
| Finished | Oct 15 03:40:17 AM UTC 24 |
| Peak memory | 221844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033729051 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.4033729051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.952269807 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1736801887 ps |
| CPU time | 7.93 seconds |
| Started | Oct 15 03:40:07 AM UTC 24 |
| Finished | Oct 15 03:40:16 AM UTC 24 |
| Peak memory | 221576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952269807 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.952269807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3288926525 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 15772981172 ps |
| CPU time | 440.84 seconds |
| Started | Oct 15 03:38:39 AM UTC 24 |
| Finished | Oct 15 03:46:06 AM UTC 24 |
| Peak memory | 380036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288926525 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.3288926525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2243375804 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 475904212 ps |
| CPU time | 2.63 seconds |
| Started | Oct 15 03:39:03 AM UTC 24 |
| Finished | Oct 15 03:39:07 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243375804 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.2243375804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2833125310 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 11608639624 ps |
| CPU time | 348.31 seconds |
| Started | Oct 15 03:39:05 AM UTC 24 |
| Finished | Oct 15 03:44:58 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833125310 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc ess_b2b.2833125310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3864199293 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 29791514 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 03:40:03 AM UTC 24 |
| Finished | Oct 15 03:40:06 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864199293 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3864199293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_readback_err.2983586549 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 50523149 ps |
| CPU time | 1.37 seconds |
| Started | Oct 15 03:40:16 AM UTC 24 |
| Finished | Oct 15 03:40:18 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983586549 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_readback_err.2983586549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.3081481695 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6517491137 ps |
| CPU time | 549.4 seconds |
| Started | Oct 15 03:39:50 AM UTC 24 |
| Finished | Oct 15 03:49:06 AM UTC 24 |
| Peak memory | 378048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081481695 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3081481695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.3466583821 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 42308926 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 03:38:36 AM UTC 24 |
| Finished | Oct 15 03:38:39 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466583821 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3466583821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1935170066 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 7327834206 ps |
| CPU time | 1262.1 seconds |
| Started | Oct 15 03:40:19 AM UTC 24 |
| Finished | Oct 15 04:01:35 AM UTC 24 |
| Peak memory | 382152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193517006 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.1935170066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2156403407 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 45627738709 ps |
| CPU time | 347.82 seconds |
| Started | Oct 15 03:38:42 AM UTC 24 |
| Finished | Oct 15 03:44:35 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156403407 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.2156403407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2175594681 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 159190465 ps |
| CPU time | 98.41 seconds |
| Started | Oct 15 03:39:10 AM UTC 24 |
| Finished | Oct 15 03:40:51 AM UTC 24 |
| Peak memory | 378040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2175594681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t hroughput_w_partial_write.2175594681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.359129502 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 7222350761 ps |
| CPU time | 652.69 seconds |
| Started | Oct 15 03:41:13 AM UTC 24 |
| Finished | Oct 15 03:52:13 AM UTC 24 |
| Peak memory | 384184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359129502 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during_ key_req.359129502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2016070971 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 13999731 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 03:42:10 AM UTC 24 |
| Finished | Oct 15 03:42:12 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016070971 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2016070971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2212334937 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1382864672 ps |
| CPU time | 27.95 seconds |
| Started | Oct 15 03:40:38 AM UTC 24 |
| Finished | Oct 15 03:41:07 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212334937 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.2212334937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.4125425082 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 39219441538 ps |
| CPU time | 774.92 seconds |
| Started | Oct 15 03:41:19 AM UTC 24 |
| Finished | Oct 15 03:54:23 AM UTC 24 |
| Peak memory | 380160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125425082 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.4125425082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3402774273 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 738457686 ps |
| CPU time | 6.52 seconds |
| Started | Oct 15 03:41:11 AM UTC 24 |
| Finished | Oct 15 03:41:18 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402774273 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.3402774273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3004089740 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 468339505 ps |
| CPU time | 44.48 seconds |
| Started | Oct 15 03:40:56 AM UTC 24 |
| Finished | Oct 15 03:41:42 AM UTC 24 |
| Peak memory | 341168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 004089740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma x_throughput.3004089740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1484888984 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 90755720 ps |
| CPU time | 4.87 seconds |
| Started | Oct 15 03:41:55 AM UTC 24 |
| Finished | Oct 15 03:42:01 AM UTC 24 |
| Peak memory | 221708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484888984 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.1484888984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1087957611 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1194404975 ps |
| CPU time | 12.29 seconds |
| Started | Oct 15 03:41:49 AM UTC 24 |
| Finished | Oct 15 03:42:02 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087957611 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1087957611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1898752596 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 22941224269 ps |
| CPU time | 322.53 seconds |
| Started | Oct 15 03:40:31 AM UTC 24 |
| Finished | Oct 15 03:45:57 AM UTC 24 |
| Peak memory | 369920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898752596 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.1898752596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.3962264333 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2701016597 ps |
| CPU time | 74.97 seconds |
| Started | Oct 15 03:40:52 AM UTC 24 |
| Finished | Oct 15 03:42:09 AM UTC 24 |
| Peak memory | 365816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962264333 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.3962264333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3885434735 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 51832232085 ps |
| CPU time | 245.97 seconds |
| Started | Oct 15 03:40:53 AM UTC 24 |
| Finished | Oct 15 03:45:03 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885434735 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc ess_b2b.3885434735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2970628539 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 50300908 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 03:41:46 AM UTC 24 |
| Finished | Oct 15 03:41:48 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970628539 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2970628539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_readback_err.262786850 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 53698695 ps |
| CPU time | 1.41 seconds |
| Started | Oct 15 03:42:02 AM UTC 24 |
| Finished | Oct 15 03:42:04 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262786850 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_readback_err.262786850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1173168294 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 10447387358 ps |
| CPU time | 243.03 seconds |
| Started | Oct 15 03:41:43 AM UTC 24 |
| Finished | Oct 15 03:45:50 AM UTC 24 |
| Peak memory | 331008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173168294 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1173168294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.3126453548 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 76678731 ps |
| CPU time | 2.06 seconds |
| Started | Oct 15 03:40:27 AM UTC 24 |
| Finished | Oct 15 03:40:30 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126453548 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3126453548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.892347805 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 91997840538 ps |
| CPU time | 1469.1 seconds |
| Started | Oct 15 03:42:05 AM UTC 24 |
| Finished | Oct 15 04:06:50 AM UTC 24 |
| Peak memory | 384388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892347805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.892347805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2466570610 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 648763157 ps |
| CPU time | 14.92 seconds |
| Started | Oct 15 03:42:03 AM UTC 24 |
| Finished | Oct 15 03:42:19 AM UTC 24 |
| Peak memory | 221736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466570610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2466570610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.828901170 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2826875985 ps |
| CPU time | 160.71 seconds |
| Started | Oct 15 03:40:42 AM UTC 24 |
| Finished | Oct 15 03:43:25 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828901170 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.828901170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1264689140 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1057211497 ps |
| CPU time | 84.73 seconds |
| Started | Oct 15 03:41:09 AM UTC 24 |
| Finished | Oct 15 03:42:35 AM UTC 24 |
| Peak memory | 378044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1264689140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_t hroughput_w_partial_write.1264689140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3589603607 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 14684838939 ps |
| CPU time | 704.99 seconds |
| Started | Oct 15 03:42:41 AM UTC 24 |
| Finished | Oct 15 03:54:34 AM UTC 24 |
| Peak memory | 384392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589603607 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during _key_req.3589603607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.550829327 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 47342333 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 03:42:55 AM UTC 24 |
| Finished | Oct 15 03:42:57 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550829327 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.550829327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.2456515701 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 25371663698 ps |
| CPU time | 27.07 seconds |
| Started | Oct 15 03:42:17 AM UTC 24 |
| Finished | Oct 15 03:42:45 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456515701 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.2456515701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.911348258 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 12975145190 ps |
| CPU time | 432.3 seconds |
| Started | Oct 15 03:42:41 AM UTC 24 |
| Finished | Oct 15 03:49:59 AM UTC 24 |
| Peak memory | 363888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911348258 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.911348258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2624338379 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4310853122 ps |
| CPU time | 7.63 seconds |
| Started | Oct 15 03:42:37 AM UTC 24 |
| Finished | Oct 15 03:42:46 AM UTC 24 |
| Peak memory | 221592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624338379 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.2624338379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.391708363 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 310279569 ps |
| CPU time | 23.85 seconds |
| Started | Oct 15 03:42:29 AM UTC 24 |
| Finished | Oct 15 03:42:54 AM UTC 24 |
| Peak memory | 285804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 91708363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max _throughput.391708363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1849011647 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 155922902 ps |
| CPU time | 7.85 seconds |
| Started | Oct 15 03:42:51 AM UTC 24 |
| Finished | Oct 15 03:42:59 AM UTC 24 |
| Peak memory | 221632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849011647 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.1849011647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3864802699 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1837731482 ps |
| CPU time | 9.67 seconds |
| Started | Oct 15 03:42:47 AM UTC 24 |
| Finished | Oct 15 03:42:58 AM UTC 24 |
| Peak memory | 221576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864802699 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.3864802699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3295604914 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3964575662 ps |
| CPU time | 77.37 seconds |
| Started | Oct 15 03:42:14 AM UTC 24 |
| Finished | Oct 15 03:43:33 AM UTC 24 |
| Peak memory | 343280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295604914 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.3295604914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2078432634 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 612941276 ps |
| CPU time | 17.98 seconds |
| Started | Oct 15 03:42:20 AM UTC 24 |
| Finished | Oct 15 03:42:40 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078432634 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.2078432634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2492460971 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 18869331462 ps |
| CPU time | 353.31 seconds |
| Started | Oct 15 03:42:26 AM UTC 24 |
| Finished | Oct 15 03:48:24 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492460971 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc ess_b2b.2492460971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.2941261960 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 83108716 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 03:42:47 AM UTC 24 |
| Finished | Oct 15 03:42:50 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941261960 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2941261960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_readback_err.109598871 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 29503218 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 03:42:52 AM UTC 24 |
| Finished | Oct 15 03:42:54 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109598871 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_readback_err.109598871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1959900279 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 9284943280 ps |
| CPU time | 395.5 seconds |
| Started | Oct 15 03:42:46 AM UTC 24 |
| Finished | Oct 15 03:49:27 AM UTC 24 |
| Peak memory | 376200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959900279 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1959900279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.3471625880 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 153855230 ps |
| CPU time | 4.26 seconds |
| Started | Oct 15 03:42:14 AM UTC 24 |
| Finished | Oct 15 03:42:19 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471625880 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3471625880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2466235199 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 193012440257 ps |
| CPU time | 4013.59 seconds |
| Started | Oct 15 03:42:55 AM UTC 24 |
| Finished | Oct 15 04:50:27 AM UTC 24 |
| Peak memory | 393980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246623519 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.2466235199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2212221314 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1951662646 ps |
| CPU time | 191.17 seconds |
| Started | Oct 15 03:42:20 AM UTC 24 |
| Finished | Oct 15 03:45:35 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212221314 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2212221314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.583704593 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 152538530 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 03:42:37 AM UTC 24 |
| Finished | Oct 15 03:42:41 AM UTC 24 |
| Peak memory | 221580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 583704593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_th roughput_w_partial_write.583704593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3893550881 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 5992207299 ps |
| CPU time | 686.46 seconds |
| Started | Oct 15 03:43:45 AM UTC 24 |
| Finished | Oct 15 03:55:19 AM UTC 24 |
| Peak memory | 382208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893550881 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during _key_req.3893550881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3686364679 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 52452401 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:44:27 AM UTC 24 |
| Finished | Oct 15 03:44:29 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686364679 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3686364679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.3088000370 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 8139075690 ps |
| CPU time | 41.17 seconds |
| Started | Oct 15 03:43:00 AM UTC 24 |
| Finished | Oct 15 03:43:43 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088000370 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.3088000370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.994284208 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 51895924605 ps |
| CPU time | 1532.33 seconds |
| Started | Oct 15 03:43:45 AM UTC 24 |
| Finished | Oct 15 04:09:33 AM UTC 24 |
| Peak memory | 382196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994284208 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.994284208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2316843434 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1175618731 ps |
| CPU time | 6.82 seconds |
| Started | Oct 15 03:43:43 AM UTC 24 |
| Finished | Oct 15 03:43:51 AM UTC 24 |
| Peak memory | 221580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316843434 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2316843434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.682930118 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 203651035 ps |
| CPU time | 15.68 seconds |
| Started | Oct 15 03:43:27 AM UTC 24 |
| Finished | Oct 15 03:43:44 AM UTC 24 |
| Peak memory | 261368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 82930118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_max _throughput.682930118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3734350334 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 121151044 ps |
| CPU time | 3.93 seconds |
| Started | Oct 15 03:43:57 AM UTC 24 |
| Finished | Oct 15 03:44:03 AM UTC 24 |
| Peak memory | 221584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734350334 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3734350334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2469024694 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1165719860 ps |
| CPU time | 10.06 seconds |
| Started | Oct 15 03:43:55 AM UTC 24 |
| Finished | Oct 15 03:44:07 AM UTC 24 |
| Peak memory | 221716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469024694 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2469024694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2598673480 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 8982949455 ps |
| CPU time | 626.67 seconds |
| Started | Oct 15 03:42:59 AM UTC 24 |
| Finished | Oct 15 03:53:33 AM UTC 24 |
| Peak memory | 367788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598673480 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2598673480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.321817247 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1200291563 ps |
| CPU time | 23.06 seconds |
| Started | Oct 15 03:43:18 AM UTC 24 |
| Finished | Oct 15 03:43:42 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321817247 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.321817247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2883347645 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3394435102 ps |
| CPU time | 330.51 seconds |
| Started | Oct 15 03:43:18 AM UTC 24 |
| Finished | Oct 15 03:48:53 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883347645 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acc ess_b2b.2883347645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2657453755 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 30242720 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 03:43:52 AM UTC 24 |
| Finished | Oct 15 03:43:54 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657453755 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2657453755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_readback_err.3770847162 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 320097074 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 03:44:04 AM UTC 24 |
| Finished | Oct 15 03:44:06 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770847162 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_readback_err.3770847162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3346794754 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 108282409964 ps |
| CPU time | 1663.97 seconds |
| Started | Oct 15 03:43:45 AM UTC 24 |
| Finished | Oct 15 04:11:45 AM UTC 24 |
| Peak memory | 384456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346794754 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3346794754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.410641183 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 779295794 ps |
| CPU time | 17.08 seconds |
| Started | Oct 15 03:42:58 AM UTC 24 |
| Finished | Oct 15 03:43:17 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410641183 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.410641183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1685423819 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 10746694717 ps |
| CPU time | 763.94 seconds |
| Started | Oct 15 03:44:08 AM UTC 24 |
| Finished | Oct 15 03:57:01 AM UTC 24 |
| Peak memory | 382292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168542381 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.1685423819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3808531239 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 500143513 ps |
| CPU time | 28.37 seconds |
| Started | Oct 15 03:44:07 AM UTC 24 |
| Finished | Oct 15 03:44:36 AM UTC 24 |
| Peak memory | 236260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808531239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3808531239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1836261253 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 13863765642 ps |
| CPU time | 426.78 seconds |
| Started | Oct 15 03:43:14 AM UTC 24 |
| Finished | Oct 15 03:50:26 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836261253 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1836261253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.870805686 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 240117854 ps |
| CPU time | 8.26 seconds |
| Started | Oct 15 03:43:34 AM UTC 24 |
| Finished | Oct 15 03:43:43 AM UTC 24 |
| Peak memory | 244864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 870805686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_th roughput_w_partial_write.870805686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3209727295 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 12219511159 ps |
| CPU time | 760.4 seconds |
| Started | Oct 15 03:44:57 AM UTC 24 |
| Finished | Oct 15 03:57:46 AM UTC 24 |
| Peak memory | 369928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209727295 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during _key_req.3209727295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.4294225330 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 18226927 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 03:45:26 AM UTC 24 |
| Finished | Oct 15 03:45:28 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294225330 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.4294225330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.654932023 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 5122370406 ps |
| CPU time | 49.77 seconds |
| Started | Oct 15 03:44:34 AM UTC 24 |
| Finished | Oct 15 03:45:25 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654932023 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.654932023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2452564446 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 36405075075 ps |
| CPU time | 682.14 seconds |
| Started | Oct 15 03:44:59 AM UTC 24 |
| Finished | Oct 15 03:56:29 AM UTC 24 |
| Peak memory | 380152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452564446 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.2452564446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2062740794 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 416811979 ps |
| CPU time | 6.73 seconds |
| Started | Oct 15 03:44:56 AM UTC 24 |
| Finished | Oct 15 03:45:03 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062740794 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.2062740794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1615999605 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 314972028 ps |
| CPU time | 5.06 seconds |
| Started | Oct 15 03:44:48 AM UTC 24 |
| Finished | Oct 15 03:44:54 AM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 615999605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ma x_throughput.1615999605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2267115707 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 671502606 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 03:45:15 AM UTC 24 |
| Finished | Oct 15 03:45:19 AM UTC 24 |
| Peak memory | 221540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267115707 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.2267115707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2292423359 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 549286578 ps |
| CPU time | 13.55 seconds |
| Started | Oct 15 03:45:07 AM UTC 24 |
| Finished | Oct 15 03:45:22 AM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292423359 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.2292423359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.292615574 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 15942924776 ps |
| CPU time | 255.29 seconds |
| Started | Oct 15 03:44:33 AM UTC 24 |
| Finished | Oct 15 03:48:52 AM UTC 24 |
| Peak memory | 382032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292615574 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.292615574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.3910473856 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 152195576 ps |
| CPU time | 2.15 seconds |
| Started | Oct 15 03:44:37 AM UTC 24 |
| Finished | Oct 15 03:44:40 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910473856 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.3910473856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1659641720 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 49709863877 ps |
| CPU time | 305.97 seconds |
| Started | Oct 15 03:44:41 AM UTC 24 |
| Finished | Oct 15 03:49:51 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659641720 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc ess_b2b.1659641720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2569227531 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 28782466 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 03:45:04 AM UTC 24 |
| Finished | Oct 15 03:45:06 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569227531 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2569227531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3510368822 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 94898312 ps |
| CPU time | 1.29 seconds |
| Started | Oct 15 03:45:21 AM UTC 24 |
| Finished | Oct 15 03:45:23 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510368822 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_readback_err.3510368822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.3052799587 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 52848755761 ps |
| CPU time | 441.12 seconds |
| Started | Oct 15 03:45:04 AM UTC 24 |
| Finished | Oct 15 03:52:31 AM UTC 24 |
| Peak memory | 376076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052799587 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3052799587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.421005180 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 787982884 ps |
| CPU time | 16.37 seconds |
| Started | Oct 15 03:44:30 AM UTC 24 |
| Finished | Oct 15 03:44:48 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421005180 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.421005180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3713086993 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 65768910049 ps |
| CPU time | 3956.7 seconds |
| Started | Oct 15 03:45:24 AM UTC 24 |
| Finished | Oct 15 04:52:01 AM UTC 24 |
| Peak memory | 385676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371308699 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.3713086993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3642269433 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 7997534010 ps |
| CPU time | 195.9 seconds |
| Started | Oct 15 03:44:36 AM UTC 24 |
| Finished | Oct 15 03:47:55 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642269433 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.3642269433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3253684663 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 321700256 ps |
| CPU time | 6.48 seconds |
| Started | Oct 15 03:44:48 AM UTC 24 |
| Finished | Oct 15 03:44:56 AM UTC 24 |
| Peak memory | 234612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3253684663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t hroughput_w_partial_write.3253684663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.596637955 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 834427524 ps |
| CPU time | 212.36 seconds |
| Started | Oct 15 03:46:35 AM UTC 24 |
| Finished | Oct 15 03:50:10 AM UTC 24 |
| Peak memory | 379964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596637955 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during_ key_req.596637955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2356760768 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 13817133 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:47:19 AM UTC 24 |
| Finished | Oct 15 03:47:21 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356760768 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2356760768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1107197489 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 8439557623 ps |
| CPU time | 83.27 seconds |
| Started | Oct 15 03:45:36 AM UTC 24 |
| Finished | Oct 15 03:47:01 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107197489 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.1107197489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.4132895283 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 14868634725 ps |
| CPU time | 1008.42 seconds |
| Started | Oct 15 03:46:42 AM UTC 24 |
| Finished | Oct 15 04:03:43 AM UTC 24 |
| Peak memory | 382092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132895283 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.4132895283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3221755874 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 263509035 ps |
| CPU time | 4.55 seconds |
| Started | Oct 15 03:46:28 AM UTC 24 |
| Finished | Oct 15 03:46:34 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221755874 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.3221755874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1242363920 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 558119112 ps |
| CPU time | 6.98 seconds |
| Started | Oct 15 03:46:06 AM UTC 24 |
| Finished | Oct 15 03:46:15 AM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 242363920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma x_throughput.1242363920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4071627792 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 136572077 ps |
| CPU time | 3.91 seconds |
| Started | Oct 15 03:47:13 AM UTC 24 |
| Finished | Oct 15 03:47:18 AM UTC 24 |
| Peak memory | 221716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071627792 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.4071627792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1986775001 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 154996053 ps |
| CPU time | 5.93 seconds |
| Started | Oct 15 03:47:07 AM UTC 24 |
| Finished | Oct 15 03:47:14 AM UTC 24 |
| Peak memory | 221716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986775001 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1986775001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.938719096 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 9405080159 ps |
| CPU time | 1113.99 seconds |
| Started | Oct 15 03:45:33 AM UTC 24 |
| Finished | Oct 15 04:04:19 AM UTC 24 |
| Peak memory | 382324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938719096 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.938719096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3277750977 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 616536421 ps |
| CPU time | 26.95 seconds |
| Started | Oct 15 03:45:58 AM UTC 24 |
| Finished | Oct 15 03:46:26 AM UTC 24 |
| Peak memory | 283972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277750977 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3277750977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3403105577 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5964015375 ps |
| CPU time | 230.11 seconds |
| Started | Oct 15 03:46:01 AM UTC 24 |
| Finished | Oct 15 03:49:55 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403105577 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc ess_b2b.3403105577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1641909008 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 48458176 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 03:47:04 AM UTC 24 |
| Finished | Oct 15 03:47:06 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641909008 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1641909008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_readback_err.497587600 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 28483588 ps |
| CPU time | 1.33 seconds |
| Started | Oct 15 03:47:13 AM UTC 24 |
| Finished | Oct 15 03:47:16 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497587600 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_readback_err.497587600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.2281642872 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 10907416222 ps |
| CPU time | 1031.35 seconds |
| Started | Oct 15 03:47:02 AM UTC 24 |
| Finished | Oct 15 04:04:25 AM UTC 24 |
| Peak memory | 378040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281642872 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2281642872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2278595130 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 563803939 ps |
| CPU time | 69.63 seconds |
| Started | Oct 15 03:45:29 AM UTC 24 |
| Finished | Oct 15 03:46:41 AM UTC 24 |
| Peak memory | 376012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278595130 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2278595130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.3342701741 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 5208574059 ps |
| CPU time | 522.01 seconds |
| Started | Oct 15 03:47:17 AM UTC 24 |
| Finished | Oct 15 03:56:05 AM UTC 24 |
| Peak memory | 369936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334270174 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.3342701741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.4083175753 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1635176760 ps |
| CPU time | 198.41 seconds |
| Started | Oct 15 03:45:51 AM UTC 24 |
| Finished | Oct 15 03:49:13 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083175753 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.4083175753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2961712117 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 287408758 ps |
| CPU time | 102.54 seconds |
| Started | Oct 15 03:46:16 AM UTC 24 |
| Finished | Oct 15 03:48:00 AM UTC 24 |
| Peak memory | 375936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2961712117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t hroughput_w_partial_write.2961712117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1022750592 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 960360947 ps |
| CPU time | 92.25 seconds |
| Started | Oct 15 03:48:54 AM UTC 24 |
| Finished | Oct 15 03:50:28 AM UTC 24 |
| Peak memory | 369860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022750592 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during _key_req.1022750592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.4193442208 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 22347984 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 03:49:08 AM UTC 24 |
| Finished | Oct 15 03:49:11 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193442208 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.4193442208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3384252799 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 8127977945 ps |
| CPU time | 64.54 seconds |
| Started | Oct 15 03:47:41 AM UTC 24 |
| Finished | Oct 15 03:48:48 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384252799 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.3384252799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.1056327485 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 69932322249 ps |
| CPU time | 806.72 seconds |
| Started | Oct 15 03:48:54 AM UTC 24 |
| Finished | Oct 15 04:02:30 AM UTC 24 |
| Peak memory | 380148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056327485 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.1056327485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1593020450 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1418306043 ps |
| CPU time | 10.93 seconds |
| Started | Oct 15 03:48:48 AM UTC 24 |
| Finished | Oct 15 03:49:00 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593020450 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.1593020450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2782121744 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 157196042 ps |
| CPU time | 20.36 seconds |
| Started | Oct 15 03:48:33 AM UTC 24 |
| Finished | Oct 15 03:48:55 AM UTC 24 |
| Peak memory | 285880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 782121744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ma x_throughput.2782121744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2343432092 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 99445236 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 03:49:02 AM UTC 24 |
| Finished | Oct 15 03:49:07 AM UTC 24 |
| Peak memory | 221592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343432092 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.2343432092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.131828274 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 244889784 ps |
| CPU time | 8.89 seconds |
| Started | Oct 15 03:48:58 AM UTC 24 |
| Finished | Oct 15 03:49:08 AM UTC 24 |
| Peak memory | 221544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131828274 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.131828274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3094940615 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 201098818998 ps |
| CPU time | 1102.44 seconds |
| Started | Oct 15 03:47:29 AM UTC 24 |
| Finished | Oct 15 04:06:04 AM UTC 24 |
| Peak memory | 382160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094940615 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3094940615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.4251148815 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3508174926 ps |
| CPU time | 29.52 seconds |
| Started | Oct 15 03:48:02 AM UTC 24 |
| Finished | Oct 15 03:48:32 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251148815 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.4251148815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.182131139 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 38647811565 ps |
| CPU time | 277.63 seconds |
| Started | Oct 15 03:48:26 AM UTC 24 |
| Finished | Oct 15 03:53:07 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182131139 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acce ss_b2b.182131139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3011005552 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 43634956 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 03:48:55 AM UTC 24 |
| Finished | Oct 15 03:48:57 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011005552 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3011005552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_readback_err.2369779514 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 79785179 ps |
| CPU time | 1.44 seconds |
| Started | Oct 15 03:49:02 AM UTC 24 |
| Finished | Oct 15 03:49:04 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369779514 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_readback_err.2369779514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.779562960 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 90272278834 ps |
| CPU time | 1239.26 seconds |
| Started | Oct 15 03:48:54 AM UTC 24 |
| Finished | Oct 15 04:09:46 AM UTC 24 |
| Peak memory | 380176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779562960 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.779562960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.572930881 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1265787013 ps |
| CPU time | 16.52 seconds |
| Started | Oct 15 03:47:22 AM UTC 24 |
| Finished | Oct 15 03:47:40 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572930881 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.572930881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.987455226 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 166099626812 ps |
| CPU time | 2311.39 seconds |
| Started | Oct 15 03:49:07 AM UTC 24 |
| Finished | Oct 15 04:28:02 AM UTC 24 |
| Peak memory | 394028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987455226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.987455226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1650331022 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2957895596 ps |
| CPU time | 78.27 seconds |
| Started | Oct 15 03:49:06 AM UTC 24 |
| Finished | Oct 15 03:50:27 AM UTC 24 |
| Peak memory | 316904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650331022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1650331022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3124964325 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3137075007 ps |
| CPU time | 342.3 seconds |
| Started | Oct 15 03:47:56 AM UTC 24 |
| Finished | Oct 15 03:53:43 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124964325 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.3124964325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.209583675 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 321975526 ps |
| CPU time | 15.4 seconds |
| Started | Oct 15 03:48:36 AM UTC 24 |
| Finished | Oct 15 03:48:53 AM UTC 24 |
| Peak memory | 283836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 209583675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_th roughput_w_partial_write.209583675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.543272575 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 16975644364 ps |
| CPU time | 1088.43 seconds |
| Started | Oct 15 03:50:00 AM UTC 24 |
| Finished | Oct 15 04:08:20 AM UTC 24 |
| Peak memory | 382108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543272575 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_ key_req.543272575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.233231060 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 15621850 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 03:50:31 AM UTC 24 |
| Finished | Oct 15 03:50:33 AM UTC 24 |
| Peak memory | 209964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233231060 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.233231060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.765066187 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4015310820 ps |
| CPU time | 74.59 seconds |
| Started | Oct 15 03:49:14 AM UTC 24 |
| Finished | Oct 15 03:50:30 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765066187 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.765066187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3353236848 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2691120001 ps |
| CPU time | 306.87 seconds |
| Started | Oct 15 03:50:00 AM UTC 24 |
| Finished | Oct 15 03:55:11 AM UTC 24 |
| Peak memory | 376068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353236848 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.3353236848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.805107548 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 114868808 ps |
| CPU time | 2.65 seconds |
| Started | Oct 15 03:49:55 AM UTC 24 |
| Finished | Oct 15 03:49:59 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805107548 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.805107548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2170893310 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 287632695 ps |
| CPU time | 16.82 seconds |
| Started | Oct 15 03:49:41 AM UTC 24 |
| Finished | Oct 15 03:49:59 AM UTC 24 |
| Peak memory | 271472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 170893310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ma x_throughput.2170893310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3289419212 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 115251109 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 03:50:28 AM UTC 24 |
| Finished | Oct 15 03:50:33 AM UTC 24 |
| Peak memory | 221524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289419212 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.3289419212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.4009375374 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 457077438 ps |
| CPU time | 14.34 seconds |
| Started | Oct 15 03:50:14 AM UTC 24 |
| Finished | Oct 15 03:50:30 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009375374 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.4009375374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1032500584 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1342684520 ps |
| CPU time | 472.04 seconds |
| Started | Oct 15 03:49:11 AM UTC 24 |
| Finished | Oct 15 03:57:09 AM UTC 24 |
| Peak memory | 382060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032500584 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.1032500584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.156264674 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 387469562 ps |
| CPU time | 11.26 seconds |
| Started | Oct 15 03:49:28 AM UTC 24 |
| Finished | Oct 15 03:49:40 AM UTC 24 |
| Peak memory | 253120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156264674 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.156264674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3398376704 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 12479556273 ps |
| CPU time | 221.29 seconds |
| Started | Oct 15 03:49:37 AM UTC 24 |
| Finished | Oct 15 03:53:22 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398376704 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acc ess_b2b.3398376704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2737187576 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 30407899 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:50:11 AM UTC 24 |
| Finished | Oct 15 03:50:13 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737187576 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2737187576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_readback_err.3909605864 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 55617299 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 03:50:28 AM UTC 24 |
| Finished | Oct 15 03:50:30 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909605864 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_readback_err.3909605864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.583665541 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3487004681 ps |
| CPU time | 1243.83 seconds |
| Started | Oct 15 03:50:01 AM UTC 24 |
| Finished | Oct 15 04:10:58 AM UTC 24 |
| Peak memory | 382224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583665541 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.583665541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.3027017080 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 369489606 ps |
| CPU time | 25.03 seconds |
| Started | Oct 15 03:49:09 AM UTC 24 |
| Finished | Oct 15 03:49:36 AM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027017080 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3027017080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.4200092673 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 192181972374 ps |
| CPU time | 1862.64 seconds |
| Started | Oct 15 03:50:31 AM UTC 24 |
| Finished | Oct 15 04:21:54 AM UTC 24 |
| Peak memory | 383928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420009267 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.4200092673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.777227238 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 7464442666 ps |
| CPU time | 327.76 seconds |
| Started | Oct 15 03:50:29 AM UTC 24 |
| Finished | Oct 15 03:56:01 AM UTC 24 |
| Peak memory | 382272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777227238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.777227238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2199038025 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3368012869 ps |
| CPU time | 250.29 seconds |
| Started | Oct 15 03:49:27 AM UTC 24 |
| Finished | Oct 15 03:53:41 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199038025 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2199038025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2778952873 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 136928838 ps |
| CPU time | 76.33 seconds |
| Started | Oct 15 03:49:52 AM UTC 24 |
| Finished | Oct 15 03:51:10 AM UTC 24 |
| Peak memory | 357560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2778952873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t hroughput_w_partial_write.2778952873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1564846411 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 14596694013 ps |
| CPU time | 1181.93 seconds |
| Started | Oct 15 03:51:27 AM UTC 24 |
| Finished | Oct 15 04:11:21 AM UTC 24 |
| Peak memory | 384200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564846411 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during _key_req.1564846411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1829796995 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 36667060 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 03:52:34 AM UTC 24 |
| Finished | Oct 15 03:52:36 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829796995 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1829796995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1078992853 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3972834328 ps |
| CPU time | 99.43 seconds |
| Started | Oct 15 03:50:34 AM UTC 24 |
| Finished | Oct 15 03:52:16 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078992853 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.1078992853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.497901605 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 55543196058 ps |
| CPU time | 1790.41 seconds |
| Started | Oct 15 03:52:08 AM UTC 24 |
| Finished | Oct 15 04:22:19 AM UTC 24 |
| Peak memory | 382448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497901605 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.497901605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.476143058 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 966152351 ps |
| CPU time | 7.97 seconds |
| Started | Oct 15 03:51:16 AM UTC 24 |
| Finished | Oct 15 03:51:25 AM UTC 24 |
| Peak memory | 225336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476143058 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.476143058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.4215872430 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2598133427 ps |
| CPU time | 138.14 seconds |
| Started | Oct 15 03:51:14 AM UTC 24 |
| Finished | Oct 15 03:53:35 AM UTC 24 |
| Peak memory | 378108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 215872430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ma x_throughput.4215872430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3344705356 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 97994056 ps |
| CPU time | 6.85 seconds |
| Started | Oct 15 03:52:17 AM UTC 24 |
| Finished | Oct 15 03:52:25 AM UTC 24 |
| Peak memory | 221572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344705356 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.3344705356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1177016 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1842651613 ps |
| CPU time | 14.11 seconds |
| Started | Oct 15 03:52:17 AM UTC 24 |
| Finished | Oct 15 03:52:32 AM UTC 24 |
| Peak memory | 221468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177016 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.1177016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1982084335 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 33474090186 ps |
| CPU time | 1800.4 seconds |
| Started | Oct 15 03:50:34 AM UTC 24 |
| Finished | Oct 15 04:20:55 AM UTC 24 |
| Peak memory | 378128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982084335 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.1982084335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2114954229 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 260911368 ps |
| CPU time | 20.33 seconds |
| Started | Oct 15 03:50:52 AM UTC 24 |
| Finished | Oct 15 03:51:13 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114954229 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.2114954229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3884754307 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3008411460 ps |
| CPU time | 267.5 seconds |
| Started | Oct 15 03:51:12 AM UTC 24 |
| Finished | Oct 15 03:55:43 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884754307 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acc ess_b2b.3884754307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1630066874 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 36742562 ps |
| CPU time | 1.34 seconds |
| Started | Oct 15 03:52:14 AM UTC 24 |
| Finished | Oct 15 03:52:16 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630066874 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1630066874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_readback_err.1330648573 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 71508464 ps |
| CPU time | 1.56 seconds |
| Started | Oct 15 03:52:26 AM UTC 24 |
| Finished | Oct 15 03:52:29 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330648573 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_readback_err.1330648573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.3316696084 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 61344948379 ps |
| CPU time | 717.08 seconds |
| Started | Oct 15 03:52:13 AM UTC 24 |
| Finished | Oct 15 04:04:18 AM UTC 24 |
| Peak memory | 382304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316696084 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3316696084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1162622545 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 231621094 ps |
| CPU time | 18.88 seconds |
| Started | Oct 15 03:50:31 AM UTC 24 |
| Finished | Oct 15 03:50:51 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162622545 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1162622545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.4251200439 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 192133285821 ps |
| CPU time | 3561.86 seconds |
| Started | Oct 15 03:52:31 AM UTC 24 |
| Finished | Oct 15 04:52:29 AM UTC 24 |
| Peak memory | 391928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425120043 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.4251200439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2799415954 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3685426657 ps |
| CPU time | 41.23 seconds |
| Started | Oct 15 03:52:30 AM UTC 24 |
| Finished | Oct 15 03:53:13 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799415954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2799415954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.2483683675 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3106381986 ps |
| CPU time | 165.09 seconds |
| Started | Oct 15 03:50:37 AM UTC 24 |
| Finished | Oct 15 03:53:26 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483683675 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.2483683675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3901384742 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 155094811 ps |
| CPU time | 53.3 seconds |
| Started | Oct 15 03:51:16 AM UTC 24 |
| Finished | Oct 15 03:52:11 AM UTC 24 |
| Peak memory | 348992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3901384742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t hroughput_w_partial_write.3901384742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4257723317 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 5613704237 ps |
| CPU time | 542.84 seconds |
| Started | Oct 15 03:53:40 AM UTC 24 |
| Finished | Oct 15 04:02:49 AM UTC 24 |
| Peak memory | 376096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257723317 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.4257723317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.267651090 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 12109710 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 03:54:04 AM UTC 24 |
| Finished | Oct 15 03:54:06 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267651090 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.267651090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3264156078 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 10897145637 ps |
| CPU time | 59.31 seconds |
| Started | Oct 15 03:53:08 AM UTC 24 |
| Finished | Oct 15 03:54:09 AM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264156078 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.3264156078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3428461594 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 931131920 ps |
| CPU time | 98.77 seconds |
| Started | Oct 15 03:53:42 AM UTC 24 |
| Finished | Oct 15 03:55:23 AM UTC 24 |
| Peak memory | 371896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428461594 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3428461594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1039462197 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 783525918 ps |
| CPU time | 4.3 seconds |
| Started | Oct 15 03:53:37 AM UTC 24 |
| Finished | Oct 15 03:53:42 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039462197 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.1039462197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2349489376 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 242497723 ps |
| CPU time | 9.33 seconds |
| Started | Oct 15 03:53:34 AM UTC 24 |
| Finished | Oct 15 03:53:44 AM UTC 24 |
| Peak memory | 261304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 349489376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma x_throughput.2349489376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1149952888 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 347748805 ps |
| CPU time | 3.93 seconds |
| Started | Oct 15 03:53:48 AM UTC 24 |
| Finished | Oct 15 03:53:53 AM UTC 24 |
| Peak memory | 221600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149952888 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.1149952888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.4196302356 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 849803777 ps |
| CPU time | 9.03 seconds |
| Started | Oct 15 03:53:44 AM UTC 24 |
| Finished | Oct 15 03:53:54 AM UTC 24 |
| Peak memory | 221560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196302356 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.4196302356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.779689170 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 6874005049 ps |
| CPU time | 520.32 seconds |
| Started | Oct 15 03:52:54 AM UTC 24 |
| Finished | Oct 15 04:01:40 AM UTC 24 |
| Peak memory | 361668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779689170 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.779689170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1417131813 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 102004848 ps |
| CPU time | 15.19 seconds |
| Started | Oct 15 03:53:22 AM UTC 24 |
| Finished | Oct 15 03:53:39 AM UTC 24 |
| Peak memory | 271548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417131813 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.1417131813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1632630549 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 23477236059 ps |
| CPU time | 216.71 seconds |
| Started | Oct 15 03:53:26 AM UTC 24 |
| Finished | Oct 15 03:57:07 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632630549 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc ess_b2b.1632630549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1179920757 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 29279702 ps |
| CPU time | 1.33 seconds |
| Started | Oct 15 03:53:44 AM UTC 24 |
| Finished | Oct 15 03:53:47 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179920757 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1179920757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1414233091 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 103637850 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 03:53:54 AM UTC 24 |
| Finished | Oct 15 03:53:57 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414233091 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_readback_err.1414233091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.341452299 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 14576974291 ps |
| CPU time | 1084.28 seconds |
| Started | Oct 15 03:53:43 AM UTC 24 |
| Finished | Oct 15 04:12:00 AM UTC 24 |
| Peak memory | 378096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341452299 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.341452299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.1756146349 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1801395442 ps |
| CPU time | 14.96 seconds |
| Started | Oct 15 03:52:37 AM UTC 24 |
| Finished | Oct 15 03:52:53 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756146349 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1756146349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1832491479 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 24820412242 ps |
| CPU time | 2996.71 seconds |
| Started | Oct 15 03:53:58 AM UTC 24 |
| Finished | Oct 15 04:44:27 AM UTC 24 |
| Peak memory | 385772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183249147 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.1832491479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1781552510 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 181474547 ps |
| CPU time | 14.38 seconds |
| Started | Oct 15 03:53:56 AM UTC 24 |
| Finished | Oct 15 03:54:12 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781552510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1781552510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2725181756 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 13997682939 ps |
| CPU time | 218.43 seconds |
| Started | Oct 15 03:53:14 AM UTC 24 |
| Finished | Oct 15 03:56:56 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725181756 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.2725181756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.605000892 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 92064014 ps |
| CPU time | 26.35 seconds |
| Started | Oct 15 03:53:36 AM UTC 24 |
| Finished | Oct 15 03:54:03 AM UTC 24 |
| Peak memory | 287860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 605000892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_th roughput_w_partial_write.605000892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2374469959 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6834134803 ps |
| CPU time | 281.82 seconds |
| Started | Oct 15 03:07:56 AM UTC 24 |
| Finished | Oct 15 03:12:43 AM UTC 24 |
| Peak memory | 361660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374469959 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_ key_req.2374469959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.222426579 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 82545105 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 03:09:21 AM UTC 24 |
| Finished | Oct 15 03:09:23 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222426579 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.222426579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3783979071 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2831465001 ps |
| CPU time | 66.7 seconds |
| Started | Oct 15 03:06:27 AM UTC 24 |
| Finished | Oct 15 03:07:35 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783979071 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3783979071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2334977173 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1728033474 ps |
| CPU time | 9.81 seconds |
| Started | Oct 15 03:07:55 AM UTC 24 |
| Finished | Oct 15 03:08:06 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334977173 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.2334977173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2427681927 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 101171708 ps |
| CPU time | 41.9 seconds |
| Started | Oct 15 03:07:36 AM UTC 24 |
| Finished | Oct 15 03:08:19 AM UTC 24 |
| Peak memory | 316600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 427681927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max _throughput.2427681927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1488757112 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 753087757 ps |
| CPU time | 5.83 seconds |
| Started | Oct 15 03:08:20 AM UTC 24 |
| Finished | Oct 15 03:08:27 AM UTC 24 |
| Peak memory | 221772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488757112 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1488757112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3763392540 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1883315644 ps |
| CPU time | 13.81 seconds |
| Started | Oct 15 03:08:18 AM UTC 24 |
| Finished | Oct 15 03:08:33 AM UTC 24 |
| Peak memory | 221772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763392540 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.3763392540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1350855831 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6914090026 ps |
| CPU time | 809.32 seconds |
| Started | Oct 15 03:06:21 AM UTC 24 |
| Finished | Oct 15 03:20:00 AM UTC 24 |
| Peak memory | 384172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350855831 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.1350855831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2417330430 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 59598449 ps |
| CPU time | 2.29 seconds |
| Started | Oct 15 03:06:56 AM UTC 24 |
| Finished | Oct 15 03:06:59 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417330430 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.2417330430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1017295965 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 12701035642 ps |
| CPU time | 393.22 seconds |
| Started | Oct 15 03:07:00 AM UTC 24 |
| Finished | Oct 15 03:13:39 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017295965 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce ss_b2b.1017295965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1550215546 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 31471513 ps |
| CPU time | 1.35 seconds |
| Started | Oct 15 03:08:15 AM UTC 24 |
| Finished | Oct 15 03:08:17 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550215546 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1550215546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3165884415 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 51438974 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 03:08:28 AM UTC 24 |
| Finished | Oct 15 03:08:30 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165884415 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_readback_err.3165884415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1252998239 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 13431817831 ps |
| CPU time | 1254.41 seconds |
| Started | Oct 15 03:08:15 AM UTC 24 |
| Finished | Oct 15 03:29:22 AM UTC 24 |
| Peak memory | 380172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252998239 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1252998239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.541996749 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 448678180 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 03:09:16 AM UTC 24 |
| Finished | Oct 15 03:09:20 AM UTC 24 |
| Peak memory | 247572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541996749 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.541996749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.4122225139 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1067309379 ps |
| CPU time | 19.86 seconds |
| Started | Oct 15 03:06:19 AM UTC 24 |
| Finished | Oct 15 03:06:41 AM UTC 24 |
| Peak memory | 265608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122225139 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.4122225139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3417823191 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 384307117755 ps |
| CPU time | 6691.57 seconds |
| Started | Oct 15 03:08:34 AM UTC 24 |
| Finished | Oct 15 05:01:11 AM UTC 24 |
| Peak memory | 385844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341782319 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3417823191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2909040747 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 921894634 ps |
| CPU time | 92.5 seconds |
| Started | Oct 15 03:08:31 AM UTC 24 |
| Finished | Oct 15 03:10:05 AM UTC 24 |
| Peak memory | 355664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909040747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2909040747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3241746950 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 6645365316 ps |
| CPU time | 279.56 seconds |
| Started | Oct 15 03:06:42 AM UTC 24 |
| Finished | Oct 15 03:11:26 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241746950 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3241746950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.2241741829 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 52179598 ps |
| CPU time | 4.99 seconds |
| Started | Oct 15 03:07:48 AM UTC 24 |
| Finished | Oct 15 03:07:54 AM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2241741829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th roughput_w_partial_write.2241741829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3737603627 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 5992937934 ps |
| CPU time | 472.31 seconds |
| Started | Oct 15 03:54:52 AM UTC 24 |
| Finished | Oct 15 04:02:50 AM UTC 24 |
| Peak memory | 384264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737603627 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during _key_req.3737603627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2884967754 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 56238611 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 03:55:30 AM UTC 24 |
| Finished | Oct 15 03:55:32 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884967754 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.2884967754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.3391587646 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1711572113 ps |
| CPU time | 34.4 seconds |
| Started | Oct 15 03:54:13 AM UTC 24 |
| Finished | Oct 15 03:54:49 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391587646 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.3391587646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2765919091 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2758619504 ps |
| CPU time | 72.93 seconds |
| Started | Oct 15 03:55:01 AM UTC 24 |
| Finished | Oct 15 03:56:16 AM UTC 24 |
| Peak memory | 370036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765919091 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.2765919091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2871321576 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2130761170 ps |
| CPU time | 8.8 seconds |
| Started | Oct 15 03:54:50 AM UTC 24 |
| Finished | Oct 15 03:54:59 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871321576 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.2871321576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3951648665 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 225273728 ps |
| CPU time | 92.69 seconds |
| Started | Oct 15 03:54:48 AM UTC 24 |
| Finished | Oct 15 03:56:23 AM UTC 24 |
| Peak memory | 367668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 951648665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma x_throughput.3951648665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2745723221 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 126250344 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 03:55:20 AM UTC 24 |
| Finished | Oct 15 03:55:25 AM UTC 24 |
| Peak memory | 221656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745723221 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.2745723221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3182735443 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 181976452 ps |
| CPU time | 11.94 seconds |
| Started | Oct 15 03:55:16 AM UTC 24 |
| Finished | Oct 15 03:55:29 AM UTC 24 |
| Peak memory | 221672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182735443 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.3182735443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3511153463 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 83987720097 ps |
| CPU time | 1384.2 seconds |
| Started | Oct 15 03:54:10 AM UTC 24 |
| Finished | Oct 15 04:17:28 AM UTC 24 |
| Peak memory | 380160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511153463 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.3511153463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3654835616 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2407428661 ps |
| CPU time | 22.17 seconds |
| Started | Oct 15 03:54:27 AM UTC 24 |
| Finished | Oct 15 03:54:50 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654835616 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.3654835616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1699212087 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 5984450208 ps |
| CPU time | 467.21 seconds |
| Started | Oct 15 03:54:35 AM UTC 24 |
| Finished | Oct 15 04:02:29 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699212087 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acc ess_b2b.1699212087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2278552254 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 29729541 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 03:55:13 AM UTC 24 |
| Finished | Oct 15 03:55:15 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278552254 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2278552254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_readback_err.1080254855 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 59149524 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 03:55:24 AM UTC 24 |
| Finished | Oct 15 03:55:26 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080254855 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_readback_err.1080254855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.3025602631 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 48313315581 ps |
| CPU time | 599.3 seconds |
| Started | Oct 15 03:55:12 AM UTC 24 |
| Finished | Oct 15 04:05:19 AM UTC 24 |
| Peak memory | 372068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025602631 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3025602631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3253800578 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1035795764 ps |
| CPU time | 17.1 seconds |
| Started | Oct 15 03:54:07 AM UTC 24 |
| Finished | Oct 15 03:54:26 AM UTC 24 |
| Peak memory | 257164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253800578 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3253800578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.485899167 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 162127035965 ps |
| CPU time | 3019.02 seconds |
| Started | Oct 15 03:55:27 AM UTC 24 |
| Finished | Oct 15 04:46:18 AM UTC 24 |
| Peak memory | 387832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485899167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.485899167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1480670103 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 15244001548 ps |
| CPU time | 485.61 seconds |
| Started | Oct 15 03:55:27 AM UTC 24 |
| Finished | Oct 15 04:03:39 AM UTC 24 |
| Peak memory | 374084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480670103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1480670103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3216508249 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2518026744 ps |
| CPU time | 145.29 seconds |
| Started | Oct 15 03:54:24 AM UTC 24 |
| Finished | Oct 15 03:56:52 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216508249 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.3216508249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3859014182 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 418099974 ps |
| CPU time | 21.55 seconds |
| Started | Oct 15 03:54:50 AM UTC 24 |
| Finished | Oct 15 03:55:12 AM UTC 24 |
| Peak memory | 304372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3859014182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_t hroughput_w_partial_write.3859014182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1838669365 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 9606908238 ps |
| CPU time | 454.52 seconds |
| Started | Oct 15 03:56:30 AM UTC 24 |
| Finished | Oct 15 04:04:10 AM UTC 24 |
| Peak memory | 374148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838669365 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during _key_req.1838669365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.1636132171 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 12873136 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 03:57:03 AM UTC 24 |
| Finished | Oct 15 03:57:05 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636132171 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.1636132171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3713246268 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 673607814 ps |
| CPU time | 52.87 seconds |
| Started | Oct 15 03:55:50 AM UTC 24 |
| Finished | Oct 15 03:56:45 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713246268 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.3713246268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1205768745 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3254986185 ps |
| CPU time | 466 seconds |
| Started | Oct 15 03:56:39 AM UTC 24 |
| Finished | Oct 15 04:04:31 AM UTC 24 |
| Peak memory | 371836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205768745 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.1205768745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.1464169154 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1494483387 ps |
| CPU time | 12.34 seconds |
| Started | Oct 15 03:56:24 AM UTC 24 |
| Finished | Oct 15 03:56:38 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464169154 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.1464169154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.4049253288 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 343404844 ps |
| CPU time | 32.63 seconds |
| Started | Oct 15 03:56:16 AM UTC 24 |
| Finished | Oct 15 03:56:50 AM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 049253288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma x_throughput.4049253288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1392920591 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 93052073 ps |
| CPU time | 6.34 seconds |
| Started | Oct 15 03:56:54 AM UTC 24 |
| Finished | Oct 15 03:57:02 AM UTC 24 |
| Peak memory | 221840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392920591 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1392920591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2073063145 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 253802323 ps |
| CPU time | 11.21 seconds |
| Started | Oct 15 03:56:53 AM UTC 24 |
| Finished | Oct 15 03:57:05 AM UTC 24 |
| Peak memory | 221648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073063145 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.2073063145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1351690339 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 7647975794 ps |
| CPU time | 345.61 seconds |
| Started | Oct 15 03:55:44 AM UTC 24 |
| Finished | Oct 15 04:01:35 AM UTC 24 |
| Peak memory | 372088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351690339 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.1351690339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1676547071 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 738208480 ps |
| CPU time | 12.68 seconds |
| Started | Oct 15 03:56:02 AM UTC 24 |
| Finished | Oct 15 03:56:16 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676547071 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1676547071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1192459998 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 17548398022 ps |
| CPU time | 491.05 seconds |
| Started | Oct 15 03:56:06 AM UTC 24 |
| Finished | Oct 15 04:04:23 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192459998 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc ess_b2b.1192459998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3731485983 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 190474255 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 03:56:51 AM UTC 24 |
| Finished | Oct 15 03:56:53 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731485983 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3731485983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_readback_err.220892990 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 30611834 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 03:56:57 AM UTC 24 |
| Finished | Oct 15 03:57:00 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220892990 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_readback_err.220892990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.1674836077 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4290909944 ps |
| CPU time | 728.98 seconds |
| Started | Oct 15 03:56:46 AM UTC 24 |
| Finished | Oct 15 04:09:03 AM UTC 24 |
| Peak memory | 375996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674836077 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1674836077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2117295458 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 754241606 ps |
| CPU time | 15.76 seconds |
| Started | Oct 15 03:55:33 AM UTC 24 |
| Finished | Oct 15 03:55:50 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117295458 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2117295458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3537037951 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 44379825886 ps |
| CPU time | 3792.25 seconds |
| Started | Oct 15 03:57:02 AM UTC 24 |
| Finished | Oct 15 05:00:52 AM UTC 24 |
| Peak memory | 385980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353703795 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.3537037951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.251968354 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1869242552 ps |
| CPU time | 274.08 seconds |
| Started | Oct 15 03:57:01 AM UTC 24 |
| Finished | Oct 15 04:01:38 AM UTC 24 |
| Peak memory | 374184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251968354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.251968354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3621995587 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 6163309578 ps |
| CPU time | 201.2 seconds |
| Started | Oct 15 03:55:52 AM UTC 24 |
| Finished | Oct 15 03:59:16 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621995587 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.3621995587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2965655212 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 678044131 ps |
| CPU time | 84.39 seconds |
| Started | Oct 15 03:56:16 AM UTC 24 |
| Finished | Oct 15 03:57:42 AM UTC 24 |
| Peak memory | 373880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2965655212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t hroughput_w_partial_write.2965655212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2480897537 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 15746979476 ps |
| CPU time | 746.2 seconds |
| Started | Oct 15 03:57:45 AM UTC 24 |
| Finished | Oct 15 04:10:21 AM UTC 24 |
| Peak memory | 367876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480897537 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.2480897537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2006000110 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 36339270 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:59:17 AM UTC 24 |
| Finished | Oct 15 03:59:19 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006000110 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2006000110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.3366971873 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2068847733 ps |
| CPU time | 35.56 seconds |
| Started | Oct 15 03:57:07 AM UTC 24 |
| Finished | Oct 15 03:57:44 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366971873 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.3366971873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.474744412 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 35489781235 ps |
| CPU time | 645.15 seconds |
| Started | Oct 15 03:57:46 AM UTC 24 |
| Finished | Oct 15 04:08:39 AM UTC 24 |
| Peak memory | 384376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474744412 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.474744412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1569660704 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 249751053 ps |
| CPU time | 3.98 seconds |
| Started | Oct 15 03:57:43 AM UTC 24 |
| Finished | Oct 15 03:57:48 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569660704 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.1569660704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3652079661 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 87886956 ps |
| CPU time | 18.79 seconds |
| Started | Oct 15 03:57:33 AM UTC 24 |
| Finished | Oct 15 03:57:53 AM UTC 24 |
| Peak memory | 285884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 652079661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma x_throughput.3652079661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2892424679 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 155182284 ps |
| CPU time | 6.39 seconds |
| Started | Oct 15 03:58:06 AM UTC 24 |
| Finished | Oct 15 03:58:14 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892424679 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2892424679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2145580659 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 338077995 ps |
| CPU time | 7.54 seconds |
| Started | Oct 15 03:57:57 AM UTC 24 |
| Finished | Oct 15 03:58:05 AM UTC 24 |
| Peak memory | 221536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145580659 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.2145580659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1138360467 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 23421450673 ps |
| CPU time | 330.67 seconds |
| Started | Oct 15 03:57:06 AM UTC 24 |
| Finished | Oct 15 04:02:41 AM UTC 24 |
| Peak memory | 361780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138360467 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.1138360467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1005510408 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1647966230 ps |
| CPU time | 11.56 seconds |
| Started | Oct 15 03:57:13 AM UTC 24 |
| Finished | Oct 15 03:57:26 AM UTC 24 |
| Peak memory | 240692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005510408 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1005510408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.220449765 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 5086143906 ps |
| CPU time | 438.07 seconds |
| Started | Oct 15 03:57:27 AM UTC 24 |
| Finished | Oct 15 04:04:52 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220449765 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acce ss_b2b.220449765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2820864343 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 53295717 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 03:57:54 AM UTC 24 |
| Finished | Oct 15 03:57:56 AM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820864343 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2820864343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3475891442 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 32424408 ps |
| CPU time | 1.62 seconds |
| Started | Oct 15 03:58:14 AM UTC 24 |
| Finished | Oct 15 03:58:17 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475891442 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_readback_err.3475891442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.3708969119 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2652795397 ps |
| CPU time | 133.86 seconds |
| Started | Oct 15 03:57:50 AM UTC 24 |
| Finished | Oct 15 04:00:06 AM UTC 24 |
| Peak memory | 382344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708969119 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3708969119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.40529524 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 247510590 ps |
| CPU time | 5.74 seconds |
| Started | Oct 15 03:57:06 AM UTC 24 |
| Finished | Oct 15 03:57:13 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40529524 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.40529524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1998107919 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3400133548 ps |
| CPU time | 1220.27 seconds |
| Started | Oct 15 03:58:17 AM UTC 24 |
| Finished | Oct 15 04:18:50 AM UTC 24 |
| Peak memory | 378092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199810791 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.1998107919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.309058241 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 411344702 ps |
| CPU time | 137.55 seconds |
| Started | Oct 15 03:58:16 AM UTC 24 |
| Finished | Oct 15 04:00:36 AM UTC 24 |
| Peak memory | 378120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309058241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.309058241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2202854823 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2378566473 ps |
| CPU time | 282.1 seconds |
| Started | Oct 15 03:57:10 AM UTC 24 |
| Finished | Oct 15 04:01:56 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202854823 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.2202854823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1680737100 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 230027019 ps |
| CPU time | 34.92 seconds |
| Started | Oct 15 03:57:39 AM UTC 24 |
| Finished | Oct 15 03:58:16 AM UTC 24 |
| Peak memory | 329016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1680737100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t hroughput_w_partial_write.1680737100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3646855468 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 15454018355 ps |
| CPU time | 1014.03 seconds |
| Started | Oct 15 04:01:30 AM UTC 24 |
| Finished | Oct 15 04:18:36 AM UTC 24 |
| Peak memory | 384264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646855468 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during _key_req.3646855468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2344916325 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 35419334 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 04:01:47 AM UTC 24 |
| Finished | Oct 15 04:01:49 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344916325 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2344916325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2351545362 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 8158660683 ps |
| CPU time | 39.87 seconds |
| Started | Oct 15 04:00:07 AM UTC 24 |
| Finished | Oct 15 04:00:48 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351545362 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.2351545362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2140688834 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2090541411 ps |
| CPU time | 148.2 seconds |
| Started | Oct 15 04:01:33 AM UTC 24 |
| Finished | Oct 15 04:04:04 AM UTC 24 |
| Peak memory | 326912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140688834 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.2140688834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2837732240 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2177788661 ps |
| CPU time | 7.05 seconds |
| Started | Oct 15 04:01:21 AM UTC 24 |
| Finished | Oct 15 04:01:29 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837732240 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.2837732240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1469396843 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 202524753 ps |
| CPU time | 28.96 seconds |
| Started | Oct 15 04:00:49 AM UTC 24 |
| Finished | Oct 15 04:01:20 AM UTC 24 |
| Peak memory | 294072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 469396843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma x_throughput.1469396843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1161960041 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 133590434 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 04:01:39 AM UTC 24 |
| Finished | Oct 15 04:01:45 AM UTC 24 |
| Peak memory | 221652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161960041 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.1161960041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.229074846 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 96386600 ps |
| CPU time | 5.87 seconds |
| Started | Oct 15 04:01:39 AM UTC 24 |
| Finished | Oct 15 04:01:46 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229074846 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.229074846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.4085415045 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2091004432 ps |
| CPU time | 451.82 seconds |
| Started | Oct 15 03:59:42 AM UTC 24 |
| Finished | Oct 15 04:07:20 AM UTC 24 |
| Peak memory | 373860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085415045 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.4085415045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1091929355 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1246654762 ps |
| CPU time | 21.67 seconds |
| Started | Oct 15 04:00:31 AM UTC 24 |
| Finished | Oct 15 04:00:54 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091929355 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1091929355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.322719233 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 17738488965 ps |
| CPU time | 372.11 seconds |
| Started | Oct 15 04:00:37 AM UTC 24 |
| Finished | Oct 15 04:06:54 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322719233 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acce ss_b2b.322719233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3686654150 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 178187479 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 04:01:36 AM UTC 24 |
| Finished | Oct 15 04:01:38 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686654150 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3686654150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_readback_err.2398629764 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 61329242 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 04:01:42 AM UTC 24 |
| Finished | Oct 15 04:01:44 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398629764 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_readback_err.2398629764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.3551000663 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 38199539184 ps |
| CPU time | 764.91 seconds |
| Started | Oct 15 04:01:36 AM UTC 24 |
| Finished | Oct 15 04:14:30 AM UTC 24 |
| Peak memory | 381976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551000663 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3551000663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1288345646 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 4122254284 ps |
| CPU time | 67.48 seconds |
| Started | Oct 15 03:59:20 AM UTC 24 |
| Finished | Oct 15 04:00:30 AM UTC 24 |
| Peak memory | 343312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288345646 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1288345646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2533985482 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 79266059090 ps |
| CPU time | 2732.95 seconds |
| Started | Oct 15 04:01:46 AM UTC 24 |
| Finished | Oct 15 04:47:49 AM UTC 24 |
| Peak memory | 394036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253398548 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.2533985482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1235811408 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 8287909593 ps |
| CPU time | 110.98 seconds |
| Started | Oct 15 04:01:45 AM UTC 24 |
| Finished | Oct 15 04:03:38 AM UTC 24 |
| Peak memory | 320908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235811408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1235811408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.988854029 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 6795515130 ps |
| CPU time | 175.81 seconds |
| Started | Oct 15 04:00:27 AM UTC 24 |
| Finished | Oct 15 04:03:26 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988854029 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.988854029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.905914022 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 220655859 ps |
| CPU time | 36.43 seconds |
| Started | Oct 15 04:00:54 AM UTC 24 |
| Finished | Oct 15 04:01:32 AM UTC 24 |
| Peak memory | 302268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 905914022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_th roughput_w_partial_write.905914022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.52495933 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 10812112673 ps |
| CPU time | 525.54 seconds |
| Started | Oct 15 04:03:05 AM UTC 24 |
| Finished | Oct 15 04:11:56 AM UTC 24 |
| Peak memory | 378024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52495933 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during_k ey_req.52495933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.765668818 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 12559416 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 04:03:39 AM UTC 24 |
| Finished | Oct 15 04:03:41 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765668818 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.765668818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1265035148 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2704402822 ps |
| CPU time | 54.33 seconds |
| Started | Oct 15 04:02:08 AM UTC 24 |
| Finished | Oct 15 04:03:04 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265035148 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1265035148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3504127020 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2511864214 ps |
| CPU time | 830.83 seconds |
| Started | Oct 15 04:03:08 AM UTC 24 |
| Finished | Oct 15 04:17:07 AM UTC 24 |
| Peak memory | 378032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504127020 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.3504127020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2900818677 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 598698101 ps |
| CPU time | 9.89 seconds |
| Started | Oct 15 04:02:56 AM UTC 24 |
| Finished | Oct 15 04:03:06 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900818677 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.2900818677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1911987708 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 459375269 ps |
| CPU time | 41.03 seconds |
| Started | Oct 15 04:02:50 AM UTC 24 |
| Finished | Oct 15 04:03:33 AM UTC 24 |
| Peak memory | 353532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 911987708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ma x_throughput.1911987708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2659333557 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1059027276 ps |
| CPU time | 8.22 seconds |
| Started | Oct 15 04:03:33 AM UTC 24 |
| Finished | Oct 15 04:03:42 AM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659333557 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.2659333557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1167939815 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3094748936 ps |
| CPU time | 12.07 seconds |
| Started | Oct 15 04:03:29 AM UTC 24 |
| Finished | Oct 15 04:03:43 AM UTC 24 |
| Peak memory | 221844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167939815 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.1167939815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1427484478 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 9122832961 ps |
| CPU time | 467.84 seconds |
| Started | Oct 15 04:01:57 AM UTC 24 |
| Finished | Oct 15 04:09:51 AM UTC 24 |
| Peak memory | 369916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427484478 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.1427484478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3359624821 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 723877801 ps |
| CPU time | 37.07 seconds |
| Started | Oct 15 04:02:31 AM UTC 24 |
| Finished | Oct 15 04:03:09 AM UTC 24 |
| Peak memory | 341176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359624821 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.3359624821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1052486330 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 83492751979 ps |
| CPU time | 493.98 seconds |
| Started | Oct 15 04:02:42 AM UTC 24 |
| Finished | Oct 15 04:11:02 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052486330 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc ess_b2b.1052486330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3580664544 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 29084009 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 04:03:26 AM UTC 24 |
| Finished | Oct 15 04:03:28 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580664544 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3580664544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_readback_err.369753287 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 51162271 ps |
| CPU time | 1.35 seconds |
| Started | Oct 15 04:03:34 AM UTC 24 |
| Finished | Oct 15 04:03:36 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369753287 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_readback_err.369753287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2689181163 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 19847560381 ps |
| CPU time | 887.92 seconds |
| Started | Oct 15 04:03:10 AM UTC 24 |
| Finished | Oct 15 04:18:07 AM UTC 24 |
| Peak memory | 384188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689181163 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2689181163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.295371943 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 657177363 ps |
| CPU time | 15.51 seconds |
| Started | Oct 15 04:01:50 AM UTC 24 |
| Finished | Oct 15 04:02:07 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295371943 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.295371943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3181285801 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 87767929042 ps |
| CPU time | 1361.8 seconds |
| Started | Oct 15 04:03:39 AM UTC 24 |
| Finished | Oct 15 04:26:37 AM UTC 24 |
| Peak memory | 384404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318128580 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.3181285801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.612542016 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2366541432 ps |
| CPU time | 47.68 seconds |
| Started | Oct 15 04:03:37 AM UTC 24 |
| Finished | Oct 15 04:04:26 AM UTC 24 |
| Peak memory | 316740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612542016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.612542016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2262915228 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 8221625061 ps |
| CPU time | 186.62 seconds |
| Started | Oct 15 04:02:30 AM UTC 24 |
| Finished | Oct 15 04:05:40 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262915228 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.2262915228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.4179352604 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 76548117 ps |
| CPU time | 2.62 seconds |
| Started | Oct 15 04:02:51 AM UTC 24 |
| Finished | Oct 15 04:02:55 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4179352604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t hroughput_w_partial_write.4179352604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1038081943 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 13033968362 ps |
| CPU time | 813.99 seconds |
| Started | Oct 15 04:04:19 AM UTC 24 |
| Finished | Oct 15 04:18:03 AM UTC 24 |
| Peak memory | 380096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038081943 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during _key_req.1038081943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1168087602 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 11868471 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 04:04:37 AM UTC 24 |
| Finished | Oct 15 04:04:39 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168087602 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1168087602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.3377227534 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2372830366 ps |
| CPU time | 33 seconds |
| Started | Oct 15 04:03:44 AM UTC 24 |
| Finished | Oct 15 04:04:19 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377227534 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.3377227534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.3640969204 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 6703748457 ps |
| CPU time | 756.07 seconds |
| Started | Oct 15 04:04:20 AM UTC 24 |
| Finished | Oct 15 04:17:05 AM UTC 24 |
| Peak memory | 380312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640969204 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.3640969204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3909799821 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1739792100 ps |
| CPU time | 6.21 seconds |
| Started | Oct 15 04:04:19 AM UTC 24 |
| Finished | Oct 15 04:04:26 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909799821 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.3909799821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2599620530 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 603399688 ps |
| CPU time | 68.79 seconds |
| Started | Oct 15 04:04:11 AM UTC 24 |
| Finished | Oct 15 04:05:22 AM UTC 24 |
| Peak memory | 378036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 599620530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma x_throughput.2599620530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3149511148 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 630856651 ps |
| CPU time | 6.87 seconds |
| Started | Oct 15 04:04:28 AM UTC 24 |
| Finished | Oct 15 04:04:36 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149511148 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.3149511148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2610771970 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 906672169 ps |
| CPU time | 15.32 seconds |
| Started | Oct 15 04:04:28 AM UTC 24 |
| Finished | Oct 15 04:04:45 AM UTC 24 |
| Peak memory | 221552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610771970 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.2610771970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3036750761 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2120456980 ps |
| CPU time | 51.9 seconds |
| Started | Oct 15 04:03:44 AM UTC 24 |
| Finished | Oct 15 04:04:38 AM UTC 24 |
| Peak memory | 273564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036750761 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3036750761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3579400779 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 295788895 ps |
| CPU time | 5.1 seconds |
| Started | Oct 15 04:04:05 AM UTC 24 |
| Finished | Oct 15 04:04:11 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579400779 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.3579400779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.342396379 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 21343656478 ps |
| CPU time | 484.96 seconds |
| Started | Oct 15 04:04:05 AM UTC 24 |
| Finished | Oct 15 04:12:16 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342396379 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acce ss_b2b.342396379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2140925785 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 296261089 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 04:04:25 AM UTC 24 |
| Finished | Oct 15 04:04:28 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140925785 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2140925785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_readback_err.3368990904 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 450473317 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 04:04:29 AM UTC 24 |
| Finished | Oct 15 04:04:31 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368990904 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_readback_err.3368990904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.730288797 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 176163829208 ps |
| CPU time | 1330.98 seconds |
| Started | Oct 15 04:04:24 AM UTC 24 |
| Finished | Oct 15 04:26:50 AM UTC 24 |
| Peak memory | 382216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730288797 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.730288797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.1683125383 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1401899465 ps |
| CPU time | 19.45 seconds |
| Started | Oct 15 04:03:43 AM UTC 24 |
| Finished | Oct 15 04:04:03 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683125383 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1683125383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1954398923 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6194609957 ps |
| CPU time | 1190.56 seconds |
| Started | Oct 15 04:04:32 AM UTC 24 |
| Finished | Oct 15 04:24:35 AM UTC 24 |
| Peak memory | 382416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195439892 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.1954398923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1350753310 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 6141410639 ps |
| CPU time | 144.6 seconds |
| Started | Oct 15 04:04:32 AM UTC 24 |
| Finished | Oct 15 04:06:59 AM UTC 24 |
| Peak memory | 359944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350753310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1350753310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.4291567555 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 8352501155 ps |
| CPU time | 289.63 seconds |
| Started | Oct 15 04:03:44 AM UTC 24 |
| Finished | Oct 15 04:08:39 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291567555 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.4291567555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1433909332 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 586630396 ps |
| CPU time | 103.12 seconds |
| Started | Oct 15 04:04:12 AM UTC 24 |
| Finished | Oct 15 04:05:57 AM UTC 24 |
| Peak memory | 371896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1433909332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t hroughput_w_partial_write.1433909332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1455882559 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3198914478 ps |
| CPU time | 621.53 seconds |
| Started | Oct 15 04:05:46 AM UTC 24 |
| Finished | Oct 15 04:16:15 AM UTC 24 |
| Peak memory | 380156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455882559 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during _key_req.1455882559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3806507160 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 173797119 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 04:06:16 AM UTC 24 |
| Finished | Oct 15 04:06:18 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806507160 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3806507160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2721188300 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3081658095 ps |
| CPU time | 77.46 seconds |
| Started | Oct 15 04:04:46 AM UTC 24 |
| Finished | Oct 15 04:06:05 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721188300 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.2721188300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.2385763474 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4066970103 ps |
| CPU time | 1000.61 seconds |
| Started | Oct 15 04:05:54 AM UTC 24 |
| Finished | Oct 15 04:22:46 AM UTC 24 |
| Peak memory | 384252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385763474 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.2385763474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.636436755 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 815550579 ps |
| CPU time | 11.76 seconds |
| Started | Oct 15 04:05:41 AM UTC 24 |
| Finished | Oct 15 04:05:54 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636436755 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.636436755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3827214981 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 111980636 ps |
| CPU time | 48.33 seconds |
| Started | Oct 15 04:05:22 AM UTC 24 |
| Finished | Oct 15 04:06:12 AM UTC 24 |
| Peak memory | 331064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 827214981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ma x_throughput.3827214981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.31259490 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 61577353 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 04:06:09 AM UTC 24 |
| Finished | Oct 15 04:06:14 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31259490 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.31259490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2972758920 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 175146663 ps |
| CPU time | 6.95 seconds |
| Started | Oct 15 04:06:05 AM UTC 24 |
| Finished | Oct 15 04:06:14 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972758920 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.2972758920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.2272857312 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 33822416731 ps |
| CPU time | 1416.95 seconds |
| Started | Oct 15 04:04:40 AM UTC 24 |
| Finished | Oct 15 04:28:32 AM UTC 24 |
| Peak memory | 380152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272857312 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.2272857312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.191144747 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6453830803 ps |
| CPU time | 25.14 seconds |
| Started | Oct 15 04:04:56 AM UTC 24 |
| Finished | Oct 15 04:05:22 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191144747 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.191144747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.421329006 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 8130395533 ps |
| CPU time | 281.18 seconds |
| Started | Oct 15 04:05:20 AM UTC 24 |
| Finished | Oct 15 04:10:05 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421329006 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acce ss_b2b.421329006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1270873994 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 109039601 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 04:06:05 AM UTC 24 |
| Finished | Oct 15 04:06:08 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270873994 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1270873994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_readback_err.1841211107 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 161455010 ps |
| CPU time | 1.42 seconds |
| Started | Oct 15 04:06:13 AM UTC 24 |
| Finished | Oct 15 04:06:15 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841211107 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_readback_err.1841211107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.50299163 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 21708847018 ps |
| CPU time | 725.58 seconds |
| Started | Oct 15 04:05:58 AM UTC 24 |
| Finished | Oct 15 04:18:12 AM UTC 24 |
| Peak memory | 378056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50299163 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.50299163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.424515848 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2579989114 ps |
| CPU time | 15.84 seconds |
| Started | Oct 15 04:04:38 AM UTC 24 |
| Finished | Oct 15 04:04:55 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424515848 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.424515848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.451922631 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 6218717849 ps |
| CPU time | 249.23 seconds |
| Started | Oct 15 04:06:15 AM UTC 24 |
| Finished | Oct 15 04:10:27 AM UTC 24 |
| Peak memory | 382148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451922631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.451922631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2485895166 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 6385733361 ps |
| CPU time | 108.44 seconds |
| Started | Oct 15 04:06:15 AM UTC 24 |
| Finished | Oct 15 04:08:06 AM UTC 24 |
| Peak memory | 333120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485895166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2485895166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.4097206724 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 14606564205 ps |
| CPU time | 271.48 seconds |
| Started | Oct 15 04:04:53 AM UTC 24 |
| Finished | Oct 15 04:09:28 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097206724 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.4097206724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3338876732 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 285134231 ps |
| CPU time | 114.12 seconds |
| Started | Oct 15 04:05:23 AM UTC 24 |
| Finished | Oct 15 04:07:20 AM UTC 24 |
| Peak memory | 378168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3338876732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t hroughput_w_partial_write.3338876732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.976355606 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3977234682 ps |
| CPU time | 807.13 seconds |
| Started | Oct 15 04:07:27 AM UTC 24 |
| Finished | Oct 15 04:21:04 AM UTC 24 |
| Peak memory | 384380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976355606 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_ key_req.976355606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2253210157 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 15307377 ps |
| CPU time | 1 seconds |
| Started | Oct 15 04:08:44 AM UTC 24 |
| Finished | Oct 15 04:08:46 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253210157 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.2253210157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1668627663 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1544701176 ps |
| CPU time | 17.36 seconds |
| Started | Oct 15 04:06:51 AM UTC 24 |
| Finished | Oct 15 04:07:09 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668627663 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.1668627663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.731233371 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2518987438 ps |
| CPU time | 923.05 seconds |
| Started | Oct 15 04:07:48 AM UTC 24 |
| Finished | Oct 15 04:23:20 AM UTC 24 |
| Peak memory | 382188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731233371 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.731233371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.215280387 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 225987140 ps |
| CPU time | 4.43 seconds |
| Started | Oct 15 04:07:21 AM UTC 24 |
| Finished | Oct 15 04:07:26 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215280387 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.215280387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1208419502 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 782374645 ps |
| CPU time | 29.99 seconds |
| Started | Oct 15 04:07:16 AM UTC 24 |
| Finished | Oct 15 04:07:48 AM UTC 24 |
| Peak memory | 298252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 208419502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ma x_throughput.1208419502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1902773315 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 287324035 ps |
| CPU time | 4.05 seconds |
| Started | Oct 15 04:08:40 AM UTC 24 |
| Finished | Oct 15 04:08:45 AM UTC 24 |
| Peak memory | 221528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902773315 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1902773315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3310453022 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 7259872195 ps |
| CPU time | 15.73 seconds |
| Started | Oct 15 04:08:23 AM UTC 24 |
| Finished | Oct 15 04:08:40 AM UTC 24 |
| Peak memory | 221624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310453022 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.3310453022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2514346539 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 45057159287 ps |
| CPU time | 721.58 seconds |
| Started | Oct 15 04:06:29 AM UTC 24 |
| Finished | Oct 15 04:18:40 AM UTC 24 |
| Peak memory | 374024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514346539 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.2514346539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3421207409 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 205071570 ps |
| CPU time | 14.01 seconds |
| Started | Oct 15 04:07:00 AM UTC 24 |
| Finished | Oct 15 04:07:15 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421207409 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3421207409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.930324503 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 20994047975 ps |
| CPU time | 426.29 seconds |
| Started | Oct 15 04:07:10 AM UTC 24 |
| Finished | Oct 15 04:14:22 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930324503 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acce ss_b2b.930324503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2030974205 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 106032968 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 04:08:20 AM UTC 24 |
| Finished | Oct 15 04:08:22 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030974205 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2030974205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_readback_err.1968901951 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 37223741 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 04:08:41 AM UTC 24 |
| Finished | Oct 15 04:08:43 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968901951 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_readback_err.1968901951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2440908546 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5797191452 ps |
| CPU time | 437.02 seconds |
| Started | Oct 15 04:08:06 AM UTC 24 |
| Finished | Oct 15 04:15:29 AM UTC 24 |
| Peak memory | 378236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440908546 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2440908546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.3726028835 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 388636791 ps |
| CPU time | 8.49 seconds |
| Started | Oct 15 04:06:19 AM UTC 24 |
| Finished | Oct 15 04:06:29 AM UTC 24 |
| Peak memory | 236880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726028835 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3726028835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.6612200 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 122536077971 ps |
| CPU time | 2038.88 seconds |
| Started | Oct 15 04:08:44 AM UTC 24 |
| Finished | Oct 15 04:43:03 AM UTC 24 |
| Peak memory | 385720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6612200 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.6612200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2159771048 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2685910475 ps |
| CPU time | 271.6 seconds |
| Started | Oct 15 04:08:41 AM UTC 24 |
| Finished | Oct 15 04:13:16 AM UTC 24 |
| Peak memory | 388488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159771048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2159771048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2025194683 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4036940897 ps |
| CPU time | 426.37 seconds |
| Started | Oct 15 04:06:56 AM UTC 24 |
| Finished | Oct 15 04:14:08 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025194683 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2025194683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1950152385 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 524448535 ps |
| CPU time | 80.23 seconds |
| Started | Oct 15 04:07:21 AM UTC 24 |
| Finished | Oct 15 04:08:43 AM UTC 24 |
| Peak memory | 357504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1950152385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t hroughput_w_partial_write.1950152385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2334693804 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3041332808 ps |
| CPU time | 1067.29 seconds |
| Started | Oct 15 04:09:53 AM UTC 24 |
| Finished | Oct 15 04:27:52 AM UTC 24 |
| Peak memory | 380172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334693804 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during _key_req.2334693804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1600280412 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 32426469 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 04:10:30 AM UTC 24 |
| Finished | Oct 15 04:10:32 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600280412 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1600280412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.359495926 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 258275721 ps |
| CPU time | 18.39 seconds |
| Started | Oct 15 04:08:57 AM UTC 24 |
| Finished | Oct 15 04:09:16 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359495926 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.359495926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.2539153726 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 12116671099 ps |
| CPU time | 917 seconds |
| Started | Oct 15 04:09:58 AM UTC 24 |
| Finished | Oct 15 04:25:25 AM UTC 24 |
| Peak memory | 382140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539153726 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.2539153726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.37329930 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1435151676 ps |
| CPU time | 9.55 seconds |
| Started | Oct 15 04:09:46 AM UTC 24 |
| Finished | Oct 15 04:09:57 AM UTC 24 |
| Peak memory | 221572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37329930 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.37329930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.4037126216 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 141102095 ps |
| CPU time | 90.91 seconds |
| Started | Oct 15 04:09:34 AM UTC 24 |
| Finished | Oct 15 04:11:07 AM UTC 24 |
| Peak memory | 371900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 037126216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ma x_throughput.4037126216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1345419869 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 356996190 ps |
| CPU time | 7.1 seconds |
| Started | Oct 15 04:10:21 AM UTC 24 |
| Finished | Oct 15 04:10:29 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345419869 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.1345419869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2108260904 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 643172234 ps |
| CPU time | 11.47 seconds |
| Started | Oct 15 04:10:20 AM UTC 24 |
| Finished | Oct 15 04:10:33 AM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108260904 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.2108260904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2075186676 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1764638845 ps |
| CPU time | 152.87 seconds |
| Started | Oct 15 04:08:46 AM UTC 24 |
| Finished | Oct 15 04:11:22 AM UTC 24 |
| Peak memory | 332984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075186676 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.2075186676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1706612801 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2425199197 ps |
| CPU time | 14.47 seconds |
| Started | Oct 15 04:09:17 AM UTC 24 |
| Finished | Oct 15 04:09:33 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706612801 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.1706612801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1840447294 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 66853266408 ps |
| CPU time | 291.94 seconds |
| Started | Oct 15 04:09:29 AM UTC 24 |
| Finished | Oct 15 04:14:25 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840447294 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc ess_b2b.1840447294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4248076367 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 377140061 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 04:10:17 AM UTC 24 |
| Finished | Oct 15 04:10:19 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248076367 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.4248076367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_readback_err.3719441192 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 28187009 ps |
| CPU time | 1.47 seconds |
| Started | Oct 15 04:10:25 AM UTC 24 |
| Finished | Oct 15 04:10:28 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719441192 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_readback_err.3719441192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1291621226 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1699453105 ps |
| CPU time | 95.89 seconds |
| Started | Oct 15 04:10:06 AM UTC 24 |
| Finished | Oct 15 04:11:44 AM UTC 24 |
| Peak memory | 382076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291621226 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1291621226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.3747048099 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1733477383 ps |
| CPU time | 9.76 seconds |
| Started | Oct 15 04:08:45 AM UTC 24 |
| Finished | Oct 15 04:08:56 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747048099 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3747048099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1465564453 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 10278913347 ps |
| CPU time | 2557.25 seconds |
| Started | Oct 15 04:10:29 AM UTC 24 |
| Finished | Oct 15 04:53:33 AM UTC 24 |
| Peak memory | 393988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146556445 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.1465564453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.916037297 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 974766298 ps |
| CPU time | 24.75 seconds |
| Started | Oct 15 04:10:29 AM UTC 24 |
| Finished | Oct 15 04:10:56 AM UTC 24 |
| Peak memory | 221760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916037297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.916037297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.12719207 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 11252750295 ps |
| CPU time | 327.27 seconds |
| Started | Oct 15 04:09:05 AM UTC 24 |
| Finished | Oct 15 04:14:37 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12719207 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.12719207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1018821807 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 136093729 ps |
| CPU time | 40.19 seconds |
| Started | Oct 15 04:09:34 AM UTC 24 |
| Finished | Oct 15 04:10:16 AM UTC 24 |
| Peak memory | 337084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1018821807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t hroughput_w_partial_write.1018821807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1744076103 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5688170537 ps |
| CPU time | 744.97 seconds |
| Started | Oct 15 04:11:22 AM UTC 24 |
| Finished | Oct 15 04:23:56 AM UTC 24 |
| Peak memory | 380100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744076103 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during _key_req.1744076103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2457626804 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 19579970 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 04:11:58 AM UTC 24 |
| Finished | Oct 15 04:12:00 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457626804 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2457626804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.870294582 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 13580132409 ps |
| CPU time | 53.66 seconds |
| Started | Oct 15 04:10:47 AM UTC 24 |
| Finished | Oct 15 04:11:42 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870294582 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.870294582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.880018807 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 17089074144 ps |
| CPU time | 1818.65 seconds |
| Started | Oct 15 04:11:34 AM UTC 24 |
| Finished | Oct 15 04:42:11 AM UTC 24 |
| Peak memory | 384404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880018807 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.880018807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3806632545 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1211244897 ps |
| CPU time | 9.5 seconds |
| Started | Oct 15 04:11:22 AM UTC 24 |
| Finished | Oct 15 04:11:33 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806632545 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.3806632545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1050171118 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 111779706 ps |
| CPU time | 1.35 seconds |
| Started | Oct 15 04:11:08 AM UTC 24 |
| Finished | Oct 15 04:11:10 AM UTC 24 |
| Peak memory | 210000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 050171118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ma x_throughput.1050171118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2812015816 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 678763838 ps |
| CPU time | 3.23 seconds |
| Started | Oct 15 04:11:48 AM UTC 24 |
| Finished | Oct 15 04:11:52 AM UTC 24 |
| Peak memory | 221520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812015816 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.2812015816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1955503066 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 71853177 ps |
| CPU time | 5.99 seconds |
| Started | Oct 15 04:11:46 AM UTC 24 |
| Finished | Oct 15 04:11:53 AM UTC 24 |
| Peak memory | 221588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955503066 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.1955503066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4287082617 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5550346109 ps |
| CPU time | 1012.25 seconds |
| Started | Oct 15 04:10:33 AM UTC 24 |
| Finished | Oct 15 04:27:36 AM UTC 24 |
| Peak memory | 384172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287082617 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.4287082617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3593077741 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2040185115 ps |
| CPU time | 68.75 seconds |
| Started | Oct 15 04:10:59 AM UTC 24 |
| Finished | Oct 15 04:12:09 AM UTC 24 |
| Peak memory | 341184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593077741 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.3593077741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1831847223 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 60712986054 ps |
| CPU time | 606.88 seconds |
| Started | Oct 15 04:11:03 AM UTC 24 |
| Finished | Oct 15 04:21:17 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831847223 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acc ess_b2b.1831847223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1751472094 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 76691765 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 04:11:45 AM UTC 24 |
| Finished | Oct 15 04:11:47 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751472094 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1751472094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_readback_err.2763341470 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 95264718 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 04:11:53 AM UTC 24 |
| Finished | Oct 15 04:11:56 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763341470 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_readback_err.2763341470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2729406752 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 5331008824 ps |
| CPU time | 293.01 seconds |
| Started | Oct 15 04:11:43 AM UTC 24 |
| Finished | Oct 15 04:16:40 AM UTC 24 |
| Peak memory | 324996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729406752 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2729406752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2104129748 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 257270172 ps |
| CPU time | 11 seconds |
| Started | Oct 15 04:10:33 AM UTC 24 |
| Finished | Oct 15 04:10:46 AM UTC 24 |
| Peak memory | 253060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104129748 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2104129748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2866461990 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 13868084976 ps |
| CPU time | 375.2 seconds |
| Started | Oct 15 04:11:56 AM UTC 24 |
| Finished | Oct 15 04:18:17 AM UTC 24 |
| Peak memory | 388496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286646199 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.2866461990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3050851680 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 23640204924 ps |
| CPU time | 286.98 seconds |
| Started | Oct 15 04:10:57 AM UTC 24 |
| Finished | Oct 15 04:15:48 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050851680 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3050851680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.432871115 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 279792337 ps |
| CPU time | 83.58 seconds |
| Started | Oct 15 04:11:11 AM UTC 24 |
| Finished | Oct 15 04:12:37 AM UTC 24 |
| Peak memory | 361724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 432871115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_th roughput_w_partial_write.432871115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3089847042 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3065551067 ps |
| CPU time | 833.75 seconds |
| Started | Oct 15 03:10:16 AM UTC 24 |
| Finished | Oct 15 03:24:18 AM UTC 24 |
| Peak memory | 382216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089847042 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_ key_req.3089847042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3297686594 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 16891651 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:11:16 AM UTC 24 |
| Finished | Oct 15 03:11:18 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297686594 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.3297686594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.1332336854 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3868078129 ps |
| CPU time | 103.04 seconds |
| Started | Oct 15 03:09:24 AM UTC 24 |
| Finished | Oct 15 03:11:10 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332336854 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.1332336854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2472826873 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9516924060 ps |
| CPU time | 481.03 seconds |
| Started | Oct 15 03:10:49 AM UTC 24 |
| Finished | Oct 15 03:18:56 AM UTC 24 |
| Peak memory | 384240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472826873 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.2472826873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2019943455 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 796191875 ps |
| CPU time | 6.59 seconds |
| Started | Oct 15 03:10:07 AM UTC 24 |
| Finished | Oct 15 03:10:14 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019943455 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2019943455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3466314803 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 129871322 ps |
| CPU time | 76.71 seconds |
| Started | Oct 15 03:09:52 AM UTC 24 |
| Finished | Oct 15 03:11:11 AM UTC 24 |
| Peak memory | 365876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 466314803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max _throughput.3466314803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3584881270 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 106084260 ps |
| CPU time | 4.61 seconds |
| Started | Oct 15 03:11:10 AM UTC 24 |
| Finished | Oct 15 03:11:16 AM UTC 24 |
| Peak memory | 221588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584881270 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.3584881270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1674925423 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 76888339 ps |
| CPU time | 6.3 seconds |
| Started | Oct 15 03:11:07 AM UTC 24 |
| Finished | Oct 15 03:11:15 AM UTC 24 |
| Peak memory | 221504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674925423 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.1674925423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3184780946 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 117430624521 ps |
| CPU time | 878.94 seconds |
| Started | Oct 15 03:09:23 AM UTC 24 |
| Finished | Oct 15 03:24:11 AM UTC 24 |
| Peak memory | 378040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184780946 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.3184780946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1832017420 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 10877346172 ps |
| CPU time | 23.34 seconds |
| Started | Oct 15 03:09:26 AM UTC 24 |
| Finished | Oct 15 03:09:51 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832017420 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.1832017420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2424592054 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 16406108858 ps |
| CPU time | 500.11 seconds |
| Started | Oct 15 03:09:42 AM UTC 24 |
| Finished | Oct 15 03:18:09 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424592054 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce ss_b2b.2424592054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.325358415 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 31894494 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 03:11:04 AM UTC 24 |
| Finished | Oct 15 03:11:07 AM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325358415 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.325358415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_readback_err.779018462 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 151865392 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 03:11:12 AM UTC 24 |
| Finished | Oct 15 03:11:14 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779018462 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_readback_err.779018462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1023367290 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 12566693968 ps |
| CPU time | 1074.5 seconds |
| Started | Oct 15 03:11:01 AM UTC 24 |
| Finished | Oct 15 03:29:06 AM UTC 24 |
| Peak memory | 384392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023367290 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1023367290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3110937218 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2345864110 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 03:11:15 AM UTC 24 |
| Finished | Oct 15 03:11:20 AM UTC 24 |
| Peak memory | 247624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110937218 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3110937218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.1936375932 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 513593169 ps |
| CPU time | 109 seconds |
| Started | Oct 15 03:09:21 AM UTC 24 |
| Finished | Oct 15 03:11:12 AM UTC 24 |
| Peak memory | 374092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936375932 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1936375932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2285709924 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 19975614770 ps |
| CPU time | 780.24 seconds |
| Started | Oct 15 03:11:14 AM UTC 24 |
| Finished | Oct 15 03:24:23 AM UTC 24 |
| Peak memory | 378068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228570992 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.2285709924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3769660127 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 135952601 ps |
| CPU time | 15.59 seconds |
| Started | Oct 15 03:11:13 AM UTC 24 |
| Finished | Oct 15 03:11:30 AM UTC 24 |
| Peak memory | 221620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769660127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3769660127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1227961408 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 5176025015 ps |
| CPU time | 529.13 seconds |
| Started | Oct 15 03:09:25 AM UTC 24 |
| Finished | Oct 15 03:18:22 AM UTC 24 |
| Peak memory | 211600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227961408 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.1227961408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3631106902 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 107194623 ps |
| CPU time | 41.99 seconds |
| Started | Oct 15 03:10:05 AM UTC 24 |
| Finished | Oct 15 03:10:48 AM UTC 24 |
| Peak memory | 310456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3631106902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th roughput_w_partial_write.3631106902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3845629651 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 14846301256 ps |
| CPU time | 1328.04 seconds |
| Started | Oct 15 04:13:47 AM UTC 24 |
| Finished | Oct 15 04:36:10 AM UTC 24 |
| Peak memory | 378108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845629651 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during _key_req.3845629651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1379315298 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 51516569 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 04:14:29 AM UTC 24 |
| Finished | Oct 15 04:14:30 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379315298 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1379315298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1219077537 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 2520382819 ps |
| CPU time | 48.61 seconds |
| Started | Oct 15 04:12:10 AM UTC 24 |
| Finished | Oct 15 04:13:00 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219077537 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.1219077537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.914203204 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 9355051712 ps |
| CPU time | 771.18 seconds |
| Started | Oct 15 04:13:55 AM UTC 24 |
| Finished | Oct 15 04:26:56 AM UTC 24 |
| Peak memory | 374004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914203204 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.914203204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1980982437 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 2161040800 ps |
| CPU time | 11.82 seconds |
| Started | Oct 15 04:13:33 AM UTC 24 |
| Finished | Oct 15 04:13:46 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980982437 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.1980982437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3653471734 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 449172146 ps |
| CPU time | 90.34 seconds |
| Started | Oct 15 04:13:03 AM UTC 24 |
| Finished | Oct 15 04:14:35 AM UTC 24 |
| Peak memory | 359604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 653471734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ma x_throughput.3653471734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1282913401 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 370210272 ps |
| CPU time | 4.48 seconds |
| Started | Oct 15 04:14:22 AM UTC 24 |
| Finished | Oct 15 04:14:27 AM UTC 24 |
| Peak memory | 221656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282913401 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.1282913401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2414237980 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 939004750 ps |
| CPU time | 8.23 seconds |
| Started | Oct 15 04:14:12 AM UTC 24 |
| Finished | Oct 15 04:14:21 AM UTC 24 |
| Peak memory | 221532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414237980 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2414237980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3855090184 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 8898756838 ps |
| CPU time | 716.49 seconds |
| Started | Oct 15 04:12:01 AM UTC 24 |
| Finished | Oct 15 04:24:05 AM UTC 24 |
| Peak memory | 376080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855090184 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.3855090184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2219126272 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1625187652 ps |
| CPU time | 22.7 seconds |
| Started | Oct 15 04:12:37 AM UTC 24 |
| Finished | Oct 15 04:13:01 AM UTC 24 |
| Peak memory | 277784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219126272 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.2219126272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1390404044 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 82298750995 ps |
| CPU time | 317.17 seconds |
| Started | Oct 15 04:13:02 AM UTC 24 |
| Finished | Oct 15 04:18:23 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390404044 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc ess_b2b.1390404044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2704775174 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 29474326 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 04:14:09 AM UTC 24 |
| Finished | Oct 15 04:14:11 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704775174 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2704775174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_readback_err.2987328604 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 106074345 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 04:14:23 AM UTC 24 |
| Finished | Oct 15 04:14:25 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987328604 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_readback_err.2987328604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2291989869 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1764104050 ps |
| CPU time | 796.4 seconds |
| Started | Oct 15 04:13:57 AM UTC 24 |
| Finished | Oct 15 04:27:23 AM UTC 24 |
| Peak memory | 367944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291989869 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2291989869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.2068192603 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 637105657 ps |
| CPU time | 89.09 seconds |
| Started | Oct 15 04:12:01 AM UTC 24 |
| Finished | Oct 15 04:13:32 AM UTC 24 |
| Peak memory | 375944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068192603 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2068192603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2043288866 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 55238896214 ps |
| CPU time | 3910.42 seconds |
| Started | Oct 15 04:14:26 AM UTC 24 |
| Finished | Oct 15 05:20:17 AM UTC 24 |
| Peak memory | 385776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204328886 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.2043288866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1279628028 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1467215142 ps |
| CPU time | 177.13 seconds |
| Started | Oct 15 04:12:17 AM UTC 24 |
| Finished | Oct 15 04:15:18 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279628028 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.1279628028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1967135393 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 214263704 ps |
| CPU time | 38.41 seconds |
| Started | Oct 15 04:13:17 AM UTC 24 |
| Finished | Oct 15 04:13:57 AM UTC 24 |
| Peak memory | 312420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1967135393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_t hroughput_w_partial_write.1967135393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2039680622 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 13096191798 ps |
| CPU time | 609.9 seconds |
| Started | Oct 15 04:15:28 AM UTC 24 |
| Finished | Oct 15 04:25:45 AM UTC 24 |
| Peak memory | 380124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039680622 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during _key_req.2039680622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.685011758 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 39957333 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 04:16:05 AM UTC 24 |
| Finished | Oct 15 04:16:07 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685011758 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.685011758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1349179951 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 7254509691 ps |
| CPU time | 95.28 seconds |
| Started | Oct 15 04:14:36 AM UTC 24 |
| Finished | Oct 15 04:16:13 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349179951 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.1349179951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.1348011668 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 29193957324 ps |
| CPU time | 1051.06 seconds |
| Started | Oct 15 04:15:30 AM UTC 24 |
| Finished | Oct 15 04:33:14 AM UTC 24 |
| Peak memory | 382196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348011668 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.1348011668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1283625344 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4021887865 ps |
| CPU time | 5.67 seconds |
| Started | Oct 15 04:15:23 AM UTC 24 |
| Finished | Oct 15 04:15:29 AM UTC 24 |
| Peak memory | 221652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283625344 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.1283625344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.924184989 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 96956210 ps |
| CPU time | 36.16 seconds |
| Started | Oct 15 04:14:49 AM UTC 24 |
| Finished | Oct 15 04:15:27 AM UTC 24 |
| Peak memory | 300220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 24184989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_max _throughput.924184989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2114392420 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 91304744 ps |
| CPU time | 6.38 seconds |
| Started | Oct 15 04:15:50 AM UTC 24 |
| Finished | Oct 15 04:15:57 AM UTC 24 |
| Peak memory | 221712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114392420 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.2114392420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.871244455 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 751760187 ps |
| CPU time | 13.32 seconds |
| Started | Oct 15 04:15:44 AM UTC 24 |
| Finished | Oct 15 04:15:59 AM UTC 24 |
| Peak memory | 221644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871244455 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.871244455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2642257956 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 13524857589 ps |
| CPU time | 899.21 seconds |
| Started | Oct 15 04:14:32 AM UTC 24 |
| Finished | Oct 15 04:29:41 AM UTC 24 |
| Peak memory | 378112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642257956 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2642257956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2199084199 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 417369569 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 04:14:44 AM UTC 24 |
| Finished | Oct 15 04:14:48 AM UTC 24 |
| Peak memory | 217628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199084199 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.2199084199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2072610938 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 12494342818 ps |
| CPU time | 356.98 seconds |
| Started | Oct 15 04:14:46 AM UTC 24 |
| Finished | Oct 15 04:20:48 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072610938 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc ess_b2b.2072610938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3553094892 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 30809660 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 04:15:41 AM UTC 24 |
| Finished | Oct 15 04:15:43 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553094892 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3553094892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_readback_err.2715280741 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 28507484 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 04:15:58 AM UTC 24 |
| Finished | Oct 15 04:16:00 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715280741 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_readback_err.2715280741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.3981266605 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4962052244 ps |
| CPU time | 1510.42 seconds |
| Started | Oct 15 04:15:30 AM UTC 24 |
| Finished | Oct 15 04:40:57 AM UTC 24 |
| Peak memory | 378040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981266605 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3981266605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.3374658162 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 652235397 ps |
| CPU time | 11.7 seconds |
| Started | Oct 15 04:14:31 AM UTC 24 |
| Finished | Oct 15 04:14:43 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374658162 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3374658162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2497376819 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 103663498916 ps |
| CPU time | 1218.46 seconds |
| Started | Oct 15 04:16:01 AM UTC 24 |
| Finished | Oct 15 04:36:32 AM UTC 24 |
| Peak memory | 384404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249737681 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.2497376819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1427182908 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1225445870 ps |
| CPU time | 82.09 seconds |
| Started | Oct 15 04:16:00 AM UTC 24 |
| Finished | Oct 15 04:17:24 AM UTC 24 |
| Peak memory | 322828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427182908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1427182908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.559651540 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 9146804958 ps |
| CPU time | 135.59 seconds |
| Started | Oct 15 04:14:38 AM UTC 24 |
| Finished | Oct 15 04:16:56 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559651540 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.559651540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2471861920 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 426719639 ps |
| CPU time | 43.71 seconds |
| Started | Oct 15 04:15:19 AM UTC 24 |
| Finished | Oct 15 04:16:04 AM UTC 24 |
| Peak memory | 310584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2471861920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t hroughput_w_partial_write.2471861920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1699487872 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 25966104073 ps |
| CPU time | 562.45 seconds |
| Started | Oct 15 04:17:09 AM UTC 24 |
| Finished | Oct 15 04:26:39 AM UTC 24 |
| Peak memory | 375956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699487872 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during _key_req.1699487872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1300755724 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 15853279 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 04:18:04 AM UTC 24 |
| Finished | Oct 15 04:18:05 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300755724 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1300755724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3797347201 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5494597625 ps |
| CPU time | 30.89 seconds |
| Started | Oct 15 04:16:16 AM UTC 24 |
| Finished | Oct 15 04:16:48 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797347201 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.3797347201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.1194749272 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 15725106067 ps |
| CPU time | 439.58 seconds |
| Started | Oct 15 04:17:16 AM UTC 24 |
| Finished | Oct 15 04:24:41 AM UTC 24 |
| Peak memory | 380280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194749272 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.1194749272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1375889082 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 292241660 ps |
| CPU time | 5.94 seconds |
| Started | Oct 15 04:17:08 AM UTC 24 |
| Finished | Oct 15 04:17:15 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375889082 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.1375889082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1448708801 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 518239826 ps |
| CPU time | 107.68 seconds |
| Started | Oct 15 04:16:57 AM UTC 24 |
| Finished | Oct 15 04:18:46 AM UTC 24 |
| Peak memory | 377912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 448708801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma x_throughput.1448708801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1315060352 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 124885241 ps |
| CPU time | 5.66 seconds |
| Started | Oct 15 04:17:30 AM UTC 24 |
| Finished | Oct 15 04:17:37 AM UTC 24 |
| Peak memory | 221748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315060352 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.1315060352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.3657952214 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 142294312 ps |
| CPU time | 8.44 seconds |
| Started | Oct 15 04:17:28 AM UTC 24 |
| Finished | Oct 15 04:17:38 AM UTC 24 |
| Peak memory | 221596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657952214 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.3657952214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.4081077664 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 21406531461 ps |
| CPU time | 1004.71 seconds |
| Started | Oct 15 04:16:14 AM UTC 24 |
| Finished | Oct 15 04:33:11 AM UTC 24 |
| Peak memory | 382196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081077664 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.4081077664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.636159773 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 386051283 ps |
| CPU time | 40.14 seconds |
| Started | Oct 15 04:16:41 AM UTC 24 |
| Finished | Oct 15 04:17:23 AM UTC 24 |
| Peak memory | 318652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636159773 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.636159773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3274189381 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 51931131114 ps |
| CPU time | 665.88 seconds |
| Started | Oct 15 04:16:48 AM UTC 24 |
| Finished | Oct 15 04:28:03 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274189381 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acc ess_b2b.3274189381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.624257925 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 27539650 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 04:17:25 AM UTC 24 |
| Finished | Oct 15 04:17:27 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624257925 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.624257925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_readback_err.1744069056 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 61147535 ps |
| CPU time | 1.32 seconds |
| Started | Oct 15 04:17:37 AM UTC 24 |
| Finished | Oct 15 04:17:39 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744069056 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_readback_err.1744069056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3900257450 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 19926536258 ps |
| CPU time | 1169.29 seconds |
| Started | Oct 15 04:17:23 AM UTC 24 |
| Finished | Oct 15 04:37:05 AM UTC 24 |
| Peak memory | 382160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900257450 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3900257450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.4284232409 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 1780896796 ps |
| CPU time | 17.24 seconds |
| Started | Oct 15 04:16:08 AM UTC 24 |
| Finished | Oct 15 04:16:27 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284232409 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4284232409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.4060683685 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 7325423017 ps |
| CPU time | 1793.58 seconds |
| Started | Oct 15 04:17:40 AM UTC 24 |
| Finished | Oct 15 04:47:53 AM UTC 24 |
| Peak memory | 385788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406068368 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.4060683685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2690698338 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1319212672 ps |
| CPU time | 122.65 seconds |
| Started | Oct 15 04:17:38 AM UTC 24 |
| Finished | Oct 15 04:19:43 AM UTC 24 |
| Peak memory | 265436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690698338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2690698338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1882181411 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 8530573519 ps |
| CPU time | 273.35 seconds |
| Started | Oct 15 04:16:28 AM UTC 24 |
| Finished | Oct 15 04:21:06 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882181411 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1882181411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.489517804 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 45384994 ps |
| CPU time | 1.57 seconds |
| Started | Oct 15 04:17:06 AM UTC 24 |
| Finished | Oct 15 04:17:08 AM UTC 24 |
| Peak memory | 220296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 489517804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_th roughput_w_partial_write.489517804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2304441462 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 13332054934 ps |
| CPU time | 672.94 seconds |
| Started | Oct 15 04:18:43 AM UTC 24 |
| Finished | Oct 15 04:30:03 AM UTC 24 |
| Peak memory | 374220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304441462 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during _key_req.2304441462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1820137598 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 12521423 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 04:19:14 AM UTC 24 |
| Finished | Oct 15 04:19:16 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820137598 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1820137598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.1037114692 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 13332895317 ps |
| CPU time | 29.78 seconds |
| Started | Oct 15 04:18:13 AM UTC 24 |
| Finished | Oct 15 04:18:44 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037114692 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.1037114692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.890097883 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 19854367108 ps |
| CPU time | 547.11 seconds |
| Started | Oct 15 04:18:45 AM UTC 24 |
| Finished | Oct 15 04:27:59 AM UTC 24 |
| Peak memory | 384364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890097883 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.890097883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4180266437 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1092673093 ps |
| CPU time | 4.13 seconds |
| Started | Oct 15 04:18:40 AM UTC 24 |
| Finished | Oct 15 04:18:45 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180266437 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.4180266437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3839896858 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 49485753 ps |
| CPU time | 4.27 seconds |
| Started | Oct 15 04:18:37 AM UTC 24 |
| Finished | Oct 15 04:18:42 AM UTC 24 |
| Peak memory | 228540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 839896858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma x_throughput.3839896858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3116533797 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 94389868 ps |
| CPU time | 4.1 seconds |
| Started | Oct 15 04:18:51 AM UTC 24 |
| Finished | Oct 15 04:18:56 AM UTC 24 |
| Peak memory | 221784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116533797 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.3116533797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1361215255 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 93685697 ps |
| CPU time | 7.56 seconds |
| Started | Oct 15 04:18:51 AM UTC 24 |
| Finished | Oct 15 04:19:00 AM UTC 24 |
| Peak memory | 221656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361215255 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.1361215255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3655139152 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 13599368843 ps |
| CPU time | 622.54 seconds |
| Started | Oct 15 04:18:08 AM UTC 24 |
| Finished | Oct 15 04:28:38 AM UTC 24 |
| Peak memory | 384260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655139152 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.3655139152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1860752541 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1457434275 ps |
| CPU time | 18.62 seconds |
| Started | Oct 15 04:18:18 AM UTC 24 |
| Finished | Oct 15 04:18:38 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860752541 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.1860752541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3439123100 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 50614770381 ps |
| CPU time | 398.41 seconds |
| Started | Oct 15 04:18:24 AM UTC 24 |
| Finished | Oct 15 04:25:08 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439123100 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc ess_b2b.3439123100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2664971566 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 201117041 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 04:18:48 AM UTC 24 |
| Finished | Oct 15 04:18:50 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664971566 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.2664971566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_readback_err.126058307 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 30402705 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 04:18:57 AM UTC 24 |
| Finished | Oct 15 04:19:00 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126058307 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_readback_err.126058307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1335204870 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 5567433547 ps |
| CPU time | 1277.5 seconds |
| Started | Oct 15 04:18:46 AM UTC 24 |
| Finished | Oct 15 04:40:17 AM UTC 24 |
| Peak memory | 382336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335204870 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1335204870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.4259643854 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 180761652 ps |
| CPU time | 6.27 seconds |
| Started | Oct 15 04:18:07 AM UTC 24 |
| Finished | Oct 15 04:18:14 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259643854 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4259643854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2535142692 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 35375654367 ps |
| CPU time | 2524.7 seconds |
| Started | Oct 15 04:19:02 AM UTC 24 |
| Finished | Oct 15 05:01:31 AM UTC 24 |
| Peak memory | 385848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253514269 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.2535142692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3851361484 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2713669979 ps |
| CPU time | 11.62 seconds |
| Started | Oct 15 04:19:00 AM UTC 24 |
| Finished | Oct 15 04:19:13 AM UTC 24 |
| Peak memory | 228712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851361484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3851361484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.501928796 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2932040036 ps |
| CPU time | 302.14 seconds |
| Started | Oct 15 04:18:15 AM UTC 24 |
| Finished | Oct 15 04:23:21 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501928796 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.501928796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2783484895 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 438409223 ps |
| CPU time | 48.47 seconds |
| Started | Oct 15 04:18:39 AM UTC 24 |
| Finished | Oct 15 04:19:29 AM UTC 24 |
| Peak memory | 320696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2783484895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_t hroughput_w_partial_write.2783484895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2277678907 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 11807715687 ps |
| CPU time | 938.82 seconds |
| Started | Oct 15 04:21:04 AM UTC 24 |
| Finished | Oct 15 04:36:52 AM UTC 24 |
| Peak memory | 384188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277678907 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during _key_req.2277678907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2302942689 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 16938145 ps |
| CPU time | 1 seconds |
| Started | Oct 15 04:21:50 AM UTC 24 |
| Finished | Oct 15 04:21:52 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302942689 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2302942689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1025634187 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3496181154 ps |
| CPU time | 61.79 seconds |
| Started | Oct 15 04:19:34 AM UTC 24 |
| Finished | Oct 15 04:20:38 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025634187 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.1025634187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.2072178714 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 17077134352 ps |
| CPU time | 786.43 seconds |
| Started | Oct 15 04:21:07 AM UTC 24 |
| Finished | Oct 15 04:34:22 AM UTC 24 |
| Peak memory | 384256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072178714 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.2072178714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2423618432 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1358495331 ps |
| CPU time | 6.74 seconds |
| Started | Oct 15 04:20:59 AM UTC 24 |
| Finished | Oct 15 04:21:07 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423618432 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.2423618432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3580268423 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 117556328 ps |
| CPU time | 79.69 seconds |
| Started | Oct 15 04:20:49 AM UTC 24 |
| Finished | Oct 15 04:22:11 AM UTC 24 |
| Peak memory | 349364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 580268423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ma x_throughput.3580268423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1294986071 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 379158820 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 04:21:27 AM UTC 24 |
| Finished | Oct 15 04:21:33 AM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294986071 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.1294986071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3345938850 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 722243006 ps |
| CPU time | 14.62 seconds |
| Started | Oct 15 04:21:21 AM UTC 24 |
| Finished | Oct 15 04:21:37 AM UTC 24 |
| Peak memory | 221648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345938850 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.3345938850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2822493793 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 6647243645 ps |
| CPU time | 114.09 seconds |
| Started | Oct 15 04:19:30 AM UTC 24 |
| Finished | Oct 15 04:21:27 AM UTC 24 |
| Peak memory | 376188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822493793 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.2822493793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2700771676 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 87942332 ps |
| CPU time | 3.09 seconds |
| Started | Oct 15 04:20:39 AM UTC 24 |
| Finished | Oct 15 04:20:43 AM UTC 24 |
| Peak memory | 213388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700771676 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2700771676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3200260015 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 4406937644 ps |
| CPU time | 385.47 seconds |
| Started | Oct 15 04:20:44 AM UTC 24 |
| Finished | Oct 15 04:27:15 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200260015 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc ess_b2b.3200260015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3320803892 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 48975989 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 04:21:18 AM UTC 24 |
| Finished | Oct 15 04:21:20 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320803892 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3320803892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_readback_err.603902844 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 135796672 ps |
| CPU time | 1.48 seconds |
| Started | Oct 15 04:21:33 AM UTC 24 |
| Finished | Oct 15 04:21:36 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603902844 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_readback_err.603902844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.3850950549 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 50458728689 ps |
| CPU time | 662.09 seconds |
| Started | Oct 15 04:21:08 AM UTC 24 |
| Finished | Oct 15 04:32:17 AM UTC 24 |
| Peak memory | 382216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850950549 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3850950549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.4092111929 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 372702504 ps |
| CPU time | 15.13 seconds |
| Started | Oct 15 04:19:17 AM UTC 24 |
| Finished | Oct 15 04:19:33 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092111929 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.4092111929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3392759530 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 295151172 ps |
| CPU time | 11.44 seconds |
| Started | Oct 15 04:21:37 AM UTC 24 |
| Finished | Oct 15 04:21:50 AM UTC 24 |
| Peak memory | 221792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392759530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3392759530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1578417746 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 14948772191 ps |
| CPU time | 413.68 seconds |
| Started | Oct 15 04:19:44 AM UTC 24 |
| Finished | Oct 15 04:26:44 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578417746 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1578417746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1127500256 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 35071508 ps |
| CPU time | 1.33 seconds |
| Started | Oct 15 04:20:56 AM UTC 24 |
| Finished | Oct 15 04:20:58 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1127500256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t hroughput_w_partial_write.1127500256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.4248943647 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 5717594083 ps |
| CPU time | 809.97 seconds |
| Started | Oct 15 04:23:19 AM UTC 24 |
| Finished | Oct 15 04:36:58 AM UTC 24 |
| Peak memory | 382136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248943647 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during _key_req.4248943647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1110369199 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 15155528 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 04:23:57 AM UTC 24 |
| Finished | Oct 15 04:24:00 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110369199 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1110369199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3781596263 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3236614645 ps |
| CPU time | 61.89 seconds |
| Started | Oct 15 04:21:57 AM UTC 24 |
| Finished | Oct 15 04:23:00 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781596263 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.3781596263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.4102461012 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 26816161156 ps |
| CPU time | 1128.56 seconds |
| Started | Oct 15 04:23:20 AM UTC 24 |
| Finished | Oct 15 04:42:21 AM UTC 24 |
| Peak memory | 380156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102461012 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.4102461012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.729998129 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1726419479 ps |
| CPU time | 6.9 seconds |
| Started | Oct 15 04:23:10 AM UTC 24 |
| Finished | Oct 15 04:23:18 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729998129 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.729998129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1474059459 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 94879062 ps |
| CPU time | 21.55 seconds |
| Started | Oct 15 04:22:47 AM UTC 24 |
| Finished | Oct 15 04:23:09 AM UTC 24 |
| Peak memory | 294068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 474059459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ma x_throughput.1474059459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.1661561426 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 67569721 ps |
| CPU time | 5.62 seconds |
| Started | Oct 15 04:23:45 AM UTC 24 |
| Finished | Oct 15 04:23:52 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661561426 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.1661561426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.4205781818 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2713330435 ps |
| CPU time | 16.73 seconds |
| Started | Oct 15 04:23:26 AM UTC 24 |
| Finished | Oct 15 04:23:44 AM UTC 24 |
| Peak memory | 221600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205781818 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.4205781818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2465510705 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 4471253393 ps |
| CPU time | 222.3 seconds |
| Started | Oct 15 04:21:55 AM UTC 24 |
| Finished | Oct 15 04:25:40 AM UTC 24 |
| Peak memory | 376052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465510705 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.2465510705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.4105894849 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 240309330 ps |
| CPU time | 5.07 seconds |
| Started | Oct 15 04:22:20 AM UTC 24 |
| Finished | Oct 15 04:22:26 AM UTC 24 |
| Peak memory | 228540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105894849 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.4105894849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2363863501 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 49103667705 ps |
| CPU time | 404.32 seconds |
| Started | Oct 15 04:22:27 AM UTC 24 |
| Finished | Oct 15 04:29:17 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363863501 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acc ess_b2b.2363863501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.831278912 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 307469935 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 04:23:23 AM UTC 24 |
| Finished | Oct 15 04:23:25 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831278912 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.831278912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_readback_err.4001830394 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 90648986 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 04:23:47 AM UTC 24 |
| Finished | Oct 15 04:23:49 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001830394 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_readback_err.4001830394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.350700637 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 68915918911 ps |
| CPU time | 1332.79 seconds |
| Started | Oct 15 04:23:22 AM UTC 24 |
| Finished | Oct 15 04:45:49 AM UTC 24 |
| Peak memory | 380300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350700637 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.350700637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3033730896 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 176397353 ps |
| CPU time | 1.41 seconds |
| Started | Oct 15 04:21:53 AM UTC 24 |
| Finished | Oct 15 04:21:56 AM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033730896 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3033730896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.4142379280 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 19423201437 ps |
| CPU time | 6460.57 seconds |
| Started | Oct 15 04:23:53 AM UTC 24 |
| Finished | Oct 15 06:12:40 AM UTC 24 |
| Peak memory | 385908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414237928 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.4142379280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2389363891 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 587557106 ps |
| CPU time | 63.63 seconds |
| Started | Oct 15 04:23:50 AM UTC 24 |
| Finished | Oct 15 04:24:55 AM UTC 24 |
| Peak memory | 339272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389363891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2389363891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1015862077 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 5348131655 ps |
| CPU time | 153.84 seconds |
| Started | Oct 15 04:22:12 AM UTC 24 |
| Finished | Oct 15 04:24:49 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015862077 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1015862077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2733143210 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 219816900 ps |
| CPU time | 16.29 seconds |
| Started | Oct 15 04:23:02 AM UTC 24 |
| Finished | Oct 15 04:23:19 AM UTC 24 |
| Peak memory | 265324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2733143210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t hroughput_w_partial_write.2733143210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.2266439284 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 8259464871 ps |
| CPU time | 1071.02 seconds |
| Started | Oct 15 04:25:12 AM UTC 24 |
| Finished | Oct 15 04:43:15 AM UTC 24 |
| Peak memory | 384292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266439284 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during _key_req.2266439284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3437977092 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 33609699 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 04:25:55 AM UTC 24 |
| Finished | Oct 15 04:25:57 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437977092 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.3437977092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3803378627 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 3689328619 ps |
| CPU time | 89.31 seconds |
| Started | Oct 15 04:24:36 AM UTC 24 |
| Finished | Oct 15 04:26:07 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803378627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.3803378627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1599000303 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 22220280405 ps |
| CPU time | 993.82 seconds |
| Started | Oct 15 04:25:24 AM UTC 24 |
| Finished | Oct 15 04:42:08 AM UTC 24 |
| Peak memory | 382332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599000303 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.1599000303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.3599579202 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 4168391493 ps |
| CPU time | 12.2 seconds |
| Started | Oct 15 04:25:09 AM UTC 24 |
| Finished | Oct 15 04:25:22 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599579202 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.3599579202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2261628187 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 507872936 ps |
| CPU time | 86.15 seconds |
| Started | Oct 15 04:24:56 AM UTC 24 |
| Finished | Oct 15 04:26:24 AM UTC 24 |
| Peak memory | 371832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 261628187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ma x_throughput.2261628187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1353573104 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 341154730 ps |
| CPU time | 7.52 seconds |
| Started | Oct 15 04:25:46 AM UTC 24 |
| Finished | Oct 15 04:25:54 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353573104 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.1353573104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.582995250 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 881347037 ps |
| CPU time | 7.23 seconds |
| Started | Oct 15 04:25:44 AM UTC 24 |
| Finished | Oct 15 04:25:53 AM UTC 24 |
| Peak memory | 221480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582995250 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.582995250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2411065348 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 19300665580 ps |
| CPU time | 688.26 seconds |
| Started | Oct 15 04:24:06 AM UTC 24 |
| Finished | Oct 15 04:35:43 AM UTC 24 |
| Peak memory | 380144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411065348 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.2411065348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.25851586 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4144106289 ps |
| CPU time | 28.1 seconds |
| Started | Oct 15 04:24:42 AM UTC 24 |
| Finished | Oct 15 04:25:12 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25851586 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.25851586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1206204127 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 23723777944 ps |
| CPU time | 424.05 seconds |
| Started | Oct 15 04:24:49 AM UTC 24 |
| Finished | Oct 15 04:31:59 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206204127 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc ess_b2b.1206204127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3609112663 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 27518807 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 04:25:41 AM UTC 24 |
| Finished | Oct 15 04:25:44 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609112663 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3609112663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_readback_err.2942212666 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 52463251 ps |
| CPU time | 1.63 seconds |
| Started | Oct 15 04:25:47 AM UTC 24 |
| Finished | Oct 15 04:25:49 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942212666 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_readback_err.2942212666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.1983686230 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 10344271825 ps |
| CPU time | 680.14 seconds |
| Started | Oct 15 04:25:26 AM UTC 24 |
| Finished | Oct 15 04:36:55 AM UTC 24 |
| Peak memory | 382340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983686230 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1983686230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.3227067107 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 222073098 ps |
| CPU time | 54.99 seconds |
| Started | Oct 15 04:24:00 AM UTC 24 |
| Finished | Oct 15 04:24:57 AM UTC 24 |
| Peak memory | 347304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227067107 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3227067107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.65487058 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 148424991610 ps |
| CPU time | 3000.98 seconds |
| Started | Oct 15 04:25:54 AM UTC 24 |
| Finished | Oct 15 05:16:26 AM UTC 24 |
| Peak memory | 385772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65487058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.65487058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1234400191 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 276294618 ps |
| CPU time | 80.4 seconds |
| Started | Oct 15 04:25:50 AM UTC 24 |
| Finished | Oct 15 04:27:12 AM UTC 24 |
| Peak memory | 343500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234400191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1234400191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3112906027 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2682432418 ps |
| CPU time | 293.42 seconds |
| Started | Oct 15 04:24:38 AM UTC 24 |
| Finished | Oct 15 04:29:35 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112906027 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.3112906027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1714875078 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 139947449 ps |
| CPU time | 45.45 seconds |
| Started | Oct 15 04:24:58 AM UTC 24 |
| Finished | Oct 15 04:25:45 AM UTC 24 |
| Peak memory | 341180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1714875078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t hroughput_w_partial_write.1714875078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3701228290 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 9427769299 ps |
| CPU time | 594.48 seconds |
| Started | Oct 15 04:27:02 AM UTC 24 |
| Finished | Oct 15 04:37:04 AM UTC 24 |
| Peak memory | 380164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701228290 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during _key_req.3701228290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3312886601 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 22276621 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 04:27:24 AM UTC 24 |
| Finished | Oct 15 04:27:26 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312886601 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3312886601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.1791150241 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 816021104 ps |
| CPU time | 54.3 seconds |
| Started | Oct 15 04:26:16 AM UTC 24 |
| Finished | Oct 15 04:27:12 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791150241 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.1791150241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.1873577741 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 10824991548 ps |
| CPU time | 676.92 seconds |
| Started | Oct 15 04:27:06 AM UTC 24 |
| Finished | Oct 15 04:38:31 AM UTC 24 |
| Peak memory | 378240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873577741 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.1873577741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3950670512 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 656988762 ps |
| CPU time | 11.13 seconds |
| Started | Oct 15 04:26:57 AM UTC 24 |
| Finished | Oct 15 04:27:09 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950670512 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.3950670512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.658821041 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 145575349 ps |
| CPU time | 19.79 seconds |
| Started | Oct 15 04:26:44 AM UTC 24 |
| Finished | Oct 15 04:27:05 AM UTC 24 |
| Peak memory | 279668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 58821041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_max _throughput.658821041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3478844752 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 71220880 ps |
| CPU time | 5.84 seconds |
| Started | Oct 15 04:27:16 AM UTC 24 |
| Finished | Oct 15 04:27:23 AM UTC 24 |
| Peak memory | 221716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478844752 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.3478844752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1430190894 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 163190883 ps |
| CPU time | 5.76 seconds |
| Started | Oct 15 04:27:13 AM UTC 24 |
| Finished | Oct 15 04:27:19 AM UTC 24 |
| Peak memory | 221776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430190894 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.1430190894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.691462198 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 8477756580 ps |
| CPU time | 591.79 seconds |
| Started | Oct 15 04:26:08 AM UTC 24 |
| Finished | Oct 15 04:36:06 AM UTC 24 |
| Peak memory | 378180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691462198 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.691462198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2515753028 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 302327395 ps |
| CPU time | 22.54 seconds |
| Started | Oct 15 04:26:37 AM UTC 24 |
| Finished | Oct 15 04:27:01 AM UTC 24 |
| Peak memory | 273728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515753028 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2515753028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.570132383 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3464835583 ps |
| CPU time | 237.59 seconds |
| Started | Oct 15 04:26:40 AM UTC 24 |
| Finished | Oct 15 04:30:41 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570132383 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acce ss_b2b.570132383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2119348519 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 31035800 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 04:27:13 AM UTC 24 |
| Finished | Oct 15 04:27:15 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119348519 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2119348519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_readback_err.2333966900 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 34232177 ps |
| CPU time | 1.65 seconds |
| Started | Oct 15 04:27:16 AM UTC 24 |
| Finished | Oct 15 04:27:19 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333966900 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_readback_err.2333966900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.4000726265 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 9575719705 ps |
| CPU time | 628.17 seconds |
| Started | Oct 15 04:27:10 AM UTC 24 |
| Finished | Oct 15 04:37:46 AM UTC 24 |
| Peak memory | 382140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000726265 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.4000726265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3932197261 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1476925751 ps |
| CPU time | 14.96 seconds |
| Started | Oct 15 04:25:58 AM UTC 24 |
| Finished | Oct 15 04:26:14 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932197261 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3932197261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2563389619 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 19438435433 ps |
| CPU time | 945.78 seconds |
| Started | Oct 15 04:27:20 AM UTC 24 |
| Finished | Oct 15 04:43:16 AM UTC 24 |
| Peak memory | 384340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256338961 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.2563389619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3190430279 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 6111605084 ps |
| CPU time | 107.97 seconds |
| Started | Oct 15 04:27:20 AM UTC 24 |
| Finished | Oct 15 04:29:11 AM UTC 24 |
| Peak memory | 337164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190430279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3190430279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.4289900637 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 4497169561 ps |
| CPU time | 248.74 seconds |
| Started | Oct 15 04:26:25 AM UTC 24 |
| Finished | Oct 15 04:30:37 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289900637 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.4289900637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1231738459 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1041037988 ps |
| CPU time | 41.12 seconds |
| Started | Oct 15 04:26:51 AM UTC 24 |
| Finished | Oct 15 04:27:34 AM UTC 24 |
| Peak memory | 310376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1231738459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t hroughput_w_partial_write.1231738459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3807195196 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 22112866184 ps |
| CPU time | 1300.05 seconds |
| Started | Oct 15 04:28:03 AM UTC 24 |
| Finished | Oct 15 04:49:57 AM UTC 24 |
| Peak memory | 382340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807195196 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during _key_req.3807195196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1265874166 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 24073327 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 04:28:49 AM UTC 24 |
| Finished | Oct 15 04:28:51 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265874166 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1265874166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.3810526014 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 21575777791 ps |
| CPU time | 87.16 seconds |
| Started | Oct 15 04:27:30 AM UTC 24 |
| Finished | Oct 15 04:28:59 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810526014 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.3810526014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1620059346 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 173268329271 ps |
| CPU time | 885.01 seconds |
| Started | Oct 15 04:28:05 AM UTC 24 |
| Finished | Oct 15 04:43:00 AM UTC 24 |
| Peak memory | 382200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620059346 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1620059346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3659005627 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3047789133 ps |
| CPU time | 8.77 seconds |
| Started | Oct 15 04:28:03 AM UTC 24 |
| Finished | Oct 15 04:28:13 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659005627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.3659005627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2078484585 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 430295701 ps |
| CPU time | 46.56 seconds |
| Started | Oct 15 04:27:57 AM UTC 24 |
| Finished | Oct 15 04:28:45 AM UTC 24 |
| Peak memory | 326840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 078484585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ma x_throughput.2078484585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2013785652 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 158392838 ps |
| CPU time | 6.86 seconds |
| Started | Oct 15 04:28:39 AM UTC 24 |
| Finished | Oct 15 04:28:47 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013785652 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2013785652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.791151367 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 144213912 ps |
| CPU time | 8.22 seconds |
| Started | Oct 15 04:28:37 AM UTC 24 |
| Finished | Oct 15 04:28:46 AM UTC 24 |
| Peak memory | 221588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791151367 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.791151367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.439895184 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 17799024696 ps |
| CPU time | 532.37 seconds |
| Started | Oct 15 04:27:28 AM UTC 24 |
| Finished | Oct 15 04:36:27 AM UTC 24 |
| Peak memory | 378108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439895184 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.439895184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.4034582883 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 294326374 ps |
| CPU time | 18.8 seconds |
| Started | Oct 15 04:27:36 AM UTC 24 |
| Finished | Oct 15 04:27:56 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034582883 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.4034582883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2014869792 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 12891325573 ps |
| CPU time | 298.41 seconds |
| Started | Oct 15 04:27:53 AM UTC 24 |
| Finished | Oct 15 04:32:55 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014869792 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc ess_b2b.2014869792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2384358684 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 82605599 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 04:28:34 AM UTC 24 |
| Finished | Oct 15 04:28:36 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384358684 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2384358684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_readback_err.526165158 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 39067891 ps |
| CPU time | 1.56 seconds |
| Started | Oct 15 04:28:45 AM UTC 24 |
| Finished | Oct 15 04:28:48 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526165158 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_readback_err.526165158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.545007852 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 158363959956 ps |
| CPU time | 1163.63 seconds |
| Started | Oct 15 04:28:13 AM UTC 24 |
| Finished | Oct 15 04:47:49 AM UTC 24 |
| Peak memory | 378120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545007852 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.545007852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.2973958497 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 89963951 ps |
| CPU time | 3.78 seconds |
| Started | Oct 15 04:27:24 AM UTC 24 |
| Finished | Oct 15 04:27:29 AM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973958497 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2973958497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1435232697 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 17398125048 ps |
| CPU time | 962.1 seconds |
| Started | Oct 15 04:28:48 AM UTC 24 |
| Finished | Oct 15 04:45:00 AM UTC 24 |
| Peak memory | 384204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143523269 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.1435232697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.942459432 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 4401271315 ps |
| CPU time | 98.14 seconds |
| Started | Oct 15 04:28:47 AM UTC 24 |
| Finished | Oct 15 04:30:27 AM UTC 24 |
| Peak memory | 357636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942459432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.942459432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1758173609 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 3110862070 ps |
| CPU time | 309.88 seconds |
| Started | Oct 15 04:27:35 AM UTC 24 |
| Finished | Oct 15 04:32:49 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758173609 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.1758173609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2734239741 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 91443445 ps |
| CPU time | 3.02 seconds |
| Started | Oct 15 04:28:00 AM UTC 24 |
| Finished | Oct 15 04:28:04 AM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2734239741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t hroughput_w_partial_write.2734239741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2747767625 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 5644646981 ps |
| CPU time | 188.72 seconds |
| Started | Oct 15 04:30:15 AM UTC 24 |
| Finished | Oct 15 04:33:27 AM UTC 24 |
| Peak memory | 361688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747767625 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during _key_req.2747767625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3125168256 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 55051190 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 04:30:48 AM UTC 24 |
| Finished | Oct 15 04:30:50 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125168256 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.3125168256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.1345731256 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3111146009 ps |
| CPU time | 72.11 seconds |
| Started | Oct 15 04:29:11 AM UTC 24 |
| Finished | Oct 15 04:30:25 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345731256 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.1345731256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.2635347292 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1701436718 ps |
| CPU time | 135.76 seconds |
| Started | Oct 15 04:30:26 AM UTC 24 |
| Finished | Oct 15 04:32:44 AM UTC 24 |
| Peak memory | 373944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635347292 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.2635347292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1100056600 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 551397550 ps |
| CPU time | 7.68 seconds |
| Started | Oct 15 04:30:05 AM UTC 24 |
| Finished | Oct 15 04:30:14 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100056600 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.1100056600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1156312996 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 104291070 ps |
| CPU time | 50.2 seconds |
| Started | Oct 15 04:29:36 AM UTC 24 |
| Finished | Oct 15 04:30:28 AM UTC 24 |
| Peak memory | 318652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 156312996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma x_throughput.1156312996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2647290162 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 158089392 ps |
| CPU time | 7.59 seconds |
| Started | Oct 15 04:30:38 AM UTC 24 |
| Finished | Oct 15 04:30:47 AM UTC 24 |
| Peak memory | 221784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647290162 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.2647290162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3922732438 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1376934852 ps |
| CPU time | 7.94 seconds |
| Started | Oct 15 04:30:32 AM UTC 24 |
| Finished | Oct 15 04:30:42 AM UTC 24 |
| Peak memory | 221588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922732438 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.3922732438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1970704544 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 3622692065 ps |
| CPU time | 657.38 seconds |
| Started | Oct 15 04:28:59 AM UTC 24 |
| Finished | Oct 15 04:40:04 AM UTC 24 |
| Peak memory | 361636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970704544 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.1970704544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2209525261 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 54619272 ps |
| CPU time | 1.75 seconds |
| Started | Oct 15 04:29:19 AM UTC 24 |
| Finished | Oct 15 04:29:21 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209525261 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.2209525261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1258208548 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 16402800175 ps |
| CPU time | 312.91 seconds |
| Started | Oct 15 04:29:22 AM UTC 24 |
| Finished | Oct 15 04:34:39 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258208548 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc ess_b2b.1258208548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1534402832 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 35136670 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 04:30:29 AM UTC 24 |
| Finished | Oct 15 04:30:31 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534402832 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1534402832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_readback_err.3031392947 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 28368090 ps |
| CPU time | 1.61 seconds |
| Started | Oct 15 04:30:43 AM UTC 24 |
| Finished | Oct 15 04:30:45 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031392947 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_readback_err.3031392947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.4269354226 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 4473810349 ps |
| CPU time | 335.13 seconds |
| Started | Oct 15 04:30:29 AM UTC 24 |
| Finished | Oct 15 04:36:09 AM UTC 24 |
| Peak memory | 345284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269354226 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.4269354226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.1744264507 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 977448348 ps |
| CPU time | 16.98 seconds |
| Started | Oct 15 04:28:52 AM UTC 24 |
| Finished | Oct 15 04:29:10 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744264507 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1744264507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.479940398 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 6716589728 ps |
| CPU time | 1965.48 seconds |
| Started | Oct 15 04:30:46 AM UTC 24 |
| Finished | Oct 15 05:03:52 AM UTC 24 |
| Peak memory | 396012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479940398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.479940398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.57819649 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2455059575 ps |
| CPU time | 137.75 seconds |
| Started | Oct 15 04:30:43 AM UTC 24 |
| Finished | Oct 15 04:33:03 AM UTC 24 |
| Peak memory | 363912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57819649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.57819649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.912275879 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 9803841377 ps |
| CPU time | 249.46 seconds |
| Started | Oct 15 04:29:11 AM UTC 24 |
| Finished | Oct 15 04:33:25 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912275879 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.912275879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3217922419 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 584933861 ps |
| CPU time | 83.6 seconds |
| Started | Oct 15 04:29:41 AM UTC 24 |
| Finished | Oct 15 04:31:07 AM UTC 24 |
| Peak memory | 375992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3217922419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t hroughput_w_partial_write.3217922419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3197694064 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 11781614247 ps |
| CPU time | 569.14 seconds |
| Started | Oct 15 03:12:45 AM UTC 24 |
| Finished | Oct 15 03:22:22 AM UTC 24 |
| Peak memory | 382204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197694064 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_ key_req.3197694064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.353722359 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 32308333 ps |
| CPU time | 0.82 seconds |
| Started | Oct 15 03:13:40 AM UTC 24 |
| Finished | Oct 15 03:13:42 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353722359 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.353722359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.3059817811 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 17844376409 ps |
| CPU time | 98.52 seconds |
| Started | Oct 15 03:11:21 AM UTC 24 |
| Finished | Oct 15 03:13:02 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059817811 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.3059817811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.3577221384 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 30104470059 ps |
| CPU time | 576.15 seconds |
| Started | Oct 15 03:12:47 AM UTC 24 |
| Finished | Oct 15 03:22:30 AM UTC 24 |
| Peak memory | 382328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577221384 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.3577221384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.409045687 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 410546964 ps |
| CPU time | 2.37 seconds |
| Started | Oct 15 03:12:43 AM UTC 24 |
| Finished | Oct 15 03:12:46 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409045687 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.409045687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3316836701 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 286194872 ps |
| CPU time | 30 seconds |
| Started | Oct 15 03:12:36 AM UTC 24 |
| Finished | Oct 15 03:13:07 AM UTC 24 |
| Peak memory | 288056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 316836701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max _throughput.3316836701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.540767298 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 153892002 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 03:13:23 AM UTC 24 |
| Finished | Oct 15 03:13:28 AM UTC 24 |
| Peak memory | 221652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540767298 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.540767298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2844407162 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 142165425 ps |
| CPU time | 12.33 seconds |
| Started | Oct 15 03:13:11 AM UTC 24 |
| Finished | Oct 15 03:13:25 AM UTC 24 |
| Peak memory | 221580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844407162 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.2844407162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2439274430 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 22378426276 ps |
| CPU time | 333.4 seconds |
| Started | Oct 15 03:11:19 AM UTC 24 |
| Finished | Oct 15 03:16:57 AM UTC 24 |
| Peak memory | 345460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439274430 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.2439274430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1851554261 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 667479944 ps |
| CPU time | 71.99 seconds |
| Started | Oct 15 03:11:30 AM UTC 24 |
| Finished | Oct 15 03:12:44 AM UTC 24 |
| Peak memory | 345396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851554261 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.1851554261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1725395808 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 46477167203 ps |
| CPU time | 289.8 seconds |
| Started | Oct 15 03:11:40 AM UTC 24 |
| Finished | Oct 15 03:16:34 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725395808 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce ss_b2b.1725395808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3612261379 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 106365914 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 03:13:08 AM UTC 24 |
| Finished | Oct 15 03:13:10 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612261379 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3612261379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_readback_err.2810466919 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 52695224 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 03:13:26 AM UTC 24 |
| Finished | Oct 15 03:13:28 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810466919 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_readback_err.2810466919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2307298304 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 32030560458 ps |
| CPU time | 1166.04 seconds |
| Started | Oct 15 03:13:02 AM UTC 24 |
| Finished | Oct 15 03:32:41 AM UTC 24 |
| Peak memory | 382164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307298304 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2307298304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.4200126524 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2640751745 ps |
| CPU time | 21.27 seconds |
| Started | Oct 15 03:11:17 AM UTC 24 |
| Finished | Oct 15 03:11:39 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200126524 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4200126524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2660445484 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 46056598122 ps |
| CPU time | 2787.53 seconds |
| Started | Oct 15 03:13:29 AM UTC 24 |
| Finished | Oct 15 04:00:26 AM UTC 24 |
| Peak memory | 385776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266044548 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.2660445484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1668734868 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 14109318496 ps |
| CPU time | 368.37 seconds |
| Started | Oct 15 03:11:26 AM UTC 24 |
| Finished | Oct 15 03:17:40 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668734868 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.1668734868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1469270052 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 142936559 ps |
| CPU time | 63.31 seconds |
| Started | Oct 15 03:12:37 AM UTC 24 |
| Finished | Oct 15 03:13:42 AM UTC 24 |
| Peak memory | 359736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1469270052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th roughput_w_partial_write.1469270052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2835088938 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2872464386 ps |
| CPU time | 666.71 seconds |
| Started | Oct 15 03:15:02 AM UTC 24 |
| Finished | Oct 15 03:26:17 AM UTC 24 |
| Peak memory | 380124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835088938 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_ key_req.2835088938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3476506389 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 42346283 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 03:16:13 AM UTC 24 |
| Finished | Oct 15 03:16:15 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476506389 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3476506389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1210793087 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 436605414 ps |
| CPU time | 25.51 seconds |
| Started | Oct 15 03:14:11 AM UTC 24 |
| Finished | Oct 15 03:14:38 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210793087 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.1210793087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.774778799 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5357029260 ps |
| CPU time | 648.75 seconds |
| Started | Oct 15 03:15:03 AM UTC 24 |
| Finished | Oct 15 03:26:00 AM UTC 24 |
| Peak memory | 382140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774778799 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.774778799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2135915882 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 796875239 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 03:14:59 AM UTC 24 |
| Finished | Oct 15 03:15:03 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135915882 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2135915882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1503426992 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 122164118 ps |
| CPU time | 63.46 seconds |
| Started | Oct 15 03:14:47 AM UTC 24 |
| Finished | Oct 15 03:15:52 AM UTC 24 |
| Peak memory | 357624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 503426992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max _throughput.1503426992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1248135038 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 201661899 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 03:15:41 AM UTC 24 |
| Finished | Oct 15 03:15:46 AM UTC 24 |
| Peak memory | 221648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248135038 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.1248135038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1688294037 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 228853658 ps |
| CPU time | 7.03 seconds |
| Started | Oct 15 03:15:32 AM UTC 24 |
| Finished | Oct 15 03:15:40 AM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688294037 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.1688294037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2425117522 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 22122242147 ps |
| CPU time | 1014.33 seconds |
| Started | Oct 15 03:13:43 AM UTC 24 |
| Finished | Oct 15 03:30:49 AM UTC 24 |
| Peak memory | 384164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425117522 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.2425117522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1949550191 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2146620741 ps |
| CPU time | 21.97 seconds |
| Started | Oct 15 03:14:39 AM UTC 24 |
| Finished | Oct 15 03:15:02 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949550191 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1949550191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3658375329 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4452913065 ps |
| CPU time | 318.4 seconds |
| Started | Oct 15 03:14:45 AM UTC 24 |
| Finished | Oct 15 03:20:07 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658375329 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce ss_b2b.3658375329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1811880699 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 83213400 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 03:15:29 AM UTC 24 |
| Finished | Oct 15 03:15:31 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811880699 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1811880699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_readback_err.1651636130 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 49206029 ps |
| CPU time | 1.94 seconds |
| Started | Oct 15 03:15:47 AM UTC 24 |
| Finished | Oct 15 03:15:51 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651636130 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_readback_err.1651636130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.264395514 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 28575388852 ps |
| CPU time | 862.2 seconds |
| Started | Oct 15 03:15:15 AM UTC 24 |
| Finished | Oct 15 03:29:47 AM UTC 24 |
| Peak memory | 373952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264395514 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.264395514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.680399872 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 636537011 ps |
| CPU time | 73.61 seconds |
| Started | Oct 15 03:13:43 AM UTC 24 |
| Finished | Oct 15 03:14:59 AM UTC 24 |
| Peak memory | 357512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680399872 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.680399872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.4244325577 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 36157743300 ps |
| CPU time | 2312.01 seconds |
| Started | Oct 15 03:15:53 AM UTC 24 |
| Finished | Oct 15 03:54:48 AM UTC 24 |
| Peak memory | 385708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424432557 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.4244325577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4275262076 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4259446359 ps |
| CPU time | 469.86 seconds |
| Started | Oct 15 03:15:51 AM UTC 24 |
| Finished | Oct 15 03:23:47 AM UTC 24 |
| Peak memory | 386572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275262076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.4275262076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3169053434 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 22262474614 ps |
| CPU time | 469.64 seconds |
| Started | Oct 15 03:14:26 AM UTC 24 |
| Finished | Oct 15 03:22:23 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169053434 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.3169053434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2943378858 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 358709713 ps |
| CPU time | 29.58 seconds |
| Started | Oct 15 03:14:57 AM UTC 24 |
| Finished | Oct 15 03:15:28 AM UTC 24 |
| Peak memory | 287856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2943378858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th roughput_w_partial_write.2943378858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1664707858 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2677487910 ps |
| CPU time | 827.88 seconds |
| Started | Oct 15 03:16:58 AM UTC 24 |
| Finished | Oct 15 03:30:55 AM UTC 24 |
| Peak memory | 382208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664707858 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_ key_req.1664707858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.228003058 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 46124023 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 03:18:14 AM UTC 24 |
| Finished | Oct 15 03:18:16 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228003058 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.228003058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.679181906 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4294587760 ps |
| CPU time | 32.85 seconds |
| Started | Oct 15 03:16:15 AM UTC 24 |
| Finished | Oct 15 03:16:49 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679181906 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.679181906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.1342599948 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 15293136922 ps |
| CPU time | 320.05 seconds |
| Started | Oct 15 03:17:01 AM UTC 24 |
| Finished | Oct 15 03:22:25 AM UTC 24 |
| Peak memory | 353528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342599948 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.1342599948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3966481536 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2497251973 ps |
| CPU time | 9.48 seconds |
| Started | Oct 15 03:16:50 AM UTC 24 |
| Finished | Oct 15 03:17:00 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966481536 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3966481536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3361510316 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 869516577 ps |
| CPU time | 119.36 seconds |
| Started | Oct 15 03:16:40 AM UTC 24 |
| Finished | Oct 15 03:18:41 AM UTC 24 |
| Peak memory | 377972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 361510316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max _throughput.3361510316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1837033492 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 421405247 ps |
| CPU time | 7.14 seconds |
| Started | Oct 15 03:18:02 AM UTC 24 |
| Finished | Oct 15 03:18:11 AM UTC 24 |
| Peak memory | 221708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837033492 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.1837033492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3556141242 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 688749631 ps |
| CPU time | 11.01 seconds |
| Started | Oct 15 03:17:49 AM UTC 24 |
| Finished | Oct 15 03:18:01 AM UTC 24 |
| Peak memory | 221468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556141242 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.3556141242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3043807919 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 20642397890 ps |
| CPU time | 697.85 seconds |
| Started | Oct 15 03:16:14 AM UTC 24 |
| Finished | Oct 15 03:28:00 AM UTC 24 |
| Peak memory | 382200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043807919 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.3043807919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2920866512 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 225530025 ps |
| CPU time | 2.01 seconds |
| Started | Oct 15 03:16:35 AM UTC 24 |
| Finished | Oct 15 03:16:38 AM UTC 24 |
| Peak memory | 209820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920866512 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.2920866512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.619525618 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 165036685793 ps |
| CPU time | 551.19 seconds |
| Started | Oct 15 03:16:36 AM UTC 24 |
| Finished | Oct 15 03:25:54 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619525618 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acces s_b2b.619525618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.559885544 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 53132322 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 03:17:46 AM UTC 24 |
| Finished | Oct 15 03:17:48 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559885544 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.559885544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_readback_err.3410850992 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 96369179 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 03:18:11 AM UTC 24 |
| Finished | Oct 15 03:18:13 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410850992 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_readback_err.3410850992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.4227544253 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 17925807973 ps |
| CPU time | 506.53 seconds |
| Started | Oct 15 03:17:40 AM UTC 24 |
| Finished | Oct 15 03:26:13 AM UTC 24 |
| Peak memory | 384328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227544253 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.4227544253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2532378794 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 7382442964 ps |
| CPU time | 1039.49 seconds |
| Started | Oct 15 03:18:12 AM UTC 24 |
| Finished | Oct 15 03:35:42 AM UTC 24 |
| Peak memory | 382416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253237879 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.2532378794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2153214469 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1488941334 ps |
| CPU time | 535.89 seconds |
| Started | Oct 15 03:18:11 AM UTC 24 |
| Finished | Oct 15 03:27:13 AM UTC 24 |
| Peak memory | 378184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153214469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2153214469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2221486980 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2933538577 ps |
| CPU time | 332.19 seconds |
| Started | Oct 15 03:16:15 AM UTC 24 |
| Finished | Oct 15 03:21:52 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221486980 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.2221486980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3733304534 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 593390080 ps |
| CPU time | 100.06 seconds |
| Started | Oct 15 03:16:43 AM UTC 24 |
| Finished | Oct 15 03:18:25 AM UTC 24 |
| Peak memory | 378164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3733304534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th roughput_w_partial_write.3733304534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1386239365 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 20788231017 ps |
| CPU time | 2137.69 seconds |
| Started | Oct 15 03:18:48 AM UTC 24 |
| Finished | Oct 15 03:54:48 AM UTC 24 |
| Peak memory | 383724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386239365 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_ key_req.1386239365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.401271929 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 17172576 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:19:14 AM UTC 24 |
| Finished | Oct 15 03:19:16 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401271929 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.401271929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2753029962 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3022267996 ps |
| CPU time | 78.97 seconds |
| Started | Oct 15 03:18:23 AM UTC 24 |
| Finished | Oct 15 03:19:44 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753029962 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.2753029962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1533501618 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4329447769 ps |
| CPU time | 470.43 seconds |
| Started | Oct 15 03:18:50 AM UTC 24 |
| Finished | Oct 15 03:26:46 AM UTC 24 |
| Peak memory | 382268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533501618 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1533501618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1230356303 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 677510426 ps |
| CPU time | 5.1 seconds |
| Started | Oct 15 03:18:47 AM UTC 24 |
| Finished | Oct 15 03:18:53 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230356303 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.1230356303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4066709932 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 166674675 ps |
| CPU time | 5.6 seconds |
| Started | Oct 15 03:18:40 AM UTC 24 |
| Finished | Oct 15 03:18:47 AM UTC 24 |
| Peak memory | 230524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 066709932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max _throughput.4066709932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3350383780 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 908900266 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 03:18:58 AM UTC 24 |
| Finished | Oct 15 03:19:03 AM UTC 24 |
| Peak memory | 221592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350383780 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.3350383780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1112452729 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 599121891 ps |
| CPU time | 14.5 seconds |
| Started | Oct 15 03:18:57 AM UTC 24 |
| Finished | Oct 15 03:19:13 AM UTC 24 |
| Peak memory | 221604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112452729 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.1112452729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.4212470622 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 10462686519 ps |
| CPU time | 752.09 seconds |
| Started | Oct 15 03:18:21 AM UTC 24 |
| Finished | Oct 15 03:31:01 AM UTC 24 |
| Peak memory | 384256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212470622 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.4212470622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3713091424 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2286607023 ps |
| CPU time | 12.52 seconds |
| Started | Oct 15 03:18:32 AM UTC 24 |
| Finished | Oct 15 03:18:46 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713091424 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3713091424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.855773777 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 190520247026 ps |
| CPU time | 541.91 seconds |
| Started | Oct 15 03:18:37 AM UTC 24 |
| Finished | Oct 15 03:27:46 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855773777 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acces s_b2b.855773777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3847118419 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 31125832 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 03:18:55 AM UTC 24 |
| Finished | Oct 15 03:18:57 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847118419 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3847118419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1055668655 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 123351681 ps |
| CPU time | 1.5 seconds |
| Started | Oct 15 03:19:03 AM UTC 24 |
| Finished | Oct 15 03:19:06 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055668655 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_readback_err.1055668655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3358548650 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 10970188654 ps |
| CPU time | 1051.77 seconds |
| Started | Oct 15 03:18:54 AM UTC 24 |
| Finished | Oct 15 03:36:37 AM UTC 24 |
| Peak memory | 382348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358548650 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3358548650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.339707787 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 138787036 ps |
| CPU time | 13.14 seconds |
| Started | Oct 15 03:18:17 AM UTC 24 |
| Finished | Oct 15 03:18:31 AM UTC 24 |
| Peak memory | 275668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339707787 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.339707787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3728964516 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 66658163235 ps |
| CPU time | 1313.12 seconds |
| Started | Oct 15 03:19:06 AM UTC 24 |
| Finished | Oct 15 03:41:12 AM UTC 24 |
| Peak memory | 392388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372896451 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.3728964516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.10400518 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9745589458 ps |
| CPU time | 44.52 seconds |
| Started | Oct 15 03:19:04 AM UTC 24 |
| Finished | Oct 15 03:19:50 AM UTC 24 |
| Peak memory | 296216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10400518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.10400518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1980138559 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 15402447397 ps |
| CPU time | 464.89 seconds |
| Started | Oct 15 03:18:25 AM UTC 24 |
| Finished | Oct 15 03:26:16 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980138559 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.1980138559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2638376555 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 205817195 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 03:18:43 AM UTC 24 |
| Finished | Oct 15 03:18:49 AM UTC 24 |
| Peak memory | 244992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2638376555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th roughput_w_partial_write.2638376555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.270292123 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 12426471844 ps |
| CPU time | 821.63 seconds |
| Started | Oct 15 03:20:25 AM UTC 24 |
| Finished | Oct 15 03:34:16 AM UTC 24 |
| Peak memory | 382212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270292123 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_k ey_req.270292123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2194902139 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 45351911 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 03:21:22 AM UTC 24 |
| Finished | Oct 15 03:21:24 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194902139 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2194902139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.830829943 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2314824151 ps |
| CPU time | 33.9 seconds |
| Started | Oct 15 03:19:45 AM UTC 24 |
| Finished | Oct 15 03:20:20 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830829943 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.830829943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3218662778 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 26162316157 ps |
| CPU time | 895.76 seconds |
| Started | Oct 15 03:20:31 AM UTC 24 |
| Finished | Oct 15 03:35:36 AM UTC 24 |
| Peak memory | 382140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218662778 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.3218662778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2484489208 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 931543938 ps |
| CPU time | 15.22 seconds |
| Started | Oct 15 03:20:21 AM UTC 24 |
| Finished | Oct 15 03:20:37 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484489208 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2484489208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.4197791728 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 158937073 ps |
| CPU time | 53.19 seconds |
| Started | Oct 15 03:20:09 AM UTC 24 |
| Finished | Oct 15 03:21:03 AM UTC 24 |
| Peak memory | 318776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 197791728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max _throughput.4197791728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.449150212 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 131825508 ps |
| CPU time | 3.56 seconds |
| Started | Oct 15 03:21:04 AM UTC 24 |
| Finished | Oct 15 03:21:08 AM UTC 24 |
| Peak memory | 221572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449150212 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.449150212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1816660703 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 74318861 ps |
| CPU time | 5.96 seconds |
| Started | Oct 15 03:20:57 AM UTC 24 |
| Finished | Oct 15 03:21:04 AM UTC 24 |
| Peak memory | 221764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816660703 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1816660703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.4069919167 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2074835012 ps |
| CPU time | 204.14 seconds |
| Started | Oct 15 03:19:34 AM UTC 24 |
| Finished | Oct 15 03:23:01 AM UTC 24 |
| Peak memory | 367872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069919167 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.4069919167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.983039358 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 852027936 ps |
| CPU time | 82.62 seconds |
| Started | Oct 15 03:19:56 AM UTC 24 |
| Finished | Oct 15 03:21:21 AM UTC 24 |
| Peak memory | 363832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983039358 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.983039358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1204269913 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 31104445250 ps |
| CPU time | 303.84 seconds |
| Started | Oct 15 03:20:01 AM UTC 24 |
| Finished | Oct 15 03:25:10 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204269913 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acce ss_b2b.1204269913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3676900439 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 125694615 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:20:54 AM UTC 24 |
| Finished | Oct 15 03:20:56 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676900439 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3676900439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_readback_err.4002866844 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 34164339 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 03:21:05 AM UTC 24 |
| Finished | Oct 15 03:21:07 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002866844 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_readback_err.4002866844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.385165969 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 13054737697 ps |
| CPU time | 1152.03 seconds |
| Started | Oct 15 03:20:38 AM UTC 24 |
| Finished | Oct 15 03:40:03 AM UTC 24 |
| Peak memory | 380172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385165969 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.385165969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1144628698 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 505882991 ps |
| CPU time | 57.67 seconds |
| Started | Oct 15 03:19:17 AM UTC 24 |
| Finished | Oct 15 03:20:16 AM UTC 24 |
| Peak memory | 341124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144628698 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1144628698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1034567202 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 15508096350 ps |
| CPU time | 1786.12 seconds |
| Started | Oct 15 03:21:09 AM UTC 24 |
| Finished | Oct 15 03:51:15 AM UTC 24 |
| Peak memory | 386480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103456720 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.1034567202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3062981550 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3114216118 ps |
| CPU time | 287.38 seconds |
| Started | Oct 15 03:19:51 AM UTC 24 |
| Finished | Oct 15 03:24:42 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062981550 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.3062981550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4191806439 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 218375281 ps |
| CPU time | 6.25 seconds |
| Started | Oct 15 03:20:17 AM UTC 24 |
| Finished | Oct 15 03:20:24 AM UTC 24 |
| Peak memory | 244864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4191806439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th roughput_w_partial_write.4191806439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |