| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.98 | 99.16 | 94.49 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
| T1001 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.830947339 | Feb 08 10:03:37 AM UTC 25 | Feb 08 10:03:43 AM UTC 25 | 597251596 ps | ||
| T1002 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.681254766 | Feb 08 10:03:41 AM UTC 25 | Feb 08 10:03:44 AM UTC 25 | 41101435 ps | ||
| T1003 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3754940031 | Feb 08 10:03:42 AM UTC 25 | Feb 08 10:03:46 AM UTC 25 | 111343640 ps | ||
| T1004 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3293105110 | Feb 08 10:03:40 AM UTC 25 | Feb 08 10:03:46 AM UTC 25 | 318797445 ps | ||
| T1005 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4045987412 | Feb 08 10:03:44 AM UTC 25 | Feb 08 10:03:46 AM UTC 25 | 91473074 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2924297612 | Feb 08 10:03:44 AM UTC 25 | Feb 08 10:03:46 AM UTC 25 | 120427514 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4211845501 | Feb 08 10:03:39 AM UTC 25 | Feb 08 10:03:47 AM UTC 25 | 1494988152 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.310747470 | Feb 08 10:03:39 AM UTC 25 | Feb 08 10:03:47 AM UTC 25 | 606269838 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1847961234 | Feb 08 10:03:44 AM UTC 25 | Feb 08 10:03:49 AM UTC 25 | 217242115 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3939706321 | Feb 08 10:03:44 AM UTC 25 | Feb 08 10:03:50 AM UTC 25 | 203267189 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.549785744 | Feb 08 10:03:47 AM UTC 25 | Feb 08 10:03:50 AM UTC 25 | 11624776 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1784071875 | Feb 08 10:03:47 AM UTC 25 | Feb 08 10:03:50 AM UTC 25 | 30743434 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3344274919 | Feb 08 10:03:43 AM UTC 25 | Feb 08 10:03:50 AM UTC 25 | 466856071 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1283948529 | Feb 08 10:03:45 AM UTC 25 | Feb 08 10:03:50 AM UTC 25 | 38350780 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3188456627 | Feb 08 10:03:47 AM UTC 25 | Feb 08 10:03:50 AM UTC 25 | 81157882 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2191778657 | Feb 08 10:03:46 AM UTC 25 | Feb 08 10:03:51 AM UTC 25 | 97458114 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2683975300 | Feb 08 10:03:47 AM UTC 25 | Feb 08 10:03:51 AM UTC 25 | 585646039 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3475860445 | Feb 08 10:03:47 AM UTC 25 | Feb 08 10:03:51 AM UTC 25 | 224705887 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3561462290 | Feb 08 10:03:45 AM UTC 25 | Feb 08 10:03:52 AM UTC 25 | 1576369376 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3547137771 | Feb 08 10:03:49 AM UTC 25 | Feb 08 10:03:52 AM UTC 25 | 41608533 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1738576236 | Feb 08 10:03:50 AM UTC 25 | Feb 08 10:03:53 AM UTC 25 | 59438138 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1235775570 | Feb 08 10:03:49 AM UTC 25 | Feb 08 10:03:53 AM UTC 25 | 135572858 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3808281670 | Feb 08 10:03:51 AM UTC 25 | Feb 08 10:03:55 AM UTC 25 | 184128390 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.468526221 | Feb 08 10:03:49 AM UTC 25 | Feb 08 10:03:55 AM UTC 25 | 236417095 ps |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.851908330 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3751476038 ps |
| CPU time | 8.01 seconds |
| Started | Feb 08 11:36:48 AM UTC 25 |
| Finished | Feb 08 11:36:57 AM UTC 25 |
| Peak memory | 223868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851908330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.851908330 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3953752583 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 920186935 ps |
| CPU time | 4.94 seconds |
| Started | Feb 08 11:37:16 AM UTC 25 |
| Finished | Feb 08 11:37:23 AM UTC 25 |
| Peak memory | 213488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953752583 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.3953752583 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1232858980 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1590317579 ps |
| CPU time | 97.97 seconds |
| Started | Feb 08 11:37:25 AM UTC 25 |
| Finished | Feb 08 11:39:06 AM UTC 25 |
| Peak memory | 348044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232858980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1232858980 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2143557783 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 691049542 ps |
| CPU time | 4.54 seconds |
| Started | Feb 08 11:36:48 AM UTC 25 |
| Finished | Feb 08 11:36:54 AM UTC 25 |
| Peak memory | 256568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143557783 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2143557783 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.1202055391 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 19739164826 ps |
| CPU time | 498.71 seconds |
| Started | Feb 08 11:36:46 AM UTC 25 |
| Finished | Feb 08 11:45:11 AM UTC 25 |
| Peak memory | 376528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202055391 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1202055391 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2451314622 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 438941752 ps |
| CPU time | 3.47 seconds |
| Started | Feb 08 10:03:10 AM UTC 25 |
| Finished | Feb 08 10:03:15 AM UTC 25 |
| Peak memory | 221996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451314622 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_intg_err.2451314622 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2550474902 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 61527357 ps |
| CPU time | 4.22 seconds |
| Started | Feb 08 11:36:47 AM UTC 25 |
| Finished | Feb 08 11:36:53 AM UTC 25 |
| Peak memory | 223676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550474902 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.2550474902 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.759660118 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 678810982 ps |
| CPU time | 12.62 seconds |
| Started | Feb 08 11:37:54 AM UTC 25 |
| Finished | Feb 08 11:38:08 AM UTC 25 |
| Peak memory | 227912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759660118 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.759660118 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3815227630 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 18024868397 ps |
| CPU time | 224.14 seconds |
| Started | Feb 08 11:38:43 AM UTC 25 |
| Finished | Feb 08 11:42:31 AM UTC 25 |
| Peak memory | 213572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815227630 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access_b2b.3815227630 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2718891129 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 773665049 ps |
| CPU time | 3.31 seconds |
| Started | Feb 08 10:02:18 AM UTC 25 |
| Finished | Feb 08 10:02:22 AM UTC 25 |
| Peak memory | 211460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718891129 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2718891129 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3840063225 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 12169284496 ps |
| CPU time | 672.91 seconds |
| Started | Feb 08 11:40:01 AM UTC 25 |
| Finished | Feb 08 11:51:22 AM UTC 25 |
| Peak memory | 384596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840063225 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.3840063225 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3543619052 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 85457371 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 11:38:05 AM UTC 25 |
| Finished | Feb 08 11:38:08 AM UTC 25 |
| Peak memory | 212500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543619052 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3543619052 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.2134342351 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11211265362 ps |
| CPU time | 325.2 seconds |
| Started | Feb 08 11:38:04 AM UTC 25 |
| Finished | Feb 08 11:43:35 AM UTC 25 |
| Peak memory | 343692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134342351 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2134342351 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3931444002 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 263934364 ps |
| CPU time | 3.27 seconds |
| Started | Feb 08 10:03:35 AM UTC 25 |
| Finished | Feb 08 10:03:40 AM UTC 25 |
| Peak memory | 211812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931444002 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_intg_err.3931444002 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1829394964 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 15864886 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 11:38:29 AM UTC 25 |
| Finished | Feb 08 11:38:31 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829394964 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1829394964 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.182994878 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 32188150636 ps |
| CPU time | 2043.24 seconds |
| Started | Feb 08 11:36:48 AM UTC 25 |
| Finished | Feb 08 12:11:12 PM UTC 25 |
| Peak memory | 388524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182994878 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.182994878 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2683552823 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6023037974 ps |
| CPU time | 102.43 seconds |
| Started | Feb 08 11:36:55 AM UTC 25 |
| Finished | Feb 08 11:38:41 AM UTC 25 |
| Peak memory | 292744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683552823 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_key_req.2683552823 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2390300940 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 297189456 ps |
| CPU time | 4.52 seconds |
| Started | Feb 08 10:03:07 AM UTC 25 |
| Finished | Feb 08 10:03:13 AM UTC 25 |
| Peak memory | 221716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390300940 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_intg_err.2390300940 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4105015455 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1791350649 ps |
| CPU time | 75.16 seconds |
| Started | Feb 08 11:36:59 AM UTC 25 |
| Finished | Feb 08 11:38:17 AM UTC 25 |
| Peak memory | 296628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105015455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.4105015455 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.686163307 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 98301280 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 10:03:25 AM UTC 25 |
| Finished | Feb 08 10:03:28 AM UTC 25 |
| Peak memory | 210148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686163307 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_intg_err.686163307 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1575066244 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 29060984566 ps |
| CPU time | 1144.11 seconds |
| Started | Feb 08 11:37:00 AM UTC 25 |
| Finished | Feb 08 11:56:17 AM UTC 25 |
| Peak memory | 384884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575066244 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.1575066244 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2347560794 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 57654310 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 10:02:38 AM UTC 25 |
| Finished | Feb 08 10:02:41 AM UTC 25 |
| Peak memory | 210200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347560794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.2347560794 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3415147694 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 16702111 ps |
| CPU time | 1 seconds |
| Started | Feb 08 11:36:48 AM UTC 25 |
| Finished | Feb 08 11:36:50 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415147694 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3415147694 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1281376111 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 44284555 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 10:02:29 AM UTC 25 |
| Finished | Feb 08 10:02:32 AM UTC 25 |
| Peak memory | 211404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281376111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.1281376111 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.195801551 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 28520709 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 10:02:28 AM UTC 25 |
| Finished | Feb 08 10:02:32 AM UTC 25 |
| Peak memory | 211444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195801551 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.195801551 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.119992164 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 74033899 ps |
| CPU time | 1 seconds |
| Started | Feb 08 10:02:26 AM UTC 25 |
| Finished | Feb 08 10:02:29 AM UTC 25 |
| Peak memory | 210836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119992164 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.119992164 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.148997704 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 33290494 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 10:02:30 AM UTC 25 |
| Finished | Feb 08 10:02:34 AM UTC 25 |
| Peak memory | 220144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=148997704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.sram_ctrl_csr_mem_rw_with_rand_reset.148997704 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3408614355 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 22876605 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 10:02:27 AM UTC 25 |
| Finished | Feb 08 10:02:30 AM UTC 25 |
| Peak memory | 210452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408614355 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.3408614355 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1398861245 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 73556423 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 10:02:30 AM UTC 25 |
| Finished | Feb 08 10:02:33 AM UTC 25 |
| Peak memory | 211416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398861 245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_same_csr_outstandi ng.1398861245 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3089599395 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 29976048 ps |
| CPU time | 3.1 seconds |
| Started | Feb 08 10:02:22 AM UTC 25 |
| Finished | Feb 08 10:02:27 AM UTC 25 |
| Peak memory | 221852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089599395 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.3089599395 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3457701861 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 348835003 ps |
| CPU time | 2.29 seconds |
| Started | Feb 08 10:02:23 AM UTC 25 |
| Finished | Feb 08 10:02:27 AM UTC 25 |
| Peak memory | 221852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457701861 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_intg_err.3457701861 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.638358473 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 391954858 ps |
| CPU time | 3.65 seconds |
| Started | Feb 08 10:02:37 AM UTC 25 |
| Finished | Feb 08 10:02:42 AM UTC 25 |
| Peak memory | 211460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638358473 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.638358473 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3549703247 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 145606612 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 10:02:34 AM UTC 25 |
| Finished | Feb 08 10:02:36 AM UTC 25 |
| Peak memory | 211228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549703247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_reset.3549703247 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1559928772 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 59826586 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 10:02:40 AM UTC 25 |
| Finished | Feb 08 10:02:43 AM UTC 25 |
| Peak memory | 210024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1559928772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1559928772 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2167305625 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 45603003 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 10:02:35 AM UTC 25 |
| Finished | Feb 08 10:02:37 AM UTC 25 |
| Peak memory | 210160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167305625 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.2167305625 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3375988967 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1723672261 ps |
| CPU time | 6.69 seconds |
| Started | Feb 08 10:02:32 AM UTC 25 |
| Finished | Feb 08 10:02:41 AM UTC 25 |
| Peak memory | 211688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375988967 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3375988967 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1764242042 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 52848979 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 10:02:39 AM UTC 25 |
| Finished | Feb 08 10:02:42 AM UTC 25 |
| Peak memory | 210148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764242 042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_same_csr_outstandi ng.1764242042 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.878410272 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 81450997 ps |
| CPU time | 5.26 seconds |
| Started | Feb 08 10:02:32 AM UTC 25 |
| Finished | Feb 08 10:02:39 AM UTC 25 |
| Peak memory | 211516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878410272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.878410272 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1405738668 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 294847856 ps |
| CPU time | 2.33 seconds |
| Started | Feb 08 10:02:34 AM UTC 25 |
| Finished | Feb 08 10:02:38 AM UTC 25 |
| Peak memory | 221732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405738668 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_intg_err.1405738668 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2841488074 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 35817714 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 10:03:22 AM UTC 25 |
| Finished | Feb 08 10:03:25 AM UTC 25 |
| Peak memory | 220264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2841488074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2841488074 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2230064948 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 16422332 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 10:03:21 AM UTC 25 |
| Finished | Feb 08 10:03:24 AM UTC 25 |
| Peak memory | 210832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230064948 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2230064948 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2853229974 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 5149795789 ps |
| CPU time | 8.62 seconds |
| Started | Feb 08 10:03:18 AM UTC 25 |
| Finished | Feb 08 10:03:29 AM UTC 25 |
| Peak memory | 211816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853229974 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2853229974 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3380578176 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 18061188 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 10:03:21 AM UTC 25 |
| Finished | Feb 08 10:03:24 AM UTC 25 |
| Peak memory | 210208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380578 176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_same_csr_outstand ing.3380578176 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2761672994 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 233243496 ps |
| CPU time | 5.84 seconds |
| Started | Feb 08 10:03:20 AM UTC 25 |
| Finished | Feb 08 10:03:28 AM UTC 25 |
| Peak memory | 211716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761672994 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.2761672994 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1764952584 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 602916816 ps |
| CPU time | 3.86 seconds |
| Started | Feb 08 10:03:20 AM UTC 25 |
| Finished | Feb 08 10:03:26 AM UTC 25 |
| Peak memory | 221784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764952584 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_intg_err.1764952584 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1276111095 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 447579084 ps |
| CPU time | 2.57 seconds |
| Started | Feb 08 10:03:26 AM UTC 25 |
| Finished | Feb 08 10:03:30 AM UTC 25 |
| Peak memory | 223896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1276111095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1276111095 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2140299491 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 29381904 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 10:03:25 AM UTC 25 |
| Finished | Feb 08 10:03:27 AM UTC 25 |
| Peak memory | 210380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140299491 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.2140299491 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1440512379 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 236533678 ps |
| CPU time | 3.68 seconds |
| Started | Feb 08 10:03:23 AM UTC 25 |
| Finished | Feb 08 10:03:28 AM UTC 25 |
| Peak memory | 211460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440512379 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1440512379 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3266411522 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 92193328 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 10:03:25 AM UTC 25 |
| Finished | Feb 08 10:03:27 AM UTC 25 |
| Peak memory | 210208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266411 522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_same_csr_outstand ing.3266411522 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2366469359 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 213648284 ps |
| CPU time | 3.13 seconds |
| Started | Feb 08 10:03:24 AM UTC 25 |
| Finished | Feb 08 10:03:28 AM UTC 25 |
| Peak memory | 211840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366469359 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.2366469359 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.670034533 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 168004362 ps |
| CPU time | 2.39 seconds |
| Started | Feb 08 10:03:29 AM UTC 25 |
| Finished | Feb 08 10:03:33 AM UTC 25 |
| Peak memory | 221896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=670034533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_mem_rw_with_rand_reset.670034533 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2341729163 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 12790849 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 10:03:29 AM UTC 25 |
| Finished | Feb 08 10:03:32 AM UTC 25 |
| Peak memory | 210256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341729163 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.2341729163 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.65352362 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 801778357 ps |
| CPU time | 3.97 seconds |
| Started | Feb 08 10:03:27 AM UTC 25 |
| Finished | Feb 08 10:03:33 AM UTC 25 |
| Peak memory | 211460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65352362 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.65352362 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4071828169 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 15771114 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 10:03:29 AM UTC 25 |
| Finished | Feb 08 10:03:32 AM UTC 25 |
| Peak memory | 210180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071828 169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_same_csr_outstand ing.4071828169 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3465725410 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 115511649 ps |
| CPU time | 3.82 seconds |
| Started | Feb 08 10:03:28 AM UTC 25 |
| Finished | Feb 08 10:03:34 AM UTC 25 |
| Peak memory | 221716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465725410 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.3465725410 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4028574806 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 258326436 ps |
| CPU time | 4.04 seconds |
| Started | Feb 08 10:03:28 AM UTC 25 |
| Finished | Feb 08 10:03:34 AM UTC 25 |
| Peak memory | 221672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028574806 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_intg_err.4028574806 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2472600930 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 94444759 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 10:03:34 AM UTC 25 |
| Finished | Feb 08 10:03:36 AM UTC 25 |
| Peak memory | 210024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2472600930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2472600930 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2864414562 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 10846380 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 10:03:32 AM UTC 25 |
| Finished | Feb 08 10:03:35 AM UTC 25 |
| Peak memory | 210380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864414562 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.2864414562 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2308264243 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 1667306129 ps |
| CPU time | 6.35 seconds |
| Started | Feb 08 10:03:29 AM UTC 25 |
| Finished | Feb 08 10:03:37 AM UTC 25 |
| Peak memory | 211996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308264243 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2308264243 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1220492584 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 41308318 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 10:03:32 AM UTC 25 |
| Finished | Feb 08 10:03:35 AM UTC 25 |
| Peak memory | 210208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220492 584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_same_csr_outstand ing.1220492584 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2440333161 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 83469859 ps |
| CPU time | 4.47 seconds |
| Started | Feb 08 10:03:30 AM UTC 25 |
| Finished | Feb 08 10:03:36 AM UTC 25 |
| Peak memory | 223784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440333161 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.2440333161 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2805238177 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 301887839 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 10:03:31 AM UTC 25 |
| Finished | Feb 08 10:03:35 AM UTC 25 |
| Peak memory | 211560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805238177 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_intg_err.2805238177 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3634407232 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 498453849 ps |
| CPU time | 2.6 seconds |
| Started | Feb 08 10:03:36 AM UTC 25 |
| Finished | Feb 08 10:03:40 AM UTC 25 |
| Peak memory | 221844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3634407232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3634407232 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4002229923 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 12708245 ps |
| CPU time | 1 seconds |
| Started | Feb 08 10:03:36 AM UTC 25 |
| Finished | Feb 08 10:03:38 AM UTC 25 |
| Peak memory | 211232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002229923 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.4002229923 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3805672929 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 829364782 ps |
| CPU time | 3.09 seconds |
| Started | Feb 08 10:03:34 AM UTC 25 |
| Finished | Feb 08 10:03:38 AM UTC 25 |
| Peak memory | 211464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805672929 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3805672929 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1826601915 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 55283106 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 10:03:36 AM UTC 25 |
| Finished | Feb 08 10:03:38 AM UTC 25 |
| Peak memory | 210208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826601 915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_same_csr_outstand ing.1826601915 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.324280758 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 765660703 ps |
| CPU time | 2.68 seconds |
| Started | Feb 08 10:03:35 AM UTC 25 |
| Finished | Feb 08 10:03:39 AM UTC 25 |
| Peak memory | 211556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324280758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.324280758 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.895675493 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 47375805 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 10:03:39 AM UTC 25 |
| Finished | Feb 08 10:03:43 AM UTC 25 |
| Peak memory | 220264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=895675493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_csr_mem_rw_with_rand_reset.895675493 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.653636015 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 31181628 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 10:03:38 AM UTC 25 |
| Finished | Feb 08 10:03:41 AM UTC 25 |
| Peak memory | 210500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653636015 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.653636015 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3730337364 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 1679831935 ps |
| CPU time | 3.87 seconds |
| Started | Feb 08 10:03:36 AM UTC 25 |
| Finished | Feb 08 10:03:41 AM UTC 25 |
| Peak memory | 211712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730337364 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3730337364 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4012536299 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 88139629 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 10:03:39 AM UTC 25 |
| Finished | Feb 08 10:03:42 AM UTC 25 |
| Peak memory | 210440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012536 299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_same_csr_outstand ing.4012536299 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.830947339 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 597251596 ps |
| CPU time | 4.83 seconds |
| Started | Feb 08 10:03:37 AM UTC 25 |
| Finished | Feb 08 10:03:43 AM UTC 25 |
| Peak memory | 221780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830947339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.830947339 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2824567773 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 436763704 ps |
| CPU time | 1.88 seconds |
| Started | Feb 08 10:03:37 AM UTC 25 |
| Finished | Feb 08 10:03:40 AM UTC 25 |
| Peak memory | 220376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824567773 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_intg_err.2824567773 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3754940031 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 111343640 ps |
| CPU time | 2.34 seconds |
| Started | Feb 08 10:03:42 AM UTC 25 |
| Finished | Feb 08 10:03:46 AM UTC 25 |
| Peak memory | 221984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3754940031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3754940031 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.815838527 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 17557689 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 10:03:40 AM UTC 25 |
| Finished | Feb 08 10:03:43 AM UTC 25 |
| Peak memory | 210500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815838527 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.815838527 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4211845501 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 1494988152 ps |
| CPU time | 6.17 seconds |
| Started | Feb 08 10:03:39 AM UTC 25 |
| Finished | Feb 08 10:03:47 AM UTC 25 |
| Peak memory | 211684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211845501 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.4211845501 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.681254766 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 41101435 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 10:03:41 AM UTC 25 |
| Finished | Feb 08 10:03:44 AM UTC 25 |
| Peak memory | 209608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6812547 66 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.681254766 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.310747470 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 606269838 ps |
| CPU time | 5.98 seconds |
| Started | Feb 08 10:03:39 AM UTC 25 |
| Finished | Feb 08 10:03:47 AM UTC 25 |
| Peak memory | 221724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310747470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.310747470 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3293105110 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 318797445 ps |
| CPU time | 4.13 seconds |
| Started | Feb 08 10:03:40 AM UTC 25 |
| Finished | Feb 08 10:03:46 AM UTC 25 |
| Peak memory | 221960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293105110 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_intg_err.3293105110 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1283948529 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 38350780 ps |
| CPU time | 3.35 seconds |
| Started | Feb 08 10:03:45 AM UTC 25 |
| Finished | Feb 08 10:03:50 AM UTC 25 |
| Peak memory | 221736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1283948529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1283948529 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2924297612 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 120427514 ps |
| CPU time | 1 seconds |
| Started | Feb 08 10:03:44 AM UTC 25 |
| Finished | Feb 08 10:03:46 AM UTC 25 |
| Peak memory | 210380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924297612 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.2924297612 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3344274919 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 466856071 ps |
| CPU time | 6.01 seconds |
| Started | Feb 08 10:03:43 AM UTC 25 |
| Finished | Feb 08 10:03:50 AM UTC 25 |
| Peak memory | 211880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344274919 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3344274919 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4045987412 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 91473074 ps |
| CPU time | 0.85 seconds |
| Started | Feb 08 10:03:44 AM UTC 25 |
| Finished | Feb 08 10:03:46 AM UTC 25 |
| Peak memory | 210208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045987 412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_same_csr_outstand ing.4045987412 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3939706321 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 203267189 ps |
| CPU time | 4.45 seconds |
| Started | Feb 08 10:03:44 AM UTC 25 |
| Finished | Feb 08 10:03:50 AM UTC 25 |
| Peak memory | 221588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939706321 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.3939706321 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1847961234 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 217242115 ps |
| CPU time | 3.95 seconds |
| Started | Feb 08 10:03:44 AM UTC 25 |
| Finished | Feb 08 10:03:49 AM UTC 25 |
| Peak memory | 221676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847961234 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_intg_err.1847961234 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3188456627 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 81157882 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 10:03:47 AM UTC 25 |
| Finished | Feb 08 10:03:50 AM UTC 25 |
| Peak memory | 221392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3188456627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3188456627 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.549785744 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 11624776 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 10:03:47 AM UTC 25 |
| Finished | Feb 08 10:03:50 AM UTC 25 |
| Peak memory | 211408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549785744 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.549785744 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3561462290 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 1576369376 ps |
| CPU time | 4.7 seconds |
| Started | Feb 08 10:03:45 AM UTC 25 |
| Finished | Feb 08 10:03:52 AM UTC 25 |
| Peak memory | 211888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561462290 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3561462290 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1784071875 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 30743434 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 10:03:47 AM UTC 25 |
| Finished | Feb 08 10:03:50 AM UTC 25 |
| Peak memory | 211356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784071 875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_same_csr_outstand ing.1784071875 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2191778657 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 97458114 ps |
| CPU time | 3.53 seconds |
| Started | Feb 08 10:03:46 AM UTC 25 |
| Finished | Feb 08 10:03:51 AM UTC 25 |
| Peak memory | 221972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191778657 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.2191778657 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2683975300 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 585646039 ps |
| CPU time | 2.37 seconds |
| Started | Feb 08 10:03:47 AM UTC 25 |
| Finished | Feb 08 10:03:51 AM UTC 25 |
| Peak memory | 221956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683975300 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_intg_err.2683975300 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3808281670 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 184128390 ps |
| CPU time | 2.47 seconds |
| Started | Feb 08 10:03:51 AM UTC 25 |
| Finished | Feb 08 10:03:55 AM UTC 25 |
| Peak memory | 224032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3808281670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3808281670 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3547137771 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 41608533 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 10:03:49 AM UTC 25 |
| Finished | Feb 08 10:03:52 AM UTC 25 |
| Peak memory | 210832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547137771 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.3547137771 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3475860445 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 224705887 ps |
| CPU time | 2.26 seconds |
| Started | Feb 08 10:03:47 AM UTC 25 |
| Finished | Feb 08 10:03:51 AM UTC 25 |
| Peak memory | 211468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475860445 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3475860445 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1738576236 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 59438138 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 10:03:50 AM UTC 25 |
| Finished | Feb 08 10:03:53 AM UTC 25 |
| Peak memory | 210148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738576 236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_same_csr_outstand ing.1738576236 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.468526221 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 236417095 ps |
| CPU time | 4.41 seconds |
| Started | Feb 08 10:03:49 AM UTC 25 |
| Finished | Feb 08 10:03:55 AM UTC 25 |
| Peak memory | 221700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468526221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.468526221 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1235775570 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 135572858 ps |
| CPU time | 2.37 seconds |
| Started | Feb 08 10:03:49 AM UTC 25 |
| Finished | Feb 08 10:03:53 AM UTC 25 |
| Peak memory | 221792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235775570 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_intg_err.1235775570 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2304281792 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 66644612 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 10:02:46 AM UTC 25 |
| Finished | Feb 08 10:02:49 AM UTC 25 |
| Peak memory | 210200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304281792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.2304281792 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.856520892 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 82513981 ps |
| CPU time | 2.69 seconds |
| Started | Feb 08 10:02:44 AM UTC 25 |
| Finished | Feb 08 10:02:49 AM UTC 25 |
| Peak memory | 211520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856520892 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.856520892 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2854881639 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 16925026 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 10:02:43 AM UTC 25 |
| Finished | Feb 08 10:02:46 AM UTC 25 |
| Peak memory | 209948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854881639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.2854881639 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4018169975 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 113063859 ps |
| CPU time | 2.58 seconds |
| Started | Feb 08 10:02:47 AM UTC 25 |
| Finished | Feb 08 10:02:51 AM UTC 25 |
| Peak memory | 221720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4018169975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_mem_rw_with_rand_reset.4018169975 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3331350321 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 18178941 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 10:02:43 AM UTC 25 |
| Finished | Feb 08 10:02:46 AM UTC 25 |
| Peak memory | 210360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331350321 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.3331350321 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1529531365 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 391639549 ps |
| CPU time | 6.25 seconds |
| Started | Feb 08 10:02:41 AM UTC 25 |
| Finished | Feb 08 10:02:49 AM UTC 25 |
| Peak memory | 211732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529531365 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1529531365 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2721853702 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 26420095 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 10:02:46 AM UTC 25 |
| Finished | Feb 08 10:02:49 AM UTC 25 |
| Peak memory | 211420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721853 702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_same_csr_outstandi ng.2721853702 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1335284795 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 476274376 ps |
| CPU time | 5.17 seconds |
| Started | Feb 08 10:02:41 AM UTC 25 |
| Finished | Feb 08 10:02:48 AM UTC 25 |
| Peak memory | 221720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335284795 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.1335284795 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2307977598 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 124495131 ps |
| CPU time | 2.52 seconds |
| Started | Feb 08 10:02:42 AM UTC 25 |
| Finished | Feb 08 10:02:46 AM UTC 25 |
| Peak memory | 221744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307977598 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_intg_err.2307977598 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3508293086 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 98440685 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 10:02:54 AM UTC 25 |
| Finished | Feb 08 10:02:57 AM UTC 25 |
| Peak memory | 210896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508293086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.3508293086 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1547783789 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 29813500 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 10:02:53 AM UTC 25 |
| Finished | Feb 08 10:02:56 AM UTC 25 |
| Peak memory | 210584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547783789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_bash.1547783789 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1788878745 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 40077248 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 10:02:50 AM UTC 25 |
| Finished | Feb 08 10:02:53 AM UTC 25 |
| Peak memory | 210764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788878745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.1788878745 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3558839029 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 327068131 ps |
| CPU time | 2.48 seconds |
| Started | Feb 08 10:02:54 AM UTC 25 |
| Finished | Feb 08 10:02:58 AM UTC 25 |
| Peak memory | 221768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3558839029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3558839029 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2286636387 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 20432232 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 10:02:50 AM UTC 25 |
| Finished | Feb 08 10:02:53 AM UTC 25 |
| Peak memory | 211428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286636387 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.2286636387 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3003139249 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 328482465 ps |
| CPU time | 3.67 seconds |
| Started | Feb 08 10:02:49 AM UTC 25 |
| Finished | Feb 08 10:02:54 AM UTC 25 |
| Peak memory | 211460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003139249 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3003139249 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.925801806 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 57952529 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 10:02:54 AM UTC 25 |
| Finished | Feb 08 10:02:57 AM UTC 25 |
| Peak memory | 210212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9258018 06 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.925801806 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1465124158 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 60540725 ps |
| CPU time | 3.72 seconds |
| Started | Feb 08 10:02:50 AM UTC 25 |
| Finished | Feb 08 10:02:55 AM UTC 25 |
| Peak memory | 221708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465124158 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.1465124158 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.26968303 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 222852227 ps |
| CPU time | 3.96 seconds |
| Started | Feb 08 10:02:50 AM UTC 25 |
| Finished | Feb 08 10:02:55 AM UTC 25 |
| Peak memory | 221616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26968303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_intg_err.26968303 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2617222028 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 44277418 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 10:02:59 AM UTC 25 |
| Finished | Feb 08 10:03:02 AM UTC 25 |
| Peak memory | 210432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617222028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.2617222028 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3916770715 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 681246398 ps |
| CPU time | 3.88 seconds |
| Started | Feb 08 10:02:58 AM UTC 25 |
| Finished | Feb 08 10:03:04 AM UTC 25 |
| Peak memory | 211796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916770715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_bash.3916770715 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1933702891 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 52635023 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 10:02:57 AM UTC 25 |
| Finished | Feb 08 10:03:00 AM UTC 25 |
| Peak memory | 210372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933702891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.1933702891 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.736992399 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 42517698 ps |
| CPU time | 2.1 seconds |
| Started | Feb 08 10:03:01 AM UTC 25 |
| Finished | Feb 08 10:03:04 AM UTC 25 |
| Peak memory | 223304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=736992399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_csr_mem_rw_with_rand_reset.736992399 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2503869395 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 21963426 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 10:02:57 AM UTC 25 |
| Finished | Feb 08 10:03:00 AM UTC 25 |
| Peak memory | 210904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503869395 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.2503869395 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2440543801 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 269909872 ps |
| CPU time | 3.85 seconds |
| Started | Feb 08 10:02:55 AM UTC 25 |
| Finished | Feb 08 10:03:01 AM UTC 25 |
| Peak memory | 211456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440543801 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2440543801 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1330972394 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 14922511 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 10:03:00 AM UTC 25 |
| Finished | Feb 08 10:03:03 AM UTC 25 |
| Peak memory | 210716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330972 394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_same_csr_outstandi ng.1330972394 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2625813903 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 212426044 ps |
| CPU time | 5.95 seconds |
| Started | Feb 08 10:02:56 AM UTC 25 |
| Finished | Feb 08 10:03:04 AM UTC 25 |
| Peak memory | 221852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625813903 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.2625813903 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.343812655 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 138258076 ps |
| CPU time | 2.66 seconds |
| Started | Feb 08 10:02:56 AM UTC 25 |
| Finished | Feb 08 10:03:01 AM UTC 25 |
| Peak memory | 221800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343812655 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_intg_err.343812655 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1363003890 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 57184231 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 10:03:05 AM UTC 25 |
| Finished | Feb 08 10:03:08 AM UTC 25 |
| Peak memory | 222312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1363003890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1363003890 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.705356125 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 24031440 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 10:03:04 AM UTC 25 |
| Finished | Feb 08 10:03:06 AM UTC 25 |
| Peak memory | 211020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705356125 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.705356125 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2620035512 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 719992989 ps |
| CPU time | 3.39 seconds |
| Started | Feb 08 10:03:02 AM UTC 25 |
| Finished | Feb 08 10:03:06 AM UTC 25 |
| Peak memory | 211724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620035512 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2620035512 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3351205999 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 26963187 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 10:03:04 AM UTC 25 |
| Finished | Feb 08 10:03:06 AM UTC 25 |
| Peak memory | 210440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351205 999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_same_csr_outstandi ng.3351205999 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1274425939 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 75632429 ps |
| CPU time | 4.21 seconds |
| Started | Feb 08 10:03:02 AM UTC 25 |
| Finished | Feb 08 10:03:07 AM UTC 25 |
| Peak memory | 211540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274425939 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.1274425939 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4118954221 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1091756808 ps |
| CPU time | 2.37 seconds |
| Started | Feb 08 10:03:03 AM UTC 25 |
| Finished | Feb 08 10:03:06 AM UTC 25 |
| Peak memory | 211692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118954221 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_intg_err.4118954221 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.478794922 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 35823807 ps |
| CPU time | 3.11 seconds |
| Started | Feb 08 10:03:07 AM UTC 25 |
| Finished | Feb 08 10:03:12 AM UTC 25 |
| Peak memory | 223780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=478794922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_csr_mem_rw_with_rand_reset.478794922 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3617839215 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 60557581 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 10:03:07 AM UTC 25 |
| Finished | Feb 08 10:03:09 AM UTC 25 |
| Peak memory | 210072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617839215 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.3617839215 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2859469984 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1765374241 ps |
| CPU time | 6.22 seconds |
| Started | Feb 08 10:03:05 AM UTC 25 |
| Finished | Feb 08 10:03:13 AM UTC 25 |
| Peak memory | 211732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859469984 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2859469984 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3176115326 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 23420346 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 10:03:07 AM UTC 25 |
| Finished | Feb 08 10:03:10 AM UTC 25 |
| Peak memory | 210208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176115 326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_same_csr_outstandi ng.3176115326 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.51975754 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 31031548 ps |
| CPU time | 2.84 seconds |
| Started | Feb 08 10:03:05 AM UTC 25 |
| Finished | Feb 08 10:03:09 AM UTC 25 |
| Peak memory | 211620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51975754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.51975754 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3032591028 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 86690681 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 10:03:13 AM UTC 25 |
| Finished | Feb 08 10:03:16 AM UTC 25 |
| Peak memory | 220260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3032591028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3032591028 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1211007237 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 14301507 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 10:03:10 AM UTC 25 |
| Finished | Feb 08 10:03:13 AM UTC 25 |
| Peak memory | 210220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211007237 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.1211007237 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4236637512 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 914943501 ps |
| CPU time | 3.88 seconds |
| Started | Feb 08 10:03:08 AM UTC 25 |
| Finished | Feb 08 10:03:14 AM UTC 25 |
| Peak memory | 211400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236637512 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.4236637512 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2631845690 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 34053819 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 10:03:11 AM UTC 25 |
| Finished | Feb 08 10:03:13 AM UTC 25 |
| Peak memory | 210208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631845 690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_same_csr_outstandi ng.2631845690 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2741593220 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 105794155 ps |
| CPU time | 4.96 seconds |
| Started | Feb 08 10:03:09 AM UTC 25 |
| Finished | Feb 08 10:03:16 AM UTC 25 |
| Peak memory | 221688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741593220 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.2741593220 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2524577953 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 31430306 ps |
| CPU time | 2.06 seconds |
| Started | Feb 08 10:03:16 AM UTC 25 |
| Finished | Feb 08 10:03:20 AM UTC 25 |
| Peak memory | 221744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2524577953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2524577953 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1900771329 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 18010700 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 10:03:14 AM UTC 25 |
| Finished | Feb 08 10:03:16 AM UTC 25 |
| Peak memory | 211428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900771329 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.1900771329 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4126070811 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 447287540 ps |
| CPU time | 2.21 seconds |
| Started | Feb 08 10:03:14 AM UTC 25 |
| Finished | Feb 08 10:03:17 AM UTC 25 |
| Peak memory | 211524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126070811 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.4126070811 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.317536912 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 42349315 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 10:03:15 AM UTC 25 |
| Finished | Feb 08 10:03:18 AM UTC 25 |
| Peak memory | 211472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175369 12 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.317536912 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2692756852 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 74472555 ps |
| CPU time | 2 seconds |
| Started | Feb 08 10:03:14 AM UTC 25 |
| Finished | Feb 08 10:03:17 AM UTC 25 |
| Peak memory | 221492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692756852 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.2692756852 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2652784645 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 339151450 ps |
| CPU time | 2.36 seconds |
| Started | Feb 08 10:03:14 AM UTC 25 |
| Finished | Feb 08 10:03:17 AM UTC 25 |
| Peak memory | 221724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652784645 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_intg_err.2652784645 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1551966819 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 67471342 ps |
| CPU time | 1.94 seconds |
| Started | Feb 08 10:03:18 AM UTC 25 |
| Finished | Feb 08 10:03:22 AM UTC 25 |
| Peak memory | 220260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1551966819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1551966819 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.553859976 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 18661993 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 10:03:18 AM UTC 25 |
| Finished | Feb 08 10:03:21 AM UTC 25 |
| Peak memory | 210808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553859976 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.553859976 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2085854333 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 464282494 ps |
| CPU time | 3.71 seconds |
| Started | Feb 08 10:03:17 AM UTC 25 |
| Finished | Feb 08 10:03:22 AM UTC 25 |
| Peak memory | 211352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085854333 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2085854333 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.160616522 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 50718098 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 10:03:18 AM UTC 25 |
| Finished | Feb 08 10:03:21 AM UTC 25 |
| Peak memory | 210044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606165 22 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.160616522 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3262398962 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 50271989 ps |
| CPU time | 4.66 seconds |
| Started | Feb 08 10:03:17 AM UTC 25 |
| Finished | Feb 08 10:03:23 AM UTC 25 |
| Peak memory | 211360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262398962 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.3262398962 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.349074959 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 130219581 ps |
| CPU time | 2.24 seconds |
| Started | Feb 08 10:03:17 AM UTC 25 |
| Finished | Feb 08 10:03:21 AM UTC 25 |
| Peak memory | 221848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349074959 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_intg_err.349074959 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1912887076 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 11803842899 ps |
| CPU time | 774.77 seconds |
| Started | Feb 08 11:36:46 AM UTC 25 |
| Finished | Feb 08 11:49:50 AM UTC 25 |
| Peak memory | 384728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912887076 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_key_req.1912887076 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3611254851 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 10820393380 ps |
| CPU time | 47.45 seconds |
| Started | Feb 08 11:36:44 AM UTC 25 |
| Finished | Feb 08 11:37:33 AM UTC 25 |
| Peak memory | 213748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611254851 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.3611254851 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2758472443 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4315914125 ps |
| CPU time | 305.14 seconds |
| Started | Feb 08 11:36:46 AM UTC 25 |
| Finished | Feb 08 11:41:56 AM UTC 25 |
| Peak memory | 384184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758472443 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2758472443 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3699137770 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 153636539 ps |
| CPU time | 3.25 seconds |
| Started | Feb 08 11:36:46 AM UTC 25 |
| Finished | Feb 08 11:36:51 AM UTC 25 |
| Peak memory | 212864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699137770 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.3699137770 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1461834259 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 333406562 ps |
| CPU time | 8.7 seconds |
| Started | Feb 08 11:36:45 AM UTC 25 |
| Finished | Feb 08 11:36:56 AM UTC 25 |
| Peak memory | 263744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461834259 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max_throughput.1461834259 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.418131009 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 291619860 ps |
| CPU time | 5.57 seconds |
| Started | Feb 08 11:36:46 AM UTC 25 |
| Finished | Feb 08 11:36:54 AM UTC 25 |
| Peak memory | 223776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418131009 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.418131009 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1403511878 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4502902115 ps |
| CPU time | 46.21 seconds |
| Started | Feb 08 11:36:44 AM UTC 25 |
| Finished | Feb 08 11:37:32 AM UTC 25 |
| Peak memory | 231012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403511878 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.1403511878 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3510788219 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 30123917 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 11:36:45 AM UTC 25 |
| Finished | Feb 08 11:36:48 AM UTC 25 |
| Peak memory | 212956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510788219 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.3510788219 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2633981846 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 13751278218 ps |
| CPU time | 275.99 seconds |
| Started | Feb 08 11:36:45 AM UTC 25 |
| Finished | Feb 08 11:41:25 AM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633981846 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access_b2b.2633981846 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2650964618 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 32300978 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 11:36:46 AM UTC 25 |
| Finished | Feb 08 11:36:49 AM UTC 25 |
| Peak memory | 212968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650964618 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2650964618 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2885458847 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2970849534 ps |
| CPU time | 51.35 seconds |
| Started | Feb 08 11:36:44 AM UTC 25 |
| Finished | Feb 08 11:37:38 AM UTC 25 |
| Peak memory | 378584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885458847 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2885458847 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.3853308490 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 6672987868 ps |
| CPU time | 369.91 seconds |
| Started | Feb 08 11:36:45 AM UTC 25 |
| Finished | Feb 08 11:43:01 AM UTC 25 |
| Peak memory | 213732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853308490 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.3853308490 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1809939690 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 245797423 ps |
| CPU time | 28.52 seconds |
| Started | Feb 08 11:36:46 AM UTC 25 |
| Finished | Feb 08 11:37:17 AM UTC 25 |
| Peak memory | 304784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809939690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_throughput_w_partial_wri te.1809939690 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3319886168 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 33324117 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 11:37:02 AM UTC 25 |
| Finished | Feb 08 11:37:04 AM UTC 25 |
| Peak memory | 212904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319886168 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3319886168 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.348572765 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 377730143 ps |
| CPU time | 28.56 seconds |
| Started | Feb 08 11:36:50 AM UTC 25 |
| Finished | Feb 08 11:37:20 AM UTC 25 |
| Peak memory | 213472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348572765 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.348572765 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1622408051 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4536046424 ps |
| CPU time | 1097.06 seconds |
| Started | Feb 08 11:36:55 AM UTC 25 |
| Finished | Feb 08 11:55:24 AM UTC 25 |
| Peak memory | 386852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622408051 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.1622408051 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3587481184 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 198611717 ps |
| CPU time | 2.72 seconds |
| Started | Feb 08 11:36:55 AM UTC 25 |
| Finished | Feb 08 11:37:00 AM UTC 25 |
| Peak memory | 223816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587481184 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3587481184 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2813625930 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 427924351 ps |
| CPU time | 3.74 seconds |
| Started | Feb 08 11:36:53 AM UTC 25 |
| Finished | Feb 08 11:36:59 AM UTC 25 |
| Peak memory | 230876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813625930 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max_throughput.2813625930 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3535764521 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 463662702 ps |
| CPU time | 3.96 seconds |
| Started | Feb 08 11:36:59 AM UTC 25 |
| Finished | Feb 08 11:37:05 AM UTC 25 |
| Peak memory | 223836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535764521 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.3535764521 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.89116546 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 392969339 ps |
| CPU time | 6.5 seconds |
| Started | Feb 08 11:36:58 AM UTC 25 |
| Finished | Feb 08 11:37:06 AM UTC 25 |
| Peak memory | 213772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89116546 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.89116546 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1862199212 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 45110046109 ps |
| CPU time | 1120.21 seconds |
| Started | Feb 08 11:36:49 AM UTC 25 |
| Finished | Feb 08 11:55:41 AM UTC 25 |
| Peak memory | 388692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862199212 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.1862199212 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3164987795 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 117710734 ps |
| CPU time | 8.44 seconds |
| Started | Feb 08 11:36:51 AM UTC 25 |
| Finished | Feb 08 11:37:01 AM UTC 25 |
| Peak memory | 243508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164987795 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.3164987795 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2594101120 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 11768287703 ps |
| CPU time | 229.02 seconds |
| Started | Feb 08 11:36:52 AM UTC 25 |
| Finished | Feb 08 11:40:45 AM UTC 25 |
| Peak memory | 213924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594101120 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access_b2b.2594101120 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3454292424 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 25292222 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 11:36:57 AM UTC 25 |
| Finished | Feb 08 11:37:00 AM UTC 25 |
| Peak memory | 212500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454292424 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3454292424 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.693210968 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 17915066209 ps |
| CPU time | 638.29 seconds |
| Started | Feb 08 11:36:56 AM UTC 25 |
| Finished | Feb 08 11:47:43 AM UTC 25 |
| Peak memory | 380784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693210968 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.693210968 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.565506347 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 586803767 ps |
| CPU time | 3.07 seconds |
| Started | Feb 08 11:37:01 AM UTC 25 |
| Finished | Feb 08 11:37:05 AM UTC 25 |
| Peak memory | 249480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565506347 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.565506347 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.2421760538 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 936945866 ps |
| CPU time | 25.24 seconds |
| Started | Feb 08 11:36:49 AM UTC 25 |
| Finished | Feb 08 11:37:16 AM UTC 25 |
| Peak memory | 213512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421760538 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2421760538 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3983845052 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 9508464654 ps |
| CPU time | 260.93 seconds |
| Started | Feb 08 11:36:50 AM UTC 25 |
| Finished | Feb 08 11:41:15 AM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983845052 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.3983845052 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.625587641 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 166295159 ps |
| CPU time | 7.33 seconds |
| Started | Feb 08 11:36:54 AM UTC 25 |
| Finished | Feb 08 11:37:03 AM UTC 25 |
| Peak memory | 253764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625587641 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.625587641 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.1115623103 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 3452656422 ps |
| CPU time | 637.05 seconds |
| Started | Feb 08 11:48:08 AM UTC 25 |
| Finished | Feb 08 11:58:52 AM UTC 25 |
| Peak memory | 382576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115623103 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during_key_req.1115623103 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3737208081 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 16884177 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 11:48:31 AM UTC 25 |
| Finished | Feb 08 11:48:33 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737208081 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3737208081 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.516536074 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 439288354 ps |
| CPU time | 34.67 seconds |
| Started | Feb 08 11:47:32 AM UTC 25 |
| Finished | Feb 08 11:48:09 AM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516536074 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.516536074 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2264523595 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 4312302451 ps |
| CPU time | 121.87 seconds |
| Started | Feb 08 11:48:10 AM UTC 25 |
| Finished | Feb 08 11:50:15 AM UTC 25 |
| Peak memory | 333716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264523595 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2264523595 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.444760350 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 152798185 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 11:48:06 AM UTC 25 |
| Finished | Feb 08 11:48:09 AM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444760350 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.444760350 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1455066573 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 958057131 ps |
| CPU time | 85.81 seconds |
| Started | Feb 08 11:48:00 AM UTC 25 |
| Finished | Feb 08 11:49:28 AM UTC 25 |
| Peak memory | 360012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455066573 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_max_throughput.1455066573 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.89638165 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 374158816 ps |
| CPU time | 4.18 seconds |
| Started | Feb 08 11:48:24 AM UTC 25 |
| Finished | Feb 08 11:48:30 AM UTC 25 |
| Peak memory | 223860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89638165 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.89638165 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1763122565 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2836587875 ps |
| CPU time | 12.12 seconds |
| Started | Feb 08 11:48:20 AM UTC 25 |
| Finished | Feb 08 11:48:34 AM UTC 25 |
| Peak memory | 223892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763122565 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.1763122565 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.1041088712 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 18050425897 ps |
| CPU time | 1056.45 seconds |
| Started | Feb 08 11:47:28 AM UTC 25 |
| Finished | Feb 08 12:05:16 PM UTC 25 |
| Peak memory | 386936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041088712 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.1041088712 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1493656548 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1100790198 ps |
| CPU time | 62.72 seconds |
| Started | Feb 08 11:47:51 AM UTC 25 |
| Finished | Feb 08 11:48:55 AM UTC 25 |
| Peak memory | 329284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493656548 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.1493656548 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2566907740 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 18062361739 ps |
| CPU time | 308.56 seconds |
| Started | Feb 08 11:47:59 AM UTC 25 |
| Finished | Feb 08 11:53:12 AM UTC 25 |
| Peak memory | 213640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566907740 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access_b2b.2566907740 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3434868844 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 96875591 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 11:48:17 AM UTC 25 |
| Finished | Feb 08 11:48:20 AM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434868844 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3434868844 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.3246000372 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 234637714 ps |
| CPU time | 14.46 seconds |
| Started | Feb 08 11:48:10 AM UTC 25 |
| Finished | Feb 08 11:48:26 AM UTC 25 |
| Peak memory | 213608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246000372 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3246000372 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.251089951 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1942964243 ps |
| CPU time | 21.29 seconds |
| Started | Feb 08 11:47:27 AM UTC 25 |
| Finished | Feb 08 11:47:50 AM UTC 25 |
| Peak memory | 271944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251089951 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.251089951 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2364830564 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 25510690527 ps |
| CPU time | 1405.09 seconds |
| Started | Feb 08 11:48:28 AM UTC 25 |
| Finished | Feb 08 12:12:08 PM UTC 25 |
| Peak memory | 386708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364830564 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.2364830564 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1950570749 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 538083518 ps |
| CPU time | 10.62 seconds |
| Started | Feb 08 11:48:26 AM UTC 25 |
| Finished | Feb 08 11:48:39 AM UTC 25 |
| Peak memory | 230780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950570749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1950570749 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.893097731 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 14144977135 ps |
| CPU time | 352.74 seconds |
| Started | Feb 08 11:47:44 AM UTC 25 |
| Finished | Feb 08 11:53:42 AM UTC 25 |
| Peak memory | 213660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893097731 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.893097731 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.441495830 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 441313757 ps |
| CPU time | 43 seconds |
| Started | Feb 08 11:48:02 AM UTC 25 |
| Finished | Feb 08 11:48:47 AM UTC 25 |
| Peak memory | 319056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441495830 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.441495830 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.4277436821 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4485315040 ps |
| CPU time | 282.96 seconds |
| Started | Feb 08 11:48:58 AM UTC 25 |
| Finished | Feb 08 11:53:45 AM UTC 25 |
| Peak memory | 341652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277436821 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_key_req.4277436821 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2291655382 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 164629581 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 11:49:29 AM UTC 25 |
| Finished | Feb 08 11:49:32 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291655382 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2291655382 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.1524171904 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 746524918 ps |
| CPU time | 47.78 seconds |
| Started | Feb 08 11:48:35 AM UTC 25 |
| Finished | Feb 08 11:49:24 AM UTC 25 |
| Peak memory | 213660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524171904 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.1524171904 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2911512530 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 62516724654 ps |
| CPU time | 721.66 seconds |
| Started | Feb 08 11:49:04 AM UTC 25 |
| Finished | Feb 08 12:01:14 PM UTC 25 |
| Peak memory | 386696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911512530 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2911512530 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.252198147 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 355363790 ps |
| CPU time | 5.58 seconds |
| Started | Feb 08 11:48:56 AM UTC 25 |
| Finished | Feb 08 11:49:03 AM UTC 25 |
| Peak memory | 213568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252198147 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.252198147 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.302175060 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 176449875 ps |
| CPU time | 32.78 seconds |
| Started | Feb 08 11:48:55 AM UTC 25 |
| Finished | Feb 08 11:49:30 AM UTC 25 |
| Peak memory | 300804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302175060 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_max_throughput.302175060 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.928070486 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 91658934 ps |
| CPU time | 6.24 seconds |
| Started | Feb 08 11:49:19 AM UTC 25 |
| Finished | Feb 08 11:49:27 AM UTC 25 |
| Peak memory | 223736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928070486 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.928070486 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1161596287 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2741126687 ps |
| CPU time | 15.77 seconds |
| Started | Feb 08 11:49:18 AM UTC 25 |
| Finished | Feb 08 11:49:35 AM UTC 25 |
| Peak memory | 224080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161596287 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.1161596287 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3593167486 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 7370460757 ps |
| CPU time | 773.89 seconds |
| Started | Feb 08 11:48:34 AM UTC 25 |
| Finished | Feb 08 12:01:36 PM UTC 25 |
| Peak memory | 376492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593167486 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.3593167486 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.3952203683 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 286442456 ps |
| CPU time | 6.89 seconds |
| Started | Feb 08 11:48:47 AM UTC 25 |
| Finished | Feb 08 11:48:55 AM UTC 25 |
| Peak memory | 213608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952203683 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.3952203683 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.502115743 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 49993081682 ps |
| CPU time | 304.22 seconds |
| Started | Feb 08 11:48:47 AM UTC 25 |
| Finished | Feb 08 11:53:56 AM UTC 25 |
| Peak memory | 213888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502115743 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access_b2b.502115743 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.365480903 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 40927930 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 11:49:15 AM UTC 25 |
| Finished | Feb 08 11:49:17 AM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365480903 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.365480903 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.3237586891 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 77923702317 ps |
| CPU time | 715.54 seconds |
| Started | Feb 08 11:49:11 AM UTC 25 |
| Finished | Feb 08 12:01:14 PM UTC 25 |
| Peak memory | 380560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237586891 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3237586891 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.74016608 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1371025667 ps |
| CPU time | 10.74 seconds |
| Started | Feb 08 11:48:34 AM UTC 25 |
| Finished | Feb 08 11:48:46 AM UTC 25 |
| Peak memory | 213484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74016608 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.74016608 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1536769731 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8246789725 ps |
| CPU time | 100.19 seconds |
| Started | Feb 08 11:49:28 AM UTC 25 |
| Finished | Feb 08 11:51:11 AM UTC 25 |
| Peak memory | 213624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536769731 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.1536769731 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4257064088 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 275090938 ps |
| CPU time | 88.1 seconds |
| Started | Feb 08 11:49:25 AM UTC 25 |
| Finished | Feb 08 11:50:56 AM UTC 25 |
| Peak memory | 364508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257064088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.4257064088 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.261813179 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 8961263875 ps |
| CPU time | 210.91 seconds |
| Started | Feb 08 11:48:39 AM UTC 25 |
| Finished | Feb 08 11:52:13 AM UTC 25 |
| Peak memory | 213672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261813179 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.261813179 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2275265713 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 102154923 ps |
| CPU time | 37.47 seconds |
| Started | Feb 08 11:48:56 AM UTC 25 |
| Finished | Feb 08 11:49:36 AM UTC 25 |
| Peak memory | 302648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275265713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_throughput_w_partial_wr ite.2275265713 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.695358340 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4714268131 ps |
| CPU time | 382.81 seconds |
| Started | Feb 08 11:49:51 AM UTC 25 |
| Finished | Feb 08 11:56:19 AM UTC 25 |
| Peak memory | 386956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695358340 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_key_req.695358340 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3673816257 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 20331610 ps |
| CPU time | 1 seconds |
| Started | Feb 08 11:50:23 AM UTC 25 |
| Finished | Feb 08 11:50:26 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673816257 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3673816257 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1231106508 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1076579319 ps |
| CPU time | 75.85 seconds |
| Started | Feb 08 11:49:33 AM UTC 25 |
| Finished | Feb 08 11:50:51 AM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231106508 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.1231106508 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3192569593 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 39190350619 ps |
| CPU time | 1069.83 seconds |
| Started | Feb 08 11:50:04 AM UTC 25 |
| Finished | Feb 08 12:08:06 PM UTC 25 |
| Peak memory | 386696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192569593 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.3192569593 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1958355058 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 774518440 ps |
| CPU time | 10.71 seconds |
| Started | Feb 08 11:49:51 AM UTC 25 |
| Finished | Feb 08 11:50:03 AM UTC 25 |
| Peak memory | 227952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958355058 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.1958355058 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2333767072 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 52463992 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 11:49:46 AM UTC 25 |
| Finished | Feb 08 11:49:49 AM UTC 25 |
| Peak memory | 222740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333767072 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_max_throughput.2333767072 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1471381039 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1976506125 ps |
| CPU time | 7.24 seconds |
| Started | Feb 08 11:50:14 AM UTC 25 |
| Finished | Feb 08 11:50:23 AM UTC 25 |
| Peak memory | 224056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471381039 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.1471381039 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.4267488847 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1681676723 ps |
| CPU time | 10.69 seconds |
| Started | Feb 08 11:50:11 AM UTC 25 |
| Finished | Feb 08 11:50:23 AM UTC 25 |
| Peak memory | 224016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267488847 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.4267488847 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.641663005 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3158655418 ps |
| CPU time | 830.72 seconds |
| Started | Feb 08 11:49:32 AM UTC 25 |
| Finished | Feb 08 12:03:32 PM UTC 25 |
| Peak memory | 380524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641663005 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.641663005 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.598856218 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1242526927 ps |
| CPU time | 69.25 seconds |
| Started | Feb 08 11:49:36 AM UTC 25 |
| Finished | Feb 08 11:50:48 AM UTC 25 |
| Peak memory | 370172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598856218 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.598856218 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.661086409 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 23992355444 ps |
| CPU time | 440.06 seconds |
| Started | Feb 08 11:49:40 AM UTC 25 |
| Finished | Feb 08 11:57:06 AM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661086409 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access_b2b.661086409 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1574084020 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 30597186 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 11:50:08 AM UTC 25 |
| Finished | Feb 08 11:50:11 AM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574084020 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1574084020 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.1170218132 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 18806663468 ps |
| CPU time | 458.78 seconds |
| Started | Feb 08 11:50:05 AM UTC 25 |
| Finished | Feb 08 11:57:50 AM UTC 25 |
| Peak memory | 374652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170218132 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1170218132 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.2275225684 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2980510757 ps |
| CPU time | 17.62 seconds |
| Started | Feb 08 11:49:31 AM UTC 25 |
| Finished | Feb 08 11:49:50 AM UTC 25 |
| Peak memory | 213924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275225684 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2275225684 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3025519588 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 61166907941 ps |
| CPU time | 2221.05 seconds |
| Started | Feb 08 11:50:16 AM UTC 25 |
| Finished | Feb 08 12:27:41 PM UTC 25 |
| Peak memory | 388596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025519588 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.3025519588 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2499963957 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 43583260138 ps |
| CPU time | 327.75 seconds |
| Started | Feb 08 11:49:36 AM UTC 25 |
| Finished | Feb 08 11:55:09 AM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499963957 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.2499963957 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2465693884 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 301826578 ps |
| CPU time | 13.54 seconds |
| Started | Feb 08 11:49:50 AM UTC 25 |
| Finished | Feb 08 11:50:04 AM UTC 25 |
| Peak memory | 267844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465693884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_throughput_w_partial_wr ite.2465693884 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2105924948 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3140289234 ps |
| CPU time | 786.88 seconds |
| Started | Feb 08 11:51:12 AM UTC 25 |
| Finished | Feb 08 12:04:29 PM UTC 25 |
| Peak memory | 372628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105924948 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_key_req.2105924948 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1360848687 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 13854459 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 11:52:14 AM UTC 25 |
| Finished | Feb 08 11:52:16 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360848687 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1360848687 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.3404411379 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 9851571538 ps |
| CPU time | 71.97 seconds |
| Started | Feb 08 11:50:27 AM UTC 25 |
| Finished | Feb 08 11:51:41 AM UTC 25 |
| Peak memory | 213980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404411379 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.3404411379 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.648098620 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 113099181431 ps |
| CPU time | 1502.93 seconds |
| Started | Feb 08 11:51:13 AM UTC 25 |
| Finished | Feb 08 12:16:31 PM UTC 25 |
| Peak memory | 386928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648098620 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.648098620 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2768043949 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 572060742 ps |
| CPU time | 10.1 seconds |
| Started | Feb 08 11:51:01 AM UTC 25 |
| Finished | Feb 08 11:51:13 AM UTC 25 |
| Peak memory | 228160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768043949 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.2768043949 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3203354304 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 149930829 ps |
| CPU time | 78.22 seconds |
| Started | Feb 08 11:50:54 AM UTC 25 |
| Finished | Feb 08 11:52:15 AM UTC 25 |
| Peak memory | 360092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203354304 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_max_throughput.3203354304 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3350631997 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 50318615 ps |
| CPU time | 3.85 seconds |
| Started | Feb 08 11:51:42 AM UTC 25 |
| Finished | Feb 08 11:51:47 AM UTC 25 |
| Peak memory | 223764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350631997 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.3350631997 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3509918789 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 680979054 ps |
| CPU time | 6.68 seconds |
| Started | Feb 08 11:51:37 AM UTC 25 |
| Finished | Feb 08 11:51:45 AM UTC 25 |
| Peak memory | 223756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509918789 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3509918789 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.2298561275 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 11637472133 ps |
| CPU time | 605.34 seconds |
| Started | Feb 08 11:50:27 AM UTC 25 |
| Finished | Feb 08 12:00:39 PM UTC 25 |
| Peak memory | 370304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298561275 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.2298561275 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3744070517 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 49584643275 ps |
| CPU time | 372.74 seconds |
| Started | Feb 08 11:50:52 AM UTC 25 |
| Finished | Feb 08 11:57:10 AM UTC 25 |
| Peak memory | 213692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744070517 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access_b2b.3744070517 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3919632944 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 46144664 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 11:51:34 AM UTC 25 |
| Finished | Feb 08 11:51:36 AM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919632944 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3919632944 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.3578948415 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 17723415997 ps |
| CPU time | 1018.87 seconds |
| Started | Feb 08 11:51:23 AM UTC 25 |
| Finished | Feb 08 12:08:32 PM UTC 25 |
| Peak memory | 382652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578948415 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3578948415 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3492852652 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3939329437 ps |
| CPU time | 8.42 seconds |
| Started | Feb 08 11:50:24 AM UTC 25 |
| Finished | Feb 08 11:50:34 AM UTC 25 |
| Peak memory | 213944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492852652 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3492852652 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1472031712 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5192049214 ps |
| CPU time | 1677.84 seconds |
| Started | Feb 08 11:51:48 AM UTC 25 |
| Finished | Feb 08 12:20:04 PM UTC 25 |
| Peak memory | 396716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472031712 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.1472031712 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.847271039 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 40587233399 ps |
| CPU time | 343.91 seconds |
| Started | Feb 08 11:50:35 AM UTC 25 |
| Finished | Feb 08 11:56:24 AM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847271039 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.847271039 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1397749030 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 135418509 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 11:50:57 AM UTC 25 |
| Finished | Feb 08 11:51:00 AM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397749030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_throughput_w_partial_wr ite.1397749030 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3991619882 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1139655868 ps |
| CPU time | 304.3 seconds |
| Started | Feb 08 11:53:03 AM UTC 25 |
| Finished | Feb 08 11:58:12 AM UTC 25 |
| Peak memory | 384664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991619882 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during_key_req.3991619882 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.1972256459 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 15447702 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 11:53:37 AM UTC 25 |
| Finished | Feb 08 11:53:39 AM UTC 25 |
| Peak memory | 212960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972256459 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1972256459 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.857219890 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 10045496620 ps |
| CPU time | 85.09 seconds |
| Started | Feb 08 11:52:17 AM UTC 25 |
| Finished | Feb 08 11:53:45 AM UTC 25 |
| Peak memory | 213832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857219890 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.857219890 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1087873549 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 9607749711 ps |
| CPU time | 764.96 seconds |
| Started | Feb 08 11:53:07 AM UTC 25 |
| Finished | Feb 08 12:06:01 PM UTC 25 |
| Peak memory | 374480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087873549 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.1087873549 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.2206542253 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 705490210 ps |
| CPU time | 14.16 seconds |
| Started | Feb 08 11:52:52 AM UTC 25 |
| Finished | Feb 08 11:53:08 AM UTC 25 |
| Peak memory | 213620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206542253 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.2206542253 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3173971660 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 93335140 ps |
| CPU time | 24.89 seconds |
| Started | Feb 08 11:52:40 AM UTC 25 |
| Finished | Feb 08 11:53:06 AM UTC 25 |
| Peak memory | 304724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173971660 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_max_throughput.3173971660 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.712032276 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 171093989 ps |
| CPU time | 6.84 seconds |
| Started | Feb 08 11:53:24 AM UTC 25 |
| Finished | Feb 08 11:53:33 AM UTC 25 |
| Peak memory | 224024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712032276 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.712032276 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.691066217 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2372480562 ps |
| CPU time | 15.98 seconds |
| Started | Feb 08 11:53:15 AM UTC 25 |
| Finished | Feb 08 11:53:33 AM UTC 25 |
| Peak memory | 223892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691066217 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.691066217 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1328710134 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 463642367 ps |
| CPU time | 76.47 seconds |
| Started | Feb 08 11:52:17 AM UTC 25 |
| Finished | Feb 08 11:53:36 AM UTC 25 |
| Peak memory | 310852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328710134 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.1328710134 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1140544843 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1109720726 ps |
| CPU time | 21.1 seconds |
| Started | Feb 08 11:52:28 AM UTC 25 |
| Finished | Feb 08 11:52:50 AM UTC 25 |
| Peak memory | 213884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140544843 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1140544843 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1132876269 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 113834819242 ps |
| CPU time | 459.58 seconds |
| Started | Feb 08 11:52:37 AM UTC 25 |
| Finished | Feb 08 12:00:22 PM UTC 25 |
| Peak memory | 213996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132876269 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access_b2b.1132876269 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3701045816 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 45530217 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 11:53:12 AM UTC 25 |
| Finished | Feb 08 11:53:15 AM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701045816 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3701045816 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.884541791 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 11377429114 ps |
| CPU time | 536.15 seconds |
| Started | Feb 08 11:53:08 AM UTC 25 |
| Finished | Feb 08 12:02:11 PM UTC 25 |
| Peak memory | 384928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884541791 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.884541791 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.276317910 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2132462857 ps |
| CPU time | 18.67 seconds |
| Started | Feb 08 11:52:15 AM UTC 25 |
| Finished | Feb 08 11:52:36 AM UTC 25 |
| Peak memory | 213692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276317910 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.276317910 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3220244202 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 68710203718 ps |
| CPU time | 933.88 seconds |
| Started | Feb 08 11:53:34 AM UTC 25 |
| Finished | Feb 08 12:09:18 PM UTC 25 |
| Peak memory | 386648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220244202 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.3220244202 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2008735449 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2693367697 ps |
| CPU time | 254.26 seconds |
| Started | Feb 08 11:52:26 AM UTC 25 |
| Finished | Feb 08 11:56:45 AM UTC 25 |
| Peak memory | 213652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008735449 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.2008735449 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.243956495 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 71369673 ps |
| CPU time | 10.24 seconds |
| Started | Feb 08 11:52:51 AM UTC 25 |
| Finished | Feb 08 11:53:03 AM UTC 25 |
| Peak memory | 263756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243956495 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.243956495 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1328391732 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 220834074 ps |
| CPU time | 13.93 seconds |
| Started | Feb 08 11:54:11 AM UTC 25 |
| Finished | Feb 08 11:54:27 AM UTC 25 |
| Peak memory | 235072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328391732 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during_key_req.1328391732 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.4069766311 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 35580200 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 11:54:42 AM UTC 25 |
| Finished | Feb 08 11:54:44 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069766311 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.4069766311 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.2192602901 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 15656112497 ps |
| CPU time | 46.98 seconds |
| Started | Feb 08 11:53:43 AM UTC 25 |
| Finished | Feb 08 11:54:32 AM UTC 25 |
| Peak memory | 213608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192602901 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.2192602901 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.3727654913 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1880070576 ps |
| CPU time | 97.17 seconds |
| Started | Feb 08 11:54:14 AM UTC 25 |
| Finished | Feb 08 11:55:54 AM UTC 25 |
| Peak memory | 314980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727654913 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.3727654913 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3548678709 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5593124425 ps |
| CPU time | 9.6 seconds |
| Started | Feb 08 11:53:59 AM UTC 25 |
| Finished | Feb 08 11:54:10 AM UTC 25 |
| Peak memory | 213528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548678709 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.3548678709 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2298857970 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 91030568 ps |
| CPU time | 22.15 seconds |
| Started | Feb 08 11:53:54 AM UTC 25 |
| Finished | Feb 08 11:54:18 AM UTC 25 |
| Peak memory | 282260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298857970 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_max_throughput.2298857970 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3033177549 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 150347906 ps |
| CPU time | 7.33 seconds |
| Started | Feb 08 11:54:32 AM UTC 25 |
| Finished | Feb 08 11:54:41 AM UTC 25 |
| Peak memory | 224028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033177549 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.3033177549 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.4218145428 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 608185540 ps |
| CPU time | 6.64 seconds |
| Started | Feb 08 11:54:29 AM UTC 25 |
| Finished | Feb 08 11:54:38 AM UTC 25 |
| Peak memory | 223756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218145428 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.4218145428 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.4168111439 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5600016970 ps |
| CPU time | 499.85 seconds |
| Started | Feb 08 11:53:42 AM UTC 25 |
| Finished | Feb 08 12:02:08 PM UTC 25 |
| Peak memory | 364500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168111439 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.4168111439 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1589391393 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 112972608 ps |
| CPU time | 5.93 seconds |
| Started | Feb 08 11:53:46 AM UTC 25 |
| Finished | Feb 08 11:53:53 AM UTC 25 |
| Peak memory | 213784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589391393 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.1589391393 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.174656312 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 68704380379 ps |
| CPU time | 482.6 seconds |
| Started | Feb 08 11:53:46 AM UTC 25 |
| Finished | Feb 08 12:01:55 PM UTC 25 |
| Peak memory | 213648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174656312 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access_b2b.174656312 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3866531797 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 29783239 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 11:54:28 AM UTC 25 |
| Finished | Feb 08 11:54:31 AM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866531797 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3866531797 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2039603434 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 28702785761 ps |
| CPU time | 863.4 seconds |
| Started | Feb 08 11:54:19 AM UTC 25 |
| Finished | Feb 08 12:08:52 PM UTC 25 |
| Peak memory | 382688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039603434 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2039603434 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2960450625 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 175886601 ps |
| CPU time | 3.15 seconds |
| Started | Feb 08 11:53:40 AM UTC 25 |
| Finished | Feb 08 11:53:44 AM UTC 25 |
| Peak memory | 213616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960450625 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2960450625 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.2610655619 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 24280397213 ps |
| CPU time | 3726.25 seconds |
| Started | Feb 08 11:54:39 AM UTC 25 |
| Finished | Feb 08 12:57:22 PM UTC 25 |
| Peak memory | 386476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610655619 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.2610655619 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2037597767 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 320312960 ps |
| CPU time | 13.79 seconds |
| Started | Feb 08 11:54:33 AM UTC 25 |
| Finished | Feb 08 11:54:48 AM UTC 25 |
| Peak memory | 251556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037597767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2037597767 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2149416353 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 16332850633 ps |
| CPU time | 235.96 seconds |
| Started | Feb 08 11:53:45 AM UTC 25 |
| Finished | Feb 08 11:57:45 AM UTC 25 |
| Peak memory | 213764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149416353 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.2149416353 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3920410835 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 447907209 ps |
| CPU time | 62.45 seconds |
| Started | Feb 08 11:53:56 AM UTC 25 |
| Finished | Feb 08 11:55:01 AM UTC 25 |
| Peak memory | 321112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920410835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_throughput_w_partial_wr ite.3920410835 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2400858713 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4585893104 ps |
| CPU time | 579.59 seconds |
| Started | Feb 08 11:55:26 AM UTC 25 |
| Finished | Feb 08 12:05:12 PM UTC 25 |
| Peak memory | 382680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400858713 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during_key_req.2400858713 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3020020953 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 67867008 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 11:56:07 AM UTC 25 |
| Finished | Feb 08 11:56:09 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020020953 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3020020953 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1780043631 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3062784423 ps |
| CPU time | 34.09 seconds |
| Started | Feb 08 11:54:49 AM UTC 25 |
| Finished | Feb 08 11:55:25 AM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780043631 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1780043631 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1200267890 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 49731981906 ps |
| CPU time | 908.64 seconds |
| Started | Feb 08 11:55:40 AM UTC 25 |
| Finished | Feb 08 12:10:59 PM UTC 25 |
| Peak memory | 382600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200267890 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.1200267890 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4005317015 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 743133542 ps |
| CPU time | 12.96 seconds |
| Started | Feb 08 11:55:25 AM UTC 25 |
| Finished | Feb 08 11:55:39 AM UTC 25 |
| Peak memory | 223752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005317015 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.4005317015 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2204968573 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 379367183 ps |
| CPU time | 43.14 seconds |
| Started | Feb 08 11:55:21 AM UTC 25 |
| Finished | Feb 08 11:56:06 AM UTC 25 |
| Peak memory | 321100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204968573 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_max_throughput.2204968573 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.445031525 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 98750508 ps |
| CPU time | 4.95 seconds |
| Started | Feb 08 11:55:55 AM UTC 25 |
| Finished | Feb 08 11:56:02 AM UTC 25 |
| Peak memory | 223792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445031525 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.445031525 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.2345991191 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2055791936 ps |
| CPU time | 7.8 seconds |
| Started | Feb 08 11:55:53 AM UTC 25 |
| Finished | Feb 08 11:56:03 AM UTC 25 |
| Peak memory | 223808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345991191 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.2345991191 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2347509375 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8019442627 ps |
| CPU time | 320.76 seconds |
| Started | Feb 08 11:54:45 AM UTC 25 |
| Finished | Feb 08 12:00:11 PM UTC 25 |
| Peak memory | 335528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347509375 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.2347509375 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1540709840 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 209633912 ps |
| CPU time | 16.23 seconds |
| Started | Feb 08 11:55:01 AM UTC 25 |
| Finished | Feb 08 11:55:19 AM UTC 25 |
| Peak memory | 272028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540709840 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.1540709840 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3734890472 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 12419885064 ps |
| CPU time | 419.84 seconds |
| Started | Feb 08 11:55:10 AM UTC 25 |
| Finished | Feb 08 12:02:15 PM UTC 25 |
| Peak memory | 213712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734890472 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access_b2b.3734890472 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.725050128 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 27537582 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 11:55:50 AM UTC 25 |
| Finished | Feb 08 11:55:53 AM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725050128 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.725050128 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.793694195 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1068637314 ps |
| CPU time | 61.84 seconds |
| Started | Feb 08 11:54:45 AM UTC 25 |
| Finished | Feb 08 11:55:49 AM UTC 25 |
| Peak memory | 331284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793694195 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.793694195 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3104531838 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 82194182513 ps |
| CPU time | 5116.44 seconds |
| Started | Feb 08 11:56:04 AM UTC 25 |
| Finished | Feb 08 01:22:08 PM UTC 25 |
| Peak memory | 396608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104531838 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.3104531838 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3193544469 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 296171561 ps |
| CPU time | 7.44 seconds |
| Started | Feb 08 11:56:02 AM UTC 25 |
| Finished | Feb 08 11:56:11 AM UTC 25 |
| Peak memory | 223948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193544469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3193544469 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2557757506 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 6105648688 ps |
| CPU time | 176.6 seconds |
| Started | Feb 08 11:54:57 AM UTC 25 |
| Finished | Feb 08 11:57:58 AM UTC 25 |
| Peak memory | 213860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557757506 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.2557757506 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2135444583 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 586146592 ps |
| CPU time | 124.46 seconds |
| Started | Feb 08 11:55:21 AM UTC 25 |
| Finished | Feb 08 11:57:28 AM UTC 25 |
| Peak memory | 378704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135444583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_throughput_w_partial_wr ite.2135444583 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1032770522 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6268259212 ps |
| CPU time | 434.77 seconds |
| Started | Feb 08 11:57:02 AM UTC 25 |
| Finished | Feb 08 12:04:22 PM UTC 25 |
| Peak memory | 370388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032770522 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_key_req.1032770522 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.4010093110 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 85100946 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 11:57:42 AM UTC 25 |
| Finished | Feb 08 11:57:45 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010093110 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.4010093110 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.3666758824 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2095438080 ps |
| CPU time | 83.46 seconds |
| Started | Feb 08 11:56:16 AM UTC 25 |
| Finished | Feb 08 11:57:41 AM UTC 25 |
| Peak memory | 213616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666758824 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.3666758824 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.3464318778 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 51991213773 ps |
| CPU time | 752.9 seconds |
| Started | Feb 08 11:57:07 AM UTC 25 |
| Finished | Feb 08 12:09:49 PM UTC 25 |
| Peak memory | 382588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464318778 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.3464318778 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3944452928 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1526434341 ps |
| CPU time | 8.64 seconds |
| Started | Feb 08 11:56:50 AM UTC 25 |
| Finished | Feb 08 11:57:01 AM UTC 25 |
| Peak memory | 213876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944452928 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.3944452928 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3389166815 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 138425138 ps |
| CPU time | 105.02 seconds |
| Started | Feb 08 11:56:37 AM UTC 25 |
| Finished | Feb 08 11:58:25 AM UTC 25 |
| Peak memory | 380564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389166815 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_max_throughput.3389166815 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.4060564958 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 185003565 ps |
| CPU time | 3.68 seconds |
| Started | Feb 08 11:57:29 AM UTC 25 |
| Finished | Feb 08 11:57:34 AM UTC 25 |
| Peak memory | 223784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060564958 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.4060564958 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4248238009 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 230657780 ps |
| CPU time | 6.69 seconds |
| Started | Feb 08 11:57:25 AM UTC 25 |
| Finished | Feb 08 11:57:33 AM UTC 25 |
| Peak memory | 213612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248238009 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.4248238009 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1185624515 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1306473279 ps |
| CPU time | 194.01 seconds |
| Started | Feb 08 11:56:13 AM UTC 25 |
| Finished | Feb 08 11:59:30 AM UTC 25 |
| Peak memory | 360040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185624515 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.1185624515 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1165952970 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2288488940 ps |
| CPU time | 16.18 seconds |
| Started | Feb 08 11:56:19 AM UTC 25 |
| Finished | Feb 08 11:56:37 AM UTC 25 |
| Peak memory | 213580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165952970 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1165952970 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1851252720 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 51043759604 ps |
| CPU time | 287.61 seconds |
| Started | Feb 08 11:56:24 AM UTC 25 |
| Finished | Feb 08 12:01:16 PM UTC 25 |
| Peak memory | 213716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851252720 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access_b2b.1851252720 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3452533893 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 181404884 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 11:57:22 AM UTC 25 |
| Finished | Feb 08 11:57:24 AM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452533893 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3452533893 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.2440465219 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 11508596084 ps |
| CPU time | 899.33 seconds |
| Started | Feb 08 11:57:11 AM UTC 25 |
| Finished | Feb 08 12:12:20 PM UTC 25 |
| Peak memory | 386788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440465219 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2440465219 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.2473886611 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 299361888 ps |
| CPU time | 3.86 seconds |
| Started | Feb 08 11:56:10 AM UTC 25 |
| Finished | Feb 08 11:56:15 AM UTC 25 |
| Peak memory | 213700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473886611 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2473886611 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2928755215 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 143665255702 ps |
| CPU time | 1904.78 seconds |
| Started | Feb 08 11:57:35 AM UTC 25 |
| Finished | Feb 08 12:29:40 PM UTC 25 |
| Peak memory | 376212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928755215 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.2928755215 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3409676329 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 11058685501 ps |
| CPU time | 826.15 seconds |
| Started | Feb 08 11:57:34 AM UTC 25 |
| Finished | Feb 08 12:11:30 PM UTC 25 |
| Peak memory | 388796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409676329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3409676329 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.637758079 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 13429036207 ps |
| CPU time | 319.54 seconds |
| Started | Feb 08 11:56:18 AM UTC 25 |
| Finished | Feb 08 12:01:42 PM UTC 25 |
| Peak memory | 213652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637758079 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.637758079 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1196468447 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 82526729 ps |
| CPU time | 2.86 seconds |
| Started | Feb 08 11:56:45 AM UTC 25 |
| Finished | Feb 08 11:56:49 AM UTC 25 |
| Peak memory | 229976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196468447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_throughput_w_partial_wr ite.1196468447 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.307285273 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 10640998430 ps |
| CPU time | 707.92 seconds |
| Started | Feb 08 11:58:25 AM UTC 25 |
| Finished | Feb 08 12:10:21 PM UTC 25 |
| Peak memory | 378468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307285273 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during_key_req.307285273 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.14677995 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 16371723 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 11:59:06 AM UTC 25 |
| Finished | Feb 08 11:59:08 AM UTC 25 |
| Peak memory | 212952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14677995 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.14677995 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.688017993 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1809729591 ps |
| CPU time | 26.47 seconds |
| Started | Feb 08 11:57:51 AM UTC 25 |
| Finished | Feb 08 11:58:19 AM UTC 25 |
| Peak memory | 213732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688017993 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.688017993 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1791256382 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 12125896766 ps |
| CPU time | 1651.98 seconds |
| Started | Feb 08 11:58:29 AM UTC 25 |
| Finished | Feb 08 12:26:19 PM UTC 25 |
| Peak memory | 380552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791256382 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.1791256382 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3208832498 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3001186599 ps |
| CPU time | 6.7 seconds |
| Started | Feb 08 11:58:20 AM UTC 25 |
| Finished | Feb 08 11:58:28 AM UTC 25 |
| Peak memory | 213948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208832498 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.3208832498 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2516082200 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 392297510 ps |
| CPU time | 79.98 seconds |
| Started | Feb 08 11:58:13 AM UTC 25 |
| Finished | Feb 08 11:59:35 AM UTC 25 |
| Peak memory | 345784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516082200 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_max_throughput.2516082200 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3548950925 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 253095221 ps |
| CPU time | 7.1 seconds |
| Started | Feb 08 11:58:53 AM UTC 25 |
| Finished | Feb 08 11:59:03 AM UTC 25 |
| Peak memory | 223500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548950925 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.3548950925 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2992783681 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 531290724 ps |
| CPU time | 9.78 seconds |
| Started | Feb 08 11:58:41 AM UTC 25 |
| Finished | Feb 08 11:58:53 AM UTC 25 |
| Peak memory | 223828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992783681 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.2992783681 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1942413023 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 8549514846 ps |
| CPU time | 433.31 seconds |
| Started | Feb 08 11:57:45 AM UTC 25 |
| Finished | Feb 08 12:05:04 PM UTC 25 |
| Peak memory | 378252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942413023 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.1942413023 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3066372370 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 131527452 ps |
| CPU time | 4.14 seconds |
| Started | Feb 08 11:58:04 AM UTC 25 |
| Finished | Feb 08 11:58:09 AM UTC 25 |
| Peak memory | 213608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066372370 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.3066372370 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2476583678 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 23348052836 ps |
| CPU time | 409.16 seconds |
| Started | Feb 08 11:58:10 AM UTC 25 |
| Finished | Feb 08 12:05:05 PM UTC 25 |
| Peak memory | 213656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476583678 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access_b2b.2476583678 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2758949705 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 48310343 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 11:58:38 AM UTC 25 |
| Finished | Feb 08 11:58:41 AM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758949705 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2758949705 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1237244602 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 11202616665 ps |
| CPU time | 749.06 seconds |
| Started | Feb 08 11:58:34 AM UTC 25 |
| Finished | Feb 08 12:11:11 PM UTC 25 |
| Peak memory | 386688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237244602 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1237244602 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.718382856 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 938027150 ps |
| CPU time | 15.44 seconds |
| Started | Feb 08 11:57:45 AM UTC 25 |
| Finished | Feb 08 11:58:02 AM UTC 25 |
| Peak memory | 261212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718382856 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.718382856 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3151332117 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 57192361587 ps |
| CPU time | 2152.28 seconds |
| Started | Feb 08 11:59:04 AM UTC 25 |
| Finished | Feb 08 12:35:18 PM UTC 25 |
| Peak memory | 388540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151332117 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.3151332117 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.522964924 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1087679409 ps |
| CPU time | 150.22 seconds |
| Started | Feb 08 11:58:53 AM UTC 25 |
| Finished | Feb 08 12:01:27 PM UTC 25 |
| Peak memory | 388788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522964924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.522964924 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2047869238 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1696185226 ps |
| CPU time | 203.9 seconds |
| Started | Feb 08 11:57:59 AM UTC 25 |
| Finished | Feb 08 12:01:26 PM UTC 25 |
| Peak memory | 213688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047869238 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2047869238 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2031500904 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 142801167 ps |
| CPU time | 99.4 seconds |
| Started | Feb 08 11:58:20 AM UTC 25 |
| Finished | Feb 08 12:00:02 PM UTC 25 |
| Peak memory | 368200 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031500904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_throughput_w_partial_wr ite.2031500904 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.653173928 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 13001032909 ps |
| CPU time | 1056.69 seconds |
| Started | Feb 08 12:00:40 PM UTC 25 |
| Finished | Feb 08 12:18:27 PM UTC 25 |
| Peak memory | 384688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653173928 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during_key_req.653173928 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1055870431 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 12859804 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 12:01:16 PM UTC 25 |
| Finished | Feb 08 12:01:18 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055870431 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1055870431 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2758847417 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3817682325 ps |
| CPU time | 59.93 seconds |
| Started | Feb 08 11:59:31 AM UTC 25 |
| Finished | Feb 08 12:00:33 PM UTC 25 |
| Peak memory | 213720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758847417 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.2758847417 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.958329878 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3207801859 ps |
| CPU time | 469.47 seconds |
| Started | Feb 08 12:00:48 PM UTC 25 |
| Finished | Feb 08 12:08:43 PM UTC 25 |
| Peak memory | 384720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958329878 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.958329878 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1435506411 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2515714003 ps |
| CPU time | 12.65 seconds |
| Started | Feb 08 12:00:34 PM UTC 25 |
| Finished | Feb 08 12:00:48 PM UTC 25 |
| Peak memory | 223816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435506411 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.1435506411 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.4096501028 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 141322417 ps |
| CPU time | 13.8 seconds |
| Started | Feb 08 12:00:30 PM UTC 25 |
| Finished | Feb 08 12:00:47 PM UTC 25 |
| Peak memory | 263760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096501028 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_max_throughput.4096501028 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.4153700965 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 202597225 ps |
| CPU time | 8.12 seconds |
| Started | Feb 08 12:01:05 PM UTC 25 |
| Finished | Feb 08 12:01:15 PM UTC 25 |
| Peak memory | 223792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153700965 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.4153700965 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2479930816 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 850592328 ps |
| CPU time | 16.47 seconds |
| Started | Feb 08 12:00:56 PM UTC 25 |
| Finished | Feb 08 12:01:14 PM UTC 25 |
| Peak memory | 224016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479930816 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.2479930816 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3600983696 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 50056306617 ps |
| CPU time | 857.81 seconds |
| Started | Feb 08 11:59:30 AM UTC 25 |
| Finished | Feb 08 12:13:58 PM UTC 25 |
| Peak memory | 380620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600983696 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.3600983696 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2448949553 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 477634911 ps |
| CPU time | 18.72 seconds |
| Started | Feb 08 12:00:22 PM UTC 25 |
| Finished | Feb 08 12:00:52 PM UTC 25 |
| Peak memory | 213700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448949553 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.2448949553 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3481810705 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 25879634720 ps |
| CPU time | 419.01 seconds |
| Started | Feb 08 12:00:29 PM UTC 25 |
| Finished | Feb 08 12:07:37 PM UTC 25 |
| Peak memory | 213564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481810705 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access_b2b.3481810705 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.298580419 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 83728449 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 12:00:53 PM UTC 25 |
| Finished | Feb 08 12:00:56 PM UTC 25 |
| Peak memory | 212896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298580419 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.298580419 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.4190177507 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 914396738 ps |
| CPU time | 122.57 seconds |
| Started | Feb 08 12:00:49 PM UTC 25 |
| Finished | Feb 08 12:02:54 PM UTC 25 |
| Peak memory | 335516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190177507 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4190177507 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.3607988941 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 313371951 ps |
| CPU time | 19.04 seconds |
| Started | Feb 08 11:59:09 AM UTC 25 |
| Finished | Feb 08 11:59:29 AM UTC 25 |
| Peak memory | 288612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607988941 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3607988941 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2332012030 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 3953019838 ps |
| CPU time | 517.14 seconds |
| Started | Feb 08 12:01:16 PM UTC 25 |
| Finished | Feb 08 12:09:59 PM UTC 25 |
| Peak memory | 358100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332012030 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.2332012030 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4063823318 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 5666727349 ps |
| CPU time | 426.27 seconds |
| Started | Feb 08 12:01:15 PM UTC 25 |
| Finished | Feb 08 12:08:27 PM UTC 25 |
| Peak memory | 378652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063823318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.4063823318 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3777642582 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4253465704 ps |
| CPU time | 198.35 seconds |
| Started | Feb 08 11:59:36 AM UTC 25 |
| Finished | Feb 08 12:02:57 PM UTC 25 |
| Peak memory | 213680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777642582 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.3777642582 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.889591115 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 177537230 ps |
| CPU time | 31.44 seconds |
| Started | Feb 08 12:00:30 PM UTC 25 |
| Finished | Feb 08 12:01:05 PM UTC 25 |
| Peak memory | 290620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889591115 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.889591115 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2321095520 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 46428948539 ps |
| CPU time | 1035.64 seconds |
| Started | Feb 08 11:37:17 AM UTC 25 |
| Finished | Feb 08 11:54:45 AM UTC 25 |
| Peak memory | 386688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321095520 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_key_req.2321095520 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.4285809442 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 49281592 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 11:37:33 AM UTC 25 |
| Finished | Feb 08 11:37:35 AM UTC 25 |
| Peak memory | 212892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285809442 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4285809442 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.1841092181 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 19220089903 ps |
| CPU time | 116.14 seconds |
| Started | Feb 08 11:37:05 AM UTC 25 |
| Finished | Feb 08 11:39:03 AM UTC 25 |
| Peak memory | 213640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841092181 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.1841092181 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.2921278693 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 40089299861 ps |
| CPU time | 1489.18 seconds |
| Started | Feb 08 11:37:19 AM UTC 25 |
| Finished | Feb 08 12:02:23 PM UTC 25 |
| Peak memory | 386476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921278693 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.2921278693 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.265692684 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 96139069 ps |
| CPU time | 27.9 seconds |
| Started | Feb 08 11:37:15 AM UTC 25 |
| Finished | Feb 08 11:37:45 AM UTC 25 |
| Peak memory | 302748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265692684 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max_throughput.265692684 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.6673696 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 116145823 ps |
| CPU time | 4.36 seconds |
| Started | Feb 08 11:37:25 AM UTC 25 |
| Finished | Feb 08 11:37:31 AM UTC 25 |
| Peak memory | 223844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6673696 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.6673696 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3338394202 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 229460754 ps |
| CPU time | 8.13 seconds |
| Started | Feb 08 11:37:23 AM UTC 25 |
| Finished | Feb 08 11:37:33 AM UTC 25 |
| Peak memory | 213532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338394202 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.3338394202 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.318252361 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 7094224981 ps |
| CPU time | 594.71 seconds |
| Started | Feb 08 11:37:05 AM UTC 25 |
| Finished | Feb 08 11:47:07 AM UTC 25 |
| Peak memory | 378496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318252361 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.318252361 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1888126378 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2226746067 ps |
| CPU time | 20.12 seconds |
| Started | Feb 08 11:37:06 AM UTC 25 |
| Finished | Feb 08 11:37:28 AM UTC 25 |
| Peak memory | 282248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888126378 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.1888126378 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3803729485 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 8325645014 ps |
| CPU time | 157.99 seconds |
| Started | Feb 08 11:37:07 AM UTC 25 |
| Finished | Feb 08 11:39:48 AM UTC 25 |
| Peak memory | 213632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803729485 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access_b2b.3803729485 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3401470576 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 28658861 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 11:37:22 AM UTC 25 |
| Finished | Feb 08 11:37:25 AM UTC 25 |
| Peak memory | 212500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401470576 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3401470576 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.2730091274 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 9829468508 ps |
| CPU time | 496.26 seconds |
| Started | Feb 08 11:37:21 AM UTC 25 |
| Finished | Feb 08 11:45:44 AM UTC 25 |
| Peak memory | 384720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730091274 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2730091274 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2945425743 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 238111353 ps |
| CPU time | 3.61 seconds |
| Started | Feb 08 11:37:32 AM UTC 25 |
| Finished | Feb 08 11:37:37 AM UTC 25 |
| Peak memory | 249360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945425743 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2945425743 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.3692006688 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 187671602 ps |
| CPU time | 10.75 seconds |
| Started | Feb 08 11:37:02 AM UTC 25 |
| Finished | Feb 08 11:37:14 AM UTC 25 |
| Peak memory | 213828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692006688 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3692006688 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2701688039 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 76468974937 ps |
| CPU time | 2797.92 seconds |
| Started | Feb 08 11:37:29 AM UTC 25 |
| Finished | Feb 08 12:24:34 PM UTC 25 |
| Peak memory | 388520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701688039 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.2701688039 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2296668531 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5310675367 ps |
| CPU time | 315.37 seconds |
| Started | Feb 08 11:37:06 AM UTC 25 |
| Finished | Feb 08 11:42:26 AM UTC 25 |
| Peak memory | 213680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296668531 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.2296668531 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2425178271 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 36914820 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 11:37:15 AM UTC 25 |
| Finished | Feb 08 11:37:18 AM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425178271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_throughput_w_partial_wri te.2425178271 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.1240971969 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 8740812736 ps |
| CPU time | 766.86 seconds |
| Started | Feb 08 12:01:44 PM UTC 25 |
| Finished | Feb 08 12:14:39 PM UTC 25 |
| Peak memory | 384644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240971969 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during_key_req.1240971969 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2997751439 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 23786878 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 12:02:24 PM UTC 25 |
| Finished | Feb 08 12:02:26 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997751439 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.2997751439 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.1878561376 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 16717190026 ps |
| CPU time | 100.68 seconds |
| Started | Feb 08 12:01:19 PM UTC 25 |
| Finished | Feb 08 12:03:02 PM UTC 25 |
| Peak memory | 213752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878561376 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.1878561376 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3544470675 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4039509431 ps |
| CPU time | 980.35 seconds |
| Started | Feb 08 12:01:54 PM UTC 25 |
| Finished | Feb 08 12:18:25 PM UTC 25 |
| Peak memory | 384704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544470675 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.3544470675 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2585869852 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 593678721 ps |
| CPU time | 8.78 seconds |
| Started | Feb 08 12:01:43 PM UTC 25 |
| Finished | Feb 08 12:01:53 PM UTC 25 |
| Peak memory | 213768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585869852 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.2585869852 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3583881884 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 408749359 ps |
| CPU time | 58.14 seconds |
| Started | Feb 08 12:01:37 PM UTC 25 |
| Finished | Feb 08 12:02:37 PM UTC 25 |
| Peak memory | 329340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583881884 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max_throughput.3583881884 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.20851190 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 245303400 ps |
| CPU time | 4.72 seconds |
| Started | Feb 08 12:02:13 PM UTC 25 |
| Finished | Feb 08 12:02:19 PM UTC 25 |
| Peak memory | 223884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20851190 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.20851190 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.1107846234 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2220717909 ps |
| CPU time | 14.77 seconds |
| Started | Feb 08 12:02:12 PM UTC 25 |
| Finished | Feb 08 12:02:28 PM UTC 25 |
| Peak memory | 223936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107846234 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.1107846234 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2385966478 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 61878922695 ps |
| CPU time | 1740.72 seconds |
| Started | Feb 08 12:01:17 PM UTC 25 |
| Finished | Feb 08 12:30:37 PM UTC 25 |
| Peak memory | 384876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385966478 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.2385966478 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.767774335 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1249683804 ps |
| CPU time | 14.29 seconds |
| Started | Feb 08 12:01:27 PM UTC 25 |
| Finished | Feb 08 12:01:43 PM UTC 25 |
| Peak memory | 213600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767774335 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.767774335 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.4022096773 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 38096455888 ps |
| CPU time | 253.74 seconds |
| Started | Feb 08 12:01:28 PM UTC 25 |
| Finished | Feb 08 12:05:46 PM UTC 25 |
| Peak memory | 213584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022096773 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access_b2b.4022096773 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3186895212 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 88847992 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 12:02:09 PM UTC 25 |
| Finished | Feb 08 12:02:11 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186895212 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3186895212 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.2500602873 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 36106586799 ps |
| CPU time | 863.1 seconds |
| Started | Feb 08 12:01:56 PM UTC 25 |
| Finished | Feb 08 12:16:28 PM UTC 25 |
| Peak memory | 382580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500602873 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2500602873 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2128831404 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 572265585 ps |
| CPU time | 104.49 seconds |
| Started | Feb 08 12:01:16 PM UTC 25 |
| Finished | Feb 08 12:03:03 PM UTC 25 |
| Peak memory | 364108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128831404 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2128831404 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1410217136 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 39665703455 ps |
| CPU time | 1294.06 seconds |
| Started | Feb 08 12:02:20 PM UTC 25 |
| Finished | Feb 08 12:24:08 PM UTC 25 |
| Peak memory | 394892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410217136 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.1410217136 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2581626645 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4237534714 ps |
| CPU time | 178.99 seconds |
| Started | Feb 08 12:02:16 PM UTC 25 |
| Finished | Feb 08 12:05:18 PM UTC 25 |
| Peak memory | 343784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581626645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2581626645 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.7813378 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2788798216 ps |
| CPU time | 268.29 seconds |
| Started | Feb 08 12:01:20 PM UTC 25 |
| Finished | Feb 08 12:05:52 PM UTC 25 |
| Peak memory | 213856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7813378 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.7813378 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.245188237 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2716183254 ps |
| CPU time | 91.88 seconds |
| Started | Feb 08 12:01:43 PM UTC 25 |
| Finished | Feb 08 12:03:17 PM UTC 25 |
| Peak memory | 368532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245188237 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.245188237 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1728706221 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 4758023535 ps |
| CPU time | 442.02 seconds |
| Started | Feb 08 12:02:58 PM UTC 25 |
| Finished | Feb 08 12:10:25 PM UTC 25 |
| Peak memory | 384912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728706221 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during_key_req.1728706221 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3942097210 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 54996386 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 12:03:26 PM UTC 25 |
| Finished | Feb 08 12:03:28 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942097210 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.3942097210 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.1554896199 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 233504208 ps |
| CPU time | 18.71 seconds |
| Started | Feb 08 12:02:28 PM UTC 25 |
| Finished | Feb 08 12:02:49 PM UTC 25 |
| Peak memory | 213744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554896199 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.1554896199 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.3213233672 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 5483407253 ps |
| CPU time | 662.17 seconds |
| Started | Feb 08 12:03:03 PM UTC 25 |
| Finished | Feb 08 12:14:13 PM UTC 25 |
| Peak memory | 384728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213233672 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.3213233672 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.2145213642 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1821558528 ps |
| CPU time | 9.07 seconds |
| Started | Feb 08 12:02:55 PM UTC 25 |
| Finished | Feb 08 12:03:06 PM UTC 25 |
| Peak memory | 213664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145213642 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.2145213642 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.5644891 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 372628726 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 12:02:50 PM UTC 25 |
| Finished | Feb 08 12:02:53 PM UTC 25 |
| Peak memory | 222736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5644891 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_max_throughput.5644891 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3551873536 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 315729477 ps |
| CPU time | 6.09 seconds |
| Started | Feb 08 12:03:11 PM UTC 25 |
| Finished | Feb 08 12:03:19 PM UTC 25 |
| Peak memory | 223780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551873536 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.3551873536 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1018555366 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3403755115 ps |
| CPU time | 13.54 seconds |
| Started | Feb 08 12:03:09 PM UTC 25 |
| Finished | Feb 08 12:03:24 PM UTC 25 |
| Peak memory | 223876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018555366 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1018555366 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.2569351259 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 6408133470 ps |
| CPU time | 602.5 seconds |
| Started | Feb 08 12:02:27 PM UTC 25 |
| Finished | Feb 08 12:12:37 PM UTC 25 |
| Peak memory | 364396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569351259 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.2569351259 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2254348637 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1238096283 ps |
| CPU time | 9.49 seconds |
| Started | Feb 08 12:02:38 PM UTC 25 |
| Finished | Feb 08 12:02:49 PM UTC 25 |
| Peak memory | 213796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254348637 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2254348637 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3923316199 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 4154259521 ps |
| CPU time | 346.56 seconds |
| Started | Feb 08 12:02:50 PM UTC 25 |
| Finished | Feb 08 12:08:41 PM UTC 25 |
| Peak memory | 213852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923316199 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access_b2b.3923316199 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.440624586 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 43253011 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 12:03:06 PM UTC 25 |
| Finished | Feb 08 12:03:09 PM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440624586 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.440624586 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.3750260946 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 18567316457 ps |
| CPU time | 535.78 seconds |
| Started | Feb 08 12:03:03 PM UTC 25 |
| Finished | Feb 08 12:12:06 PM UTC 25 |
| Peak memory | 384656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750260946 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3750260946 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.2904340862 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 143544258 ps |
| CPU time | 108 seconds |
| Started | Feb 08 12:02:27 PM UTC 25 |
| Finished | Feb 08 12:04:18 PM UTC 25 |
| Peak memory | 357972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904340862 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2904340862 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1381964658 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 17938239215 ps |
| CPU time | 1962.13 seconds |
| Started | Feb 08 12:03:20 PM UTC 25 |
| Finished | Feb 08 12:36:23 PM UTC 25 |
| Peak memory | 396712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381964658 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.1381964658 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1292184657 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5088930695 ps |
| CPU time | 86.55 seconds |
| Started | Feb 08 12:03:20 PM UTC 25 |
| Finished | Feb 08 12:04:48 PM UTC 25 |
| Peak memory | 231280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292184657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1292184657 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3836956878 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 13725104209 ps |
| CPU time | 339.63 seconds |
| Started | Feb 08 12:02:35 PM UTC 25 |
| Finished | Feb 08 12:08:20 PM UTC 25 |
| Peak memory | 213652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836956878 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.3836956878 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2272434191 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 134959748 ps |
| CPU time | 35.4 seconds |
| Started | Feb 08 12:02:54 PM UTC 25 |
| Finished | Feb 08 12:03:31 PM UTC 25 |
| Peak memory | 329424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272434191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_throughput_w_partial_wr ite.2272434191 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3917798338 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 22377393671 ps |
| CPU time | 389.24 seconds |
| Started | Feb 08 12:04:30 PM UTC 25 |
| Finished | Feb 08 12:11:04 PM UTC 25 |
| Peak memory | 355976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917798338 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during_key_req.3917798338 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1711837146 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 15741986 ps |
| CPU time | 0.77 seconds |
| Started | Feb 08 12:05:05 PM UTC 25 |
| Finished | Feb 08 12:05:08 PM UTC 25 |
| Peak memory | 212316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711837146 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1711837146 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3626631864 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3639763479 ps |
| CPU time | 95.01 seconds |
| Started | Feb 08 12:03:34 PM UTC 25 |
| Finished | Feb 08 12:05:11 PM UTC 25 |
| Peak memory | 213652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626631864 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.3626631864 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3833556732 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 51388291449 ps |
| CPU time | 1441.95 seconds |
| Started | Feb 08 12:04:31 PM UTC 25 |
| Finished | Feb 08 12:28:48 PM UTC 25 |
| Peak memory | 386692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833556732 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.3833556732 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3559647249 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 496260719 ps |
| CPU time | 5.89 seconds |
| Started | Feb 08 12:04:27 PM UTC 25 |
| Finished | Feb 08 12:04:34 PM UTC 25 |
| Peak memory | 223784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559647249 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.3559647249 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.599422725 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 205350321 ps |
| CPU time | 6.3 seconds |
| Started | Feb 08 12:04:18 PM UTC 25 |
| Finished | Feb 08 12:04:26 PM UTC 25 |
| Peak memory | 247372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599422725 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max_throughput.599422725 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3347260241 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 108707312 ps |
| CPU time | 4.64 seconds |
| Started | Feb 08 12:04:55 PM UTC 25 |
| Finished | Feb 08 12:05:01 PM UTC 25 |
| Peak memory | 224008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347260241 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.3347260241 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.276511363 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 236275691 ps |
| CPU time | 6.72 seconds |
| Started | Feb 08 12:04:52 PM UTC 25 |
| Finished | Feb 08 12:05:00 PM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276511363 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.276511363 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2632573379 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3449138479 ps |
| CPU time | 319.7 seconds |
| Started | Feb 08 12:03:32 PM UTC 25 |
| Finished | Feb 08 12:08:56 PM UTC 25 |
| Peak memory | 366264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632573379 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.2632573379 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3415622173 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 51210396 ps |
| CPU time | 3.08 seconds |
| Started | Feb 08 12:03:51 PM UTC 25 |
| Finished | Feb 08 12:03:56 PM UTC 25 |
| Peak memory | 219732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415622173 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.3415622173 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1091859667 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 16240093553 ps |
| CPU time | 402.65 seconds |
| Started | Feb 08 12:03:57 PM UTC 25 |
| Finished | Feb 08 12:10:45 PM UTC 25 |
| Peak memory | 213848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091859667 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access_b2b.1091859667 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.2643885954 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 217910958 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 12:04:49 PM UTC 25 |
| Finished | Feb 08 12:04:52 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643885954 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2643885954 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1189153414 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 5214207803 ps |
| CPU time | 421.05 seconds |
| Started | Feb 08 12:04:35 PM UTC 25 |
| Finished | Feb 08 12:11:42 PM UTC 25 |
| Peak memory | 380568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189153414 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1189153414 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.1380554786 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 992616614 ps |
| CPU time | 18.98 seconds |
| Started | Feb 08 12:03:30 PM UTC 25 |
| Finished | Feb 08 12:03:50 PM UTC 25 |
| Peak memory | 213608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380554786 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1380554786 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3397825464 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4220743454 ps |
| CPU time | 47.76 seconds |
| Started | Feb 08 12:05:01 PM UTC 25 |
| Finished | Feb 08 12:05:51 PM UTC 25 |
| Peak memory | 223940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397825464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3397825464 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1613187331 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 22044077137 ps |
| CPU time | 251.28 seconds |
| Started | Feb 08 12:03:48 PM UTC 25 |
| Finished | Feb 08 12:08:04 PM UTC 25 |
| Peak memory | 213700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613187331 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.1613187331 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.4287652316 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 57332380 ps |
| CPU time | 5.94 seconds |
| Started | Feb 08 12:04:22 PM UTC 25 |
| Finished | Feb 08 12:04:30 PM UTC 25 |
| Peak memory | 235080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287652316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_throughput_w_partial_wr ite.4287652316 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2263975153 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 7579434882 ps |
| CPU time | 670.68 seconds |
| Started | Feb 08 12:05:47 PM UTC 25 |
| Finished | Feb 08 12:17:06 PM UTC 25 |
| Peak memory | 378484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263975153 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during_key_req.2263975153 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3249164630 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 28257494 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 12:06:08 PM UTC 25 |
| Finished | Feb 08 12:06:10 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249164630 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3249164630 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.1091767289 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1015934335 ps |
| CPU time | 65.57 seconds |
| Started | Feb 08 12:05:13 PM UTC 25 |
| Finished | Feb 08 12:06:20 PM UTC 25 |
| Peak memory | 213688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091767289 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.1091767289 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.2742407389 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3487223781 ps |
| CPU time | 946.43 seconds |
| Started | Feb 08 12:05:51 PM UTC 25 |
| Finished | Feb 08 12:21:49 PM UTC 25 |
| Peak memory | 386772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742407389 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.2742407389 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1229438683 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3049485853 ps |
| CPU time | 9.45 seconds |
| Started | Feb 08 12:05:43 PM UTC 25 |
| Finished | Feb 08 12:05:54 PM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229438683 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.1229438683 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2139053516 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 93581929 ps |
| CPU time | 26.66 seconds |
| Started | Feb 08 12:05:29 PM UTC 25 |
| Finished | Feb 08 12:05:57 PM UTC 25 |
| Peak memory | 300620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139053516 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_max_throughput.2139053516 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.1646535079 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 369766422 ps |
| CPU time | 8.55 seconds |
| Started | Feb 08 12:05:59 PM UTC 25 |
| Finished | Feb 08 12:06:09 PM UTC 25 |
| Peak memory | 223804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646535079 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.1646535079 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3062256789 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 229608926 ps |
| CPU time | 7.75 seconds |
| Started | Feb 08 12:05:58 PM UTC 25 |
| Finished | Feb 08 12:06:07 PM UTC 25 |
| Peak memory | 223812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062256789 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.3062256789 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.759587133 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 832243501 ps |
| CPU time | 32.28 seconds |
| Started | Feb 08 12:05:09 PM UTC 25 |
| Finished | Feb 08 12:05:43 PM UTC 25 |
| Peak memory | 278164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759587133 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.759587133 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.666256980 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1287726311 ps |
| CPU time | 9.08 seconds |
| Started | Feb 08 12:05:18 PM UTC 25 |
| Finished | Feb 08 12:05:28 PM UTC 25 |
| Peak memory | 213504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666256980 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.666256980 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3153569238 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 57034340152 ps |
| CPU time | 427.54 seconds |
| Started | Feb 08 12:05:19 PM UTC 25 |
| Finished | Feb 08 12:12:32 PM UTC 25 |
| Peak memory | 213656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153569238 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access_b2b.3153569238 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.594299627 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 288704093 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 12:05:54 PM UTC 25 |
| Finished | Feb 08 12:05:57 PM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594299627 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.594299627 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.934124724 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 15528574942 ps |
| CPU time | 791.55 seconds |
| Started | Feb 08 12:05:53 PM UTC 25 |
| Finished | Feb 08 12:19:14 PM UTC 25 |
| Peak memory | 384708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934124724 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.934124724 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.349985153 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1533354243 ps |
| CPU time | 34.54 seconds |
| Started | Feb 08 12:05:05 PM UTC 25 |
| Finished | Feb 08 12:05:42 PM UTC 25 |
| Peak memory | 296524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349985153 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.349985153 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1188700642 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 4891724616 ps |
| CPU time | 527.97 seconds |
| Started | Feb 08 12:06:02 PM UTC 25 |
| Finished | Feb 08 12:14:56 PM UTC 25 |
| Peak memory | 393152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188700642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1188700642 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2869974720 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 28370957957 ps |
| CPU time | 310.77 seconds |
| Started | Feb 08 12:05:13 PM UTC 25 |
| Finished | Feb 08 12:10:28 PM UTC 25 |
| Peak memory | 213628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869974720 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.2869974720 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1988074667 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 208924707 ps |
| CPU time | 48.72 seconds |
| Started | Feb 08 12:05:43 PM UTC 25 |
| Finished | Feb 08 12:06:34 PM UTC 25 |
| Peak memory | 312948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988074667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_throughput_w_partial_wr ite.1988074667 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2539490345 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2113092990 ps |
| CPU time | 801.32 seconds |
| Started | Feb 08 12:07:28 PM UTC 25 |
| Finished | Feb 08 12:20:59 PM UTC 25 |
| Peak memory | 382608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539490345 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during_key_req.2539490345 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2788237587 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 46805622 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 12:08:29 PM UTC 25 |
| Finished | Feb 08 12:08:31 PM UTC 25 |
| Peak memory | 212552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788237587 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2788237587 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1437563346 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2230260683 ps |
| CPU time | 52.67 seconds |
| Started | Feb 08 12:06:21 PM UTC 25 |
| Finished | Feb 08 12:07:16 PM UTC 25 |
| Peak memory | 213672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437563346 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.1437563346 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.1693588020 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 53997185865 ps |
| CPU time | 367.19 seconds |
| Started | Feb 08 12:07:38 PM UTC 25 |
| Finished | Feb 08 12:13:50 PM UTC 25 |
| Peak memory | 350100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693588020 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.1693588020 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2085301555 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 571241048 ps |
| CPU time | 8.07 seconds |
| Started | Feb 08 12:07:18 PM UTC 25 |
| Finished | Feb 08 12:07:27 PM UTC 25 |
| Peak memory | 224104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085301555 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.2085301555 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.233074002 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 139488176 ps |
| CPU time | 117.81 seconds |
| Started | Feb 08 12:07:15 PM UTC 25 |
| Finished | Feb 08 12:09:15 PM UTC 25 |
| Peak memory | 378448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233074002 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_max_throughput.233074002 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3883623348 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 667124733 ps |
| CPU time | 7.29 seconds |
| Started | Feb 08 12:08:19 PM UTC 25 |
| Finished | Feb 08 12:08:28 PM UTC 25 |
| Peak memory | 224000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883623348 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.3883623348 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1885452845 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 606998769 ps |
| CPU time | 7.86 seconds |
| Started | Feb 08 12:08:10 PM UTC 25 |
| Finished | Feb 08 12:08:20 PM UTC 25 |
| Peak memory | 223896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885452845 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.1885452845 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.1335911710 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2184509148 ps |
| CPU time | 185.34 seconds |
| Started | Feb 08 12:06:11 PM UTC 25 |
| Finished | Feb 08 12:09:20 PM UTC 25 |
| Peak memory | 321152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335911710 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.1335911710 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2312583323 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 153467118 ps |
| CPU time | 24.28 seconds |
| Started | Feb 08 12:06:48 PM UTC 25 |
| Finished | Feb 08 12:07:14 PM UTC 25 |
| Peak memory | 282268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312583323 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.2312583323 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2373504729 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 6734944992 ps |
| CPU time | 176.64 seconds |
| Started | Feb 08 12:07:00 PM UTC 25 |
| Finished | Feb 08 12:10:00 PM UTC 25 |
| Peak memory | 213824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373504729 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access_b2b.2373504729 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2053890043 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 45897682 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 12:08:07 PM UTC 25 |
| Finished | Feb 08 12:08:10 PM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053890043 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2053890043 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.147192150 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3799510676 ps |
| CPU time | 47.14 seconds |
| Started | Feb 08 12:08:04 PM UTC 25 |
| Finished | Feb 08 12:08:53 PM UTC 25 |
| Peak memory | 219800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147192150 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.147192150 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.933137361 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 926679658 ps |
| CPU time | 126.45 seconds |
| Started | Feb 08 12:06:09 PM UTC 25 |
| Finished | Feb 08 12:08:18 PM UTC 25 |
| Peak memory | 378308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933137361 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.933137361 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3876806862 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 56422466297 ps |
| CPU time | 3708.5 seconds |
| Started | Feb 08 12:08:21 PM UTC 25 |
| Finished | Feb 08 01:10:48 PM UTC 25 |
| Peak memory | 388432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876806862 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.3876806862 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2829748253 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4819326083 ps |
| CPU time | 135.23 seconds |
| Started | Feb 08 12:08:21 PM UTC 25 |
| Finished | Feb 08 12:10:38 PM UTC 25 |
| Peak memory | 386840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829748253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2829748253 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1252965487 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 13252228849 ps |
| CPU time | 380.4 seconds |
| Started | Feb 08 12:06:34 PM UTC 25 |
| Finished | Feb 08 12:13:00 PM UTC 25 |
| Peak memory | 213572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252965487 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.1252965487 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1209207980 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 450583848 ps |
| CPU time | 96.32 seconds |
| Started | Feb 08 12:07:17 PM UTC 25 |
| Finished | Feb 08 12:08:55 PM UTC 25 |
| Peak memory | 378716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209207980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_throughput_w_partial_wr ite.1209207980 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.3553548022 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3150190828 ps |
| CPU time | 767.87 seconds |
| Started | Feb 08 12:09:06 PM UTC 25 |
| Finished | Feb 08 12:22:02 PM UTC 25 |
| Peak memory | 384912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553548022 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during_key_req.3553548022 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.3958526024 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 13698422 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 12:09:41 PM UTC 25 |
| Finished | Feb 08 12:09:44 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958526024 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.3958526024 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.4167389950 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 6938636760 ps |
| CPU time | 56.53 seconds |
| Started | Feb 08 12:08:33 PM UTC 25 |
| Finished | Feb 08 12:09:31 PM UTC 25 |
| Peak memory | 213748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167389950 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.4167389950 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.2449926551 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 3540398469 ps |
| CPU time | 340.06 seconds |
| Started | Feb 08 12:09:17 PM UTC 25 |
| Finished | Feb 08 12:15:02 PM UTC 25 |
| Peak memory | 384884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449926551 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.2449926551 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.2768879909 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 282610059 ps |
| CPU time | 5.61 seconds |
| Started | Feb 08 12:08:57 PM UTC 25 |
| Finished | Feb 08 12:09:04 PM UTC 25 |
| Peak memory | 213684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768879909 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.2768879909 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4194045667 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 510791174 ps |
| CPU time | 99.69 seconds |
| Started | Feb 08 12:08:54 PM UTC 25 |
| Finished | Feb 08 12:10:36 PM UTC 25 |
| Peak memory | 370240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194045667 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_max_throughput.4194045667 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.965462283 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 611176971 ps |
| CPU time | 7.11 seconds |
| Started | Feb 08 12:09:32 PM UTC 25 |
| Finished | Feb 08 12:09:41 PM UTC 25 |
| Peak memory | 223832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965462283 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.965462283 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1615193711 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 254652556 ps |
| CPU time | 5.68 seconds |
| Started | Feb 08 12:09:24 PM UTC 25 |
| Finished | Feb 08 12:09:31 PM UTC 25 |
| Peak memory | 224128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615193711 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1615193711 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.2274076787 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 45671235668 ps |
| CPU time | 1426.15 seconds |
| Started | Feb 08 12:08:32 PM UTC 25 |
| Finished | Feb 08 12:32:34 PM UTC 25 |
| Peak memory | 384640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274076787 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.2274076787 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.79695519 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 782614726 ps |
| CPU time | 136.31 seconds |
| Started | Feb 08 12:08:44 PM UTC 25 |
| Finished | Feb 08 12:11:03 PM UTC 25 |
| Peak memory | 378512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79695519 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.79695519 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.897531613 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 64861554821 ps |
| CPU time | 313.79 seconds |
| Started | Feb 08 12:08:53 PM UTC 25 |
| Finished | Feb 08 12:14:12 PM UTC 25 |
| Peak memory | 213548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897531613 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access_b2b.897531613 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2277748359 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 31040230 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 12:09:21 PM UTC 25 |
| Finished | Feb 08 12:09:23 PM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277748359 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2277748359 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1347587924 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 489818524 ps |
| CPU time | 118.8 seconds |
| Started | Feb 08 12:09:19 PM UTC 25 |
| Finished | Feb 08 12:11:20 PM UTC 25 |
| Peak memory | 382540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347587924 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1347587924 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1843601409 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 901629214 ps |
| CPU time | 124.48 seconds |
| Started | Feb 08 12:08:29 PM UTC 25 |
| Finished | Feb 08 12:10:36 PM UTC 25 |
| Peak memory | 374424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843601409 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1843601409 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.3811481000 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 106925879316 ps |
| CPU time | 1719.4 seconds |
| Started | Feb 08 12:09:40 PM UTC 25 |
| Finished | Feb 08 12:38:38 PM UTC 25 |
| Peak memory | 388524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811481000 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.3811481000 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2000736442 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2887718416 ps |
| CPU time | 78.3 seconds |
| Started | Feb 08 12:09:32 PM UTC 25 |
| Finished | Feb 08 12:10:52 PM UTC 25 |
| Peak memory | 306948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000736442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2000736442 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2697573661 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3247424831 ps |
| CPU time | 338.51 seconds |
| Started | Feb 08 12:08:42 PM UTC 25 |
| Finished | Feb 08 12:14:25 PM UTC 25 |
| Peak memory | 213788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697573661 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.2697573661 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1959570412 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 413368412 ps |
| CPU time | 40.84 seconds |
| Started | Feb 08 12:08:56 PM UTC 25 |
| Finished | Feb 08 12:09:39 PM UTC 25 |
| Peak memory | 313168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959570412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_throughput_w_partial_wr ite.1959570412 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.730321457 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 9128596058 ps |
| CPU time | 613.63 seconds |
| Started | Feb 08 12:10:26 PM UTC 25 |
| Finished | Feb 08 12:20:47 PM UTC 25 |
| Peak memory | 380544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730321457 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_key_req.730321457 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.4272800525 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 47816063 ps |
| CPU time | 0.83 seconds |
| Started | Feb 08 12:10:46 PM UTC 25 |
| Finished | Feb 08 12:10:48 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272800525 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.4272800525 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3880966712 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6769231787 ps |
| CPU time | 25.56 seconds |
| Started | Feb 08 12:09:50 PM UTC 25 |
| Finished | Feb 08 12:10:17 PM UTC 25 |
| Peak memory | 213536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880966712 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.3880966712 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.2780706728 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 48874922443 ps |
| CPU time | 628.38 seconds |
| Started | Feb 08 12:10:29 PM UTC 25 |
| Finished | Feb 08 12:21:05 PM UTC 25 |
| Peak memory | 368216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780706728 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.2780706728 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2097994870 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1713766808 ps |
| CPU time | 6.74 seconds |
| Started | Feb 08 12:10:23 PM UTC 25 |
| Finished | Feb 08 12:10:31 PM UTC 25 |
| Peak memory | 213684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097994870 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.2097994870 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.645708436 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 112145009 ps |
| CPU time | 47.98 seconds |
| Started | Feb 08 12:10:20 PM UTC 25 |
| Finished | Feb 08 12:11:10 PM UTC 25 |
| Peak memory | 333464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645708436 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_max_throughput.645708436 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3537601708 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 46468664 ps |
| CPU time | 3.31 seconds |
| Started | Feb 08 12:10:40 PM UTC 25 |
| Finished | Feb 08 12:10:44 PM UTC 25 |
| Peak memory | 223776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537601708 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.3537601708 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3423580935 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 238080882 ps |
| CPU time | 7.37 seconds |
| Started | Feb 08 12:10:38 PM UTC 25 |
| Finished | Feb 08 12:10:46 PM UTC 25 |
| Peak memory | 223828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423580935 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.3423580935 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.379980752 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 13609207924 ps |
| CPU time | 850.7 seconds |
| Started | Feb 08 12:09:44 PM UTC 25 |
| Finished | Feb 08 12:24:06 PM UTC 25 |
| Peak memory | 382612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379980752 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.379980752 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.1926924050 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 464344719 ps |
| CPU time | 20 seconds |
| Started | Feb 08 12:10:01 PM UTC 25 |
| Finished | Feb 08 12:10:22 PM UTC 25 |
| Peak memory | 267848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926924050 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.1926924050 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2501070624 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 4566377892 ps |
| CPU time | 353.85 seconds |
| Started | Feb 08 12:10:18 PM UTC 25 |
| Finished | Feb 08 12:16:17 PM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501070624 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access_b2b.2501070624 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2731879110 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 85436624 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 12:10:36 PM UTC 25 |
| Finished | Feb 08 12:10:39 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731879110 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2731879110 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.505966952 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 27564348700 ps |
| CPU time | 732.81 seconds |
| Started | Feb 08 12:10:32 PM UTC 25 |
| Finished | Feb 08 12:22:54 PM UTC 25 |
| Peak memory | 384664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505966952 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.505966952 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.609428620 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1080382566 ps |
| CPU time | 35.02 seconds |
| Started | Feb 08 12:09:42 PM UTC 25 |
| Finished | Feb 08 12:10:19 PM UTC 25 |
| Peak memory | 327324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609428620 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.609428620 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2172523376 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 11488297878 ps |
| CPU time | 2795.01 seconds |
| Started | Feb 08 12:10:45 PM UTC 25 |
| Finished | Feb 08 12:57:48 PM UTC 25 |
| Peak memory | 386528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172523376 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.2172523376 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1894487341 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2678166135 ps |
| CPU time | 299.19 seconds |
| Started | Feb 08 12:10:40 PM UTC 25 |
| Finished | Feb 08 12:15:43 PM UTC 25 |
| Peak memory | 366360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894487341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1894487341 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2974230161 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 8136631311 ps |
| CPU time | 161.1 seconds |
| Started | Feb 08 12:10:00 PM UTC 25 |
| Finished | Feb 08 12:12:44 PM UTC 25 |
| Peak memory | 213544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974230161 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.2974230161 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3560888107 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 424648009 ps |
| CPU time | 47.29 seconds |
| Started | Feb 08 12:10:22 PM UTC 25 |
| Finished | Feb 08 12:11:11 PM UTC 25 |
| Peak memory | 319280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560888107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_throughput_w_partial_wr ite.3560888107 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1023793307 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4393310167 ps |
| CPU time | 1191.46 seconds |
| Started | Feb 08 12:11:13 PM UTC 25 |
| Finished | Feb 08 12:31:17 PM UTC 25 |
| Peak memory | 384920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023793307 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_key_req.1023793307 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2768069414 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 21171014 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 12:11:31 PM UTC 25 |
| Finished | Feb 08 12:11:33 PM UTC 25 |
| Peak memory | 212960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768069414 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.2768069414 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.229250997 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 877338336 ps |
| CPU time | 64.43 seconds |
| Started | Feb 08 12:10:53 PM UTC 25 |
| Finished | Feb 08 12:12:00 PM UTC 25 |
| Peak memory | 213512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229250997 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.229250997 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.1504034080 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 18039015739 ps |
| CPU time | 978.1 seconds |
| Started | Feb 08 12:11:17 PM UTC 25 |
| Finished | Feb 08 12:27:46 PM UTC 25 |
| Peak memory | 384520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504034080 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.1504034080 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.4247960663 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1443910357 ps |
| CPU time | 6.76 seconds |
| Started | Feb 08 12:11:12 PM UTC 25 |
| Finished | Feb 08 12:11:20 PM UTC 25 |
| Peak memory | 227840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247960663 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.4247960663 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.129276083 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 167183827 ps |
| CPU time | 3.73 seconds |
| Started | Feb 08 12:11:10 PM UTC 25 |
| Finished | Feb 08 12:11:16 PM UTC 25 |
| Peak memory | 230884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129276083 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_max_throughput.129276083 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3021854163 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1425104651 ps |
| CPU time | 8.07 seconds |
| Started | Feb 08 12:11:24 PM UTC 25 |
| Finished | Feb 08 12:11:33 PM UTC 25 |
| Peak memory | 223924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021854163 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.3021854163 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1310900613 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 114670112 ps |
| CPU time | 5.42 seconds |
| Started | Feb 08 12:11:22 PM UTC 25 |
| Finished | Feb 08 12:11:29 PM UTC 25 |
| Peak memory | 223904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310900613 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.1310900613 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2821940559 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 12290897052 ps |
| CPU time | 266.06 seconds |
| Started | Feb 08 12:10:49 PM UTC 25 |
| Finished | Feb 08 12:15:19 PM UTC 25 |
| Peak memory | 370304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821940559 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2821940559 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.119327741 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 460344641 ps |
| CPU time | 16.27 seconds |
| Started | Feb 08 12:11:04 PM UTC 25 |
| Finished | Feb 08 12:11:23 PM UTC 25 |
| Peak memory | 213504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119327741 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.119327741 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3609766354 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 57364244981 ps |
| CPU time | 374.33 seconds |
| Started | Feb 08 12:11:05 PM UTC 25 |
| Finished | Feb 08 12:17:26 PM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609766354 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access_b2b.3609766354 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.586253146 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 51452818 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 12:11:21 PM UTC 25 |
| Finished | Feb 08 12:11:24 PM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586253146 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.586253146 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.4051524440 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 19762181405 ps |
| CPU time | 1415.84 seconds |
| Started | Feb 08 12:11:20 PM UTC 25 |
| Finished | Feb 08 12:35:11 PM UTC 25 |
| Peak memory | 376504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051524440 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.4051524440 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.2808237458 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 92173687 ps |
| CPU time | 41.53 seconds |
| Started | Feb 08 12:10:47 PM UTC 25 |
| Finished | Feb 08 12:11:30 PM UTC 25 |
| Peak memory | 309092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808237458 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2808237458 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.715478124 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 51687268530 ps |
| CPU time | 3821.17 seconds |
| Started | Feb 08 12:11:30 PM UTC 25 |
| Finished | Feb 08 01:15:51 PM UTC 25 |
| Peak memory | 388532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715478124 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.715478124 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1085423858 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1149494657 ps |
| CPU time | 192.91 seconds |
| Started | Feb 08 12:11:25 PM UTC 25 |
| Finished | Feb 08 12:14:41 PM UTC 25 |
| Peak memory | 343772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085423858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.1085423858 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3280509737 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1828590663 ps |
| CPU time | 178.68 seconds |
| Started | Feb 08 12:11:00 PM UTC 25 |
| Finished | Feb 08 12:14:03 PM UTC 25 |
| Peak memory | 213560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280509737 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.3280509737 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.4189126195 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 869269154 ps |
| CPU time | 61.96 seconds |
| Started | Feb 08 12:11:12 PM UTC 25 |
| Finished | Feb 08 12:12:15 PM UTC 25 |
| Peak memory | 333576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189126195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_throughput_w_partial_wr ite.4189126195 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1691255345 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1969246618 ps |
| CPU time | 188.16 seconds |
| Started | Feb 08 12:12:21 PM UTC 25 |
| Finished | Feb 08 12:15:32 PM UTC 25 |
| Peak memory | 337460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691255345 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during_key_req.1691255345 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.169073934 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 22432214 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 12:12:42 PM UTC 25 |
| Finished | Feb 08 12:12:44 PM UTC 25 |
| Peak memory | 212956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169073934 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.169073934 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.3350368125 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 10835758228 ps |
| CPU time | 40.19 seconds |
| Started | Feb 08 12:11:34 PM UTC 25 |
| Finished | Feb 08 12:12:16 PM UTC 25 |
| Peak memory | 213884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350368125 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.3350368125 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.1344959526 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 52927522859 ps |
| CPU time | 721.84 seconds |
| Started | Feb 08 12:12:26 PM UTC 25 |
| Finished | Feb 08 12:24:36 PM UTC 25 |
| Peak memory | 380572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344959526 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.1344959526 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1543383306 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2931492927 ps |
| CPU time | 8.67 seconds |
| Started | Feb 08 12:12:17 PM UTC 25 |
| Finished | Feb 08 12:12:27 PM UTC 25 |
| Peak memory | 213544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543383306 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.1543383306 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3951388027 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 491512422 ps |
| CPU time | 70.08 seconds |
| Started | Feb 08 12:12:09 PM UTC 25 |
| Finished | Feb 08 12:13:21 PM UTC 25 |
| Peak memory | 374352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951388027 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max_throughput.3951388027 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2065172895 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 164647648 ps |
| CPU time | 3.92 seconds |
| Started | Feb 08 12:12:34 PM UTC 25 |
| Finished | Feb 08 12:12:39 PM UTC 25 |
| Peak memory | 223712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065172895 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.2065172895 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.4071237672 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 338710069 ps |
| CPU time | 8.12 seconds |
| Started | Feb 08 12:12:31 PM UTC 25 |
| Finished | Feb 08 12:12:41 PM UTC 25 |
| Peak memory | 213568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071237672 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.4071237672 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1889503510 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 30664016379 ps |
| CPU time | 1034.68 seconds |
| Started | Feb 08 12:11:34 PM UTC 25 |
| Finished | Feb 08 12:29:00 PM UTC 25 |
| Peak memory | 384596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889503510 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.1889503510 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1406227434 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1012256247 ps |
| CPU time | 23.61 seconds |
| Started | Feb 08 12:12:00 PM UTC 25 |
| Finished | Feb 08 12:12:26 PM UTC 25 |
| Peak memory | 213508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406227434 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.1406227434 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1995245378 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 4179480974 ps |
| CPU time | 299.75 seconds |
| Started | Feb 08 12:12:06 PM UTC 25 |
| Finished | Feb 08 12:17:11 PM UTC 25 |
| Peak memory | 213656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995245378 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access_b2b.1995245378 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.4193533294 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 80639770 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 12:12:28 PM UTC 25 |
| Finished | Feb 08 12:12:31 PM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193533294 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.4193533294 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.1559373451 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 16527421778 ps |
| CPU time | 790.01 seconds |
| Started | Feb 08 12:12:26 PM UTC 25 |
| Finished | Feb 08 12:25:45 PM UTC 25 |
| Peak memory | 380552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559373451 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1559373451 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.857524117 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2251755436 ps |
| CPU time | 105.78 seconds |
| Started | Feb 08 12:11:31 PM UTC 25 |
| Finished | Feb 08 12:13:19 PM UTC 25 |
| Peak memory | 362368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857524117 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.857524117 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1385827764 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 65668381419 ps |
| CPU time | 4085.27 seconds |
| Started | Feb 08 12:12:40 PM UTC 25 |
| Finished | Feb 08 01:21:26 PM UTC 25 |
| Peak memory | 396720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385827764 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.1385827764 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.306986247 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2517317516 ps |
| CPU time | 243.3 seconds |
| Started | Feb 08 12:11:42 PM UTC 25 |
| Finished | Feb 08 12:15:49 PM UTC 25 |
| Peak memory | 213652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306986247 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.306986247 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2582089209 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 208167715 ps |
| CPU time | 6.98 seconds |
| Started | Feb 08 12:12:17 PM UTC 25 |
| Finished | Feb 08 12:12:25 PM UTC 25 |
| Peak memory | 247236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582089209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_throughput_w_partial_wr ite.2582089209 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2808260160 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 15556819894 ps |
| CPU time | 1134.15 seconds |
| Started | Feb 08 12:14:11 PM UTC 25 |
| Finished | Feb 08 12:33:17 PM UTC 25 |
| Peak memory | 386772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808260160 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during_key_req.2808260160 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1136446488 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 40726940 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 12:14:31 PM UTC 25 |
| Finished | Feb 08 12:14:33 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136446488 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1136446488 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3175304268 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 12281549295 ps |
| CPU time | 79.19 seconds |
| Started | Feb 08 12:12:49 PM UTC 25 |
| Finished | Feb 08 12:14:11 PM UTC 25 |
| Peak memory | 213544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175304268 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.3175304268 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.1983873727 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 18029743022 ps |
| CPU time | 1442.74 seconds |
| Started | Feb 08 12:14:13 PM UTC 25 |
| Finished | Feb 08 12:38:31 PM UTC 25 |
| Peak memory | 382672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983873727 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.1983873727 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1078077995 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3185999599 ps |
| CPU time | 11.32 seconds |
| Started | Feb 08 12:14:04 PM UTC 25 |
| Finished | Feb 08 12:14:17 PM UTC 25 |
| Peak memory | 213552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078077995 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.1078077995 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2552829163 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 302675199 ps |
| CPU time | 19.97 seconds |
| Started | Feb 08 12:13:51 PM UTC 25 |
| Finished | Feb 08 12:14:12 PM UTC 25 |
| Peak memory | 282192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552829163 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_max_throughput.2552829163 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2457339036 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 310889609 ps |
| CPU time | 3.65 seconds |
| Started | Feb 08 12:14:18 PM UTC 25 |
| Finished | Feb 08 12:14:23 PM UTC 25 |
| Peak memory | 223832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457339036 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.2457339036 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3627181892 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 377357007 ps |
| CPU time | 10.61 seconds |
| Started | Feb 08 12:14:18 PM UTC 25 |
| Finished | Feb 08 12:14:30 PM UTC 25 |
| Peak memory | 223904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627181892 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.3627181892 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1780352682 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 25841279362 ps |
| CPU time | 644.36 seconds |
| Started | Feb 08 12:12:45 PM UTC 25 |
| Finished | Feb 08 12:23:37 PM UTC 25 |
| Peak memory | 376504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780352682 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.1780352682 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.685000023 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 580046713 ps |
| CPU time | 88.62 seconds |
| Started | Feb 08 12:13:19 PM UTC 25 |
| Finished | Feb 08 12:14:50 PM UTC 25 |
| Peak memory | 360020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685000023 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.685000023 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2649579704 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 16515869314 ps |
| CPU time | 356.15 seconds |
| Started | Feb 08 12:13:22 PM UTC 25 |
| Finished | Feb 08 12:19:23 PM UTC 25 |
| Peak memory | 213712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649579704 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access_b2b.2649579704 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.568103523 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 29408299 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 12:14:14 PM UTC 25 |
| Finished | Feb 08 12:14:17 PM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568103523 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.568103523 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.1929298232 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 11087102698 ps |
| CPU time | 1144.15 seconds |
| Started | Feb 08 12:14:13 PM UTC 25 |
| Finished | Feb 08 12:33:30 PM UTC 25 |
| Peak memory | 380828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929298232 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1929298232 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.3428678040 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 39280152 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 12:12:45 PM UTC 25 |
| Finished | Feb 08 12:12:48 PM UTC 25 |
| Peak memory | 212496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428678040 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3428678040 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.558164812 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 43389160664 ps |
| CPU time | 2780.15 seconds |
| Started | Feb 08 12:14:27 PM UTC 25 |
| Finished | Feb 08 01:01:15 PM UTC 25 |
| Peak memory | 396716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558164812 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.558164812 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.181712619 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1281505794 ps |
| CPU time | 226.73 seconds |
| Started | Feb 08 12:14:24 PM UTC 25 |
| Finished | Feb 08 12:18:14 PM UTC 25 |
| Peak memory | 390796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181712619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.181712619 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3968240997 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 36403782234 ps |
| CPU time | 220.11 seconds |
| Started | Feb 08 12:13:01 PM UTC 25 |
| Finished | Feb 08 12:16:45 PM UTC 25 |
| Peak memory | 213676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968240997 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.3968240997 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.4089050972 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 98880634 ps |
| CPU time | 30.24 seconds |
| Started | Feb 08 12:13:59 PM UTC 25 |
| Finished | Feb 08 12:14:31 PM UTC 25 |
| Peak memory | 296604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089050972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_throughput_w_partial_wr ite.4089050972 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1500061643 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 11421798847 ps |
| CPU time | 1222.26 seconds |
| Started | Feb 08 11:37:58 AM UTC 25 |
| Finished | Feb 08 11:58:33 AM UTC 25 |
| Peak memory | 386760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500061643 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_key_req.1500061643 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.952466249 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 7574524460 ps |
| CPU time | 51.8 seconds |
| Started | Feb 08 11:37:36 AM UTC 25 |
| Finished | Feb 08 11:38:30 AM UTC 25 |
| Peak memory | 213716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952466249 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.952466249 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.2114921340 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 9361767111 ps |
| CPU time | 681.74 seconds |
| Started | Feb 08 11:38:02 AM UTC 25 |
| Finished | Feb 08 11:49:32 AM UTC 25 |
| Peak memory | 384740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114921340 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.2114921340 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.281336505 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 458945227 ps |
| CPU time | 48.58 seconds |
| Started | Feb 08 11:37:52 AM UTC 25 |
| Finished | Feb 08 11:38:43 AM UTC 25 |
| Peak memory | 356004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281336505 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_throughput.281336505 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1529481775 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 163850638 ps |
| CPU time | 7.5 seconds |
| Started | Feb 08 11:38:10 AM UTC 25 |
| Finished | Feb 08 11:38:19 AM UTC 25 |
| Peak memory | 224032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529481775 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1529481775 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.915324400 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1757445731 ps |
| CPU time | 13.49 seconds |
| Started | Feb 08 11:38:10 AM UTC 25 |
| Finished | Feb 08 11:38:25 AM UTC 25 |
| Peak memory | 223780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915324400 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.915324400 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1154394922 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2573420946 ps |
| CPU time | 640.8 seconds |
| Started | Feb 08 11:37:35 AM UTC 25 |
| Finished | Feb 08 11:48:24 AM UTC 25 |
| Peak memory | 368328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154394922 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.1154394922 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2881782334 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 793164627 ps |
| CPU time | 11.54 seconds |
| Started | Feb 08 11:37:38 AM UTC 25 |
| Finished | Feb 08 11:37:51 AM UTC 25 |
| Peak memory | 213412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881782334 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.2881782334 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.588536852 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 55024337086 ps |
| CPU time | 605.45 seconds |
| Started | Feb 08 11:37:46 AM UTC 25 |
| Finished | Feb 08 11:47:59 AM UTC 25 |
| Peak memory | 213748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588536852 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access_b2b.588536852 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.336283098 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 173981773 ps |
| CPU time | 2.75 seconds |
| Started | Feb 08 11:38:26 AM UTC 25 |
| Finished | Feb 08 11:38:30 AM UTC 25 |
| Peak memory | 249408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336283098 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.336283098 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.1752301149 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1477654575 ps |
| CPU time | 17.88 seconds |
| Started | Feb 08 11:37:34 AM UTC 25 |
| Finished | Feb 08 11:37:53 AM UTC 25 |
| Peak memory | 213592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752301149 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1752301149 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1605071152 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 166173010209 ps |
| CPU time | 2540.85 seconds |
| Started | Feb 08 11:38:20 AM UTC 25 |
| Finished | Feb 08 12:21:07 PM UTC 25 |
| Peak memory | 390644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605071152 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.1605071152 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.986446021 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2306769475 ps |
| CPU time | 13.17 seconds |
| Started | Feb 08 11:38:18 AM UTC 25 |
| Finished | Feb 08 11:38:32 AM UTC 25 |
| Peak memory | 223964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986446021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.986446021 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3717897572 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3395203921 ps |
| CPU time | 452.48 seconds |
| Started | Feb 08 11:37:38 AM UTC 25 |
| Finished | Feb 08 11:45:17 AM UTC 25 |
| Peak memory | 213568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717897572 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3717897572 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1857314149 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 219431477 ps |
| CPU time | 33.02 seconds |
| Started | Feb 08 11:37:53 AM UTC 25 |
| Finished | Feb 08 11:38:28 AM UTC 25 |
| Peak memory | 319116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857314149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_throughput_w_partial_wri te.1857314149 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.4061761606 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 5237248824 ps |
| CPU time | 780.43 seconds |
| Started | Feb 08 12:15:15 PM UTC 25 |
| Finished | Feb 08 12:28:24 PM UTC 25 |
| Peak memory | 382676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061761606 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_key_req.4061761606 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3981335745 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 12243151 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 12:15:44 PM UTC 25 |
| Finished | Feb 08 12:15:47 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981335745 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3981335745 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2753664571 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2250342530 ps |
| CPU time | 24.35 seconds |
| Started | Feb 08 12:14:40 PM UTC 25 |
| Finished | Feb 08 12:15:06 PM UTC 25 |
| Peak memory | 213584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753664571 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2753664571 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2684915303 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 13848169919 ps |
| CPU time | 209.01 seconds |
| Started | Feb 08 12:15:15 PM UTC 25 |
| Finished | Feb 08 12:18:48 PM UTC 25 |
| Peak memory | 374592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684915303 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.2684915303 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2794881167 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 741503621 ps |
| CPU time | 11.08 seconds |
| Started | Feb 08 12:15:07 PM UTC 25 |
| Finished | Feb 08 12:15:20 PM UTC 25 |
| Peak memory | 213592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794881167 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.2794881167 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3277152179 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 229915605 ps |
| CPU time | 15.53 seconds |
| Started | Feb 08 12:14:58 PM UTC 25 |
| Finished | Feb 08 12:15:15 PM UTC 25 |
| Peak memory | 288404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277152179 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_max_throughput.3277152179 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.590729614 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 619227041 ps |
| CPU time | 6.47 seconds |
| Started | Feb 08 12:15:33 PM UTC 25 |
| Finished | Feb 08 12:15:40 PM UTC 25 |
| Peak memory | 223848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590729614 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.590729614 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.405249135 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 236118892 ps |
| CPU time | 7.29 seconds |
| Started | Feb 08 12:15:24 PM UTC 25 |
| Finished | Feb 08 12:15:32 PM UTC 25 |
| Peak memory | 213528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405249135 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.405249135 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1983556679 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 12479185879 ps |
| CPU time | 1301.17 seconds |
| Started | Feb 08 12:14:34 PM UTC 25 |
| Finished | Feb 08 12:36:29 PM UTC 25 |
| Peak memory | 384712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983556679 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.1983556679 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2502789731 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1198187885 ps |
| CPU time | 137.19 seconds |
| Started | Feb 08 12:14:51 PM UTC 25 |
| Finished | Feb 08 12:17:10 PM UTC 25 |
| Peak memory | 380760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502789731 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.2502789731 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1381107032 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 29686422570 ps |
| CPU time | 203.25 seconds |
| Started | Feb 08 12:14:52 PM UTC 25 |
| Finished | Feb 08 12:18:18 PM UTC 25 |
| Peak memory | 213608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381107032 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access_b2b.1381107032 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2730355667 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 54546689 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 12:15:21 PM UTC 25 |
| Finished | Feb 08 12:15:23 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730355667 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2730355667 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.3179150410 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 8426954492 ps |
| CPU time | 901.07 seconds |
| Started | Feb 08 12:15:20 PM UTC 25 |
| Finished | Feb 08 12:30:31 PM UTC 25 |
| Peak memory | 384736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179150410 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3179150410 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.2881944009 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1109896598 ps |
| CPU time | 16.02 seconds |
| Started | Feb 08 12:14:32 PM UTC 25 |
| Finished | Feb 08 12:14:50 PM UTC 25 |
| Peak memory | 213540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881944009 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2881944009 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2188543798 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 13503996833 ps |
| CPU time | 4075.36 seconds |
| Started | Feb 08 12:15:42 PM UTC 25 |
| Finished | Feb 08 01:24:18 PM UTC 25 |
| Peak memory | 388472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188543798 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.2188543798 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1656956880 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 3137786254 ps |
| CPU time | 217.63 seconds |
| Started | Feb 08 12:15:34 PM UTC 25 |
| Finished | Feb 08 12:19:15 PM UTC 25 |
| Peak memory | 347828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656956880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1656956880 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.156168443 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 13153609044 ps |
| CPU time | 238.52 seconds |
| Started | Feb 08 12:14:41 PM UTC 25 |
| Finished | Feb 08 12:18:44 PM UTC 25 |
| Peak memory | 213852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156168443 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.156168443 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3632459871 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 422287147 ps |
| CPU time | 43.33 seconds |
| Started | Feb 08 12:15:03 PM UTC 25 |
| Finished | Feb 08 12:15:48 PM UTC 25 |
| Peak memory | 313136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632459871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_throughput_w_partial_wr ite.3632459871 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.972367910 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5183377208 ps |
| CPU time | 1150.87 seconds |
| Started | Feb 08 12:17:06 PM UTC 25 |
| Finished | Feb 08 12:36:29 PM UTC 25 |
| Peak memory | 384644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972367910 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during_key_req.972367910 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3461451729 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 46577548 ps |
| CPU time | 1 seconds |
| Started | Feb 08 12:17:31 PM UTC 25 |
| Finished | Feb 08 12:17:33 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461451729 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3461451729 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.60246637 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 4894788813 ps |
| CPU time | 66.12 seconds |
| Started | Feb 08 12:15:50 PM UTC 25 |
| Finished | Feb 08 12:16:58 PM UTC 25 |
| Peak memory | 213852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60246637 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.60246637 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1220228093 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 58553720345 ps |
| CPU time | 616.94 seconds |
| Started | Feb 08 12:17:10 PM UTC 25 |
| Finished | Feb 08 12:27:35 PM UTC 25 |
| Peak memory | 382672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220228093 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.1220228093 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.849878018 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 3682250902 ps |
| CPU time | 9.17 seconds |
| Started | Feb 08 12:16:59 PM UTC 25 |
| Finished | Feb 08 12:17:10 PM UTC 25 |
| Peak memory | 213616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849878018 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.849878018 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2065146085 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 807872687 ps |
| CPU time | 40.53 seconds |
| Started | Feb 08 12:16:46 PM UTC 25 |
| Finished | Feb 08 12:17:28 PM UTC 25 |
| Peak memory | 323384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065146085 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_max_throughput.2065146085 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.177281863 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 454796606 ps |
| CPU time | 4.58 seconds |
| Started | Feb 08 12:17:24 PM UTC 25 |
| Finished | Feb 08 12:17:30 PM UTC 25 |
| Peak memory | 223808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177281863 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.177281863 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2934413109 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 74208160 ps |
| CPU time | 5.31 seconds |
| Started | Feb 08 12:17:16 PM UTC 25 |
| Finished | Feb 08 12:17:22 PM UTC 25 |
| Peak memory | 223860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934413109 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.2934413109 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.965978759 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1863332979 ps |
| CPU time | 197.61 seconds |
| Started | Feb 08 12:15:49 PM UTC 25 |
| Finished | Feb 08 12:19:10 PM UTC 25 |
| Peak memory | 382804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965978759 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.965978759 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3316848987 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 8083068491 ps |
| CPU time | 17.61 seconds |
| Started | Feb 08 12:16:29 PM UTC 25 |
| Finished | Feb 08 12:16:48 PM UTC 25 |
| Peak memory | 213596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316848987 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.3316848987 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1895343760 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 71301040070 ps |
| CPU time | 498.36 seconds |
| Started | Feb 08 12:16:33 PM UTC 25 |
| Finished | Feb 08 12:24:57 PM UTC 25 |
| Peak memory | 213688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895343760 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access_b2b.1895343760 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1921608407 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 33611799 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 12:17:12 PM UTC 25 |
| Finished | Feb 08 12:17:14 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921608407 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1921608407 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3793996628 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 18908128751 ps |
| CPU time | 388.12 seconds |
| Started | Feb 08 12:17:11 PM UTC 25 |
| Finished | Feb 08 12:23:45 PM UTC 25 |
| Peak memory | 376432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793996628 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3793996628 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2606837407 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4116727399 ps |
| CPU time | 129.85 seconds |
| Started | Feb 08 12:15:47 PM UTC 25 |
| Finished | Feb 08 12:18:00 PM UTC 25 |
| Peak memory | 366500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606837407 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2606837407 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.92068585 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 195512480282 ps |
| CPU time | 4026.08 seconds |
| Started | Feb 08 12:17:29 PM UTC 25 |
| Finished | Feb 08 01:25:13 PM UTC 25 |
| Peak memory | 396784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92068585 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.92068585 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1947777561 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2744799870 ps |
| CPU time | 140.54 seconds |
| Started | Feb 08 12:17:27 PM UTC 25 |
| Finished | Feb 08 12:19:50 PM UTC 25 |
| Peak memory | 313012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947777561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1947777561 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.889406411 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1828791339 ps |
| CPU time | 191.23 seconds |
| Started | Feb 08 12:16:18 PM UTC 25 |
| Finished | Feb 08 12:19:32 PM UTC 25 |
| Peak memory | 213580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889406411 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.889406411 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.459827485 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 489200353 ps |
| CPU time | 43.36 seconds |
| Started | Feb 08 12:16:49 PM UTC 25 |
| Finished | Feb 08 12:17:34 PM UTC 25 |
| Peak memory | 329288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459827485 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.459827485 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.1430635943 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3162536337 ps |
| CPU time | 783.52 seconds |
| Started | Feb 08 12:18:27 PM UTC 25 |
| Finished | Feb 08 12:31:40 PM UTC 25 |
| Peak memory | 372360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430635943 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during_key_req.1430635943 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4175118472 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 20061081 ps |
| CPU time | 1 seconds |
| Started | Feb 08 12:19:11 PM UTC 25 |
| Finished | Feb 08 12:19:14 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175118472 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.4175118472 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.28236021 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 5331515426 ps |
| CPU time | 37.72 seconds |
| Started | Feb 08 12:17:47 PM UTC 25 |
| Finished | Feb 08 12:18:27 PM UTC 25 |
| Peak memory | 213664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28236021 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.28236021 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3083341486 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 17956177178 ps |
| CPU time | 1556.76 seconds |
| Started | Feb 08 12:18:29 PM UTC 25 |
| Finished | Feb 08 12:44:42 PM UTC 25 |
| Peak memory | 384596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083341486 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.3083341486 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.323075696 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 861872600 ps |
| CPU time | 11.83 seconds |
| Started | Feb 08 12:18:26 PM UTC 25 |
| Finished | Feb 08 12:18:40 PM UTC 25 |
| Peak memory | 223924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323075696 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.323075696 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3606908519 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 422285575 ps |
| CPU time | 64 seconds |
| Started | Feb 08 12:18:19 PM UTC 25 |
| Finished | Feb 08 12:19:25 PM UTC 25 |
| Peak memory | 329372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606908519 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_max_throughput.3606908519 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2818475887 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 179467243 ps |
| CPU time | 7.52 seconds |
| Started | Feb 08 12:18:48 PM UTC 25 |
| Finished | Feb 08 12:18:57 PM UTC 25 |
| Peak memory | 223892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818475887 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2818475887 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.827766434 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 337908988 ps |
| CPU time | 8.07 seconds |
| Started | Feb 08 12:18:48 PM UTC 25 |
| Finished | Feb 08 12:18:57 PM UTC 25 |
| Peak memory | 223768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827766434 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.827766434 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1667980593 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 14045063857 ps |
| CPU time | 711.17 seconds |
| Started | Feb 08 12:17:35 PM UTC 25 |
| Finished | Feb 08 12:29:35 PM UTC 25 |
| Peak memory | 386672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667980593 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.1667980593 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.4106429573 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1422856823 ps |
| CPU time | 18.58 seconds |
| Started | Feb 08 12:18:05 PM UTC 25 |
| Finished | Feb 08 12:18:25 PM UTC 25 |
| Peak memory | 282188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106429573 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.4106429573 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.4141802744 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 26459241889 ps |
| CPU time | 367.05 seconds |
| Started | Feb 08 12:18:15 PM UTC 25 |
| Finished | Feb 08 12:24:27 PM UTC 25 |
| Peak memory | 213632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141802744 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access_b2b.4141802744 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2702682579 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 86215266 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 12:18:45 PM UTC 25 |
| Finished | Feb 08 12:18:47 PM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702682579 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2702682579 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.1516136572 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 7386086609 ps |
| CPU time | 1039.96 seconds |
| Started | Feb 08 12:18:41 PM UTC 25 |
| Finished | Feb 08 12:36:12 PM UTC 25 |
| Peak memory | 386880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516136572 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1516136572 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.3554192549 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 664364386 ps |
| CPU time | 10.58 seconds |
| Started | Feb 08 12:17:34 PM UTC 25 |
| Finished | Feb 08 12:17:46 PM UTC 25 |
| Peak memory | 213748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554192549 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3554192549 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1128234218 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 47660905954 ps |
| CPU time | 3993.73 seconds |
| Started | Feb 08 12:18:58 PM UTC 25 |
| Finished | Feb 08 01:26:12 PM UTC 25 |
| Peak memory | 388524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128234218 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.1128234218 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.4059551545 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2886698034 ps |
| CPU time | 96.4 seconds |
| Started | Feb 08 12:18:58 PM UTC 25 |
| Finished | Feb 08 12:20:37 PM UTC 25 |
| Peak memory | 335564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059551545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.4059551545 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1199400148 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 9709497546 ps |
| CPU time | 251.55 seconds |
| Started | Feb 08 12:18:01 PM UTC 25 |
| Finished | Feb 08 12:22:16 PM UTC 25 |
| Peak memory | 213600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199400148 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.1199400148 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.550123944 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 146164770 ps |
| CPU time | 92.52 seconds |
| Started | Feb 08 12:18:25 PM UTC 25 |
| Finished | Feb 08 12:20:00 PM UTC 25 |
| Peak memory | 362072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550123944 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.550123944 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1799558742 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 31626545099 ps |
| CPU time | 161.25 seconds |
| Started | Feb 08 12:19:52 PM UTC 25 |
| Finished | Feb 08 12:22:36 PM UTC 25 |
| Peak memory | 323288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799558742 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during_key_req.1799558742 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2579580086 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 23616846 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 12:20:37 PM UTC 25 |
| Finished | Feb 08 12:20:40 PM UTC 25 |
| Peak memory | 212960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579580086 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2579580086 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2711147631 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 39546645877 ps |
| CPU time | 78.75 seconds |
| Started | Feb 08 12:19:16 PM UTC 25 |
| Finished | Feb 08 12:20:37 PM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711147631 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.2711147631 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2099629219 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1084836836 ps |
| CPU time | 339.52 seconds |
| Started | Feb 08 12:19:55 PM UTC 25 |
| Finished | Feb 08 12:25:39 PM UTC 25 |
| Peak memory | 372292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099629219 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.2099629219 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2873895590 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 791281679 ps |
| CPU time | 11.36 seconds |
| Started | Feb 08 12:19:41 PM UTC 25 |
| Finished | Feb 08 12:19:54 PM UTC 25 |
| Peak memory | 213684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873895590 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.2873895590 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1088537361 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 55049603 ps |
| CPU time | 5.38 seconds |
| Started | Feb 08 12:19:33 PM UTC 25 |
| Finished | Feb 08 12:19:40 PM UTC 25 |
| Peak memory | 235348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088537361 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_max_throughput.1088537361 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1895922339 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 106797699 ps |
| CPU time | 6.37 seconds |
| Started | Feb 08 12:20:05 PM UTC 25 |
| Finished | Feb 08 12:20:13 PM UTC 25 |
| Peak memory | 223808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895922339 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.1895922339 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3963883475 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 288880827 ps |
| CPU time | 6.28 seconds |
| Started | Feb 08 12:20:05 PM UTC 25 |
| Finished | Feb 08 12:20:13 PM UTC 25 |
| Peak memory | 213884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963883475 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.3963883475 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1066430269 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 8097957673 ps |
| CPU time | 714.03 seconds |
| Started | Feb 08 12:19:15 PM UTC 25 |
| Finished | Feb 08 12:31:17 PM UTC 25 |
| Peak memory | 386952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066430269 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.1066430269 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2923115797 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 317741779 ps |
| CPU time | 7.6 seconds |
| Started | Feb 08 12:19:26 PM UTC 25 |
| Finished | Feb 08 12:19:35 PM UTC 25 |
| Peak memory | 241228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923115797 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.2923115797 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2231783763 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 20520225409 ps |
| CPU time | 263.02 seconds |
| Started | Feb 08 12:19:32 PM UTC 25 |
| Finished | Feb 08 12:23:59 PM UTC 25 |
| Peak memory | 213968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231783763 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access_b2b.2231783763 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.892123609 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 48029931 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 12:20:01 PM UTC 25 |
| Finished | Feb 08 12:20:04 PM UTC 25 |
| Peak memory | 212896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892123609 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.892123609 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.738709072 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 20253894352 ps |
| CPU time | 623.7 seconds |
| Started | Feb 08 12:19:59 PM UTC 25 |
| Finished | Feb 08 12:30:30 PM UTC 25 |
| Peak memory | 384632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738709072 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.738709072 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1058207126 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 70001888 ps |
| CPU time | 15.49 seconds |
| Started | Feb 08 12:19:15 PM UTC 25 |
| Finished | Feb 08 12:19:32 PM UTC 25 |
| Peak memory | 265844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058207126 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1058207126 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.3180547343 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 22036481343 ps |
| CPU time | 3216.01 seconds |
| Started | Feb 08 12:20:14 PM UTC 25 |
| Finished | Feb 08 01:14:24 PM UTC 25 |
| Peak memory | 388516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180547343 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.3180547343 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1556079568 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4246018561 ps |
| CPU time | 82.62 seconds |
| Started | Feb 08 12:20:14 PM UTC 25 |
| Finished | Feb 08 12:21:39 PM UTC 25 |
| Peak memory | 315268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556079568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1556079568 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.991191919 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1517864201 ps |
| CPU time | 160.48 seconds |
| Started | Feb 08 12:19:24 PM UTC 25 |
| Finished | Feb 08 12:22:07 PM UTC 25 |
| Peak memory | 213660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991191919 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.991191919 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2704215690 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 163696470 ps |
| CPU time | 21.18 seconds |
| Started | Feb 08 12:19:35 PM UTC 25 |
| Finished | Feb 08 12:19:58 PM UTC 25 |
| Peak memory | 282252 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704215690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_throughput_w_partial_wr ite.2704215690 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2881354930 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 4710933013 ps |
| CPU time | 428.2 seconds |
| Started | Feb 08 12:21:41 PM UTC 25 |
| Finished | Feb 08 12:28:55 PM UTC 25 |
| Peak memory | 349828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881354930 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during_key_req.2881354930 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3483527563 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 11909158 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 12:22:17 PM UTC 25 |
| Finished | Feb 08 12:22:19 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483527563 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3483527563 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1261478856 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2688396025 ps |
| CPU time | 51.75 seconds |
| Started | Feb 08 12:20:46 PM UTC 25 |
| Finished | Feb 08 12:21:40 PM UTC 25 |
| Peak memory | 213616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261478856 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1261478856 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.1069312242 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2076565689 ps |
| CPU time | 35.69 seconds |
| Started | Feb 08 12:21:50 PM UTC 25 |
| Finished | Feb 08 12:22:27 PM UTC 25 |
| Peak memory | 267800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069312242 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.1069312242 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3606598664 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 858605021 ps |
| CPU time | 6.78 seconds |
| Started | Feb 08 12:21:41 PM UTC 25 |
| Finished | Feb 08 12:21:49 PM UTC 25 |
| Peak memory | 223860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606598664 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.3606598664 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1800024492 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 125245428 ps |
| CPU time | 69.91 seconds |
| Started | Feb 08 12:21:07 PM UTC 25 |
| Finished | Feb 08 12:22:19 PM UTC 25 |
| Peak memory | 347724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800024492 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_max_throughput.1800024492 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.142738605 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 269316335 ps |
| CPU time | 5.67 seconds |
| Started | Feb 08 12:22:06 PM UTC 25 |
| Finished | Feb 08 12:22:14 PM UTC 25 |
| Peak memory | 223832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142738605 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.142738605 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3902925191 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2355107813 ps |
| CPU time | 14.36 seconds |
| Started | Feb 08 12:22:04 PM UTC 25 |
| Finished | Feb 08 12:22:20 PM UTC 25 |
| Peak memory | 213640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902925191 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.3902925191 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2320220888 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 5079689337 ps |
| CPU time | 373.11 seconds |
| Started | Feb 08 12:20:41 PM UTC 25 |
| Finished | Feb 08 12:26:59 PM UTC 25 |
| Peak memory | 382648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320220888 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.2320220888 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2188669001 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 161370154 ps |
| CPU time | 12.98 seconds |
| Started | Feb 08 12:21:00 PM UTC 25 |
| Finished | Feb 08 12:21:15 PM UTC 25 |
| Peak memory | 213872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188669001 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.2188669001 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1012472353 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 128079889036 ps |
| CPU time | 461.55 seconds |
| Started | Feb 08 12:21:06 PM UTC 25 |
| Finished | Feb 08 12:28:54 PM UTC 25 |
| Peak memory | 213828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012472353 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access_b2b.1012472353 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.360578755 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 115094696 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 12:22:03 PM UTC 25 |
| Finished | Feb 08 12:22:06 PM UTC 25 |
| Peak memory | 212896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360578755 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.360578755 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2058830275 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 119532363436 ps |
| CPU time | 993.88 seconds |
| Started | Feb 08 12:21:50 PM UTC 25 |
| Finished | Feb 08 12:38:35 PM UTC 25 |
| Peak memory | 386704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058830275 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2058830275 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.4277120700 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 380687416 ps |
| CPU time | 4.72 seconds |
| Started | Feb 08 12:20:39 PM UTC 25 |
| Finished | Feb 08 12:20:45 PM UTC 25 |
| Peak memory | 213628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277120700 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.4277120700 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2230688236 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 48051799338 ps |
| CPU time | 3453.01 seconds |
| Started | Feb 08 12:22:15 PM UTC 25 |
| Finished | Feb 08 01:20:23 PM UTC 25 |
| Peak memory | 388532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230688236 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.2230688236 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2625538633 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 166120933 ps |
| CPU time | 7.78 seconds |
| Started | Feb 08 12:22:09 PM UTC 25 |
| Finished | Feb 08 12:22:18 PM UTC 25 |
| Peak memory | 231108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625538633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2625538633 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.255531761 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 8617495172 ps |
| CPU time | 272.34 seconds |
| Started | Feb 08 12:20:48 PM UTC 25 |
| Finished | Feb 08 12:25:25 PM UTC 25 |
| Peak memory | 213628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255531761 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.255531761 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.4082520537 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 388687189 ps |
| CPU time | 46.26 seconds |
| Started | Feb 08 12:21:16 PM UTC 25 |
| Finished | Feb 08 12:22:03 PM UTC 25 |
| Peak memory | 319312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082520537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_throughput_w_partial_wr ite.4082520537 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1506552502 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1147431737 ps |
| CPU time | 538.65 seconds |
| Started | Feb 08 12:23:11 PM UTC 25 |
| Finished | Feb 08 12:32:17 PM UTC 25 |
| Peak memory | 384576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506552502 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during_key_req.1506552502 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.4087296491 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 43779849 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 12:24:00 PM UTC 25 |
| Finished | Feb 08 12:24:02 PM UTC 25 |
| Peak memory | 212552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087296491 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.4087296491 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.1238423836 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 995376298 ps |
| CPU time | 75.29 seconds |
| Started | Feb 08 12:22:20 PM UTC 25 |
| Finished | Feb 08 12:23:38 PM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238423836 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.1238423836 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.4156807919 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2407748864 ps |
| CPU time | 88.98 seconds |
| Started | Feb 08 12:23:36 PM UTC 25 |
| Finished | Feb 08 12:25:08 PM UTC 25 |
| Peak memory | 331404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156807919 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.4156807919 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2805154266 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 588018535 ps |
| CPU time | 4.75 seconds |
| Started | Feb 08 12:23:04 PM UTC 25 |
| Finished | Feb 08 12:23:10 PM UTC 25 |
| Peak memory | 213624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805154266 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.2805154266 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2711370268 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 139608923 ps |
| CPU time | 148.71 seconds |
| Started | Feb 08 12:22:39 PM UTC 25 |
| Finished | Feb 08 12:25:10 PM UTC 25 |
| Peak memory | 378708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711370268 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_max_throughput.2711370268 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.169622973 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 78335333 ps |
| CPU time | 5.55 seconds |
| Started | Feb 08 12:23:47 PM UTC 25 |
| Finished | Feb 08 12:23:54 PM UTC 25 |
| Peak memory | 223844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169622973 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.169622973 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3890125527 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 501318150 ps |
| CPU time | 12.57 seconds |
| Started | Feb 08 12:23:42 PM UTC 25 |
| Finished | Feb 08 12:23:55 PM UTC 25 |
| Peak memory | 223812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890125527 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.3890125527 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3923926784 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 51597401070 ps |
| CPU time | 681.99 seconds |
| Started | Feb 08 12:22:20 PM UTC 25 |
| Finished | Feb 08 12:33:50 PM UTC 25 |
| Peak memory | 378484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923926784 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3923926784 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2237173294 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 182622662 ps |
| CPU time | 7.97 seconds |
| Started | Feb 08 12:22:28 PM UTC 25 |
| Finished | Feb 08 12:22:38 PM UTC 25 |
| Peak memory | 235412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237173294 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.2237173294 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2883717965 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 8160361079 ps |
| CPU time | 290.6 seconds |
| Started | Feb 08 12:22:36 PM UTC 25 |
| Finished | Feb 08 12:27:31 PM UTC 25 |
| Peak memory | 213656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883717965 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access_b2b.2883717965 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3790577684 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 34274133 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 12:23:38 PM UTC 25 |
| Finished | Feb 08 12:23:41 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790577684 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3790577684 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.1716708097 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 7354444676 ps |
| CPU time | 520.7 seconds |
| Started | Feb 08 12:23:38 PM UTC 25 |
| Finished | Feb 08 12:32:25 PM UTC 25 |
| Peak memory | 378552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716708097 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1716708097 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.3224751916 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 212165944 ps |
| CPU time | 42.17 seconds |
| Started | Feb 08 12:22:19 PM UTC 25 |
| Finished | Feb 08 12:23:03 PM UTC 25 |
| Peak memory | 335416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224751916 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3224751916 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1245581548 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 62570828336 ps |
| CPU time | 2004.11 seconds |
| Started | Feb 08 12:23:57 PM UTC 25 |
| Finished | Feb 08 12:57:42 PM UTC 25 |
| Peak memory | 386780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245581548 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.1245581548 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3860869918 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3984982362 ps |
| CPU time | 414.81 seconds |
| Started | Feb 08 12:22:21 PM UTC 25 |
| Finished | Feb 08 12:29:22 PM UTC 25 |
| Peak memory | 213724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860869918 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.3860869918 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1432782532 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 110490151 ps |
| CPU time | 39.25 seconds |
| Started | Feb 08 12:22:55 PM UTC 25 |
| Finished | Feb 08 12:23:36 PM UTC 25 |
| Peak memory | 312976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432782532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_throughput_w_partial_wr ite.1432782532 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3961916577 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 7402504317 ps |
| CPU time | 700.33 seconds |
| Started | Feb 08 12:25:09 PM UTC 25 |
| Finished | Feb 08 12:36:57 PM UTC 25 |
| Peak memory | 368336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961916577 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during_key_req.3961916577 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.19043905 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 44056514 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 12:25:36 PM UTC 25 |
| Finished | Feb 08 12:25:38 PM UTC 25 |
| Peak memory | 212616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19043905 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.19043905 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.3979485879 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3271833865 ps |
| CPU time | 59.61 seconds |
| Started | Feb 08 12:24:09 PM UTC 25 |
| Finished | Feb 08 12:25:11 PM UTC 25 |
| Peak memory | 214000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979485879 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.3979485879 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3681521051 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 16568419747 ps |
| CPU time | 1252.06 seconds |
| Started | Feb 08 12:25:11 PM UTC 25 |
| Finished | Feb 08 12:46:17 PM UTC 25 |
| Peak memory | 384652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681521051 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.3681521051 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2079851287 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 320333518 ps |
| CPU time | 6.56 seconds |
| Started | Feb 08 12:25:07 PM UTC 25 |
| Finished | Feb 08 12:25:15 PM UTC 25 |
| Peak memory | 213528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079851287 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.2079851287 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.584411595 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 114581842 ps |
| CPU time | 49.42 seconds |
| Started | Feb 08 12:24:58 PM UTC 25 |
| Finished | Feb 08 12:25:49 PM UTC 25 |
| Peak memory | 337560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584411595 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max_throughput.584411595 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2369878967 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1182861306 ps |
| CPU time | 7.97 seconds |
| Started | Feb 08 12:25:26 PM UTC 25 |
| Finished | Feb 08 12:25:35 PM UTC 25 |
| Peak memory | 223768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369878967 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.2369878967 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1470793738 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3207279715 ps |
| CPU time | 9.67 seconds |
| Started | Feb 08 12:25:20 PM UTC 25 |
| Finished | Feb 08 12:25:32 PM UTC 25 |
| Peak memory | 223876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470793738 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.1470793738 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.505082291 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1343031704 ps |
| CPU time | 487.31 seconds |
| Started | Feb 08 12:24:06 PM UTC 25 |
| Finished | Feb 08 12:32:19 PM UTC 25 |
| Peak memory | 374344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505082291 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.505082291 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1410985318 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2299363843 ps |
| CPU time | 29.57 seconds |
| Started | Feb 08 12:24:35 PM UTC 25 |
| Finished | Feb 08 12:25:06 PM UTC 25 |
| Peak memory | 213648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410985318 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.1410985318 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1512795805 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 13343216179 ps |
| CPU time | 364.24 seconds |
| Started | Feb 08 12:24:38 PM UTC 25 |
| Finished | Feb 08 12:30:47 PM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512795805 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access_b2b.1512795805 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.4293480040 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 45359243 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 12:25:16 PM UTC 25 |
| Finished | Feb 08 12:25:19 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293480040 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.4293480040 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.401847993 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 6600023393 ps |
| CPU time | 911.74 seconds |
| Started | Feb 08 12:25:12 PM UTC 25 |
| Finished | Feb 08 12:40:34 PM UTC 25 |
| Peak memory | 386680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401847993 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.401847993 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2283426183 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 4388099922 ps |
| CPU time | 61.56 seconds |
| Started | Feb 08 12:24:03 PM UTC 25 |
| Finished | Feb 08 12:25:07 PM UTC 25 |
| Peak memory | 317068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283426183 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2283426183 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.552070895 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 10367676962 ps |
| CPU time | 886.05 seconds |
| Started | Feb 08 12:25:33 PM UTC 25 |
| Finished | Feb 08 12:40:29 PM UTC 25 |
| Peak memory | 382680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552070895 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.552070895 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.531861282 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4954556907 ps |
| CPU time | 77.23 seconds |
| Started | Feb 08 12:25:28 PM UTC 25 |
| Finished | Feb 08 12:26:47 PM UTC 25 |
| Peak memory | 339652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531861282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.531861282 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.430924023 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 10546066227 ps |
| CPU time | 269.31 seconds |
| Started | Feb 08 12:24:27 PM UTC 25 |
| Finished | Feb 08 12:29:01 PM UTC 25 |
| Peak memory | 213892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430924023 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.430924023 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3787980970 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 325598308 ps |
| CPU time | 17.61 seconds |
| Started | Feb 08 12:25:07 PM UTC 25 |
| Finished | Feb 08 12:25:26 PM UTC 25 |
| Peak memory | 280188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787980970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_throughput_w_partial_wr ite.3787980970 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1073237115 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1959176566 ps |
| CPU time | 297.76 seconds |
| Started | Feb 08 12:26:29 PM UTC 25 |
| Finished | Feb 08 12:31:31 PM UTC 25 |
| Peak memory | 384852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073237115 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_key_req.1073237115 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1182196400 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 43875855 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 12:27:36 PM UTC 25 |
| Finished | Feb 08 12:27:38 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182196400 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1182196400 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1153191912 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2997755006 ps |
| CPU time | 61.51 seconds |
| Started | Feb 08 12:25:46 PM UTC 25 |
| Finished | Feb 08 12:26:49 PM UTC 25 |
| Peak memory | 213752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153191912 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.1153191912 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3483411185 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 17929485769 ps |
| CPU time | 1286.59 seconds |
| Started | Feb 08 12:26:48 PM UTC 25 |
| Finished | Feb 08 12:48:29 PM UTC 25 |
| Peak memory | 380628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483411185 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.3483411185 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3645104488 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 188781592 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 12:26:25 PM UTC 25 |
| Finished | Feb 08 12:26:28 PM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645104488 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.3645104488 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2590319560 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 265276785 ps |
| CPU time | 115.92 seconds |
| Started | Feb 08 12:26:12 PM UTC 25 |
| Finished | Feb 08 12:28:10 PM UTC 25 |
| Peak memory | 378704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590319560 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max_throughput.2590319560 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3068614351 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 498828311 ps |
| CPU time | 4.88 seconds |
| Started | Feb 08 12:27:12 PM UTC 25 |
| Finished | Feb 08 12:27:18 PM UTC 25 |
| Peak memory | 224020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068614351 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.3068614351 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1010717881 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 296822188 ps |
| CPU time | 7.48 seconds |
| Started | Feb 08 12:27:03 PM UTC 25 |
| Finished | Feb 08 12:27:12 PM UTC 25 |
| Peak memory | 223908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010717881 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.1010717881 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3412908075 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 19346295644 ps |
| CPU time | 1543.86 seconds |
| Started | Feb 08 12:25:40 PM UTC 25 |
| Finished | Feb 08 12:51:41 PM UTC 25 |
| Peak memory | 386760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412908075 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.3412908075 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1463520612 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 261775436 ps |
| CPU time | 16.7 seconds |
| Started | Feb 08 12:25:53 PM UTC 25 |
| Finished | Feb 08 12:26:11 PM UTC 25 |
| Peak memory | 213664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463520612 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.1463520612 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3818552209 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2809436957 ps |
| CPU time | 193.99 seconds |
| Started | Feb 08 12:26:09 PM UTC 25 |
| Finished | Feb 08 12:29:26 PM UTC 25 |
| Peak memory | 213584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818552209 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access_b2b.3818552209 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2172822358 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 75894227 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 12:27:00 PM UTC 25 |
| Finished | Feb 08 12:27:02 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172822358 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2172822358 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.4236819773 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 15197196302 ps |
| CPU time | 663.57 seconds |
| Started | Feb 08 12:26:49 PM UTC 25 |
| Finished | Feb 08 12:38:01 PM UTC 25 |
| Peak memory | 372368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236819773 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.4236819773 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.4196313038 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1426768548 ps |
| CPU time | 26.5 seconds |
| Started | Feb 08 12:25:39 PM UTC 25 |
| Finished | Feb 08 12:26:07 PM UTC 25 |
| Peak memory | 296524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196313038 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.4196313038 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2245223376 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 48835012785 ps |
| CPU time | 3085.12 seconds |
| Started | Feb 08 12:27:32 PM UTC 25 |
| Finished | Feb 08 01:19:27 PM UTC 25 |
| Peak memory | 388592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245223376 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.2245223376 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3447739435 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2347847814 ps |
| CPU time | 271.67 seconds |
| Started | Feb 08 12:25:50 PM UTC 25 |
| Finished | Feb 08 12:30:26 PM UTC 25 |
| Peak memory | 213600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447739435 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.3447739435 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.198622541 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 44305415 ps |
| CPU time | 2.97 seconds |
| Started | Feb 08 12:26:20 PM UTC 25 |
| Finished | Feb 08 12:26:24 PM UTC 25 |
| Peak memory | 223772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198622541 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.198622541 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1041581921 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 32050131254 ps |
| CPU time | 741.12 seconds |
| Started | Feb 08 12:28:54 PM UTC 25 |
| Finished | Feb 08 12:41:24 PM UTC 25 |
| Peak memory | 384912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041581921 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during_key_req.1041581921 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1616228023 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 15087050 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 12:29:12 PM UTC 25 |
| Finished | Feb 08 12:29:14 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616228023 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1616228023 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.1663414255 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2573847156 ps |
| CPU time | 62.92 seconds |
| Started | Feb 08 12:27:47 PM UTC 25 |
| Finished | Feb 08 12:28:52 PM UTC 25 |
| Peak memory | 213648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663414255 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.1663414255 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1089585488 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2865547063 ps |
| CPU time | 971.02 seconds |
| Started | Feb 08 12:28:56 PM UTC 25 |
| Finished | Feb 08 12:45:18 PM UTC 25 |
| Peak memory | 384648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089585488 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.1089585488 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2517224130 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 444550029 ps |
| CPU time | 2.81 seconds |
| Started | Feb 08 12:28:53 PM UTC 25 |
| Finished | Feb 08 12:28:57 PM UTC 25 |
| Peak memory | 213680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517224130 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.2517224130 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.588874741 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 439026269 ps |
| CPU time | 27.42 seconds |
| Started | Feb 08 12:28:26 PM UTC 25 |
| Finished | Feb 08 12:28:55 PM UTC 25 |
| Peak memory | 296580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588874741 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_max_throughput.588874741 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.846454048 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 157114385 ps |
| CPU time | 6.15 seconds |
| Started | Feb 08 12:29:02 PM UTC 25 |
| Finished | Feb 08 12:29:10 PM UTC 25 |
| Peak memory | 223808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846454048 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.846454048 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.708311587 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1471668964 ps |
| CPU time | 12.62 seconds |
| Started | Feb 08 12:29:01 PM UTC 25 |
| Finished | Feb 08 12:29:15 PM UTC 25 |
| Peak memory | 223804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708311587 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.708311587 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1480704216 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 73415087030 ps |
| CPU time | 1420.75 seconds |
| Started | Feb 08 12:27:42 PM UTC 25 |
| Finished | Feb 08 12:51:38 PM UTC 25 |
| Peak memory | 386772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480704216 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1480704216 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1212555669 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 155811971 ps |
| CPU time | 5.5 seconds |
| Started | Feb 08 12:28:11 PM UTC 25 |
| Finished | Feb 08 12:28:18 PM UTC 25 |
| Peak memory | 228920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212555669 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.1212555669 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.4210925882 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 16952010573 ps |
| CPU time | 375.13 seconds |
| Started | Feb 08 12:28:20 PM UTC 25 |
| Finished | Feb 08 12:34:40 PM UTC 25 |
| Peak memory | 213852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210925882 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access_b2b.4210925882 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1609781066 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 81798123 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 12:28:59 PM UTC 25 |
| Finished | Feb 08 12:29:01 PM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609781066 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1609781066 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.2654068015 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 21376533551 ps |
| CPU time | 562.62 seconds |
| Started | Feb 08 12:28:56 PM UTC 25 |
| Finished | Feb 08 12:38:25 PM UTC 25 |
| Peak memory | 386776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654068015 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2654068015 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2110549199 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 912703197 ps |
| CPU time | 13.81 seconds |
| Started | Feb 08 12:27:39 PM UTC 25 |
| Finished | Feb 08 12:27:54 PM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110549199 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2110549199 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3670017325 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 178405586355 ps |
| CPU time | 6471.78 seconds |
| Started | Feb 08 12:29:10 PM UTC 25 |
| Finished | Feb 08 02:18:05 PM UTC 25 |
| Peak memory | 388520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670017325 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.3670017325 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2744775828 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1031961482 ps |
| CPU time | 299.61 seconds |
| Started | Feb 08 12:29:02 PM UTC 25 |
| Finished | Feb 08 12:34:06 PM UTC 25 |
| Peak memory | 390796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744775828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2744775828 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.4171789793 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 15665298572 ps |
| CPU time | 385.07 seconds |
| Started | Feb 08 12:27:55 PM UTC 25 |
| Finished | Feb 08 12:34:26 PM UTC 25 |
| Peak memory | 213544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171789793 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.4171789793 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2773846531 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 92063682 ps |
| CPU time | 20.38 seconds |
| Started | Feb 08 12:28:48 PM UTC 25 |
| Finished | Feb 08 12:29:10 PM UTC 25 |
| Peak memory | 288340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773846531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_throughput_w_partial_wr ite.2773846531 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2868910294 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 13735680413 ps |
| CPU time | 751.29 seconds |
| Started | Feb 08 12:30:03 PM UTC 25 |
| Finished | Feb 08 12:42:43 PM UTC 25 |
| Peak memory | 380624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868910294 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during_key_req.2868910294 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2078992863 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 12743502 ps |
| CPU time | 0.83 seconds |
| Started | Feb 08 12:30:41 PM UTC 25 |
| Finished | Feb 08 12:30:43 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078992863 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2078992863 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.189725903 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 6001181935 ps |
| CPU time | 26.8 seconds |
| Started | Feb 08 12:29:23 PM UTC 25 |
| Finished | Feb 08 12:29:52 PM UTC 25 |
| Peak memory | 213664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189725903 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.189725903 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2542335314 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 239421019757 ps |
| CPU time | 1288.01 seconds |
| Started | Feb 08 12:30:08 PM UTC 25 |
| Finished | Feb 08 12:51:51 PM UTC 25 |
| Peak memory | 384724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542335314 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.2542335314 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2099257171 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 412793303 ps |
| CPU time | 5.81 seconds |
| Started | Feb 08 12:29:55 PM UTC 25 |
| Finished | Feb 08 12:30:02 PM UTC 25 |
| Peak memory | 213560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099257171 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2099257171 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2541726264 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 472118071 ps |
| CPU time | 66.87 seconds |
| Started | Feb 08 12:29:42 PM UTC 25 |
| Finished | Feb 08 12:30:51 PM UTC 25 |
| Peak memory | 337488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541726264 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_max_throughput.2541726264 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2181027521 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 182765473 ps |
| CPU time | 6.84 seconds |
| Started | Feb 08 12:30:31 PM UTC 25 |
| Finished | Feb 08 12:30:39 PM UTC 25 |
| Peak memory | 224020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181027521 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.2181027521 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.2197363175 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1209359476 ps |
| CPU time | 14.56 seconds |
| Started | Feb 08 12:30:31 PM UTC 25 |
| Finished | Feb 08 12:30:47 PM UTC 25 |
| Peak memory | 213736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197363175 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.2197363175 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.3301627088 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5230349270 ps |
| CPU time | 480.34 seconds |
| Started | Feb 08 12:29:16 PM UTC 25 |
| Finished | Feb 08 12:37:22 PM UTC 25 |
| Peak memory | 349960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301627088 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.3301627088 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2367686040 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 263163911 ps |
| CPU time | 16.33 seconds |
| Started | Feb 08 12:29:37 PM UTC 25 |
| Finished | Feb 08 12:29:54 PM UTC 25 |
| Peak memory | 213552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367686040 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.2367686040 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1838322930 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 40245546926 ps |
| CPU time | 288.5 seconds |
| Started | Feb 08 12:29:40 PM UTC 25 |
| Finished | Feb 08 12:34:33 PM UTC 25 |
| Peak memory | 213668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838322930 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access_b2b.1838322930 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.818420694 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 29880481 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 12:30:28 PM UTC 25 |
| Finished | Feb 08 12:30:31 PM UTC 25 |
| Peak memory | 212896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818420694 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.818420694 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.3477545888 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4593915419 ps |
| CPU time | 471.67 seconds |
| Started | Feb 08 12:30:27 PM UTC 25 |
| Finished | Feb 08 12:38:24 PM UTC 25 |
| Peak memory | 380576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477545888 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3477545888 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.206927714 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1034962098 ps |
| CPU time | 22.1 seconds |
| Started | Feb 08 12:29:15 PM UTC 25 |
| Finished | Feb 08 12:29:38 PM UTC 25 |
| Peak memory | 213800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206927714 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.206927714 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.34610936 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 144261893127 ps |
| CPU time | 2280.44 seconds |
| Started | Feb 08 12:30:38 PM UTC 25 |
| Finished | Feb 08 01:09:02 PM UTC 25 |
| Peak memory | 386788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34610936 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.34610936 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3629354513 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2007764551 ps |
| CPU time | 683.06 seconds |
| Started | Feb 08 12:30:32 PM UTC 25 |
| Finished | Feb 08 12:42:04 PM UTC 25 |
| Peak memory | 388768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629354513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3629354513 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3077655931 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 6248628912 ps |
| CPU time | 297.39 seconds |
| Started | Feb 08 12:29:26 PM UTC 25 |
| Finished | Feb 08 12:34:28 PM UTC 25 |
| Peak memory | 213732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077655931 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3077655931 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.440654632 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 315188532 ps |
| CPU time | 33.59 seconds |
| Started | Feb 08 12:29:52 PM UTC 25 |
| Finished | Feb 08 12:30:27 PM UTC 25 |
| Peak memory | 298600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440654632 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.440654632 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.4180803751 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4830450707 ps |
| CPU time | 275.33 seconds |
| Started | Feb 08 11:39:06 AM UTC 25 |
| Finished | Feb 08 11:43:46 AM UTC 25 |
| Peak memory | 366280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180803751 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_key_req.4180803751 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2184909035 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 84645081 ps |
| CPU time | 1 seconds |
| Started | Feb 08 11:40:02 AM UTC 25 |
| Finished | Feb 08 11:40:04 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184909035 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2184909035 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2843594502 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1113203405 ps |
| CPU time | 86 seconds |
| Started | Feb 08 11:38:32 AM UTC 25 |
| Finished | Feb 08 11:40:00 AM UTC 25 |
| Peak memory | 213576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843594502 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.2843594502 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.782096999 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 78435669780 ps |
| CPU time | 518.4 seconds |
| Started | Feb 08 11:39:19 AM UTC 25 |
| Finished | Feb 08 11:48:05 AM UTC 25 |
| Peak memory | 374644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782096999 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.782096999 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3119315699 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3744191106 ps |
| CPU time | 11.94 seconds |
| Started | Feb 08 11:39:04 AM UTC 25 |
| Finished | Feb 08 11:39:18 AM UTC 25 |
| Peak memory | 223852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119315699 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.3119315699 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3464093495 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 898406957 ps |
| CPU time | 113.57 seconds |
| Started | Feb 08 11:38:43 AM UTC 25 |
| Finished | Feb 08 11:40:40 AM UTC 25 |
| Peak memory | 380488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464093495 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max_throughput.3464093495 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1914906421 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 168601899 ps |
| CPU time | 7.28 seconds |
| Started | Feb 08 11:39:49 AM UTC 25 |
| Finished | Feb 08 11:39:58 AM UTC 25 |
| Peak memory | 223832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914906421 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.1914906421 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1784975548 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2729025132 ps |
| CPU time | 13.02 seconds |
| Started | Feb 08 11:39:45 AM UTC 25 |
| Finished | Feb 08 11:40:00 AM UTC 25 |
| Peak memory | 223860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784975548 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.1784975548 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.4206415324 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 64322662105 ps |
| CPU time | 838.46 seconds |
| Started | Feb 08 11:38:31 AM UTC 25 |
| Finished | Feb 08 11:52:39 AM UTC 25 |
| Peak memory | 382664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206415324 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.4206415324 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1852675830 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 183972188 ps |
| CPU time | 56.69 seconds |
| Started | Feb 08 11:38:41 AM UTC 25 |
| Finished | Feb 08 11:39:40 AM UTC 25 |
| Peak memory | 349844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852675830 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.1852675830 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1691510398 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 89997981 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 11:39:41 AM UTC 25 |
| Finished | Feb 08 11:39:44 AM UTC 25 |
| Peak memory | 212968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691510398 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1691510398 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3200188787 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2394558573 ps |
| CPU time | 70.27 seconds |
| Started | Feb 08 11:39:31 AM UTC 25 |
| Finished | Feb 08 11:40:43 AM UTC 25 |
| Peak memory | 343768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200188787 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3200188787 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.232927301 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 240929584 ps |
| CPU time | 3.13 seconds |
| Started | Feb 08 11:40:01 AM UTC 25 |
| Finished | Feb 08 11:40:05 AM UTC 25 |
| Peak memory | 249416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232927301 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.232927301 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.3602431053 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1330617409 ps |
| CPU time | 24.54 seconds |
| Started | Feb 08 11:38:31 AM UTC 25 |
| Finished | Feb 08 11:38:57 AM UTC 25 |
| Peak memory | 213480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602431053 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3602431053 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2037271201 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2920786300 ps |
| CPU time | 272.84 seconds |
| Started | Feb 08 11:39:58 AM UTC 25 |
| Finished | Feb 08 11:44:35 AM UTC 25 |
| Peak memory | 374604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037271201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2037271201 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2137174710 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 8532997884 ps |
| CPU time | 286.51 seconds |
| Started | Feb 08 11:38:33 AM UTC 25 |
| Finished | Feb 08 11:43:24 AM UTC 25 |
| Peak memory | 213836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137174710 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.2137174710 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4178464145 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 128459821 ps |
| CPU time | 69.26 seconds |
| Started | Feb 08 11:38:58 AM UTC 25 |
| Finished | Feb 08 11:40:10 AM UTC 25 |
| Peak memory | 351888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178464145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_throughput_w_partial_wri te.4178464145 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3622953691 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 2937892514 ps |
| CPU time | 367.56 seconds |
| Started | Feb 08 12:31:38 PM UTC 25 |
| Finished | Feb 08 12:37:51 PM UTC 25 |
| Peak memory | 370388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622953691 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during_key_req.3622953691 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.4092673826 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 39605642 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 12:32:26 PM UTC 25 |
| Finished | Feb 08 12:32:28 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092673826 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.4092673826 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.3607661155 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1604670124 ps |
| CPU time | 41.57 seconds |
| Started | Feb 08 12:30:48 PM UTC 25 |
| Finished | Feb 08 12:31:32 PM UTC 25 |
| Peak memory | 213688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607661155 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.3607661155 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.526165716 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 68323656173 ps |
| CPU time | 819.77 seconds |
| Started | Feb 08 12:31:41 PM UTC 25 |
| Finished | Feb 08 12:45:29 PM UTC 25 |
| Peak memory | 374376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526165716 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.526165716 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2046833415 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1020010793 ps |
| CPU time | 6.31 seconds |
| Started | Feb 08 12:31:37 PM UTC 25 |
| Finished | Feb 08 12:31:45 PM UTC 25 |
| Peak memory | 223996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046833415 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.2046833415 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3891509776 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 55103177 ps |
| CPU time | 4.53 seconds |
| Started | Feb 08 12:31:32 PM UTC 25 |
| Finished | Feb 08 12:31:38 PM UTC 25 |
| Peak memory | 231032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891509776 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max_throughput.3891509776 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1666003817 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 382557081 ps |
| CPU time | 3.3 seconds |
| Started | Feb 08 12:32:17 PM UTC 25 |
| Finished | Feb 08 12:32:22 PM UTC 25 |
| Peak memory | 223804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666003817 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.1666003817 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.3677256548 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1854908934 ps |
| CPU time | 16.42 seconds |
| Started | Feb 08 12:32:07 PM UTC 25 |
| Finished | Feb 08 12:32:25 PM UTC 25 |
| Peak memory | 224140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677256548 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.3677256548 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1856113050 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1771857896 ps |
| CPU time | 492.22 seconds |
| Started | Feb 08 12:30:48 PM UTC 25 |
| Finished | Feb 08 12:39:07 PM UTC 25 |
| Peak memory | 380384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856113050 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1856113050 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.74059992 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 315518289 ps |
| CPU time | 16.92 seconds |
| Started | Feb 08 12:31:18 PM UTC 25 |
| Finished | Feb 08 12:31:36 PM UTC 25 |
| Peak memory | 213600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74059992 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.74059992 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.803113122 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 97026495977 ps |
| CPU time | 251.64 seconds |
| Started | Feb 08 12:31:18 PM UTC 25 |
| Finished | Feb 08 12:35:33 PM UTC 25 |
| Peak memory | 213884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803113122 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access_b2b.803113122 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3754177192 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 45705755 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 12:32:04 PM UTC 25 |
| Finished | Feb 08 12:32:06 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754177192 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3754177192 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1966145669 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 12504456645 ps |
| CPU time | 807.19 seconds |
| Started | Feb 08 12:31:46 PM UTC 25 |
| Finished | Feb 08 12:45:22 PM UTC 25 |
| Peak memory | 384924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966145669 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1966145669 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3134406270 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 617978035 ps |
| CPU time | 76.71 seconds |
| Started | Feb 08 12:30:44 PM UTC 25 |
| Finished | Feb 08 12:32:03 PM UTC 25 |
| Peak memory | 345924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134406270 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3134406270 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.4149293149 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 17078836627 ps |
| CPU time | 1507.81 seconds |
| Started | Feb 08 12:32:23 PM UTC 25 |
| Finished | Feb 08 12:57:46 PM UTC 25 |
| Peak memory | 386964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149293149 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.4149293149 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.611049521 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1472180887 ps |
| CPU time | 137.96 seconds |
| Started | Feb 08 12:32:21 PM UTC 25 |
| Finished | Feb 08 12:34:41 PM UTC 25 |
| Peak memory | 384644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611049521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.611049521 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.996901639 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 8616443284 ps |
| CPU time | 245.31 seconds |
| Started | Feb 08 12:30:51 PM UTC 25 |
| Finished | Feb 08 12:35:01 PM UTC 25 |
| Peak memory | 213724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996901639 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.996901639 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1619799552 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 156129756 ps |
| CPU time | 115.75 seconds |
| Started | Feb 08 12:31:32 PM UTC 25 |
| Finished | Feb 08 12:33:31 PM UTC 25 |
| Peak memory | 376476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619799552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_throughput_w_partial_wr ite.1619799552 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.149764727 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 13388386816 ps |
| CPU time | 519.6 seconds |
| Started | Feb 08 12:33:57 PM UTC 25 |
| Finished | Feb 08 12:42:43 PM UTC 25 |
| Peak memory | 372348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149764727 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during_key_req.149764727 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1363872217 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 19025642 ps |
| CPU time | 0.74 seconds |
| Started | Feb 08 12:34:32 PM UTC 25 |
| Finished | Feb 08 12:34:34 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363872217 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1363872217 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.713394901 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 10678666956 ps |
| CPU time | 84.2 seconds |
| Started | Feb 08 12:32:34 PM UTC 25 |
| Finished | Feb 08 12:34:01 PM UTC 25 |
| Peak memory | 213740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713394901 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.713394901 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3022265911 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 316302729 ps |
| CPU time | 4.64 seconds |
| Started | Feb 08 12:33:50 PM UTC 25 |
| Finished | Feb 08 12:33:56 PM UTC 25 |
| Peak memory | 213528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022265911 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.3022265911 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.109886082 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 103327547 ps |
| CPU time | 58.07 seconds |
| Started | Feb 08 12:33:32 PM UTC 25 |
| Finished | Feb 08 12:34:32 PM UTC 25 |
| Peak memory | 323224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109886082 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_max_throughput.109886082 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.181955795 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 58862865 ps |
| CPU time | 3.64 seconds |
| Started | Feb 08 12:34:26 PM UTC 25 |
| Finished | Feb 08 12:34:31 PM UTC 25 |
| Peak memory | 223812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181955795 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.181955795 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2884301407 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 277823450 ps |
| CPU time | 4.92 seconds |
| Started | Feb 08 12:34:21 PM UTC 25 |
| Finished | Feb 08 12:34:27 PM UTC 25 |
| Peak memory | 223908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884301407 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.2884301407 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2455098305 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4402000851 ps |
| CPU time | 495.75 seconds |
| Started | Feb 08 12:32:29 PM UTC 25 |
| Finished | Feb 08 12:40:52 PM UTC 25 |
| Peak memory | 380628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455098305 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2455098305 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1206159851 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 554505864 ps |
| CPU time | 13.23 seconds |
| Started | Feb 08 12:33:18 PM UTC 25 |
| Finished | Feb 08 12:33:32 PM UTC 25 |
| Peak memory | 213828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206159851 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.1206159851 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1426504484 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3391304597 ps |
| CPU time | 280.57 seconds |
| Started | Feb 08 12:33:32 PM UTC 25 |
| Finished | Feb 08 12:38:17 PM UTC 25 |
| Peak memory | 213656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426504484 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access_b2b.1426504484 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2973789557 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 69837722 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 12:34:18 PM UTC 25 |
| Finished | Feb 08 12:34:20 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973789557 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2973789557 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1571591795 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5312259679 ps |
| CPU time | 346.92 seconds |
| Started | Feb 08 12:34:08 PM UTC 25 |
| Finished | Feb 08 12:39:59 PM UTC 25 |
| Peak memory | 370348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571591795 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1571591795 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1189683782 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1328625106 ps |
| CPU time | 19.35 seconds |
| Started | Feb 08 12:32:26 PM UTC 25 |
| Finished | Feb 08 12:32:47 PM UTC 25 |
| Peak memory | 288420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189683782 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1189683782 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1332980465 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 11810347917 ps |
| CPU time | 2618.43 seconds |
| Started | Feb 08 12:34:30 PM UTC 25 |
| Finished | Feb 08 01:18:34 PM UTC 25 |
| Peak memory | 388592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332980465 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.1332980465 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.910520913 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1551827576 ps |
| CPU time | 236.3 seconds |
| Started | Feb 08 12:34:28 PM UTC 25 |
| Finished | Feb 08 12:38:28 PM UTC 25 |
| Peak memory | 380624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910520913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.910520913 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.981339464 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3414301692 ps |
| CPU time | 143.05 seconds |
| Started | Feb 08 12:32:48 PM UTC 25 |
| Finished | Feb 08 12:35:13 PM UTC 25 |
| Peak memory | 213628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981339464 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.981339464 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4206402002 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 215705685 ps |
| CPU time | 41.75 seconds |
| Started | Feb 08 12:33:33 PM UTC 25 |
| Finished | Feb 08 12:34:17 PM UTC 25 |
| Peak memory | 317084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206402002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_throughput_w_partial_wr ite.4206402002 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3984578639 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 3941076498 ps |
| CPU time | 927.25 seconds |
| Started | Feb 08 12:35:04 PM UTC 25 |
| Finished | Feb 08 12:50:42 PM UTC 25 |
| Peak memory | 382840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984578639 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during_key_req.3984578639 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2957601288 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 43776513 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 12:35:28 PM UTC 25 |
| Finished | Feb 08 12:35:30 PM UTC 25 |
| Peak memory | 212960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957601288 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2957601288 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.2462334931 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 9293009450 ps |
| CPU time | 86.78 seconds |
| Started | Feb 08 12:34:34 PM UTC 25 |
| Finished | Feb 08 12:36:03 PM UTC 25 |
| Peak memory | 213616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462334931 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.2462334931 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.1945937081 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2417020106 ps |
| CPU time | 786.3 seconds |
| Started | Feb 08 12:35:12 PM UTC 25 |
| Finished | Feb 08 12:48:27 PM UTC 25 |
| Peak memory | 386744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945937081 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.1945937081 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3714463041 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2370414436 ps |
| CPU time | 8.81 seconds |
| Started | Feb 08 12:35:01 PM UTC 25 |
| Finished | Feb 08 12:35:12 PM UTC 25 |
| Peak memory | 223852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714463041 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.3714463041 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1074511324 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 164138607 ps |
| CPU time | 3.83 seconds |
| Started | Feb 08 12:34:57 PM UTC 25 |
| Finished | Feb 08 12:35:02 PM UTC 25 |
| Peak memory | 231048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074511324 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_max_throughput.1074511324 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1672930663 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 90066846 ps |
| CPU time | 4.48 seconds |
| Started | Feb 08 12:35:18 PM UTC 25 |
| Finished | Feb 08 12:35:24 PM UTC 25 |
| Peak memory | 223756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672930663 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.1672930663 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2118682181 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 193393465 ps |
| CPU time | 7.21 seconds |
| Started | Feb 08 12:35:17 PM UTC 25 |
| Finished | Feb 08 12:35:26 PM UTC 25 |
| Peak memory | 224020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118682181 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.2118682181 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1675242493 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 18623136542 ps |
| CPU time | 595.32 seconds |
| Started | Feb 08 12:34:34 PM UTC 25 |
| Finished | Feb 08 12:44:37 PM UTC 25 |
| Peak memory | 380484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675242493 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.1675242493 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3433696703 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 185664086 ps |
| CPU time | 16.63 seconds |
| Started | Feb 08 12:34:43 PM UTC 25 |
| Finished | Feb 08 12:35:01 PM UTC 25 |
| Peak memory | 264016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433696703 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.3433696703 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.4016959852 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 10886213756 ps |
| CPU time | 225.93 seconds |
| Started | Feb 08 12:34:55 PM UTC 25 |
| Finished | Feb 08 12:38:44 PM UTC 25 |
| Peak memory | 213740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016959852 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access_b2b.4016959852 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2118150984 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 151771680 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 12:35:14 PM UTC 25 |
| Finished | Feb 08 12:35:17 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118150984 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2118150984 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.2697355740 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 22434389306 ps |
| CPU time | 827.66 seconds |
| Started | Feb 08 12:35:13 PM UTC 25 |
| Finished | Feb 08 12:49:10 PM UTC 25 |
| Peak memory | 384876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697355740 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2697355740 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.363260876 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 208459305 ps |
| CPU time | 21.23 seconds |
| Started | Feb 08 12:34:33 PM UTC 25 |
| Finished | Feb 08 12:34:56 PM UTC 25 |
| Peak memory | 288332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363260876 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.363260876 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3551759634 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 324294881867 ps |
| CPU time | 5107.08 seconds |
| Started | Feb 08 12:35:27 PM UTC 25 |
| Finished | Feb 08 02:01:24 PM UTC 25 |
| Peak memory | 388604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551759634 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.3551759634 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4257697285 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1187264020 ps |
| CPU time | 92.61 seconds |
| Started | Feb 08 12:35:26 PM UTC 25 |
| Finished | Feb 08 12:37:00 PM UTC 25 |
| Peak memory | 325596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257697285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.4257697285 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1790192813 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 9976341709 ps |
| CPU time | 222.57 seconds |
| Started | Feb 08 12:34:41 PM UTC 25 |
| Finished | Feb 08 12:38:28 PM UTC 25 |
| Peak memory | 213852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790192813 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1790192813 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.2348473273 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 414749871 ps |
| CPU time | 23.9 seconds |
| Started | Feb 08 12:35:01 PM UTC 25 |
| Finished | Feb 08 12:35:27 PM UTC 25 |
| Peak memory | 280108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348473273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_throughput_w_partial_wr ite.2348473273 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.478534716 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 9628986473 ps |
| CPU time | 351.07 seconds |
| Started | Feb 08 12:37:02 PM UTC 25 |
| Finished | Feb 08 12:42:57 PM UTC 25 |
| Peak memory | 358036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478534716 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during_key_req.478534716 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1126169716 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 34733028 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 12:37:31 PM UTC 25 |
| Finished | Feb 08 12:37:33 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126169716 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1126169716 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3440533479 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 2476430605 ps |
| CPU time | 61.28 seconds |
| Started | Feb 08 12:36:04 PM UTC 25 |
| Finished | Feb 08 12:37:08 PM UTC 25 |
| Peak memory | 213716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440533479 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.3440533479 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.425531985 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 47199981418 ps |
| CPU time | 1378.34 seconds |
| Started | Feb 08 12:37:09 PM UTC 25 |
| Finished | Feb 08 01:00:22 PM UTC 25 |
| Peak memory | 386768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425531985 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.425531985 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.587264726 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1700465288 ps |
| CPU time | 6.98 seconds |
| Started | Feb 08 12:37:02 PM UTC 25 |
| Finished | Feb 08 12:37:10 PM UTC 25 |
| Peak memory | 223856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587264726 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.587264726 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3727079877 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 268671676 ps |
| CPU time | 80.54 seconds |
| Started | Feb 08 12:36:30 PM UTC 25 |
| Finished | Feb 08 12:37:53 PM UTC 25 |
| Peak memory | 374608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727079877 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_max_throughput.3727079877 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1075571720 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 584209506 ps |
| CPU time | 6.52 seconds |
| Started | Feb 08 12:37:23 PM UTC 25 |
| Finished | Feb 08 12:37:30 PM UTC 25 |
| Peak memory | 224036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075571720 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.1075571720 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1177056279 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 304999624 ps |
| CPU time | 7.5 seconds |
| Started | Feb 08 12:37:21 PM UTC 25 |
| Finished | Feb 08 12:37:30 PM UTC 25 |
| Peak memory | 223896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177056279 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.1177056279 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.4178529937 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 22789610473 ps |
| CPU time | 433.4 seconds |
| Started | Feb 08 12:35:34 PM UTC 25 |
| Finished | Feb 08 12:42:53 PM UTC 25 |
| Peak memory | 376504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178529937 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.4178529937 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3823342919 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 261218120 ps |
| CPU time | 54.45 seconds |
| Started | Feb 08 12:36:24 PM UTC 25 |
| Finished | Feb 08 12:37:20 PM UTC 25 |
| Peak memory | 327296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823342919 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.3823342919 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.790296489 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 9825439778 ps |
| CPU time | 382.56 seconds |
| Started | Feb 08 12:36:30 PM UTC 25 |
| Finished | Feb 08 12:42:58 PM UTC 25 |
| Peak memory | 213652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790296489 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access_b2b.790296489 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3881069892 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 80170986 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 12:37:19 PM UTC 25 |
| Finished | Feb 08 12:37:22 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881069892 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3881069892 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.2626494873 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 10229030902 ps |
| CPU time | 352.74 seconds |
| Started | Feb 08 12:37:11 PM UTC 25 |
| Finished | Feb 08 12:43:09 PM UTC 25 |
| Peak memory | 380504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626494873 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2626494873 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3280032882 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 481655674 ps |
| CPU time | 86.73 seconds |
| Started | Feb 08 12:35:31 PM UTC 25 |
| Finished | Feb 08 12:37:00 PM UTC 25 |
| Peak memory | 345612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280032882 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3280032882 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.283957678 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 26912237194 ps |
| CPU time | 1689.66 seconds |
| Started | Feb 08 12:37:31 PM UTC 25 |
| Finished | Feb 08 01:05:57 PM UTC 25 |
| Peak memory | 378644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283957678 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.283957678 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.31692551 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3047816608 ps |
| CPU time | 280.41 seconds |
| Started | Feb 08 12:36:13 PM UTC 25 |
| Finished | Feb 08 12:40:57 PM UTC 25 |
| Peak memory | 213696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31692551 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.31692551 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.174434339 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 85252453 ps |
| CPU time | 17.87 seconds |
| Started | Feb 08 12:36:58 PM UTC 25 |
| Finished | Feb 08 12:37:18 PM UTC 25 |
| Peak memory | 280408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174434339 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.174434339 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.3545360629 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 11243937307 ps |
| CPU time | 902.01 seconds |
| Started | Feb 08 12:38:28 PM UTC 25 |
| Finished | Feb 08 12:53:39 PM UTC 25 |
| Peak memory | 384652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545360629 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during_key_req.3545360629 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.212539585 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 23579415 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 12:38:42 PM UTC 25 |
| Finished | Feb 08 12:38:44 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212539585 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.212539585 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1916427585 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 580150179 ps |
| CPU time | 31.64 seconds |
| Started | Feb 08 12:37:54 PM UTC 25 |
| Finished | Feb 08 12:38:27 PM UTC 25 |
| Peak memory | 213680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916427585 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.1916427585 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.3686030073 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 3358164441 ps |
| CPU time | 862.5 seconds |
| Started | Feb 08 12:38:29 PM UTC 25 |
| Finished | Feb 08 12:53:01 PM UTC 25 |
| Peak memory | 384892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686030073 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.3686030073 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3972491787 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1036075304 ps |
| CPU time | 13.9 seconds |
| Started | Feb 08 12:38:26 PM UTC 25 |
| Finished | Feb 08 12:38:42 PM UTC 25 |
| Peak memory | 213560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972491787 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.3972491787 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1851996324 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 81499632 ps |
| CPU time | 20.69 seconds |
| Started | Feb 08 12:38:18 PM UTC 25 |
| Finished | Feb 08 12:38:40 PM UTC 25 |
| Peak memory | 290380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851996324 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_max_throughput.1851996324 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2884765293 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 113303577 ps |
| CPU time | 2.98 seconds |
| Started | Feb 08 12:38:36 PM UTC 25 |
| Finished | Feb 08 12:38:41 PM UTC 25 |
| Peak memory | 223756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884765293 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.2884765293 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1642428844 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 548730675 ps |
| CPU time | 9.25 seconds |
| Started | Feb 08 12:38:35 PM UTC 25 |
| Finished | Feb 08 12:38:46 PM UTC 25 |
| Peak memory | 224096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642428844 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.1642428844 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3031145705 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1102731680 ps |
| CPU time | 226.59 seconds |
| Started | Feb 08 12:37:51 PM UTC 25 |
| Finished | Feb 08 12:41:41 PM UTC 25 |
| Peak memory | 366192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031145705 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.3031145705 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2644753365 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 148596745 ps |
| CPU time | 3.11 seconds |
| Started | Feb 08 12:38:02 PM UTC 25 |
| Finished | Feb 08 12:38:06 PM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644753365 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2644753365 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3046205636 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2616089956 ps |
| CPU time | 195.36 seconds |
| Started | Feb 08 12:38:07 PM UTC 25 |
| Finished | Feb 08 12:41:26 PM UTC 25 |
| Peak memory | 213588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046205636 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access_b2b.3046205636 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3880150204 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 33950729 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 12:38:32 PM UTC 25 |
| Finished | Feb 08 12:38:35 PM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880150204 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3880150204 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.1823001992 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 8957953062 ps |
| CPU time | 583.5 seconds |
| Started | Feb 08 12:38:30 PM UTC 25 |
| Finished | Feb 08 12:48:20 PM UTC 25 |
| Peak memory | 386972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823001992 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1823001992 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.381781196 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 235830960 ps |
| CPU time | 16.95 seconds |
| Started | Feb 08 12:37:34 PM UTC 25 |
| Finished | Feb 08 12:37:52 PM UTC 25 |
| Peak memory | 213584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381781196 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.381781196 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3443233817 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 6872238478 ps |
| CPU time | 144.5 seconds |
| Started | Feb 08 12:38:40 PM UTC 25 |
| Finished | Feb 08 12:41:07 PM UTC 25 |
| Peak memory | 386856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443233817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3443233817 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1154614602 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2525778480 ps |
| CPU time | 233.08 seconds |
| Started | Feb 08 12:37:54 PM UTC 25 |
| Finished | Feb 08 12:41:51 PM UTC 25 |
| Peak memory | 213828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154614602 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1154614602 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.15660900 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 220404505 ps |
| CPU time | 49.38 seconds |
| Started | Feb 08 12:38:25 PM UTC 25 |
| Finished | Feb 08 12:39:16 PM UTC 25 |
| Peak memory | 323476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15660900 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.15660900 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1406404932 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3763342554 ps |
| CPU time | 1158.29 seconds |
| Started | Feb 08 12:39:36 PM UTC 25 |
| Finished | Feb 08 12:59:06 PM UTC 25 |
| Peak memory | 384700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406404932 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during_key_req.1406404932 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1822143086 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 35596512 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 12:40:09 PM UTC 25 |
| Finished | Feb 08 12:40:11 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822143086 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1822143086 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2157152952 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3283928206 ps |
| CPU time | 48.94 seconds |
| Started | Feb 08 12:38:45 PM UTC 25 |
| Finished | Feb 08 12:39:36 PM UTC 25 |
| Peak memory | 213532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157152952 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.2157152952 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.516659840 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3773719873 ps |
| CPU time | 1176.08 seconds |
| Started | Feb 08 12:39:37 PM UTC 25 |
| Finished | Feb 08 12:59:25 PM UTC 25 |
| Peak memory | 384688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516659840 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.516659840 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2444715752 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1461310120 ps |
| CPU time | 5.02 seconds |
| Started | Feb 08 12:39:29 PM UTC 25 |
| Finished | Feb 08 12:39:36 PM UTC 25 |
| Peak memory | 228020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444715752 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.2444715752 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2084158507 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 167616923 ps |
| CPU time | 33.92 seconds |
| Started | Feb 08 12:39:17 PM UTC 25 |
| Finished | Feb 08 12:39:53 PM UTC 25 |
| Peak memory | 294556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084158507 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_max_throughput.2084158507 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2477205597 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 350998527 ps |
| CPU time | 6.34 seconds |
| Started | Feb 08 12:40:00 PM UTC 25 |
| Finished | Feb 08 12:40:08 PM UTC 25 |
| Peak memory | 223836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477205597 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.2477205597 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2410966616 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 144440842 ps |
| CPU time | 5.32 seconds |
| Started | Feb 08 12:39:57 PM UTC 25 |
| Finished | Feb 08 12:40:04 PM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410966616 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2410966616 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3962261477 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 57595706529 ps |
| CPU time | 724.92 seconds |
| Started | Feb 08 12:38:45 PM UTC 25 |
| Finished | Feb 08 12:50:59 PM UTC 25 |
| Peak memory | 376488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962261477 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.3962261477 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.436933285 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 885564028 ps |
| CPU time | 15.86 seconds |
| Started | Feb 08 12:39:06 PM UTC 25 |
| Finished | Feb 08 12:39:23 PM UTC 25 |
| Peak memory | 213600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436933285 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.436933285 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1167531575 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 72886544953 ps |
| CPU time | 459.23 seconds |
| Started | Feb 08 12:39:08 PM UTC 25 |
| Finished | Feb 08 12:46:53 PM UTC 25 |
| Peak memory | 213640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167531575 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access_b2b.1167531575 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3329999246 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 83437876 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 12:39:54 PM UTC 25 |
| Finished | Feb 08 12:39:57 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329999246 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3329999246 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.2558021249 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 61499094402 ps |
| CPU time | 507.32 seconds |
| Started | Feb 08 12:39:37 PM UTC 25 |
| Finished | Feb 08 12:48:10 PM UTC 25 |
| Peak memory | 366464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558021249 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2558021249 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.135473495 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 997976279 ps |
| CPU time | 20.17 seconds |
| Started | Feb 08 12:38:43 PM UTC 25 |
| Finished | Feb 08 12:39:05 PM UTC 25 |
| Peak memory | 213576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135473495 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram _ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.135473495 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2703548385 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 15166587300 ps |
| CPU time | 779.39 seconds |
| Started | Feb 08 12:40:05 PM UTC 25 |
| Finished | Feb 08 12:53:13 PM UTC 25 |
| Peak memory | 386836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703548385 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.2703548385 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4016124204 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 954371743 ps |
| CPU time | 76.04 seconds |
| Started | Feb 08 12:40:02 PM UTC 25 |
| Finished | Feb 08 12:41:20 PM UTC 25 |
| Peak memory | 317076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016124204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.4016124204 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.487719168 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3154601636 ps |
| CPU time | 169.93 seconds |
| Started | Feb 08 12:38:47 PM UTC 25 |
| Finished | Feb 08 12:41:40 PM UTC 25 |
| Peak memory | 213892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487719168 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.487719168 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1375728707 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 162253899 ps |
| CPU time | 2.53 seconds |
| Started | Feb 08 12:39:24 PM UTC 25 |
| Finished | Feb 08 12:39:28 PM UTC 25 |
| Peak memory | 223776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375728707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_throughput_w_partial_wr ite.1375728707 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.4216033815 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3271793615 ps |
| CPU time | 513.23 seconds |
| Started | Feb 08 12:40:59 PM UTC 25 |
| Finished | Feb 08 12:49:39 PM UTC 25 |
| Peak memory | 382872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216033815 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during_key_req.4216033815 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2620253540 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 19947437 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 12:41:27 PM UTC 25 |
| Finished | Feb 08 12:41:29 PM UTC 25 |
| Peak memory | 212520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620253540 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2620253540 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.351709550 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1310673336 ps |
| CPU time | 16.7 seconds |
| Started | Feb 08 12:40:26 PM UTC 25 |
| Finished | Feb 08 12:40:44 PM UTC 25 |
| Peak memory | 213600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351709550 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.351709550 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1493500421 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 15864932712 ps |
| CPU time | 33.26 seconds |
| Started | Feb 08 12:41:02 PM UTC 25 |
| Finished | Feb 08 12:41:37 PM UTC 25 |
| Peak memory | 213676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493500421 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.1493500421 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2782402858 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1610264800 ps |
| CPU time | 9.15 seconds |
| Started | Feb 08 12:40:58 PM UTC 25 |
| Finished | Feb 08 12:41:09 PM UTC 25 |
| Peak memory | 213560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782402858 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.2782402858 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1948004114 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 240632994 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 12:40:52 PM UTC 25 |
| Finished | Feb 08 12:40:56 PM UTC 25 |
| Peak memory | 212956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948004114 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_max_throughput.1948004114 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1968500286 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 48390276 ps |
| CPU time | 3.1 seconds |
| Started | Feb 08 12:41:21 PM UTC 25 |
| Finished | Feb 08 12:41:25 PM UTC 25 |
| Peak memory | 223852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968500286 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.1968500286 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.1819461873 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 453467948 ps |
| CPU time | 8.34 seconds |
| Started | Feb 08 12:41:13 PM UTC 25 |
| Finished | Feb 08 12:41:23 PM UTC 25 |
| Peak memory | 223868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819461873 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.1819461873 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.4107605202 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 399816547 ps |
| CPU time | 27.37 seconds |
| Started | Feb 08 12:40:22 PM UTC 25 |
| Finished | Feb 08 12:40:51 PM UTC 25 |
| Peak memory | 213612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107605202 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.4107605202 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1724644205 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 685204188 ps |
| CPU time | 127.12 seconds |
| Started | Feb 08 12:40:35 PM UTC 25 |
| Finished | Feb 08 12:42:45 PM UTC 25 |
| Peak memory | 378520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724644205 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.1724644205 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2252012500 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 13970192281 ps |
| CPU time | 91.16 seconds |
| Started | Feb 08 12:40:45 PM UTC 25 |
| Finished | Feb 08 12:42:18 PM UTC 25 |
| Peak memory | 213852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252012500 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access_b2b.2252012500 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3941327752 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 84695667 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 12:41:10 PM UTC 25 |
| Finished | Feb 08 12:41:12 PM UTC 25 |
| Peak memory | 212484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941327752 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3941327752 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2197385037 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 5666193563 ps |
| CPU time | 1796.24 seconds |
| Started | Feb 08 12:41:07 PM UTC 25 |
| Finished | Feb 08 01:11:22 PM UTC 25 |
| Peak memory | 378540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197385037 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2197385037 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.3976075937 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 819258365 ps |
| CPU time | 11.37 seconds |
| Started | Feb 08 12:40:12 PM UTC 25 |
| Finished | Feb 08 12:40:25 PM UTC 25 |
| Peak memory | 255748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976075937 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3976075937 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3755527530 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 23636599875 ps |
| CPU time | 1137.83 seconds |
| Started | Feb 08 12:41:24 PM UTC 25 |
| Finished | Feb 08 01:00:34 PM UTC 25 |
| Peak memory | 386700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755527530 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.3755527530 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1211153435 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 688737614 ps |
| CPU time | 44.23 seconds |
| Started | Feb 08 12:41:23 PM UTC 25 |
| Finished | Feb 08 12:42:09 PM UTC 25 |
| Peak memory | 223928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211153435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1211153435 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.4178964098 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2586638182 ps |
| CPU time | 252.62 seconds |
| Started | Feb 08 12:40:31 PM UTC 25 |
| Finished | Feb 08 12:44:47 PM UTC 25 |
| Peak memory | 213596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178964098 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.4178964098 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.4252522858 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 66800864 ps |
| CPU time | 7.1 seconds |
| Started | Feb 08 12:40:52 PM UTC 25 |
| Finished | Feb 08 12:41:01 PM UTC 25 |
| Peak memory | 247552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252522858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_throughput_w_partial_wr ite.4252522858 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.4024613988 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 19564963242 ps |
| CPU time | 804.93 seconds |
| Started | Feb 08 12:42:09 PM UTC 25 |
| Finished | Feb 08 12:55:42 PM UTC 25 |
| Peak memory | 380560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024613988 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during_key_req.4024613988 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1017655919 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 61932761 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 12:42:39 PM UTC 25 |
| Finished | Feb 08 12:42:41 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017655919 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1017655919 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.105567901 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 4652213804 ps |
| CPU time | 32.13 seconds |
| Started | Feb 08 12:41:38 PM UTC 25 |
| Finished | Feb 08 12:42:12 PM UTC 25 |
| Peak memory | 213804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105567901 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.105567901 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.349243835 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 44881144154 ps |
| CPU time | 911.8 seconds |
| Started | Feb 08 12:42:11 PM UTC 25 |
| Finished | Feb 08 12:57:33 PM UTC 25 |
| Peak memory | 384640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349243835 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.349243835 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1929881367 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 633337111 ps |
| CPU time | 8.71 seconds |
| Started | Feb 08 12:42:05 PM UTC 25 |
| Finished | Feb 08 12:42:15 PM UTC 25 |
| Peak memory | 213560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929881367 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.1929881367 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1967875857 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 71531020 ps |
| CPU time | 14.78 seconds |
| Started | Feb 08 12:41:52 PM UTC 25 |
| Finished | Feb 08 12:42:08 PM UTC 25 |
| Peak memory | 269900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967875857 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_max_throughput.1967875857 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3586562359 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 329981184 ps |
| CPU time | 3.75 seconds |
| Started | Feb 08 12:42:20 PM UTC 25 |
| Finished | Feb 08 12:42:25 PM UTC 25 |
| Peak memory | 223828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586562359 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.3586562359 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2725446957 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 664446538 ps |
| CPU time | 16.1 seconds |
| Started | Feb 08 12:42:20 PM UTC 25 |
| Finished | Feb 08 12:42:37 PM UTC 25 |
| Peak memory | 224072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725446957 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.2725446957 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2669872512 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 29966738493 ps |
| CPU time | 474.84 seconds |
| Started | Feb 08 12:41:30 PM UTC 25 |
| Finished | Feb 08 12:49:31 PM UTC 25 |
| Peak memory | 386660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669872512 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.2669872512 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3911287994 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1856052707 ps |
| CPU time | 55.96 seconds |
| Started | Feb 08 12:41:42 PM UTC 25 |
| Finished | Feb 08 12:42:40 PM UTC 25 |
| Peak memory | 325272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911287994 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.3911287994 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.545631369 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 78135769024 ps |
| CPU time | 471.19 seconds |
| Started | Feb 08 12:41:46 PM UTC 25 |
| Finished | Feb 08 12:49:43 PM UTC 25 |
| Peak memory | 213648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545631369 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access_b2b.545631369 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2431513039 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 117820902 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 12:42:16 PM UTC 25 |
| Finished | Feb 08 12:42:18 PM UTC 25 |
| Peak memory | 213020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431513039 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2431513039 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.3391043800 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 6411352223 ps |
| CPU time | 673.4 seconds |
| Started | Feb 08 12:42:13 PM UTC 25 |
| Finished | Feb 08 12:53:34 PM UTC 25 |
| Peak memory | 368184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391043800 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3391043800 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3027305172 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 233854837 ps |
| CPU time | 16.36 seconds |
| Started | Feb 08 12:41:27 PM UTC 25 |
| Finished | Feb 08 12:41:45 PM UTC 25 |
| Peak memory | 261680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027305172 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3027305172 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3737680544 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 38207914870 ps |
| CPU time | 2070.79 seconds |
| Started | Feb 08 12:42:25 PM UTC 25 |
| Finished | Feb 08 01:17:18 PM UTC 25 |
| Peak memory | 386452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737680544 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.3737680544 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2361962968 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 17848662957 ps |
| CPU time | 296.85 seconds |
| Started | Feb 08 12:41:40 PM UTC 25 |
| Finished | Feb 08 12:46:42 PM UTC 25 |
| Peak memory | 213844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361962968 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.2361962968 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3370450888 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 896214988 ps |
| CPU time | 27.33 seconds |
| Started | Feb 08 12:41:54 PM UTC 25 |
| Finished | Feb 08 12:42:23 PM UTC 25 |
| Peak memory | 312904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370450888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_throughput_w_partial_wr ite.3370450888 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1926168043 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 12770910184 ps |
| CPU time | 1009.55 seconds |
| Started | Feb 08 12:43:03 PM UTC 25 |
| Finished | Feb 08 01:00:04 PM UTC 25 |
| Peak memory | 378528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926168043 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during_key_req.1926168043 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3858413378 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 141788625 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 12:44:19 PM UTC 25 |
| Finished | Feb 08 12:44:22 PM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858413378 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3858413378 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.849917749 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3807565235 ps |
| CPU time | 91.12 seconds |
| Started | Feb 08 12:42:45 PM UTC 25 |
| Finished | Feb 08 12:44:18 PM UTC 25 |
| Peak memory | 213532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849917749 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.849917749 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1148554704 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 18797061141 ps |
| CPU time | 259.23 seconds |
| Started | Feb 08 12:43:06 PM UTC 25 |
| Finished | Feb 08 12:47:30 PM UTC 25 |
| Peak memory | 386772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148554704 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1148554704 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1607656517 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1545583202 ps |
| CPU time | 10.76 seconds |
| Started | Feb 08 12:43:00 PM UTC 25 |
| Finished | Feb 08 12:43:12 PM UTC 25 |
| Peak memory | 228020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607656517 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.1607656517 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2491364043 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 37283711 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 12:42:59 PM UTC 25 |
| Finished | Feb 08 12:43:02 PM UTC 25 |
| Peak memory | 212500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491364043 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max_throughput.2491364043 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1270565584 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 291358558 ps |
| CPU time | 4.21 seconds |
| Started | Feb 08 12:43:27 PM UTC 25 |
| Finished | Feb 08 12:43:32 PM UTC 25 |
| Peak memory | 223832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270565584 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.1270565584 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2043475081 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 569411973 ps |
| CPU time | 7.71 seconds |
| Started | Feb 08 12:43:16 PM UTC 25 |
| Finished | Feb 08 12:43:26 PM UTC 25 |
| Peak memory | 223812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043475081 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.2043475081 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3781622837 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 9579348166 ps |
| CPU time | 487.64 seconds |
| Started | Feb 08 12:42:42 PM UTC 25 |
| Finished | Feb 08 12:50:56 PM UTC 25 |
| Peak memory | 364436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781622837 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.3781622837 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1916392184 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2525015756 ps |
| CPU time | 17.74 seconds |
| Started | Feb 08 12:42:46 PM UTC 25 |
| Finished | Feb 08 12:43:05 PM UTC 25 |
| Peak memory | 213724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916392184 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.1916392184 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3981682239 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 95349244158 ps |
| CPU time | 618.78 seconds |
| Started | Feb 08 12:42:54 PM UTC 25 |
| Finished | Feb 08 12:53:21 PM UTC 25 |
| Peak memory | 213932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981682239 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access_b2b.3981682239 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.4276517408 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 133544451 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 12:43:13 PM UTC 25 |
| Finished | Feb 08 12:43:16 PM UTC 25 |
| Peak memory | 212828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276517408 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.4276517408 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3254714088 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 690151945 ps |
| CPU time | 280.09 seconds |
| Started | Feb 08 12:43:10 PM UTC 25 |
| Finished | Feb 08 12:47:54 PM UTC 25 |
| Peak memory | 384624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254714088 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3254714088 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.1502302668 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 447375952 ps |
| CPU time | 13.48 seconds |
| Started | Feb 08 12:42:42 PM UTC 25 |
| Finished | Feb 08 12:42:57 PM UTC 25 |
| Peak memory | 213508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502302668 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1502302668 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2655206449 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 126075710146 ps |
| CPU time | 3535.94 seconds |
| Started | Feb 08 12:43:33 PM UTC 25 |
| Finished | Feb 08 01:43:03 PM UTC 25 |
| Peak memory | 388532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655206449 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.2655206449 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3434052648 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 852679525 ps |
| CPU time | 52.22 seconds |
| Started | Feb 08 12:43:30 PM UTC 25 |
| Finished | Feb 08 12:44:24 PM UTC 25 |
| Peak memory | 284280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434052648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3434052648 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.4006920197 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 5561123348 ps |
| CPU time | 304.7 seconds |
| Started | Feb 08 12:42:45 PM UTC 25 |
| Finished | Feb 08 12:47:54 PM UTC 25 |
| Peak memory | 213680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006920197 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.4006920197 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3566301290 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 415589794 ps |
| CPU time | 28.17 seconds |
| Started | Feb 08 12:42:59 PM UTC 25 |
| Finished | Feb 08 12:43:28 PM UTC 25 |
| Peak memory | 312948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566301290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_throughput_w_partial_wr ite.3566301290 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2981907781 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 4852580132 ps |
| CPU time | 843.99 seconds |
| Started | Feb 08 12:45:19 PM UTC 25 |
| Finished | Feb 08 12:59:33 PM UTC 25 |
| Peak memory | 382840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981907781 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during_key_req.2981907781 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2304356271 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 35497531 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 12:45:45 PM UTC 25 |
| Finished | Feb 08 12:45:48 PM UTC 25 |
| Peak memory | 212960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304356271 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2304356271 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2416915682 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 5911605708 ps |
| CPU time | 35.47 seconds |
| Started | Feb 08 12:44:31 PM UTC 25 |
| Finished | Feb 08 12:45:08 PM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416915682 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2416915682 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1010583675 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 9807103119 ps |
| CPU time | 590.59 seconds |
| Started | Feb 08 12:45:19 PM UTC 25 |
| Finished | Feb 08 12:55:17 PM UTC 25 |
| Peak memory | 374620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010583675 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1010583675 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1758920779 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 420369012 ps |
| CPU time | 4.05 seconds |
| Started | Feb 08 12:45:13 PM UTC 25 |
| Finished | Feb 08 12:45:18 PM UTC 25 |
| Peak memory | 213620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758920779 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.1758920779 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.664179436 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 275016991 ps |
| CPU time | 16.11 seconds |
| Started | Feb 08 12:45:05 PM UTC 25 |
| Finished | Feb 08 12:45:23 PM UTC 25 |
| Peak memory | 269872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664179436 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_max_throughput.664179436 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.824400120 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 96528676 ps |
| CPU time | 6.2 seconds |
| Started | Feb 08 12:45:30 PM UTC 25 |
| Finished | Feb 08 12:45:38 PM UTC 25 |
| Peak memory | 223816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824400120 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.824400120 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1794097273 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1748110772 ps |
| CPU time | 16.03 seconds |
| Started | Feb 08 12:45:27 PM UTC 25 |
| Finished | Feb 08 12:45:45 PM UTC 25 |
| Peak memory | 223812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794097273 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.1794097273 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2910600230 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2672265175 ps |
| CPU time | 453.68 seconds |
| Started | Feb 08 12:44:25 PM UTC 25 |
| Finished | Feb 08 12:52:05 PM UTC 25 |
| Peak memory | 357988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910600230 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.2910600230 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3355955090 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 529083945 ps |
| CPU time | 19.77 seconds |
| Started | Feb 08 12:44:43 PM UTC 25 |
| Finished | Feb 08 12:45:04 PM UTC 25 |
| Peak memory | 270160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355955090 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.3355955090 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2909023745 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4609894482 ps |
| CPU time | 342.58 seconds |
| Started | Feb 08 12:44:48 PM UTC 25 |
| Finished | Feb 08 12:50:35 PM UTC 25 |
| Peak memory | 213776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909023745 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access_b2b.2909023745 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.495109244 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 49357167 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 12:45:24 PM UTC 25 |
| Finished | Feb 08 12:45:26 PM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495109244 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.495109244 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.402290921 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 28327450788 ps |
| CPU time | 870.28 seconds |
| Started | Feb 08 12:45:23 PM UTC 25 |
| Finished | Feb 08 01:00:03 PM UTC 25 |
| Peak memory | 376796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402290921 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.402290921 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.1596760670 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1186609282 ps |
| CPU time | 5.43 seconds |
| Started | Feb 08 12:44:23 PM UTC 25 |
| Finished | Feb 08 12:44:30 PM UTC 25 |
| Peak memory | 226876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596760670 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1596760670 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.488406909 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 36382359294 ps |
| CPU time | 2209.25 seconds |
| Started | Feb 08 12:45:40 PM UTC 25 |
| Finished | Feb 08 01:22:51 PM UTC 25 |
| Peak memory | 394640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488406909 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.488406909 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2410939311 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2815065131 ps |
| CPU time | 317.59 seconds |
| Started | Feb 08 12:44:37 PM UTC 25 |
| Finished | Feb 08 12:50:00 PM UTC 25 |
| Peak memory | 213680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410939311 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2410939311 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3506131146 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 200770874 ps |
| CPU time | 27.44 seconds |
| Started | Feb 08 12:45:10 PM UTC 25 |
| Finished | Feb 08 12:45:39 PM UTC 25 |
| Peak memory | 296752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506131146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_throughput_w_partial_wr ite.3506131146 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3516516554 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 12922282642 ps |
| CPU time | 1057.18 seconds |
| Started | Feb 08 11:41:16 AM UTC 25 |
| Finished | Feb 08 11:59:04 AM UTC 25 |
| Peak memory | 386952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516516554 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_key_req.3516516554 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3669895384 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 14686228 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 11:41:57 AM UTC 25 |
| Finished | Feb 08 11:42:00 AM UTC 25 |
| Peak memory | 212896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669895384 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3669895384 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2657760200 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3706964841 ps |
| CPU time | 74.35 seconds |
| Started | Feb 08 11:40:10 AM UTC 25 |
| Finished | Feb 08 11:41:27 AM UTC 25 |
| Peak memory | 213748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657760200 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2657760200 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.2794794524 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1692358437 ps |
| CPU time | 37.01 seconds |
| Started | Feb 08 11:41:23 AM UTC 25 |
| Finished | Feb 08 11:42:02 AM UTC 25 |
| Peak memory | 213636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794794524 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.2794794524 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.423570410 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1219310810 ps |
| CPU time | 10.89 seconds |
| Started | Feb 08 11:41:10 AM UTC 25 |
| Finished | Feb 08 11:41:22 AM UTC 25 |
| Peak memory | 213608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423570410 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.423570410 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1318156832 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 80337128 ps |
| CPU time | 21.5 seconds |
| Started | Feb 08 11:40:46 AM UTC 25 |
| Finished | Feb 08 11:41:09 AM UTC 25 |
| Peak memory | 288604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318156832 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max_throughput.1318156832 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2097001509 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 193781344 ps |
| CPU time | 4.4 seconds |
| Started | Feb 08 11:41:36 AM UTC 25 |
| Finished | Feb 08 11:41:42 AM UTC 25 |
| Peak memory | 223836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097001509 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.2097001509 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1868373646 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 345035071 ps |
| CPU time | 8.08 seconds |
| Started | Feb 08 11:41:32 AM UTC 25 |
| Finished | Feb 08 11:41:42 AM UTC 25 |
| Peak memory | 213828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868373646 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.1868373646 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2898873716 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 9495577062 ps |
| CPU time | 439.48 seconds |
| Started | Feb 08 11:40:06 AM UTC 25 |
| Finished | Feb 08 11:47:32 AM UTC 25 |
| Peak memory | 382508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898873716 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.2898873716 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3581354173 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 686104414 ps |
| CPU time | 75.78 seconds |
| Started | Feb 08 11:40:40 AM UTC 25 |
| Finished | Feb 08 11:41:59 AM UTC 25 |
| Peak memory | 359980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581354173 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.3581354173 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3984857710 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 70563524485 ps |
| CPU time | 283.76 seconds |
| Started | Feb 08 11:40:44 AM UTC 25 |
| Finished | Feb 08 11:45:32 AM UTC 25 |
| Peak memory | 213556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984857710 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access_b2b.3984857710 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.641638310 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 98552294 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 11:41:28 AM UTC 25 |
| Finished | Feb 08 11:41:31 AM UTC 25 |
| Peak memory | 212492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641638310 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.641638310 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1811371936 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 13044529275 ps |
| CPU time | 652.21 seconds |
| Started | Feb 08 11:41:26 AM UTC 25 |
| Finished | Feb 08 11:52:26 AM UTC 25 |
| Peak memory | 380620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811371936 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1811371936 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3452665456 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 105665822 ps |
| CPU time | 51.72 seconds |
| Started | Feb 08 11:40:05 AM UTC 25 |
| Finished | Feb 08 11:40:59 AM UTC 25 |
| Peak memory | 327512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452665456 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3452665456 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1582612166 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 35995773627 ps |
| CPU time | 1488.78 seconds |
| Started | Feb 08 11:41:43 AM UTC 25 |
| Finished | Feb 08 12:06:48 PM UTC 25 |
| Peak memory | 386472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582612166 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.1582612166 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.43230243 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4349187281 ps |
| CPU time | 256.96 seconds |
| Started | Feb 08 11:40:28 AM UTC 25 |
| Finished | Feb 08 11:44:50 AM UTC 25 |
| Peak memory | 213620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43230243 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.43230243 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1187978459 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 303025313 ps |
| CPU time | 76.6 seconds |
| Started | Feb 08 11:41:00 AM UTC 25 |
| Finished | Feb 08 11:42:18 AM UTC 25 |
| Peak memory | 380480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187978459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_throughput_w_partial_wri te.1187978459 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1089995200 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 65532552618 ps |
| CPU time | 1313.63 seconds |
| Started | Feb 08 11:42:45 AM UTC 25 |
| Finished | Feb 08 12:04:54 PM UTC 25 |
| Peak memory | 386684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089995200 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_key_req.1089995200 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3930662875 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 14514337 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 11:43:18 AM UTC 25 |
| Finished | Feb 08 11:43:20 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930662875 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3930662875 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.4062205602 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1970871521 ps |
| CPU time | 45.99 seconds |
| Started | Feb 08 11:42:03 AM UTC 25 |
| Finished | Feb 08 11:42:51 AM UTC 25 |
| Peak memory | 213468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062205602 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.4062205602 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.1735954414 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 12090962744 ps |
| CPU time | 365.01 seconds |
| Started | Feb 08 11:42:47 AM UTC 25 |
| Finished | Feb 08 11:48:57 AM UTC 25 |
| Peak memory | 366292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735954414 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.1735954414 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2874941910 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 765135334 ps |
| CPU time | 12.68 seconds |
| Started | Feb 08 11:42:32 AM UTC 25 |
| Finished | Feb 08 11:42:46 AM UTC 25 |
| Peak memory | 213560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874941910 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2874941910 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3052706157 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 119093767 ps |
| CPU time | 52.39 seconds |
| Started | Feb 08 11:42:27 AM UTC 25 |
| Finished | Feb 08 11:43:21 AM UTC 25 |
| Peak memory | 341660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052706157 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_throughput.3052706157 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.57600358 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 47097662 ps |
| CPU time | 3.9 seconds |
| Started | Feb 08 11:43:01 AM UTC 25 |
| Finished | Feb 08 11:43:07 AM UTC 25 |
| Peak memory | 223796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57600358 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.57600358 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.560082957 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4465949378 ps |
| CPU time | 9.34 seconds |
| Started | Feb 08 11:42:54 AM UTC 25 |
| Finished | Feb 08 11:43:05 AM UTC 25 |
| Peak memory | 223868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560082957 -assert nopostproc +UVM_T ESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.560082957 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3207274056 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 10103074895 ps |
| CPU time | 1221.21 seconds |
| Started | Feb 08 11:42:01 AM UTC 25 |
| Finished | Feb 08 12:02:35 PM UTC 25 |
| Peak memory | 386956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207274056 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.3207274056 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.342373124 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 298664185 ps |
| CPU time | 7.15 seconds |
| Started | Feb 08 11:42:19 AM UTC 25 |
| Finished | Feb 08 11:42:27 AM UTC 25 |
| Peak memory | 241296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342373124 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.342373124 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.149187131 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 9440065635 ps |
| CPU time | 259.02 seconds |
| Started | Feb 08 11:42:23 AM UTC 25 |
| Finished | Feb 08 11:46:46 AM UTC 25 |
| Peak memory | 213720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149187131 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access_b2b.149187131 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.118817499 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 79224719 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 11:42:51 AM UTC 25 |
| Finished | Feb 08 11:42:54 AM UTC 25 |
| Peak memory | 212496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118817499 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.118817499 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3601361990 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 9227552695 ps |
| CPU time | 450.94 seconds |
| Started | Feb 08 11:42:49 AM UTC 25 |
| Finished | Feb 08 11:50:26 AM UTC 25 |
| Peak memory | 353920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601361990 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3601361990 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3898319345 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 334409455 ps |
| CPU time | 21.28 seconds |
| Started | Feb 08 11:41:59 AM UTC 25 |
| Finished | Feb 08 11:42:22 AM UTC 25 |
| Peak memory | 282236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898319345 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3898319345 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2291977351 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 457058772507 ps |
| CPU time | 3491.2 seconds |
| Started | Feb 08 11:43:08 AM UTC 25 |
| Finished | Feb 08 12:41:53 PM UTC 25 |
| Peak memory | 388528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291977351 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.2291977351 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2642495905 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1554142239 ps |
| CPU time | 69.15 seconds |
| Started | Feb 08 11:43:06 AM UTC 25 |
| Finished | Feb 08 11:44:17 AM UTC 25 |
| Peak memory | 327372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642495905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2642495905 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1153967385 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 6608044131 ps |
| CPU time | 414.51 seconds |
| Started | Feb 08 11:42:09 AM UTC 25 |
| Finished | Feb 08 11:49:09 AM UTC 25 |
| Peak memory | 213724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153967385 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1153967385 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4060722567 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 132330661 ps |
| CPU time | 66.35 seconds |
| Started | Feb 08 11:42:28 AM UTC 25 |
| Finished | Feb 08 11:43:36 AM UTC 25 |
| Peak memory | 358028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060722567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_throughput_w_partial_wri te.4060722567 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2641411590 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 52540035893 ps |
| CPU time | 342.91 seconds |
| Started | Feb 08 11:43:57 AM UTC 25 |
| Finished | Feb 08 11:49:44 AM UTC 25 |
| Peak memory | 362104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641411590 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_key_req.2641411590 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.510289507 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 12992529 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 11:44:29 AM UTC 25 |
| Finished | Feb 08 11:44:32 AM UTC 25 |
| Peak memory | 212608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510289507 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.510289507 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2095663440 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 441758788 ps |
| CPU time | 29.41 seconds |
| Started | Feb 08 11:43:25 AM UTC 25 |
| Finished | Feb 08 11:43:56 AM UTC 25 |
| Peak memory | 213468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095663440 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.2095663440 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2281124 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 11865661294 ps |
| CPU time | 844.68 seconds |
| Started | Feb 08 11:44:05 AM UTC 25 |
| Finished | Feb 08 11:58:19 AM UTC 25 |
| Peak memory | 386608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281124 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2281124 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1877095070 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 471480058 ps |
| CPU time | 10.31 seconds |
| Started | Feb 08 11:43:51 AM UTC 25 |
| Finished | Feb 08 11:44:03 AM UTC 25 |
| Peak memory | 228196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877095070 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.1877095070 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3928416920 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 135989622 ps |
| CPU time | 83.75 seconds |
| Started | Feb 08 11:43:46 AM UTC 25 |
| Finished | Feb 08 11:45:12 AM UTC 25 |
| Peak memory | 368292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928416920 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max_throughput.3928416920 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3819838791 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 110048851 ps |
| CPU time | 4.57 seconds |
| Started | Feb 08 11:44:18 AM UTC 25 |
| Finished | Feb 08 11:44:24 AM UTC 25 |
| Peak memory | 223852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819838791 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.3819838791 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1675445614 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 894153721 ps |
| CPU time | 9.44 seconds |
| Started | Feb 08 11:44:17 AM UTC 25 |
| Finished | Feb 08 11:44:28 AM UTC 25 |
| Peak memory | 223748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675445614 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.1675445614 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.855872578 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 33320964866 ps |
| CPU time | 1401.06 seconds |
| Started | Feb 08 11:43:22 AM UTC 25 |
| Finished | Feb 08 12:06:58 PM UTC 25 |
| Peak memory | 384724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855872578 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.855872578 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1658582281 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 186863930 ps |
| CPU time | 50.17 seconds |
| Started | Feb 08 11:43:37 AM UTC 25 |
| Finished | Feb 08 11:44:29 AM UTC 25 |
| Peak memory | 353936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658582281 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.1658582281 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2595379636 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 16157538770 ps |
| CPU time | 285.09 seconds |
| Started | Feb 08 11:43:44 AM UTC 25 |
| Finished | Feb 08 11:48:33 AM UTC 25 |
| Peak memory | 213932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595379636 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access_b2b.2595379636 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2380617489 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 32555039 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 11:44:13 AM UTC 25 |
| Finished | Feb 08 11:44:16 AM UTC 25 |
| Peak memory | 212500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380617489 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2380617489 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1932813702 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 10608695240 ps |
| CPU time | 562 seconds |
| Started | Feb 08 11:44:12 AM UTC 25 |
| Finished | Feb 08 11:53:41 AM UTC 25 |
| Peak memory | 384908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932813702 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1932813702 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.4189025624 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 661765905 ps |
| CPU time | 21.52 seconds |
| Started | Feb 08 11:43:21 AM UTC 25 |
| Finished | Feb 08 11:43:44 AM UTC 25 |
| Peak memory | 213612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189025624 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.4189025624 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.475879863 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 66413966786 ps |
| CPU time | 646.95 seconds |
| Started | Feb 08 11:44:25 AM UTC 25 |
| Finished | Feb 08 11:55:20 AM UTC 25 |
| Peak memory | 386736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475879863 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.475879863 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4014100661 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 274589635 ps |
| CPU time | 9.68 seconds |
| Started | Feb 08 11:44:22 AM UTC 25 |
| Finished | Feb 08 11:44:33 AM UTC 25 |
| Peak memory | 223984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014100661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.4014100661 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1867388124 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 8268444743 ps |
| CPU time | 213.77 seconds |
| Started | Feb 08 11:43:35 AM UTC 25 |
| Finished | Feb 08 11:47:12 AM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867388124 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.1867388124 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.362157241 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 450284579 ps |
| CPU time | 23.18 seconds |
| Started | Feb 08 11:43:47 AM UTC 25 |
| Finished | Feb 08 11:44:12 AM UTC 25 |
| Peak memory | 314924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362157241 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.362157241 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3489490217 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 9012499445 ps |
| CPU time | 892.79 seconds |
| Started | Feb 08 11:45:13 AM UTC 25 |
| Finished | Feb 08 12:00:16 PM UTC 25 |
| Peak memory | 384640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489490217 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_key_req.3489490217 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.54606371 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 19900407 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 11:45:42 AM UTC 25 |
| Finished | Feb 08 11:45:44 AM UTC 25 |
| Peak memory | 212612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54606371 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.54606371 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.911889546 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1660258090 ps |
| CPU time | 33.83 seconds |
| Started | Feb 08 11:44:34 AM UTC 25 |
| Finished | Feb 08 11:45:10 AM UTC 25 |
| Peak memory | 213472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911889546 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.911889546 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1300555938 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3326032160 ps |
| CPU time | 371.05 seconds |
| Started | Feb 08 11:45:17 AM UTC 25 |
| Finished | Feb 08 11:51:33 AM UTC 25 |
| Peak memory | 360216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300555938 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1300555938 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3068416226 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2307187655 ps |
| CPU time | 8.47 seconds |
| Started | Feb 08 11:45:12 AM UTC 25 |
| Finished | Feb 08 11:45:22 AM UTC 25 |
| Peak memory | 213640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068416226 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.3068416226 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3546240823 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 420131969 ps |
| CPU time | 96.6 seconds |
| Started | Feb 08 11:45:06 AM UTC 25 |
| Finished | Feb 08 11:46:45 AM UTC 25 |
| Peak memory | 372380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546240823 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max_throughput.3546240823 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1023650836 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 376907346 ps |
| CPU time | 6.87 seconds |
| Started | Feb 08 11:45:32 AM UTC 25 |
| Finished | Feb 08 11:45:41 AM UTC 25 |
| Peak memory | 223980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023650836 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.1023650836 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3078844271 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 357681437 ps |
| CPU time | 7.62 seconds |
| Started | Feb 08 11:45:26 AM UTC 25 |
| Finished | Feb 08 11:45:35 AM UTC 25 |
| Peak memory | 223748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078844271 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3078844271 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2161259565 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 14614714064 ps |
| CPU time | 994.91 seconds |
| Started | Feb 08 11:44:33 AM UTC 25 |
| Finished | Feb 08 12:01:19 PM UTC 25 |
| Peak memory | 386700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161259565 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.2161259565 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2032277054 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 182942377 ps |
| CPU time | 12.25 seconds |
| Started | Feb 08 11:44:51 AM UTC 25 |
| Finished | Feb 08 11:45:05 AM UTC 25 |
| Peak memory | 213780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032277054 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.2032277054 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4254705199 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 9095078123 ps |
| CPU time | 187.5 seconds |
| Started | Feb 08 11:44:56 AM UTC 25 |
| Finished | Feb 08 11:48:07 AM UTC 25 |
| Peak memory | 213684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254705199 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access_b2b.4254705199 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2533466344 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 28957667 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 11:45:23 AM UTC 25 |
| Finished | Feb 08 11:45:26 AM UTC 25 |
| Peak memory | 212968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533466344 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2533466344 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1684354893 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 24353053239 ps |
| CPU time | 787.29 seconds |
| Started | Feb 08 11:45:21 AM UTC 25 |
| Finished | Feb 08 11:58:37 AM UTC 25 |
| Peak memory | 376460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684354893 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1684354893 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3165500875 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3736087269 ps |
| CPU time | 22.84 seconds |
| Started | Feb 08 11:44:30 AM UTC 25 |
| Finished | Feb 08 11:44:55 AM UTC 25 |
| Peak memory | 213644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165500875 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3165500875 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.478238729 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 40287934371 ps |
| CPU time | 2927.01 seconds |
| Started | Feb 08 11:45:38 AM UTC 25 |
| Finished | Feb 08 12:34:54 PM UTC 25 |
| Peak memory | 388828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478238729 -assert no postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.478238729 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3332744241 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 368728412 ps |
| CPU time | 15.1 seconds |
| Started | Feb 08 11:45:36 AM UTC 25 |
| Finished | Feb 08 11:45:53 AM UTC 25 |
| Peak memory | 225908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332744241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3332744241 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2170413628 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2924261710 ps |
| CPU time | 326.47 seconds |
| Started | Feb 08 11:44:35 AM UTC 25 |
| Finished | Feb 08 11:50:07 AM UTC 25 |
| Peak memory | 213852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170413628 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.2170413628 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2298266574 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 155231329 ps |
| CPU time | 66.77 seconds |
| Started | Feb 08 11:45:11 AM UTC 25 |
| Finished | Feb 08 11:46:19 AM UTC 25 |
| Peak memory | 380564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298266574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_throughput_w_partial_wri te.2298266574 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.409281974 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5092651030 ps |
| CPU time | 960.85 seconds |
| Started | Feb 08 11:46:57 AM UTC 25 |
| Finished | Feb 08 12:03:08 PM UTC 25 |
| Peak memory | 384720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409281974 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_key_req.409281974 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1413117401 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 67312183 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 11:47:24 AM UTC 25 |
| Finished | Feb 08 11:47:26 AM UTC 25 |
| Peak memory | 212896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413117401 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1413117401 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.144411144 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5260138307 ps |
| CPU time | 88.47 seconds |
| Started | Feb 08 11:45:50 AM UTC 25 |
| Finished | Feb 08 11:47:21 AM UTC 25 |
| Peak memory | 213756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144411144 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.144411144 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1396619905 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 15239537139 ps |
| CPU time | 909.39 seconds |
| Started | Feb 08 11:47:07 AM UTC 25 |
| Finished | Feb 08 12:02:27 PM UTC 25 |
| Peak memory | 386668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396619905 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.1396619905 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2168345980 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1840859123 ps |
| CPU time | 9.08 seconds |
| Started | Feb 08 11:46:46 AM UTC 25 |
| Finished | Feb 08 11:46:57 AM UTC 25 |
| Peak memory | 213560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168345980 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2168345980 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1913842309 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 750605623 ps |
| CPU time | 70.87 seconds |
| Started | Feb 08 11:46:45 AM UTC 25 |
| Finished | Feb 08 11:47:58 AM UTC 25 |
| Peak memory | 343616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913842309 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max_throughput.1913842309 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2500158636 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 633237744 ps |
| CPU time | 8.17 seconds |
| Started | Feb 08 11:47:18 AM UTC 25 |
| Finished | Feb 08 11:47:27 AM UTC 25 |
| Peak memory | 224000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500158636 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.2500158636 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1214852513 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 754320035 ps |
| CPU time | 6.47 seconds |
| Started | Feb 08 11:47:16 AM UTC 25 |
| Finished | Feb 08 11:47:24 AM UTC 25 |
| Peak memory | 223816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214852513 -assert nopostproc +UVM_ TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1214852513 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.839432264 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 52172896315 ps |
| CPU time | 1421.94 seconds |
| Started | Feb 08 11:45:45 AM UTC 25 |
| Finished | Feb 08 12:09:41 PM UTC 25 |
| Peak memory | 384620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839432264 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.839432264 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2134333510 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 294239122 ps |
| CPU time | 18.8 seconds |
| Started | Feb 08 11:46:20 AM UTC 25 |
| Finished | Feb 08 11:46:40 AM UTC 25 |
| Peak memory | 265848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134333510 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.2134333510 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.65073485 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3345178926 ps |
| CPU time | 247.94 seconds |
| Started | Feb 08 11:46:41 AM UTC 25 |
| Finished | Feb 08 11:50:53 AM UTC 25 |
| Peak memory | 213904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65073485 -assert nopostpro c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access_b2b.65073485 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1914322935 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 85347722 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 11:47:13 AM UTC 25 |
| Finished | Feb 08 11:47:15 AM UTC 25 |
| Peak memory | 212500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914322935 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1914322935 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2739407674 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4634720739 ps |
| CPU time | 1438.37 seconds |
| Started | Feb 08 11:47:08 AM UTC 25 |
| Finished | Feb 08 12:11:21 PM UTC 25 |
| Peak memory | 387188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739407674 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr am_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2739407674 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1089411772 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 67279769 ps |
| CPU time | 2.74 seconds |
| Started | Feb 08 11:45:45 AM UTC 25 |
| Finished | Feb 08 11:45:49 AM UTC 25 |
| Peak memory | 213768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089411772 -assert nopostproc +UVM_TESTNAME=sram_ ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra m_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1089411772 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1507275582 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 65870240172 ps |
| CPU time | 1823.01 seconds |
| Started | Feb 08 11:47:22 AM UTC 25 |
| Finished | Feb 08 12:18:04 PM UTC 25 |
| Peak memory | 388704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507275582 -assert n opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.1507275582 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4294248486 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1016872965 ps |
| CPU time | 39.96 seconds |
| Started | Feb 08 11:47:19 AM UTC 25 |
| Finished | Feb 08 11:48:01 AM UTC 25 |
| Peak memory | 255596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sra m_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294248486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.4294248486 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3486837416 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1560603174 ps |
| CPU time | 200.34 seconds |
| Started | Feb 08 11:45:54 AM UTC 25 |
| Finished | Feb 08 11:49:18 AM UTC 25 |
| Peak memory | 213604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486837416 -assert nopostproc +UVM _TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.3486837416 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1018533294 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 466911525 ps |
| CPU time | 30.19 seconds |
| Started | Feb 08 11:46:46 AM UTC 25 |
| Finished | Feb 08 11:47:18 AM UTC 25 |
| Peak memory | 296528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018533294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_throughput_w_partial_wri te.1018533294 |
| Directory | /workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |