| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.3657952214 |
|
|
Oct 15 04:17:28 AM UTC 24 |
Oct 15 04:17:38 AM UTC 24 |
142294312 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_readback_err.1744069056 |
|
|
Oct 15 04:17:37 AM UTC 24 |
Oct 15 04:17:39 AM UTC 24 |
61147535 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1038081943 |
|
|
Oct 15 04:04:19 AM UTC 24 |
Oct 15 04:18:03 AM UTC 24 |
13033968362 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1300755724 |
|
|
Oct 15 04:18:04 AM UTC 24 |
Oct 15 04:18:05 AM UTC 24 |
15853279 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2689181163 |
|
|
Oct 15 04:03:10 AM UTC 24 |
Oct 15 04:18:07 AM UTC 24 |
19847560381 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.50299163 |
|
|
Oct 15 04:05:58 AM UTC 24 |
Oct 15 04:18:12 AM UTC 24 |
21708847018 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.4259643854 |
|
|
Oct 15 04:18:07 AM UTC 24 |
Oct 15 04:18:14 AM UTC 24 |
180761652 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2866461990 |
|
|
Oct 15 04:11:56 AM UTC 24 |
Oct 15 04:18:17 AM UTC 24 |
13868084976 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1390404044 |
|
|
Oct 15 04:13:02 AM UTC 24 |
Oct 15 04:18:23 AM UTC 24 |
82298750995 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3646855468 |
|
|
Oct 15 04:01:30 AM UTC 24 |
Oct 15 04:18:36 AM UTC 24 |
15454018355 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1860752541 |
|
|
Oct 15 04:18:18 AM UTC 24 |
Oct 15 04:18:38 AM UTC 24 |
1457434275 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2514346539 |
|
|
Oct 15 04:06:29 AM UTC 24 |
Oct 15 04:18:40 AM UTC 24 |
45057159287 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3839896858 |
|
|
Oct 15 04:18:37 AM UTC 24 |
Oct 15 04:18:42 AM UTC 24 |
49485753 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4180266437 |
|
|
Oct 15 04:18:40 AM UTC 24 |
Oct 15 04:18:45 AM UTC 24 |
1092673093 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1448708801 |
|
|
Oct 15 04:16:57 AM UTC 24 |
Oct 15 04:18:46 AM UTC 24 |
518239826 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2664971566 |
|
|
Oct 15 04:18:48 AM UTC 24 |
Oct 15 04:18:50 AM UTC 24 |
201117041 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1998107919 |
|
|
Oct 15 03:58:17 AM UTC 24 |
Oct 15 04:18:50 AM UTC 24 |
3400133548 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3116533797 |
|
|
Oct 15 04:18:51 AM UTC 24 |
Oct 15 04:18:56 AM UTC 24 |
94389868 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_readback_err.126058307 |
|
|
Oct 15 04:18:57 AM UTC 24 |
Oct 15 04:19:00 AM UTC 24 |
30402705 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1361215255 |
|
|
Oct 15 04:18:51 AM UTC 24 |
Oct 15 04:19:00 AM UTC 24 |
93685697 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3851361484 |
|
|
Oct 15 04:19:00 AM UTC 24 |
Oct 15 04:19:13 AM UTC 24 |
2713669979 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1820137598 |
|
|
Oct 15 04:19:14 AM UTC 24 |
Oct 15 04:19:16 AM UTC 24 |
12521423 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2783484895 |
|
|
Oct 15 04:18:39 AM UTC 24 |
Oct 15 04:19:29 AM UTC 24 |
438409223 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.4092111929 |
|
|
Oct 15 04:19:17 AM UTC 24 |
Oct 15 04:19:33 AM UTC 24 |
372702504 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2690698338 |
|
|
Oct 15 04:17:38 AM UTC 24 |
Oct 15 04:19:43 AM UTC 24 |
1319212672 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1025634187 |
|
|
Oct 15 04:19:34 AM UTC 24 |
Oct 15 04:20:38 AM UTC 24 |
3496181154 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2700771676 |
|
|
Oct 15 04:20:39 AM UTC 24 |
Oct 15 04:20:43 AM UTC 24 |
87942332 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2072610938 |
|
|
Oct 15 04:14:46 AM UTC 24 |
Oct 15 04:20:48 AM UTC 24 |
12494342818 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1982084335 |
|
|
Oct 15 03:50:34 AM UTC 24 |
Oct 15 04:20:55 AM UTC 24 |
33474090186 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1127500256 |
|
|
Oct 15 04:20:56 AM UTC 24 |
Oct 15 04:20:58 AM UTC 24 |
35071508 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.976355606 |
|
|
Oct 15 04:07:27 AM UTC 24 |
Oct 15 04:21:04 AM UTC 24 |
3977234682 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1882181411 |
|
|
Oct 15 04:16:28 AM UTC 24 |
Oct 15 04:21:06 AM UTC 24 |
8530573519 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2423618432 |
|
|
Oct 15 04:20:59 AM UTC 24 |
Oct 15 04:21:07 AM UTC 24 |
1358495331 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1831847223 |
|
|
Oct 15 04:11:03 AM UTC 24 |
Oct 15 04:21:17 AM UTC 24 |
60712986054 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3320803892 |
|
|
Oct 15 04:21:18 AM UTC 24 |
Oct 15 04:21:20 AM UTC 24 |
48975989 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2822493793 |
|
|
Oct 15 04:19:30 AM UTC 24 |
Oct 15 04:21:27 AM UTC 24 |
6647243645 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1294986071 |
|
|
Oct 15 04:21:27 AM UTC 24 |
Oct 15 04:21:33 AM UTC 24 |
379158820 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_readback_err.603902844 |
|
|
Oct 15 04:21:33 AM UTC 24 |
Oct 15 04:21:36 AM UTC 24 |
135796672 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3345938850 |
|
|
Oct 15 04:21:21 AM UTC 24 |
Oct 15 04:21:37 AM UTC 24 |
722243006 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3392759530 |
|
|
Oct 15 04:21:37 AM UTC 24 |
Oct 15 04:21:50 AM UTC 24 |
295151172 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2302942689 |
|
|
Oct 15 04:21:50 AM UTC 24 |
Oct 15 04:21:52 AM UTC 24 |
16938145 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.4200092673 |
|
|
Oct 15 03:50:31 AM UTC 24 |
Oct 15 04:21:54 AM UTC 24 |
192181972374 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3033730896 |
|
|
Oct 15 04:21:53 AM UTC 24 |
Oct 15 04:21:56 AM UTC 24 |
176397353 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3580268423 |
|
|
Oct 15 04:20:49 AM UTC 24 |
Oct 15 04:22:11 AM UTC 24 |
117556328 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.497901605 |
|
|
Oct 15 03:52:08 AM UTC 24 |
Oct 15 04:22:19 AM UTC 24 |
55543196058 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.4105894849 |
|
|
Oct 15 04:22:20 AM UTC 24 |
Oct 15 04:22:26 AM UTC 24 |
240309330 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.2385763474 |
|
|
Oct 15 04:05:54 AM UTC 24 |
Oct 15 04:22:46 AM UTC 24 |
4066970103 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3781596263 |
|
|
Oct 15 04:21:57 AM UTC 24 |
Oct 15 04:23:00 AM UTC 24 |
3236614645 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1474059459 |
|
|
Oct 15 04:22:47 AM UTC 24 |
Oct 15 04:23:09 AM UTC 24 |
94879062 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.729998129 |
|
|
Oct 15 04:23:10 AM UTC 24 |
Oct 15 04:23:18 AM UTC 24 |
1726419479 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2733143210 |
|
|
Oct 15 04:23:02 AM UTC 24 |
Oct 15 04:23:19 AM UTC 24 |
219816900 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.731233371 |
|
|
Oct 15 04:07:48 AM UTC 24 |
Oct 15 04:23:20 AM UTC 24 |
2518987438 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.501928796 |
|
|
Oct 15 04:18:15 AM UTC 24 |
Oct 15 04:23:21 AM UTC 24 |
2932040036 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.831278912 |
|
|
Oct 15 04:23:23 AM UTC 24 |
Oct 15 04:23:25 AM UTC 24 |
307469935 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.4205781818 |
|
|
Oct 15 04:23:26 AM UTC 24 |
Oct 15 04:23:44 AM UTC 24 |
2713330435 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_readback_err.4001830394 |
|
|
Oct 15 04:23:47 AM UTC 24 |
Oct 15 04:23:49 AM UTC 24 |
90648986 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.1661561426 |
|
|
Oct 15 04:23:45 AM UTC 24 |
Oct 15 04:23:52 AM UTC 24 |
67569721 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1744076103 |
|
|
Oct 15 04:11:22 AM UTC 24 |
Oct 15 04:23:56 AM UTC 24 |
5688170537 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1110369199 |
|
|
Oct 15 04:23:57 AM UTC 24 |
Oct 15 04:24:00 AM UTC 24 |
15155528 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3855090184 |
|
|
Oct 15 04:12:01 AM UTC 24 |
Oct 15 04:24:05 AM UTC 24 |
8898756838 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1954398923 |
|
|
Oct 15 04:04:32 AM UTC 24 |
Oct 15 04:24:35 AM UTC 24 |
6194609957 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.531444208 |
|
|
Oct 15 03:24:57 AM UTC 24 |
Oct 15 04:24:37 AM UTC 24 |
188113252640 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.1194749272 |
|
|
Oct 15 04:17:16 AM UTC 24 |
Oct 15 04:24:41 AM UTC 24 |
15725106067 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1015862077 |
|
|
Oct 15 04:22:12 AM UTC 24 |
Oct 15 04:24:49 AM UTC 24 |
5348131655 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2389363891 |
|
|
Oct 15 04:23:50 AM UTC 24 |
Oct 15 04:24:55 AM UTC 24 |
587557106 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.3227067107 |
|
|
Oct 15 04:24:00 AM UTC 24 |
Oct 15 04:24:57 AM UTC 24 |
222073098 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3439123100 |
|
|
Oct 15 04:18:24 AM UTC 24 |
Oct 15 04:25:08 AM UTC 24 |
50614770381 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.25851586 |
|
|
Oct 15 04:24:42 AM UTC 24 |
Oct 15 04:25:12 AM UTC 24 |
4144106289 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.3599579202 |
|
|
Oct 15 04:25:09 AM UTC 24 |
Oct 15 04:25:22 AM UTC 24 |
4168391493 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.2539153726 |
|
|
Oct 15 04:09:58 AM UTC 24 |
Oct 15 04:25:25 AM UTC 24 |
12116671099 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2465510705 |
|
|
Oct 15 04:21:55 AM UTC 24 |
Oct 15 04:25:40 AM UTC 24 |
4471253393 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3609112663 |
|
|
Oct 15 04:25:41 AM UTC 24 |
Oct 15 04:25:44 AM UTC 24 |
27518807 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1714875078 |
|
|
Oct 15 04:24:58 AM UTC 24 |
Oct 15 04:25:45 AM UTC 24 |
139947449 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2039680622 |
|
|
Oct 15 04:15:28 AM UTC 24 |
Oct 15 04:25:45 AM UTC 24 |
13096191798 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_readback_err.2942212666 |
|
|
Oct 15 04:25:47 AM UTC 24 |
Oct 15 04:25:49 AM UTC 24 |
52463251 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.582995250 |
|
|
Oct 15 04:25:44 AM UTC 24 |
Oct 15 04:25:53 AM UTC 24 |
881347037 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1353573104 |
|
|
Oct 15 04:25:46 AM UTC 24 |
Oct 15 04:25:54 AM UTC 24 |
341154730 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3437977092 |
|
|
Oct 15 04:25:55 AM UTC 24 |
Oct 15 04:25:57 AM UTC 24 |
33609699 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3803378627 |
|
|
Oct 15 04:24:36 AM UTC 24 |
Oct 15 04:26:07 AM UTC 24 |
3689328619 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3932197261 |
|
|
Oct 15 04:25:58 AM UTC 24 |
Oct 15 04:26:14 AM UTC 24 |
1476925751 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2261628187 |
|
|
Oct 15 04:24:56 AM UTC 24 |
Oct 15 04:26:24 AM UTC 24 |
507872936 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3181285801 |
|
|
Oct 15 04:03:39 AM UTC 24 |
Oct 15 04:26:37 AM UTC 24 |
87767929042 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1699487872 |
|
|
Oct 15 04:17:09 AM UTC 24 |
Oct 15 04:26:39 AM UTC 24 |
25966104073 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1578417746 |
|
|
Oct 15 04:19:44 AM UTC 24 |
Oct 15 04:26:44 AM UTC 24 |
14948772191 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.730288797 |
|
|
Oct 15 04:04:24 AM UTC 24 |
Oct 15 04:26:50 AM UTC 24 |
176163829208 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.914203204 |
|
|
Oct 15 04:13:55 AM UTC 24 |
Oct 15 04:26:56 AM UTC 24 |
9355051712 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2515753028 |
|
|
Oct 15 04:26:37 AM UTC 24 |
Oct 15 04:27:01 AM UTC 24 |
302327395 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.658821041 |
|
|
Oct 15 04:26:44 AM UTC 24 |
Oct 15 04:27:05 AM UTC 24 |
145575349 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3950670512 |
|
|
Oct 15 04:26:57 AM UTC 24 |
Oct 15 04:27:09 AM UTC 24 |
656988762 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.1791150241 |
|
|
Oct 15 04:26:16 AM UTC 24 |
Oct 15 04:27:12 AM UTC 24 |
816021104 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1234400191 |
|
|
Oct 15 04:25:50 AM UTC 24 |
Oct 15 04:27:12 AM UTC 24 |
276294618 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3200260015 |
|
|
Oct 15 04:20:44 AM UTC 24 |
Oct 15 04:27:15 AM UTC 24 |
4406937644 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2119348519 |
|
|
Oct 15 04:27:13 AM UTC 24 |
Oct 15 04:27:15 AM UTC 24 |
31035800 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_readback_err.2333966900 |
|
|
Oct 15 04:27:16 AM UTC 24 |
Oct 15 04:27:19 AM UTC 24 |
34232177 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1430190894 |
|
|
Oct 15 04:27:13 AM UTC 24 |
Oct 15 04:27:19 AM UTC 24 |
163190883 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3478844752 |
|
|
Oct 15 04:27:16 AM UTC 24 |
Oct 15 04:27:23 AM UTC 24 |
71220880 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2291989869 |
|
|
Oct 15 04:13:57 AM UTC 24 |
Oct 15 04:27:23 AM UTC 24 |
1764104050 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3312886601 |
|
|
Oct 15 04:27:24 AM UTC 24 |
Oct 15 04:27:26 AM UTC 24 |
22276621 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.2973958497 |
|
|
Oct 15 04:27:24 AM UTC 24 |
Oct 15 04:27:29 AM UTC 24 |
89963951 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1231738459 |
|
|
Oct 15 04:26:51 AM UTC 24 |
Oct 15 04:27:34 AM UTC 24 |
1041037988 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4287082617 |
|
|
Oct 15 04:10:33 AM UTC 24 |
Oct 15 04:27:36 AM UTC 24 |
5550346109 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2334693804 |
|
|
Oct 15 04:09:53 AM UTC 24 |
Oct 15 04:27:52 AM UTC 24 |
3041332808 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.4034582883 |
|
|
Oct 15 04:27:36 AM UTC 24 |
Oct 15 04:27:56 AM UTC 24 |
294326374 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.890097883 |
|
|
Oct 15 04:18:45 AM UTC 24 |
Oct 15 04:27:59 AM UTC 24 |
19854367108 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.987455226 |
|
|
Oct 15 03:49:07 AM UTC 24 |
Oct 15 04:28:02 AM UTC 24 |
166099626812 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3274189381 |
|
|
Oct 15 04:16:48 AM UTC 24 |
Oct 15 04:28:03 AM UTC 24 |
51931131114 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2734239741 |
|
|
Oct 15 04:28:00 AM UTC 24 |
Oct 15 04:28:04 AM UTC 24 |
91443445 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3659005627 |
|
|
Oct 15 04:28:03 AM UTC 24 |
Oct 15 04:28:13 AM UTC 24 |
3047789133 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.2272857312 |
|
|
Oct 15 04:04:40 AM UTC 24 |
Oct 15 04:28:32 AM UTC 24 |
33822416731 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2384358684 |
|
|
Oct 15 04:28:34 AM UTC 24 |
Oct 15 04:28:36 AM UTC 24 |
82605599 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3655139152 |
|
|
Oct 15 04:18:08 AM UTC 24 |
Oct 15 04:28:38 AM UTC 24 |
13599368843 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2078484585 |
|
|
Oct 15 04:27:57 AM UTC 24 |
Oct 15 04:28:45 AM UTC 24 |
430295701 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.791151367 |
|
|
Oct 15 04:28:37 AM UTC 24 |
Oct 15 04:28:46 AM UTC 24 |
144213912 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2013785652 |
|
|
Oct 15 04:28:39 AM UTC 24 |
Oct 15 04:28:47 AM UTC 24 |
158392838 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_readback_err.526165158 |
|
|
Oct 15 04:28:45 AM UTC 24 |
Oct 15 04:28:48 AM UTC 24 |
39067891 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1265874166 |
|
|
Oct 15 04:28:49 AM UTC 24 |
Oct 15 04:28:51 AM UTC 24 |
24073327 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.3810526014 |
|
|
Oct 15 04:27:30 AM UTC 24 |
Oct 15 04:28:59 AM UTC 24 |
21575777791 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.1744264507 |
|
|
Oct 15 04:28:52 AM UTC 24 |
Oct 15 04:29:10 AM UTC 24 |
977448348 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3190430279 |
|
|
Oct 15 04:27:20 AM UTC 24 |
Oct 15 04:29:11 AM UTC 24 |
6111605084 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2363863501 |
|
|
Oct 15 04:22:27 AM UTC 24 |
Oct 15 04:29:17 AM UTC 24 |
49103667705 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2209525261 |
|
|
Oct 15 04:29:19 AM UTC 24 |
Oct 15 04:29:21 AM UTC 24 |
54619272 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3112906027 |
|
|
Oct 15 04:24:38 AM UTC 24 |
Oct 15 04:29:35 AM UTC 24 |
2682432418 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2642257956 |
|
|
Oct 15 04:14:32 AM UTC 24 |
Oct 15 04:29:41 AM UTC 24 |
13524857589 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2304441462 |
|
|
Oct 15 04:18:43 AM UTC 24 |
Oct 15 04:30:03 AM UTC 24 |
13332054934 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1100056600 |
|
|
Oct 15 04:30:05 AM UTC 24 |
Oct 15 04:30:14 AM UTC 24 |
551397550 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.1345731256 |
|
|
Oct 15 04:29:11 AM UTC 24 |
Oct 15 04:30:25 AM UTC 24 |
3111146009 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.942459432 |
|
|
Oct 15 04:28:47 AM UTC 24 |
Oct 15 04:30:27 AM UTC 24 |
4401271315 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1156312996 |
|
|
Oct 15 04:29:36 AM UTC 24 |
Oct 15 04:30:28 AM UTC 24 |
104291070 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1534402832 |
|
|
Oct 15 04:30:29 AM UTC 24 |
Oct 15 04:30:31 AM UTC 24 |
35136670 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.4289900637 |
|
|
Oct 15 04:26:25 AM UTC 24 |
Oct 15 04:30:37 AM UTC 24 |
4497169561 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.570132383 |
|
|
Oct 15 04:26:40 AM UTC 24 |
Oct 15 04:30:41 AM UTC 24 |
3464835583 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3922732438 |
|
|
Oct 15 04:30:32 AM UTC 24 |
Oct 15 04:30:42 AM UTC 24 |
1376934852 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_readback_err.3031392947 |
|
|
Oct 15 04:30:43 AM UTC 24 |
Oct 15 04:30:45 AM UTC 24 |
28368090 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2647290162 |
|
|
Oct 15 04:30:38 AM UTC 24 |
Oct 15 04:30:47 AM UTC 24 |
158089392 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3125168256 |
|
|
Oct 15 04:30:48 AM UTC 24 |
Oct 15 04:30:50 AM UTC 24 |
55051190 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3217922419 |
|
|
Oct 15 04:29:41 AM UTC 24 |
Oct 15 04:31:07 AM UTC 24 |
584933861 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1206204127 |
|
|
Oct 15 04:24:49 AM UTC 24 |
Oct 15 04:31:59 AM UTC 24 |
23723777944 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.3850950549 |
|
|
Oct 15 04:21:08 AM UTC 24 |
Oct 15 04:32:17 AM UTC 24 |
50458728689 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.2635347292 |
|
|
Oct 15 04:30:26 AM UTC 24 |
Oct 15 04:32:44 AM UTC 24 |
1701436718 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1758173609 |
|
|
Oct 15 04:27:35 AM UTC 24 |
Oct 15 04:32:49 AM UTC 24 |
3110862070 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2014869792 |
|
|
Oct 15 04:27:53 AM UTC 24 |
Oct 15 04:32:55 AM UTC 24 |
12891325573 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.57819649 |
|
|
Oct 15 04:30:43 AM UTC 24 |
Oct 15 04:33:03 AM UTC 24 |
2455059575 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.4081077664 |
|
|
Oct 15 04:16:14 AM UTC 24 |
Oct 15 04:33:11 AM UTC 24 |
21406531461 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.1348011668 |
|
|
Oct 15 04:15:30 AM UTC 24 |
Oct 15 04:33:14 AM UTC 24 |
29193957324 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.912275879 |
|
|
Oct 15 04:29:11 AM UTC 24 |
Oct 15 04:33:25 AM UTC 24 |
9803841377 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2747767625 |
|
|
Oct 15 04:30:15 AM UTC 24 |
Oct 15 04:33:27 AM UTC 24 |
5644646981 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.2072178714 |
|
|
Oct 15 04:21:07 AM UTC 24 |
Oct 15 04:34:22 AM UTC 24 |
17077134352 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1258208548 |
|
|
Oct 15 04:29:22 AM UTC 24 |
Oct 15 04:34:39 AM UTC 24 |
16402800175 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2411065348 |
|
|
Oct 15 04:24:06 AM UTC 24 |
Oct 15 04:35:43 AM UTC 24 |
19300665580 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.691462198 |
|
|
Oct 15 04:26:08 AM UTC 24 |
Oct 15 04:36:06 AM UTC 24 |
8477756580 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.4269354226 |
|
|
Oct 15 04:30:29 AM UTC 24 |
Oct 15 04:36:09 AM UTC 24 |
4473810349 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3845629651 |
|
|
Oct 15 04:13:47 AM UTC 24 |
Oct 15 04:36:10 AM UTC 24 |
14846301256 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.439895184 |
|
|
Oct 15 04:27:28 AM UTC 24 |
Oct 15 04:36:27 AM UTC 24 |
17799024696 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2497376819 |
|
|
Oct 15 04:16:01 AM UTC 24 |
Oct 15 04:36:32 AM UTC 24 |
103663498916 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2277678907 |
|
|
Oct 15 04:21:04 AM UTC 24 |
Oct 15 04:36:52 AM UTC 24 |
11807715687 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.1983686230 |
|
|
Oct 15 04:25:26 AM UTC 24 |
Oct 15 04:36:55 AM UTC 24 |
10344271825 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.4248943647 |
|
|
Oct 15 04:23:19 AM UTC 24 |
Oct 15 04:36:58 AM UTC 24 |
5717594083 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3701228290 |
|
|
Oct 15 04:27:02 AM UTC 24 |
Oct 15 04:37:04 AM UTC 24 |
9427769299 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3900257450 |
|
|
Oct 15 04:17:23 AM UTC 24 |
Oct 15 04:37:05 AM UTC 24 |
19926536258 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.4000726265 |
|
|
Oct 15 04:27:10 AM UTC 24 |
Oct 15 04:37:46 AM UTC 24 |
9575719705 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.1873577741 |
|
|
Oct 15 04:27:06 AM UTC 24 |
Oct 15 04:38:31 AM UTC 24 |
10824991548 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1970704544 |
|
|
Oct 15 04:28:59 AM UTC 24 |
Oct 15 04:40:04 AM UTC 24 |
3622692065 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1335204870 |
|
|
Oct 15 04:18:46 AM UTC 24 |
Oct 15 04:40:17 AM UTC 24 |
5567433547 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.3981266605 |
|
|
Oct 15 04:15:30 AM UTC 24 |
Oct 15 04:40:57 AM UTC 24 |
4962052244 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1599000303 |
|
|
Oct 15 04:25:24 AM UTC 24 |
Oct 15 04:42:08 AM UTC 24 |
22220280405 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.880018807 |
|
|
Oct 15 04:11:34 AM UTC 24 |
Oct 15 04:42:11 AM UTC 24 |
17089074144 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.4102461012 |
|
|
Oct 15 04:23:20 AM UTC 24 |
Oct 15 04:42:21 AM UTC 24 |
26816161156 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1620059346 |
|
|
Oct 15 04:28:05 AM UTC 24 |
Oct 15 04:43:00 AM UTC 24 |
173268329271 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.6612200 |
|
|
Oct 15 04:08:44 AM UTC 24 |
Oct 15 04:43:03 AM UTC 24 |
122536077971 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.2266439284 |
|
|
Oct 15 04:25:12 AM UTC 24 |
Oct 15 04:43:15 AM UTC 24 |
8259464871 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2563389619 |
|
|
Oct 15 04:27:20 AM UTC 24 |
Oct 15 04:43:16 AM UTC 24 |
19438435433 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1832491479 |
|
|
Oct 15 03:53:58 AM UTC 24 |
Oct 15 04:44:27 AM UTC 24 |
24820412242 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1435232697 |
|
|
Oct 15 04:28:48 AM UTC 24 |
Oct 15 04:45:00 AM UTC 24 |
17398125048 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1343304993 |
|
|
Oct 15 03:26:26 AM UTC 24 |
Oct 15 04:45:17 AM UTC 24 |
604923849789 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.350700637 |
|
|
Oct 15 04:23:22 AM UTC 24 |
Oct 15 04:45:49 AM UTC 24 |
68915918911 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.485899167 |
|
|
Oct 15 03:55:27 AM UTC 24 |
Oct 15 04:46:18 AM UTC 24 |
162127035965 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2533985482 |
|
|
Oct 15 04:01:46 AM UTC 24 |
Oct 15 04:47:49 AM UTC 24 |
79266059090 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.545007852 |
|
|
Oct 15 04:28:13 AM UTC 24 |
Oct 15 04:47:49 AM UTC 24 |
158363959956 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.4060683685 |
|
|
Oct 15 04:17:40 AM UTC 24 |
Oct 15 04:47:53 AM UTC 24 |
7325423017 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3807195196 |
|
|
Oct 15 04:28:03 AM UTC 24 |
Oct 15 04:49:57 AM UTC 24 |
22112866184 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2466235199 |
|
|
Oct 15 03:42:55 AM UTC 24 |
Oct 15 04:50:27 AM UTC 24 |
193012440257 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3713086993 |
|
|
Oct 15 03:45:24 AM UTC 24 |
Oct 15 04:52:01 AM UTC 24 |
65768910049 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.4251200439 |
|
|
Oct 15 03:52:31 AM UTC 24 |
Oct 15 04:52:29 AM UTC 24 |
192133285821 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1465564453 |
|
|
Oct 15 04:10:29 AM UTC 24 |
Oct 15 04:53:33 AM UTC 24 |
10278913347 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3946434923 |
|
|
Oct 15 03:23:11 AM UTC 24 |
Oct 15 04:58:53 AM UTC 24 |
1001652335085 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2112793690 |
|
|
Oct 15 03:36:52 AM UTC 24 |
Oct 15 05:00:00 AM UTC 24 |
414690997095 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3537037951 |
|
|
Oct 15 03:57:02 AM UTC 24 |
Oct 15 05:00:52 AM UTC 24 |
44379825886 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3417823191 |
|
|
Oct 15 03:08:34 AM UTC 24 |
Oct 15 05:01:11 AM UTC 24 |
384307117755 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2535142692 |
|
|
Oct 15 04:19:02 AM UTC 24 |
Oct 15 05:01:31 AM UTC 24 |
35375654367 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.479940398 |
|
|
Oct 15 04:30:46 AM UTC 24 |
Oct 15 05:03:52 AM UTC 24 |
6716589728 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1584581791 |
|
|
Oct 15 03:32:51 AM UTC 24 |
Oct 15 05:13:04 AM UTC 24 |
128830532836 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.65487058 |
|
|
Oct 15 04:25:54 AM UTC 24 |
Oct 15 05:16:26 AM UTC 24 |
148424991610 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2043288866 |
|
|
Oct 15 04:14:26 AM UTC 24 |
Oct 15 05:20:17 AM UTC 24 |
55238896214 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.4142379280 |
|
|
Oct 15 04:23:53 AM UTC 24 |
Oct 15 06:12:40 AM UTC 24 |
19423201437 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1578063038 |
|
|
Oct 15 12:41:56 AM UTC 24 |
Oct 15 12:42:03 AM UTC 24 |
1053076649 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.89195727 |
|
|
Oct 15 12:41:58 AM UTC 24 |
Oct 15 12:42:03 AM UTC 24 |
130000043 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.952151955 |
|
|
Oct 15 12:42:02 AM UTC 24 |
Oct 15 12:42:04 AM UTC 24 |
38154830 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.818514860 |
|
|
Oct 15 12:42:00 AM UTC 24 |
Oct 15 12:42:04 AM UTC 24 |
488055499 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2106289782 |
|
|
Oct 15 12:42:04 AM UTC 24 |
Oct 15 12:42:06 AM UTC 24 |
172926696 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4148850169 |
|
|
Oct 15 12:42:04 AM UTC 24 |
Oct 15 12:42:06 AM UTC 24 |
25071085 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1380696012 |
|
|
Oct 15 12:42:04 AM UTC 24 |
Oct 15 12:42:06 AM UTC 24 |
86021381 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2186718267 |
|
|
Oct 15 12:42:05 AM UTC 24 |
Oct 15 12:42:07 AM UTC 24 |
168336229 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2168543732 |
|
|
Oct 15 12:42:05 AM UTC 24 |
Oct 15 12:42:08 AM UTC 24 |
134720883 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.363649256 |
|
|
Oct 15 12:42:07 AM UTC 24 |
Oct 15 12:42:09 AM UTC 24 |
93063802 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3191480270 |
|
|
Oct 15 12:42:05 AM UTC 24 |
Oct 15 12:42:10 AM UTC 24 |
2910225271 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4130873243 |
|
|
Oct 15 12:42:08 AM UTC 24 |
Oct 15 12:42:10 AM UTC 24 |
15328995 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3320668369 |
|
|
Oct 15 12:42:23 AM UTC 24 |
Oct 15 12:42:26 AM UTC 24 |
74211460 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1934306797 |
|
|
Oct 15 12:42:06 AM UTC 24 |
Oct 15 12:42:10 AM UTC 24 |
361567047 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4103068146 |
|
|
Oct 15 12:42:08 AM UTC 24 |
Oct 15 12:42:10 AM UTC 24 |
19682062 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1423911711 |
|
|
Oct 15 12:42:08 AM UTC 24 |
Oct 15 12:42:10 AM UTC 24 |
63011205 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2197264771 |
|
|
Oct 15 12:42:06 AM UTC 24 |
Oct 15 12:42:11 AM UTC 24 |
26349477 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.793268684 |
|
|
Oct 15 12:42:08 AM UTC 24 |
Oct 15 12:42:12 AM UTC 24 |
78643328 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3710555463 |
|
|
Oct 15 12:42:08 AM UTC 24 |
Oct 15 12:42:12 AM UTC 24 |
126494290 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3056003679 |
|
|
Oct 15 12:42:11 AM UTC 24 |
Oct 15 12:42:13 AM UTC 24 |
14753740 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2700564088 |
|
|
Oct 15 12:42:11 AM UTC 24 |
Oct 15 12:42:13 AM UTC 24 |
25025166 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3294006067 |
|
|
Oct 15 12:42:11 AM UTC 24 |
Oct 15 12:42:13 AM UTC 24 |
36264959 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.252481284 |
|
|
Oct 15 12:42:11 AM UTC 24 |
Oct 15 12:42:13 AM UTC 24 |
47153980 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1807145668 |
|
|
Oct 15 12:42:10 AM UTC 24 |
Oct 15 12:42:13 AM UTC 24 |
216218480 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3649915872 |
|
|
Oct 15 12:42:11 AM UTC 24 |
Oct 15 12:42:14 AM UTC 24 |
28579147 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1649076052 |
|
|
Oct 15 12:42:09 AM UTC 24 |
Oct 15 12:42:14 AM UTC 24 |
302284365 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3914173576 |
|
|
Oct 15 12:42:12 AM UTC 24 |
Oct 15 12:42:15 AM UTC 24 |
35104426 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2257951891 |
|
|
Oct 15 12:42:13 AM UTC 24 |
Oct 15 12:42:15 AM UTC 24 |
21677543 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.900962148 |
|
|
Oct 15 12:42:13 AM UTC 24 |
Oct 15 12:42:15 AM UTC 24 |
19441545 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2117517974 |
|
|
Oct 15 12:42:13 AM UTC 24 |
Oct 15 12:42:15 AM UTC 24 |
35868929 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.903872278 |
|
|
Oct 15 12:42:12 AM UTC 24 |
Oct 15 12:42:16 AM UTC 24 |
201935506 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1093385554 |
|
|
Oct 15 12:42:15 AM UTC 24 |
Oct 15 12:42:16 AM UTC 24 |
24567518 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3326269633 |
|
|
Oct 15 12:42:09 AM UTC 24 |
Oct 15 12:42:17 AM UTC 24 |
116428246 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3724871671 |
|
|
Oct 15 12:42:13 AM UTC 24 |
Oct 15 12:42:17 AM UTC 24 |
156729205 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4128967206 |
|
|
Oct 15 12:42:13 AM UTC 24 |
Oct 15 12:42:17 AM UTC 24 |
587638531 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2150309652 |
|
|
Oct 15 12:42:15 AM UTC 24 |
Oct 15 12:42:18 AM UTC 24 |
35058739 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1438448216 |
|
|
Oct 15 12:42:16 AM UTC 24 |
Oct 15 12:42:18 AM UTC 24 |
19568144 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2803084411 |
|
|
Oct 15 12:42:16 AM UTC 24 |
Oct 15 12:42:18 AM UTC 24 |
30329702 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.394283388 |
|
|
Oct 15 12:42:15 AM UTC 24 |
Oct 15 12:42:19 AM UTC 24 |
246178660 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.983244746 |
|
|
Oct 15 12:42:17 AM UTC 24 |
Oct 15 12:42:19 AM UTC 24 |
13184492 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3608912883 |
|
|
Oct 15 12:42:17 AM UTC 24 |
Oct 15 12:42:19 AM UTC 24 |
13360442 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1111028637 |
|
|
Oct 15 12:42:23 AM UTC 24 |
Oct 15 12:42:26 AM UTC 24 |
246505122 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1652097382 |
|
|
Oct 15 12:42:17 AM UTC 24 |
Oct 15 12:42:20 AM UTC 24 |
57353389 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3482809342 |
|
|
Oct 15 12:42:16 AM UTC 24 |
Oct 15 12:42:20 AM UTC 24 |
169838261 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1243376367 |
|
|
Oct 15 12:42:16 AM UTC 24 |
Oct 15 12:42:20 AM UTC 24 |
715412855 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2902023121 |
|
|
Oct 15 12:42:19 AM UTC 24 |
Oct 15 12:42:21 AM UTC 24 |
38360865 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2874633073 |
|
|
Oct 15 12:42:12 AM UTC 24 |
Oct 15 12:42:21 AM UTC 24 |
292781468 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2155648348 |
|
|
Oct 15 12:42:17 AM UTC 24 |
Oct 15 12:42:21 AM UTC 24 |
88578622 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2423524950 |
|
|
Oct 15 12:42:19 AM UTC 24 |
Oct 15 12:42:21 AM UTC 24 |
93247560 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2626895695 |
|
|
Oct 15 12:42:17 AM UTC 24 |
Oct 15 12:42:21 AM UTC 24 |
922152376 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2647086324 |
|
|
Oct 15 12:42:18 AM UTC 24 |
Oct 15 12:42:21 AM UTC 24 |
92777076 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3545771531 |
|
|
Oct 15 12:42:16 AM UTC 24 |
Oct 15 12:42:21 AM UTC 24 |
46674259 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1134793722 |
|
|
Oct 15 12:42:19 AM UTC 24 |
Oct 15 12:42:22 AM UTC 24 |
106097730 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3492384076 |
|
|
Oct 15 12:42:20 AM UTC 24 |
Oct 15 12:42:22 AM UTC 24 |
29537970 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3257634207 |
|
|
Oct 15 12:42:20 AM UTC 24 |
Oct 15 12:42:23 AM UTC 24 |
299724394 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.50633323 |
|
|
Oct 15 12:42:21 AM UTC 24 |
Oct 15 12:42:23 AM UTC 24 |
17448612 ps |