| T795 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1375728707 |
|
|
Feb 08 12:39:24 PM UTC 25 |
Feb 08 12:39:28 PM UTC 25 |
162253899 ps |
| T796 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2444715752 |
|
|
Feb 08 12:39:29 PM UTC 25 |
Feb 08 12:39:36 PM UTC 25 |
1461310120 ps |
| T797 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2157152952 |
|
|
Feb 08 12:38:45 PM UTC 25 |
Feb 08 12:39:36 PM UTC 25 |
3283928206 ps |
| T798 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2084158507 |
|
|
Feb 08 12:39:17 PM UTC 25 |
Feb 08 12:39:53 PM UTC 25 |
167616923 ps |
| T799 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3329999246 |
|
|
Feb 08 12:39:54 PM UTC 25 |
Feb 08 12:39:57 PM UTC 25 |
83437876 ps |
| T800 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1571591795 |
|
|
Feb 08 12:34:08 PM UTC 25 |
Feb 08 12:39:59 PM UTC 25 |
5312259679 ps |
| T801 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2410966616 |
|
|
Feb 08 12:39:57 PM UTC 25 |
Feb 08 12:40:04 PM UTC 25 |
144440842 ps |
| T802 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2477205597 |
|
|
Feb 08 12:40:00 PM UTC 25 |
Feb 08 12:40:08 PM UTC 25 |
350998527 ps |
| T803 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1822143086 |
|
|
Feb 08 12:40:09 PM UTC 25 |
Feb 08 12:40:11 PM UTC 25 |
35596512 ps |
| T804 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.401847993 |
|
|
Feb 08 12:25:12 PM UTC 25 |
Feb 08 12:40:34 PM UTC 25 |
6600023393 ps |
| T805 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.351709550 |
|
|
Feb 08 12:40:26 PM UTC 25 |
Feb 08 12:40:44 PM UTC 25 |
1310673336 ps |
| T806 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.4107605202 |
|
|
Feb 08 12:40:22 PM UTC 25 |
Feb 08 12:40:51 PM UTC 25 |
399816547 ps |
| T807 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2455098305 |
|
|
Feb 08 12:32:29 PM UTC 25 |
Feb 08 12:40:52 PM UTC 25 |
4402000851 ps |
| T808 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1948004114 |
|
|
Feb 08 12:40:52 PM UTC 25 |
Feb 08 12:40:56 PM UTC 25 |
240632994 ps |
| T809 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.31692551 |
|
|
Feb 08 12:36:13 PM UTC 25 |
Feb 08 12:40:57 PM UTC 25 |
3047816608 ps |
| T810 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.4252522858 |
|
|
Feb 08 12:40:52 PM UTC 25 |
Feb 08 12:41:01 PM UTC 25 |
66800864 ps |
| T811 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3443233817 |
|
|
Feb 08 12:38:40 PM UTC 25 |
Feb 08 12:41:07 PM UTC 25 |
6872238478 ps |
| T812 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2782402858 |
|
|
Feb 08 12:40:58 PM UTC 25 |
Feb 08 12:41:09 PM UTC 25 |
1610264800 ps |
| T813 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3941327752 |
|
|
Feb 08 12:41:10 PM UTC 25 |
Feb 08 12:41:12 PM UTC 25 |
84695667 ps |
| T111 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4016124204 |
|
|
Feb 08 12:40:02 PM UTC 25 |
Feb 08 12:41:20 PM UTC 25 |
954371743 ps |
| T814 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.1819461873 |
|
|
Feb 08 12:41:13 PM UTC 25 |
Feb 08 12:41:23 PM UTC 25 |
453467948 ps |
| T815 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1041581921 |
|
|
Feb 08 12:28:54 PM UTC 25 |
Feb 08 12:41:24 PM UTC 25 |
32050131254 ps |
| T816 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1968500286 |
|
|
Feb 08 12:41:21 PM UTC 25 |
Feb 08 12:41:25 PM UTC 25 |
48390276 ps |
| T817 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3046205636 |
|
|
Feb 08 12:38:07 PM UTC 25 |
Feb 08 12:41:26 PM UTC 25 |
2616089956 ps |
| T818 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2620253540 |
|
|
Feb 08 12:41:27 PM UTC 25 |
Feb 08 12:41:29 PM UTC 25 |
19947437 ps |
| T819 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1493500421 |
|
|
Feb 08 12:41:02 PM UTC 25 |
Feb 08 12:41:37 PM UTC 25 |
15864932712 ps |
| T820 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.487719168 |
|
|
Feb 08 12:38:47 PM UTC 25 |
Feb 08 12:41:40 PM UTC 25 |
3154601636 ps |
| T821 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3031145705 |
|
|
Feb 08 12:37:51 PM UTC 25 |
Feb 08 12:41:41 PM UTC 25 |
1102731680 ps |
| T822 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3027305172 |
|
|
Feb 08 12:41:27 PM UTC 25 |
Feb 08 12:41:45 PM UTC 25 |
233854837 ps |
| T823 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1154614602 |
|
|
Feb 08 12:37:54 PM UTC 25 |
Feb 08 12:41:51 PM UTC 25 |
2525778480 ps |
| T824 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2291977351 |
|
|
Feb 08 11:43:08 AM UTC 25 |
Feb 08 12:41:53 PM UTC 25 |
457058772507 ps |
| T825 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3629354513 |
|
|
Feb 08 12:30:32 PM UTC 25 |
Feb 08 12:42:04 PM UTC 25 |
2007764551 ps |
| T826 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1967875857 |
|
|
Feb 08 12:41:52 PM UTC 25 |
Feb 08 12:42:08 PM UTC 25 |
71531020 ps |
| T827 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1211153435 |
|
|
Feb 08 12:41:23 PM UTC 25 |
Feb 08 12:42:09 PM UTC 25 |
688737614 ps |
| T828 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.105567901 |
|
|
Feb 08 12:41:38 PM UTC 25 |
Feb 08 12:42:12 PM UTC 25 |
4652213804 ps |
| T829 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1929881367 |
|
|
Feb 08 12:42:05 PM UTC 25 |
Feb 08 12:42:15 PM UTC 25 |
633337111 ps |
| T830 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2252012500 |
|
|
Feb 08 12:40:45 PM UTC 25 |
Feb 08 12:42:18 PM UTC 25 |
13970192281 ps |
| T831 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2431513039 |
|
|
Feb 08 12:42:16 PM UTC 25 |
Feb 08 12:42:18 PM UTC 25 |
117820902 ps |
| T832 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3370450888 |
|
|
Feb 08 12:41:54 PM UTC 25 |
Feb 08 12:42:23 PM UTC 25 |
896214988 ps |
| T86 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3586562359 |
|
|
Feb 08 12:42:20 PM UTC 25 |
Feb 08 12:42:25 PM UTC 25 |
329981184 ps |
| T833 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2725446957 |
|
|
Feb 08 12:42:20 PM UTC 25 |
Feb 08 12:42:37 PM UTC 25 |
664446538 ps |
| T834 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3911287994 |
|
|
Feb 08 12:41:42 PM UTC 25 |
Feb 08 12:42:40 PM UTC 25 |
1856052707 ps |
| T835 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1017655919 |
|
|
Feb 08 12:42:39 PM UTC 25 |
Feb 08 12:42:41 PM UTC 25 |
61932761 ps |
| T836 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.149764727 |
|
|
Feb 08 12:33:57 PM UTC 25 |
Feb 08 12:42:43 PM UTC 25 |
13388386816 ps |
| T837 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2868910294 |
|
|
Feb 08 12:30:03 PM UTC 25 |
Feb 08 12:42:43 PM UTC 25 |
13735680413 ps |
| T838 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1724644205 |
|
|
Feb 08 12:40:35 PM UTC 25 |
Feb 08 12:42:45 PM UTC 25 |
685204188 ps |
| T839 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.4178529937 |
|
|
Feb 08 12:35:34 PM UTC 25 |
Feb 08 12:42:53 PM UTC 25 |
22789610473 ps |
| T840 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.1502302668 |
|
|
Feb 08 12:42:42 PM UTC 25 |
Feb 08 12:42:57 PM UTC 25 |
447375952 ps |
| T841 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.478534716 |
|
|
Feb 08 12:37:02 PM UTC 25 |
Feb 08 12:42:57 PM UTC 25 |
9628986473 ps |
| T842 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.790296489 |
|
|
Feb 08 12:36:30 PM UTC 25 |
Feb 08 12:42:58 PM UTC 25 |
9825439778 ps |
| T843 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2491364043 |
|
|
Feb 08 12:42:59 PM UTC 25 |
Feb 08 12:43:02 PM UTC 25 |
37283711 ps |
| T844 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1916392184 |
|
|
Feb 08 12:42:46 PM UTC 25 |
Feb 08 12:43:05 PM UTC 25 |
2525015756 ps |
| T845 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.2626494873 |
|
|
Feb 08 12:37:11 PM UTC 25 |
Feb 08 12:43:09 PM UTC 25 |
10229030902 ps |
| T846 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1607656517 |
|
|
Feb 08 12:43:00 PM UTC 25 |
Feb 08 12:43:12 PM UTC 25 |
1545583202 ps |
| T847 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.4276517408 |
|
|
Feb 08 12:43:13 PM UTC 25 |
Feb 08 12:43:16 PM UTC 25 |
133544451 ps |
| T848 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2043475081 |
|
|
Feb 08 12:43:16 PM UTC 25 |
Feb 08 12:43:26 PM UTC 25 |
569411973 ps |
| T849 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3566301290 |
|
|
Feb 08 12:42:59 PM UTC 25 |
Feb 08 12:43:28 PM UTC 25 |
415589794 ps |
| T850 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1270565584 |
|
|
Feb 08 12:43:27 PM UTC 25 |
Feb 08 12:43:32 PM UTC 25 |
291358558 ps |
| T851 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.849917749 |
|
|
Feb 08 12:42:45 PM UTC 25 |
Feb 08 12:44:18 PM UTC 25 |
3807565235 ps |
| T852 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3858413378 |
|
|
Feb 08 12:44:19 PM UTC 25 |
Feb 08 12:44:22 PM UTC 25 |
141788625 ps |
| T112 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3434052648 |
|
|
Feb 08 12:43:30 PM UTC 25 |
Feb 08 12:44:24 PM UTC 25 |
852679525 ps |
| T853 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.1596760670 |
|
|
Feb 08 12:44:23 PM UTC 25 |
Feb 08 12:44:30 PM UTC 25 |
1186609282 ps |
| T854 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1675242493 |
|
|
Feb 08 12:34:34 PM UTC 25 |
Feb 08 12:44:37 PM UTC 25 |
18623136542 ps |
| T855 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3083341486 |
|
|
Feb 08 12:18:29 PM UTC 25 |
Feb 08 12:44:42 PM UTC 25 |
17956177178 ps |
| T856 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.4178964098 |
|
|
Feb 08 12:40:31 PM UTC 25 |
Feb 08 12:44:47 PM UTC 25 |
2586638182 ps |
| T857 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3355955090 |
|
|
Feb 08 12:44:43 PM UTC 25 |
Feb 08 12:45:04 PM UTC 25 |
529083945 ps |
| T858 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2416915682 |
|
|
Feb 08 12:44:31 PM UTC 25 |
Feb 08 12:45:08 PM UTC 25 |
5911605708 ps |
| T859 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1089585488 |
|
|
Feb 08 12:28:56 PM UTC 25 |
Feb 08 12:45:18 PM UTC 25 |
2865547063 ps |
| T860 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1758920779 |
|
|
Feb 08 12:45:13 PM UTC 25 |
Feb 08 12:45:18 PM UTC 25 |
420369012 ps |
| T861 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1966145669 |
|
|
Feb 08 12:31:46 PM UTC 25 |
Feb 08 12:45:22 PM UTC 25 |
12504456645 ps |
| T862 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.664179436 |
|
|
Feb 08 12:45:05 PM UTC 25 |
Feb 08 12:45:23 PM UTC 25 |
275016991 ps |
| T863 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.495109244 |
|
|
Feb 08 12:45:24 PM UTC 25 |
Feb 08 12:45:26 PM UTC 25 |
49357167 ps |
| T864 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.526165716 |
|
|
Feb 08 12:31:41 PM UTC 25 |
Feb 08 12:45:29 PM UTC 25 |
68323656173 ps |
| T865 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.824400120 |
|
|
Feb 08 12:45:30 PM UTC 25 |
Feb 08 12:45:38 PM UTC 25 |
96528676 ps |
| T866 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3506131146 |
|
|
Feb 08 12:45:10 PM UTC 25 |
Feb 08 12:45:39 PM UTC 25 |
200770874 ps |
| T867 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1794097273 |
|
|
Feb 08 12:45:27 PM UTC 25 |
Feb 08 12:45:45 PM UTC 25 |
1748110772 ps |
| T868 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2304356271 |
|
|
Feb 08 12:45:45 PM UTC 25 |
Feb 08 12:45:48 PM UTC 25 |
35497531 ps |
| T869 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3681521051 |
|
|
Feb 08 12:25:11 PM UTC 25 |
Feb 08 12:46:17 PM UTC 25 |
16568419747 ps |
| T870 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2361962968 |
|
|
Feb 08 12:41:40 PM UTC 25 |
Feb 08 12:46:42 PM UTC 25 |
17848662957 ps |
| T871 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1167531575 |
|
|
Feb 08 12:39:08 PM UTC 25 |
Feb 08 12:46:53 PM UTC 25 |
72886544953 ps |
| T872 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1148554704 |
|
|
Feb 08 12:43:06 PM UTC 25 |
Feb 08 12:47:30 PM UTC 25 |
18797061141 ps |
| T873 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.4006920197 |
|
|
Feb 08 12:42:45 PM UTC 25 |
Feb 08 12:47:54 PM UTC 25 |
5561123348 ps |
| T874 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3254714088 |
|
|
Feb 08 12:43:10 PM UTC 25 |
Feb 08 12:47:54 PM UTC 25 |
690151945 ps |
| T875 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.2558021249 |
|
|
Feb 08 12:39:37 PM UTC 25 |
Feb 08 12:48:10 PM UTC 25 |
61499094402 ps |
| T876 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.1823001992 |
|
|
Feb 08 12:38:30 PM UTC 25 |
Feb 08 12:48:20 PM UTC 25 |
8957953062 ps |
| T877 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.1945937081 |
|
|
Feb 08 12:35:12 PM UTC 25 |
Feb 08 12:48:27 PM UTC 25 |
2417020106 ps |
| T878 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3483411185 |
|
|
Feb 08 12:26:48 PM UTC 25 |
Feb 08 12:48:29 PM UTC 25 |
17929485769 ps |
| T879 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.2697355740 |
|
|
Feb 08 12:35:13 PM UTC 25 |
Feb 08 12:49:10 PM UTC 25 |
22434389306 ps |
| T880 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2669872512 |
|
|
Feb 08 12:41:30 PM UTC 25 |
Feb 08 12:49:31 PM UTC 25 |
29966738493 ps |
| T881 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.4216033815 |
|
|
Feb 08 12:40:59 PM UTC 25 |
Feb 08 12:49:39 PM UTC 25 |
3271793615 ps |
| T882 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.545631369 |
|
|
Feb 08 12:41:46 PM UTC 25 |
Feb 08 12:49:43 PM UTC 25 |
78135769024 ps |
| T883 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2410939311 |
|
|
Feb 08 12:44:37 PM UTC 25 |
Feb 08 12:50:00 PM UTC 25 |
2815065131 ps |
| T884 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2909023745 |
|
|
Feb 08 12:44:48 PM UTC 25 |
Feb 08 12:50:35 PM UTC 25 |
4609894482 ps |
| T885 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3984578639 |
|
|
Feb 08 12:35:04 PM UTC 25 |
Feb 08 12:50:42 PM UTC 25 |
3941076498 ps |
| T886 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3781622837 |
|
|
Feb 08 12:42:42 PM UTC 25 |
Feb 08 12:50:56 PM UTC 25 |
9579348166 ps |
| T887 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3962261477 |
|
|
Feb 08 12:38:45 PM UTC 25 |
Feb 08 12:50:59 PM UTC 25 |
57595706529 ps |
| T888 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1480704216 |
|
|
Feb 08 12:27:42 PM UTC 25 |
Feb 08 12:51:38 PM UTC 25 |
73415087030 ps |
| T889 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3412908075 |
|
|
Feb 08 12:25:40 PM UTC 25 |
Feb 08 12:51:41 PM UTC 25 |
19346295644 ps |
| T890 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2542335314 |
|
|
Feb 08 12:30:08 PM UTC 25 |
Feb 08 12:51:51 PM UTC 25 |
239421019757 ps |
| T891 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2910600230 |
|
|
Feb 08 12:44:25 PM UTC 25 |
Feb 08 12:52:05 PM UTC 25 |
2672265175 ps |
| T892 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.3686030073 |
|
|
Feb 08 12:38:29 PM UTC 25 |
Feb 08 12:53:01 PM UTC 25 |
3358164441 ps |
| T893 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2703548385 |
|
|
Feb 08 12:40:05 PM UTC 25 |
Feb 08 12:53:13 PM UTC 25 |
15166587300 ps |
| T894 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3981682239 |
|
|
Feb 08 12:42:54 PM UTC 25 |
Feb 08 12:53:21 PM UTC 25 |
95349244158 ps |
| T895 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.3391043800 |
|
|
Feb 08 12:42:13 PM UTC 25 |
Feb 08 12:53:34 PM UTC 25 |
6411352223 ps |
| T896 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.3545360629 |
|
|
Feb 08 12:38:28 PM UTC 25 |
Feb 08 12:53:39 PM UTC 25 |
11243937307 ps |
| T897 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1010583675 |
|
|
Feb 08 12:45:19 PM UTC 25 |
Feb 08 12:55:17 PM UTC 25 |
9807103119 ps |
| T898 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.4024613988 |
|
|
Feb 08 12:42:09 PM UTC 25 |
Feb 08 12:55:42 PM UTC 25 |
19564963242 ps |
| T899 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.2610655619 |
|
|
Feb 08 11:54:39 AM UTC 25 |
Feb 08 12:57:22 PM UTC 25 |
24280397213 ps |
| T900 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.349243835 |
|
|
Feb 08 12:42:11 PM UTC 25 |
Feb 08 12:57:33 PM UTC 25 |
44881144154 ps |
| T901 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1245581548 |
|
|
Feb 08 12:23:57 PM UTC 25 |
Feb 08 12:57:42 PM UTC 25 |
62570828336 ps |
| T902 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.4149293149 |
|
|
Feb 08 12:32:23 PM UTC 25 |
Feb 08 12:57:46 PM UTC 25 |
17078836627 ps |
| T903 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2172523376 |
|
|
Feb 08 12:10:45 PM UTC 25 |
Feb 08 12:57:48 PM UTC 25 |
11488297878 ps |
| T904 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1406404932 |
|
|
Feb 08 12:39:36 PM UTC 25 |
Feb 08 12:59:06 PM UTC 25 |
3763342554 ps |
| T905 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.516659840 |
|
|
Feb 08 12:39:37 PM UTC 25 |
Feb 08 12:59:25 PM UTC 25 |
3773719873 ps |
| T906 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2981907781 |
|
|
Feb 08 12:45:19 PM UTC 25 |
Feb 08 12:59:33 PM UTC 25 |
4852580132 ps |
| T907 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.402290921 |
|
|
Feb 08 12:45:23 PM UTC 25 |
Feb 08 01:00:03 PM UTC 25 |
28327450788 ps |
| T908 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1926168043 |
|
|
Feb 08 12:43:03 PM UTC 25 |
Feb 08 01:00:04 PM UTC 25 |
12770910184 ps |
| T909 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.425531985 |
|
|
Feb 08 12:37:09 PM UTC 25 |
Feb 08 01:00:22 PM UTC 25 |
47199981418 ps |
| T910 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3755527530 |
|
|
Feb 08 12:41:24 PM UTC 25 |
Feb 08 01:00:34 PM UTC 25 |
23636599875 ps |
| T911 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.558164812 |
|
|
Feb 08 12:14:27 PM UTC 25 |
Feb 08 01:01:15 PM UTC 25 |
43389160664 ps |
| T912 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.283957678 |
|
|
Feb 08 12:37:31 PM UTC 25 |
Feb 08 01:05:57 PM UTC 25 |
26912237194 ps |
| T913 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.34610936 |
|
|
Feb 08 12:30:38 PM UTC 25 |
Feb 08 01:09:02 PM UTC 25 |
144261893127 ps |
| T914 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3876806862 |
|
|
Feb 08 12:08:21 PM UTC 25 |
Feb 08 01:10:48 PM UTC 25 |
56422466297 ps |
| T915 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2197385037 |
|
|
Feb 08 12:41:07 PM UTC 25 |
Feb 08 01:11:22 PM UTC 25 |
5666193563 ps |
| T916 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.3180547343 |
|
|
Feb 08 12:20:14 PM UTC 25 |
Feb 08 01:14:24 PM UTC 25 |
22036481343 ps |
| T917 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.715478124 |
|
|
Feb 08 12:11:30 PM UTC 25 |
Feb 08 01:15:51 PM UTC 25 |
51687268530 ps |
| T918 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3737680544 |
|
|
Feb 08 12:42:25 PM UTC 25 |
Feb 08 01:17:18 PM UTC 25 |
38207914870 ps |
| T919 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1332980465 |
|
|
Feb 08 12:34:30 PM UTC 25 |
Feb 08 01:18:34 PM UTC 25 |
11810347917 ps |
| T920 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2245223376 |
|
|
Feb 08 12:27:32 PM UTC 25 |
Feb 08 01:19:27 PM UTC 25 |
48835012785 ps |
| T921 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2230688236 |
|
|
Feb 08 12:22:15 PM UTC 25 |
Feb 08 01:20:23 PM UTC 25 |
48051799338 ps |
| T922 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1385827764 |
|
|
Feb 08 12:12:40 PM UTC 25 |
Feb 08 01:21:26 PM UTC 25 |
65668381419 ps |
| T923 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3104531838 |
|
|
Feb 08 11:56:04 AM UTC 25 |
Feb 08 01:22:08 PM UTC 25 |
82194182513 ps |
| T924 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.488406909 |
|
|
Feb 08 12:45:40 PM UTC 25 |
Feb 08 01:22:51 PM UTC 25 |
36382359294 ps |
| T925 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2188543798 |
|
|
Feb 08 12:15:42 PM UTC 25 |
Feb 08 01:24:18 PM UTC 25 |
13503996833 ps |
| T926 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.92068585 |
|
|
Feb 08 12:17:29 PM UTC 25 |
Feb 08 01:25:13 PM UTC 25 |
195512480282 ps |
| T927 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1128234218 |
|
|
Feb 08 12:18:58 PM UTC 25 |
Feb 08 01:26:12 PM UTC 25 |
47660905954 ps |
| T928 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2655206449 |
|
|
Feb 08 12:43:33 PM UTC 25 |
Feb 08 01:43:03 PM UTC 25 |
126075710146 ps |
| T929 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3551759634 |
|
|
Feb 08 12:35:27 PM UTC 25 |
Feb 08 02:01:24 PM UTC 25 |
324294881867 ps |
| T930 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3670017325 |
|
|
Feb 08 12:29:10 PM UTC 25 |
Feb 08 02:18:05 PM UTC 25 |
178405586355 ps |
| T65 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2718891129 |
|
|
Feb 08 10:02:18 AM UTC 25 |
Feb 08 10:02:22 AM UTC 25 |
773665049 ps |
| T931 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3089599395 |
|
|
Feb 08 10:02:22 AM UTC 25 |
Feb 08 10:02:27 AM UTC 25 |
29976048 ps |
| T60 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3457701861 |
|
|
Feb 08 10:02:23 AM UTC 25 |
Feb 08 10:02:27 AM UTC 25 |
348835003 ps |
| T66 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.119992164 |
|
|
Feb 08 10:02:26 AM UTC 25 |
Feb 08 10:02:29 AM UTC 25 |
74033899 ps |
| T70 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3408614355 |
|
|
Feb 08 10:02:27 AM UTC 25 |
Feb 08 10:02:30 AM UTC 25 |
22876605 ps |
| T105 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.195801551 |
|
|
Feb 08 10:02:28 AM UTC 25 |
Feb 08 10:02:32 AM UTC 25 |
28520709 ps |
| T71 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1281376111 |
|
|
Feb 08 10:02:29 AM UTC 25 |
Feb 08 10:02:32 AM UTC 25 |
44284555 ps |
| T92 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1398861245 |
|
|
Feb 08 10:02:30 AM UTC 25 |
Feb 08 10:02:33 AM UTC 25 |
73556423 ps |
| T932 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.148997704 |
|
|
Feb 08 10:02:30 AM UTC 25 |
Feb 08 10:02:34 AM UTC 25 |
33290494 ps |
| T72 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3549703247 |
|
|
Feb 08 10:02:34 AM UTC 25 |
Feb 08 10:02:36 AM UTC 25 |
145606612 ps |
| T93 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2167305625 |
|
|
Feb 08 10:02:35 AM UTC 25 |
Feb 08 10:02:37 AM UTC 25 |
45603003 ps |
| T61 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1405738668 |
|
|
Feb 08 10:02:34 AM UTC 25 |
Feb 08 10:02:38 AM UTC 25 |
294847856 ps |
| T933 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.878410272 |
|
|
Feb 08 10:02:32 AM UTC 25 |
Feb 08 10:02:39 AM UTC 25 |
81450997 ps |
| T73 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3375988967 |
|
|
Feb 08 10:02:32 AM UTC 25 |
Feb 08 10:02:41 AM UTC 25 |
1723672261 ps |
| T74 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2347560794 |
|
|
Feb 08 10:02:38 AM UTC 25 |
Feb 08 10:02:41 AM UTC 25 |
57654310 ps |
| T94 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1764242042 |
|
|
Feb 08 10:02:39 AM UTC 25 |
Feb 08 10:02:42 AM UTC 25 |
52848979 ps |
| T75 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.638358473 |
|
|
Feb 08 10:02:37 AM UTC 25 |
Feb 08 10:02:42 AM UTC 25 |
391954858 ps |
| T934 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1559928772 |
|
|
Feb 08 10:02:40 AM UTC 25 |
Feb 08 10:02:43 AM UTC 25 |
59826586 ps |
| T76 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3331350321 |
|
|
Feb 08 10:02:43 AM UTC 25 |
Feb 08 10:02:46 AM UTC 25 |
18178941 ps |
| T935 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2854881639 |
|
|
Feb 08 10:02:43 AM UTC 25 |
Feb 08 10:02:46 AM UTC 25 |
16925026 ps |
| T62 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2307977598 |
|
|
Feb 08 10:02:42 AM UTC 25 |
Feb 08 10:02:46 AM UTC 25 |
124495131 ps |
| T936 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1335284795 |
|
|
Feb 08 10:02:41 AM UTC 25 |
Feb 08 10:02:48 AM UTC 25 |
476274376 ps |
| T77 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.856520892 |
|
|
Feb 08 10:02:44 AM UTC 25 |
Feb 08 10:02:49 AM UTC 25 |
82513981 ps |
| T78 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2304281792 |
|
|
Feb 08 10:02:46 AM UTC 25 |
Feb 08 10:02:49 AM UTC 25 |
66644612 ps |
| T95 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2721853702 |
|
|
Feb 08 10:02:46 AM UTC 25 |
Feb 08 10:02:49 AM UTC 25 |
26420095 ps |
| T79 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1529531365 |
|
|
Feb 08 10:02:41 AM UTC 25 |
Feb 08 10:02:49 AM UTC 25 |
391639549 ps |
| T937 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4018169975 |
|
|
Feb 08 10:02:47 AM UTC 25 |
Feb 08 10:02:51 AM UTC 25 |
113063859 ps |
| T80 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2286636387 |
|
|
Feb 08 10:02:50 AM UTC 25 |
Feb 08 10:02:53 AM UTC 25 |
20432232 ps |
| T938 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1788878745 |
|
|
Feb 08 10:02:50 AM UTC 25 |
Feb 08 10:02:53 AM UTC 25 |
40077248 ps |
| T87 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3003139249 |
|
|
Feb 08 10:02:49 AM UTC 25 |
Feb 08 10:02:54 AM UTC 25 |
328482465 ps |
| T939 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1465124158 |
|
|
Feb 08 10:02:50 AM UTC 25 |
Feb 08 10:02:55 AM UTC 25 |
60540725 ps |
| T113 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.26968303 |
|
|
Feb 08 10:02:50 AM UTC 25 |
Feb 08 10:02:55 AM UTC 25 |
222852227 ps |
| T940 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1547783789 |
|
|
Feb 08 10:02:53 AM UTC 25 |
Feb 08 10:02:56 AM UTC 25 |
29813500 ps |
| T941 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3508293086 |
|
|
Feb 08 10:02:54 AM UTC 25 |
Feb 08 10:02:57 AM UTC 25 |
98440685 ps |
| T96 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.925801806 |
|
|
Feb 08 10:02:54 AM UTC 25 |
Feb 08 10:02:57 AM UTC 25 |
57952529 ps |
| T942 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3558839029 |
|
|
Feb 08 10:02:54 AM UTC 25 |
Feb 08 10:02:58 AM UTC 25 |
327068131 ps |
| T943 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2503869395 |
|
|
Feb 08 10:02:57 AM UTC 25 |
Feb 08 10:03:00 AM UTC 25 |
21963426 ps |
| T944 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1933702891 |
|
|
Feb 08 10:02:57 AM UTC 25 |
Feb 08 10:03:00 AM UTC 25 |
52635023 ps |
| T117 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.343812655 |
|
|
Feb 08 10:02:56 AM UTC 25 |
Feb 08 10:03:01 AM UTC 25 |
138258076 ps |
| T81 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2440543801 |
|
|
Feb 08 10:02:55 AM UTC 25 |
Feb 08 10:03:01 AM UTC 25 |
269909872 ps |
| T945 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2617222028 |
|
|
Feb 08 10:02:59 AM UTC 25 |
Feb 08 10:03:02 AM UTC 25 |
44277418 ps |
| T946 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1330972394 |
|
|
Feb 08 10:03:00 AM UTC 25 |
Feb 08 10:03:03 AM UTC 25 |
14922511 ps |
| T947 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3916770715 |
|
|
Feb 08 10:02:58 AM UTC 25 |
Feb 08 10:03:04 AM UTC 25 |
681246398 ps |
| T948 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2625813903 |
|
|
Feb 08 10:02:56 AM UTC 25 |
Feb 08 10:03:04 AM UTC 25 |
212426044 ps |
| T949 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.736992399 |
|
|
Feb 08 10:03:01 AM UTC 25 |
Feb 08 10:03:04 AM UTC 25 |
42517698 ps |
| T950 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.705356125 |
|
|
Feb 08 10:03:04 AM UTC 25 |
Feb 08 10:03:06 AM UTC 25 |
24031440 ps |
| T82 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2620035512 |
|
|
Feb 08 10:03:02 AM UTC 25 |
Feb 08 10:03:06 AM UTC 25 |
719992989 ps |
| T114 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4118954221 |
|
|
Feb 08 10:03:03 AM UTC 25 |
Feb 08 10:03:06 AM UTC 25 |
1091756808 ps |
| T951 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3351205999 |
|
|
Feb 08 10:03:04 AM UTC 25 |
Feb 08 10:03:06 AM UTC 25 |
26963187 ps |
| T952 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1274425939 |
|
|
Feb 08 10:03:02 AM UTC 25 |
Feb 08 10:03:07 AM UTC 25 |
75632429 ps |
| T953 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1363003890 |
|
|
Feb 08 10:03:05 AM UTC 25 |
Feb 08 10:03:08 AM UTC 25 |
57184231 ps |
| T954 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.51975754 |
|
|
Feb 08 10:03:05 AM UTC 25 |
Feb 08 10:03:09 AM UTC 25 |
31031548 ps |
| T955 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3617839215 |
|
|
Feb 08 10:03:07 AM UTC 25 |
Feb 08 10:03:09 AM UTC 25 |
60557581 ps |
| T956 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3176115326 |
|
|
Feb 08 10:03:07 AM UTC 25 |
Feb 08 10:03:10 AM UTC 25 |
23420346 ps |
| T957 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.478794922 |
|
|
Feb 08 10:03:07 AM UTC 25 |
Feb 08 10:03:12 AM UTC 25 |
35823807 ps |
| T88 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2859469984 |
|
|
Feb 08 10:03:05 AM UTC 25 |
Feb 08 10:03:13 AM UTC 25 |
1765374241 ps |
| T958 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1211007237 |
|
|
Feb 08 10:03:10 AM UTC 25 |
Feb 08 10:03:13 AM UTC 25 |
14301507 ps |
| T119 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2390300940 |
|
|
Feb 08 10:03:07 AM UTC 25 |
Feb 08 10:03:13 AM UTC 25 |
297189456 ps |
| T959 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2631845690 |
|
|
Feb 08 10:03:11 AM UTC 25 |
Feb 08 10:03:13 AM UTC 25 |
34053819 ps |
| T89 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4236637512 |
|
|
Feb 08 10:03:08 AM UTC 25 |
Feb 08 10:03:14 AM UTC 25 |
914943501 ps |
| T116 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2451314622 |
|
|
Feb 08 10:03:10 AM UTC 25 |
Feb 08 10:03:15 AM UTC 25 |
438941752 ps |
| T960 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2741593220 |
|
|
Feb 08 10:03:09 AM UTC 25 |
Feb 08 10:03:16 AM UTC 25 |
105794155 ps |
| T961 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3032591028 |
|
|
Feb 08 10:03:13 AM UTC 25 |
Feb 08 10:03:16 AM UTC 25 |
86690681 ps |
| T90 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1900771329 |
|
|
Feb 08 10:03:14 AM UTC 25 |
Feb 08 10:03:16 AM UTC 25 |
18010700 ps |
| T962 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2692756852 |
|
|
Feb 08 10:03:14 AM UTC 25 |
Feb 08 10:03:17 AM UTC 25 |
74472555 ps |
| T963 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4126070811 |
|
|
Feb 08 10:03:14 AM UTC 25 |
Feb 08 10:03:17 AM UTC 25 |
447287540 ps |
| T118 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2652784645 |
|
|
Feb 08 10:03:14 AM UTC 25 |
Feb 08 10:03:17 AM UTC 25 |
339151450 ps |
| T964 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.317536912 |
|
|
Feb 08 10:03:15 AM UTC 25 |
Feb 08 10:03:18 AM UTC 25 |
42349315 ps |
| T965 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2524577953 |
|
|
Feb 08 10:03:16 AM UTC 25 |
Feb 08 10:03:20 AM UTC 25 |
31430306 ps |
| T966 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.160616522 |
|
|
Feb 08 10:03:18 AM UTC 25 |
Feb 08 10:03:21 AM UTC 25 |
50718098 ps |
| T967 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.553859976 |
|
|
Feb 08 10:03:18 AM UTC 25 |
Feb 08 10:03:21 AM UTC 25 |
18661993 ps |
| T120 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.349074959 |
|
|
Feb 08 10:03:17 AM UTC 25 |
Feb 08 10:03:21 AM UTC 25 |
130219581 ps |
| T968 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1551966819 |
|
|
Feb 08 10:03:18 AM UTC 25 |
Feb 08 10:03:22 AM UTC 25 |
67471342 ps |
| T91 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2085854333 |
|
|
Feb 08 10:03:17 AM UTC 25 |
Feb 08 10:03:22 AM UTC 25 |
464282494 ps |
| T969 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3262398962 |
|
|
Feb 08 10:03:17 AM UTC 25 |
Feb 08 10:03:23 AM UTC 25 |
50271989 ps |
| T970 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3380578176 |
|
|
Feb 08 10:03:21 AM UTC 25 |
Feb 08 10:03:24 AM UTC 25 |
18061188 ps |
| T971 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2230064948 |
|
|
Feb 08 10:03:21 AM UTC 25 |
Feb 08 10:03:24 AM UTC 25 |
16422332 ps |
| T972 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2841488074 |
|
|
Feb 08 10:03:22 AM UTC 25 |
Feb 08 10:03:25 AM UTC 25 |
35817714 ps |
| T121 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1764952584 |
|
|
Feb 08 10:03:20 AM UTC 25 |
Feb 08 10:03:26 AM UTC 25 |
602916816 ps |
| T973 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2140299491 |
|
|
Feb 08 10:03:25 AM UTC 25 |
Feb 08 10:03:27 AM UTC 25 |
29381904 ps |
| T974 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3266411522 |
|
|
Feb 08 10:03:25 AM UTC 25 |
Feb 08 10:03:27 AM UTC 25 |
92193328 ps |
| T975 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2761672994 |
|
|
Feb 08 10:03:20 AM UTC 25 |
Feb 08 10:03:28 AM UTC 25 |
233243496 ps |
| T976 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1440512379 |
|
|
Feb 08 10:03:23 AM UTC 25 |
Feb 08 10:03:28 AM UTC 25 |
236533678 ps |
| T122 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.686163307 |
|
|
Feb 08 10:03:25 AM UTC 25 |
Feb 08 10:03:28 AM UTC 25 |
98301280 ps |
| T977 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2366469359 |
|
|
Feb 08 10:03:24 AM UTC 25 |
Feb 08 10:03:28 AM UTC 25 |
213648284 ps |
| T978 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2853229974 |
|
|
Feb 08 10:03:18 AM UTC 25 |
Feb 08 10:03:29 AM UTC 25 |
5149795789 ps |
| T979 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1276111095 |
|
|
Feb 08 10:03:26 AM UTC 25 |
Feb 08 10:03:30 AM UTC 25 |
447579084 ps |
| T980 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2341729163 |
|
|
Feb 08 10:03:29 AM UTC 25 |
Feb 08 10:03:32 AM UTC 25 |
12790849 ps |
| T981 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4071828169 |
|
|
Feb 08 10:03:29 AM UTC 25 |
Feb 08 10:03:32 AM UTC 25 |
15771114 ps |
| T982 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.65352362 |
|
|
Feb 08 10:03:27 AM UTC 25 |
Feb 08 10:03:33 AM UTC 25 |
801778357 ps |
| T983 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.670034533 |
|
|
Feb 08 10:03:29 AM UTC 25 |
Feb 08 10:03:33 AM UTC 25 |
168004362 ps |
| T984 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3465725410 |
|
|
Feb 08 10:03:28 AM UTC 25 |
Feb 08 10:03:34 AM UTC 25 |
115511649 ps |
| T123 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4028574806 |
|
|
Feb 08 10:03:28 AM UTC 25 |
Feb 08 10:03:34 AM UTC 25 |
258326436 ps |
| T985 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2864414562 |
|
|
Feb 08 10:03:32 AM UTC 25 |
Feb 08 10:03:35 AM UTC 25 |
10846380 ps |
| T986 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1220492584 |
|
|
Feb 08 10:03:32 AM UTC 25 |
Feb 08 10:03:35 AM UTC 25 |
41308318 ps |
| T124 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2805238177 |
|
|
Feb 08 10:03:31 AM UTC 25 |
Feb 08 10:03:35 AM UTC 25 |
301887839 ps |
| T987 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2440333161 |
|
|
Feb 08 10:03:30 AM UTC 25 |
Feb 08 10:03:36 AM UTC 25 |
83469859 ps |
| T988 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2472600930 |
|
|
Feb 08 10:03:34 AM UTC 25 |
Feb 08 10:03:36 AM UTC 25 |
94444759 ps |
| T989 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2308264243 |
|
|
Feb 08 10:03:29 AM UTC 25 |
Feb 08 10:03:37 AM UTC 25 |
1667306129 ps |
| T990 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3805672929 |
|
|
Feb 08 10:03:34 AM UTC 25 |
Feb 08 10:03:38 AM UTC 25 |
829364782 ps |
| T991 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4002229923 |
|
|
Feb 08 10:03:36 AM UTC 25 |
Feb 08 10:03:38 AM UTC 25 |
12708245 ps |
| T992 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1826601915 |
|
|
Feb 08 10:03:36 AM UTC 25 |
Feb 08 10:03:38 AM UTC 25 |
55283106 ps |
| T993 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.324280758 |
|
|
Feb 08 10:03:35 AM UTC 25 |
Feb 08 10:03:39 AM UTC 25 |
765660703 ps |
| T115 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3931444002 |
|
|
Feb 08 10:03:35 AM UTC 25 |
Feb 08 10:03:40 AM UTC 25 |
263934364 ps |
| T994 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3634407232 |
|
|
Feb 08 10:03:36 AM UTC 25 |
Feb 08 10:03:40 AM UTC 25 |
498453849 ps |
| T995 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2824567773 |
|
|
Feb 08 10:03:37 AM UTC 25 |
Feb 08 10:03:40 AM UTC 25 |
436763704 ps |
| T996 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.653636015 |
|
|
Feb 08 10:03:38 AM UTC 25 |
Feb 08 10:03:41 AM UTC 25 |
31181628 ps |
| T997 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3730337364 |
|
|
Feb 08 10:03:36 AM UTC 25 |
Feb 08 10:03:41 AM UTC 25 |
1679831935 ps |
| T998 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4012536299 |
|
|
Feb 08 10:03:39 AM UTC 25 |
Feb 08 10:03:42 AM UTC 25 |
88139629 ps |
| T999 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.895675493 |
|
|
Feb 08 10:03:39 AM UTC 25 |
Feb 08 10:03:43 AM UTC 25 |
47375805 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.815838527 |
|
|
Feb 08 10:03:40 AM UTC 25 |
Feb 08 10:03:43 AM UTC 25 |
17557689 ps |