Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
62.93 72.20 71.99 87.44 0.00 75.49 99.67 33.72


Total tests in report: 165
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.88 61.88 71.99 71.99 66.56 66.56 92.88 92.88 0.00 0.00 75.23 75.23 97.70 97.70 28.83 28.83 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3873084869
63.10 1.21 72.14 0.15 70.37 3.82 96.69 3.82 0.00 0.00 75.45 0.22 98.19 0.49 28.83 0.00 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2392766099
63.59 0.49 72.14 0.00 71.21 0.83 97.20 0.51 0.00 0.00 75.49 0.04 98.52 0.33 30.58 1.75 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1118335
63.95 0.35 72.14 0.00 71.31 0.10 97.20 0.00 0.00 0.00 75.49 0.00 99.51 0.99 31.97 1.39 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1382391994
64.20 0.26 72.20 0.06 71.33 0.03 97.46 0.25 0.00 0.00 75.49 0.00 99.51 0.00 33.43 1.46 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2037971933
64.27 0.07 72.20 0.00 71.79 0.46 97.46 0.00 0.00 0.00 75.49 0.00 99.51 0.00 33.43 0.00 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1927417958
64.29 0.02 72.20 0.00 71.79 0.00 97.46 0.00 0.00 0.00 75.49 0.00 99.67 0.16 33.43 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.246471710
64.31 0.02 72.20 0.00 71.79 0.00 97.46 0.00 0.00 0.00 75.49 0.00 99.67 0.00 33.58 0.15 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1045495387
64.33 0.02 72.20 0.00 71.79 0.00 97.46 0.00 0.00 0.00 75.49 0.00 99.67 0.00 33.72 0.15 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1068731782
64.34 0.01 72.20 0.00 71.81 0.03 97.46 0.00 0.00 0.00 75.49 0.00 99.67 0.00 33.72 0.00 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1146765276
64.34 0.01 72.20 0.00 71.84 0.03 97.46 0.00 0.00 0.00 75.49 0.00 99.67 0.00 33.72 0.00 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.406650376

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4129391860
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3831916058
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1130925247
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1618222162
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3534591335
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3369300985
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2435266370
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3647593415
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2493894817
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1103752078
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4166271933
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.597476210
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3845389914
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.661986026
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1253079130
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3240264899
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.95672906
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3021439778
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2062524229
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2906393517
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1451528308
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.776523930
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3691550669
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.846158201
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.362689867
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2215827454
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4110045330
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1384764624
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4085221229
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2368716010
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3953408100
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.104408491
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2472819555
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.73718777
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2560663917
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2153326166
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.192823528
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2484725147
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3484124063
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3967717058
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1152130658
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3932507842
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1021231978
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1113360741
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1751837790
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4102134055
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.4189122165
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3901918388
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3235714433
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2280430058
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3545126717
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3840982125
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3499914810
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3969358219
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3365382966
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1093567161
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2706189912
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2414762215
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3829627665
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.766087033
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1189161236
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3971632166
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2210784698
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3024220999
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2930158049
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2293753652
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3982259340
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.761748544
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4049563251
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4136096359
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2403966179
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2982084637
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.264489802
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2423538995
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2471168073
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3519084093
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3249470025
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3063149297
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.119443066
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2126398336
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1070213047
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1081875711
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3010094384
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1013924888
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2517045063
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1548184925
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.4227057093
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2819845176
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3783892123
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.756489595
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.460424391
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.741933548
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2335571067
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3492058201
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2216021509
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1755270204
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3262176087
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.923751428
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.4007871247
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1203615197
/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2887292938
/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1350656723
/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2494561927
/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3511466925
/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.4291550748
/workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.539831480
/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.470713682
/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.965287564
/workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3031292498
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.829448070
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1069137930
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4253859584
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1730984277
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4001904286
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2323935987
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3671936539
/workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1220894380
/workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.569187024
/workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.887143299
/workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.824565060
/workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2037915468
/workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1393646119
/workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3318542946
/workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3340411516
/workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1456671801
/workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1081227121
/workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3121744731
/workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3997856041
/workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1891674375
/workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2773416034
/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.731558568
/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2528906666
/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2555403755
/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1527281062
/workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2585256211
/workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.781814269
/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.803419536
/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2494595294
/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1622023010
/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3362577401
/workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3256680184
/workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2337851617
/workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2286488299
/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.81195627
/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1348955165
/workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.4033667420
/workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1106545932
/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1840190228
/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3048835810
/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1292811234
/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.4230157215
/workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3079585819
/workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2987511322
/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1695786024



Total test records in report: 165
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2323935987 Aug 14 04:37:51 PM PDT 24 Aug 14 04:38:13 PM PDT 24 7148882601 ps
T2 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2706189912 Aug 14 04:37:52 PM PDT 24 Aug 14 04:37:54 PM PDT 24 2143170905 ps
T3 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.923751428 Aug 14 04:38:00 PM PDT 24 Aug 14 04:38:09 PM PDT 24 5520991181 ps
T6 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1548184925 Aug 14 04:38:09 PM PDT 24 Aug 14 04:38:12 PM PDT 24 2021135922 ps
T4 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1068731782 Aug 14 04:37:53 PM PDT 24 Aug 14 04:38:49 PM PDT 24 22247864171 ps
T14 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.766087033 Aug 14 04:37:48 PM PDT 24 Aug 14 04:37:55 PM PDT 24 5017163338 ps
T15 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2215827454 Aug 14 04:38:03 PM PDT 24 Aug 14 04:38:08 PM PDT 24 5182562111 ps
T7 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1118335 Aug 14 04:38:33 PM PDT 24 Aug 14 04:38:41 PM PDT 24 2035523028 ps
T5 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3873084869 Aug 14 04:38:10 PM PDT 24 Aug 14 04:40:06 PM PDT 24 42482035437 ps
T8 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3063149297 Aug 14 04:38:07 PM PDT 24 Aug 14 04:38:11 PM PDT 24 2017944147 ps
T9 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.965287564 Aug 14 04:38:33 PM PDT 24 Aug 14 04:38:38 PM PDT 24 2015641610 ps
T11 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2293753652 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:24 PM PDT 24 8828237413 ps
T16 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1927417958 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:58 PM PDT 24 2044340274 ps
T23 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.829448070 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:23 PM PDT 24 2860422412 ps
T24 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1618222162 Aug 14 04:37:53 PM PDT 24 Aug 14 04:37:55 PM PDT 24 2071992490 ps
T10 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.824565060 Aug 14 04:38:30 PM PDT 24 Aug 14 04:38:36 PM PDT 24 2013136776 ps
T25 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.246471710 Aug 14 04:37:56 PM PDT 24 Aug 14 04:38:10 PM PDT 24 3168746714 ps
T26 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2037971933 Aug 14 04:38:26 PM PDT 24 Aug 14 04:38:31 PM PDT 24 2013180256 ps
T27 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2392766099 Aug 14 04:38:12 PM PDT 24 Aug 14 04:38:15 PM PDT 24 5408115434 ps
T28 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1350656723 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:22 PM PDT 24 2039232101 ps
T29 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.741933548 Aug 14 04:37:52 PM PDT 24 Aug 14 04:38:01 PM PDT 24 2901914226 ps
T17 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2210784698 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:27 PM PDT 24 2040876734 ps
T18 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3240264899 Aug 14 04:38:23 PM PDT 24 Aug 14 04:38:28 PM PDT 24 2200433615 ps
T19 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2555403755 Aug 14 04:37:47 PM PDT 24 Aug 14 04:37:53 PM PDT 24 2040040873 ps
T30 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2414762215 Aug 14 04:38:03 PM PDT 24 Aug 14 04:38:09 PM PDT 24 2038860207 ps
T20 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2435266370 Aug 14 04:38:18 PM PDT 24 Aug 14 04:38:24 PM PDT 24 2307974920 ps
T38 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.539831480 Aug 14 04:38:07 PM PDT 24 Aug 14 04:38:10 PM PDT 24 2027115643 ps
T12 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1751837790 Aug 14 04:38:01 PM PDT 24 Aug 14 04:39:56 PM PDT 24 42436509891 ps
T31 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.4189122165 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:25 PM PDT 24 2050406766 ps
T39 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3318542946 Aug 14 04:38:24 PM PDT 24 Aug 14 04:38:30 PM PDT 24 2011860509 ps
T32 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3492058201 Aug 14 04:38:23 PM PDT 24 Aug 14 04:38:26 PM PDT 24 6066852931 ps
T21 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3519084093 Aug 14 04:38:00 PM PDT 24 Aug 14 04:38:06 PM PDT 24 2046607808 ps
T55 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3010094384 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:28 PM PDT 24 2013602679 ps
T22 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3967717058 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:26 PM PDT 24 2132196720 ps
T56 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3340411516 Aug 14 04:38:33 PM PDT 24 Aug 14 04:38:35 PM PDT 24 2031348205 ps
T57 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3262176087 Aug 14 04:38:13 PM PDT 24 Aug 14 04:38:18 PM PDT 24 2012582095 ps
T58 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3783892123 Aug 14 04:38:37 PM PDT 24 Aug 14 04:38:39 PM PDT 24 2032015924 ps
T47 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.776523930 Aug 14 04:38:02 PM PDT 24 Aug 14 04:38:09 PM PDT 24 2047511984 ps
T33 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3831916058 Aug 14 04:37:46 PM PDT 24 Aug 14 04:37:49 PM PDT 24 6072025005 ps
T59 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4001904286 Aug 14 04:38:09 PM PDT 24 Aug 14 04:38:11 PM PDT 24 2024817150 ps
T44 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3969358219 Aug 14 04:38:28 PM PDT 24 Aug 14 04:38:34 PM PDT 24 4430703408 ps
T13 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2423538995 Aug 14 04:37:54 PM PDT 24 Aug 14 04:38:01 PM PDT 24 22188232689 ps
T34 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.119443066 Aug 14 04:38:02 PM PDT 24 Aug 14 04:38:51 PM PDT 24 10696539747 ps
T60 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1045495387 Aug 14 04:37:46 PM PDT 24 Aug 14 04:37:48 PM PDT 24 2034273344 ps
T48 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1840190228 Aug 14 04:38:08 PM PDT 24 Aug 14 04:38:14 PM PDT 24 2032010537 ps
T53 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1070213047 Aug 14 04:37:47 PM PDT 24 Aug 14 04:39:40 PM PDT 24 42389216537 ps
T46 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1146765276 Aug 14 04:37:50 PM PDT 24 Aug 14 04:38:48 PM PDT 24 22174000557 ps
T51 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2982084637 Aug 14 04:38:23 PM PDT 24 Aug 14 04:38:28 PM PDT 24 2076892895 ps
T35 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1382391994 Aug 14 04:38:20 PM PDT 24 Aug 14 04:39:42 PM PDT 24 66194226471 ps
T61 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.4291550748 Aug 14 04:38:25 PM PDT 24 Aug 14 04:38:27 PM PDT 24 2059580313 ps
T52 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3971632166 Aug 14 04:37:52 PM PDT 24 Aug 14 04:38:20 PM PDT 24 42902387950 ps
T62 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2585256211 Aug 14 04:38:02 PM PDT 24 Aug 14 04:38:05 PM PDT 24 2021179364 ps
T36 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2335571067 Aug 14 04:37:46 PM PDT 24 Aug 14 04:38:50 PM PDT 24 24139467557 ps
T37 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1069137930 Aug 14 04:38:28 PM PDT 24 Aug 14 04:38:32 PM PDT 24 4057080788 ps
T40 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4166271933 Aug 14 04:38:06 PM PDT 24 Aug 14 04:38:11 PM PDT 24 6100413993 ps
T63 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3256680184 Aug 14 04:37:59 PM PDT 24 Aug 14 04:38:06 PM PDT 24 2010575437 ps
T64 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1021231978 Aug 14 04:38:05 PM PDT 24 Aug 14 04:38:18 PM PDT 24 4607209419 ps
T49 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.95672906 Aug 14 04:37:47 PM PDT 24 Aug 14 04:38:14 PM PDT 24 22229730447 ps
T65 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3511466925 Aug 14 04:37:52 PM PDT 24 Aug 14 04:37:55 PM PDT 24 2023319604 ps
T66 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.731558568 Aug 14 04:37:49 PM PDT 24 Aug 14 04:37:57 PM PDT 24 2126053043 ps
T67 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1106545932 Aug 14 04:38:39 PM PDT 24 Aug 14 04:39:02 PM PDT 24 8550535119 ps
T68 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2126398336 Aug 14 04:37:59 PM PDT 24 Aug 14 04:38:05 PM PDT 24 2072075333 ps
T69 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3031292498 Aug 14 04:38:25 PM PDT 24 Aug 14 04:38:27 PM PDT 24 2037862124 ps
T45 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.406650376 Aug 14 04:38:11 PM PDT 24 Aug 14 04:39:55 PM PDT 24 42499674648 ps
T70 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.362689867 Aug 14 04:38:32 PM PDT 24 Aug 14 04:38:35 PM PDT 24 2071768377 ps
T71 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3249470025 Aug 14 04:38:12 PM PDT 24 Aug 14 04:38:17 PM PDT 24 2034895909 ps
T72 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.887143299 Aug 14 04:38:16 PM PDT 24 Aug 14 04:38:20 PM PDT 24 2019783579 ps
T73 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2906393517 Aug 14 04:38:10 PM PDT 24 Aug 14 04:38:12 PM PDT 24 2037213769 ps
T74 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3953408100 Aug 14 04:37:57 PM PDT 24 Aug 14 04:38:00 PM PDT 24 2023368804 ps
T75 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.192823528 Aug 14 04:37:55 PM PDT 24 Aug 14 04:38:19 PM PDT 24 9606183954 ps
T76 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.470713682 Aug 14 04:38:30 PM PDT 24 Aug 14 04:38:36 PM PDT 24 2013928408 ps
T77 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3545126717 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:53 PM PDT 24 2072791962 ps
T78 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3362577401 Aug 14 04:38:16 PM PDT 24 Aug 14 04:38:22 PM PDT 24 2027226440 ps
T79 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2037915468 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:24 PM PDT 24 2031035557 ps
T80 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.81195627 Aug 14 04:38:34 PM PDT 24 Aug 14 04:38:36 PM PDT 24 2224832765 ps
T81 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.661986026 Aug 14 04:37:52 PM PDT 24 Aug 14 04:37:53 PM PDT 24 2091078769 ps
T82 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3369300985 Aug 14 04:38:08 PM PDT 24 Aug 14 04:38:12 PM PDT 24 4704155919 ps
T50 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.4007871247 Aug 14 04:37:52 PM PDT 24 Aug 14 04:38:00 PM PDT 24 2044793021 ps
T83 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1253079130 Aug 14 04:38:04 PM PDT 24 Aug 14 04:38:13 PM PDT 24 9883534219 ps
T84 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4110045330 Aug 14 04:38:25 PM PDT 24 Aug 14 04:38:27 PM PDT 24 2137081403 ps
T85 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.73718777 Aug 14 04:37:52 PM PDT 24 Aug 14 04:37:57 PM PDT 24 2042683278 ps
T86 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1622023010 Aug 14 04:38:10 PM PDT 24 Aug 14 04:38:13 PM PDT 24 2137004883 ps
T87 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4136096359 Aug 14 04:38:05 PM PDT 24 Aug 14 04:38:15 PM PDT 24 2014013845 ps
T88 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.803419536 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:53 PM PDT 24 2097199175 ps
T89 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.460424391 Aug 14 04:38:24 PM PDT 24 Aug 14 04:38:27 PM PDT 24 2028023837 ps
T90 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2153326166 Aug 14 04:38:08 PM PDT 24 Aug 14 04:38:10 PM PDT 24 2040954685 ps
T91 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1384764624 Aug 14 04:37:53 PM PDT 24 Aug 14 04:38:07 PM PDT 24 43876373767 ps
T92 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3048835810 Aug 14 04:38:11 PM PDT 24 Aug 14 04:38:40 PM PDT 24 42523929844 ps
T93 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1451528308 Aug 14 04:37:51 PM PDT 24 Aug 14 04:37:54 PM PDT 24 5862920530 ps
T94 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2930158049 Aug 14 04:37:49 PM PDT 24 Aug 14 04:37:51 PM PDT 24 2068503827 ps
T95 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4253859584 Aug 14 04:37:48 PM PDT 24 Aug 14 04:37:51 PM PDT 24 2096530443 ps
T42 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1730984277 Aug 14 04:38:16 PM PDT 24 Aug 14 04:38:20 PM PDT 24 2063809874 ps
T96 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2560663917 Aug 14 04:38:02 PM PDT 24 Aug 14 04:38:04 PM PDT 24 2046860805 ps
T97 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1013924888 Aug 14 04:38:16 PM PDT 24 Aug 14 04:38:19 PM PDT 24 2025375646 ps
T98 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1292811234 Aug 14 04:38:11 PM PDT 24 Aug 14 04:38:17 PM PDT 24 2065345499 ps
T99 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2773416034 Aug 14 04:38:10 PM PDT 24 Aug 14 04:38:13 PM PDT 24 5265364776 ps
T41 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.264489802 Aug 14 04:38:02 PM PDT 24 Aug 14 04:38:06 PM PDT 24 2537816164 ps
T43 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1152130658 Aug 14 04:38:32 PM PDT 24 Aug 14 04:38:35 PM PDT 24 2056323249 ps
T100 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1891674375 Aug 14 04:37:49 PM PDT 24 Aug 14 04:37:52 PM PDT 24 2018225049 ps
T101 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3024220999 Aug 14 04:37:59 PM PDT 24 Aug 14 04:38:05 PM PDT 24 2028537313 ps
T102 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2494595294 Aug 14 04:38:00 PM PDT 24 Aug 14 04:38:08 PM PDT 24 22728534628 ps
T103 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3840982125 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:54 PM PDT 24 2063486148 ps
T104 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3671936539 Aug 14 04:38:00 PM PDT 24 Aug 14 04:38:03 PM PDT 24 3634878729 ps
T105 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3499914810 Aug 14 04:37:55 PM PDT 24 Aug 14 04:38:00 PM PDT 24 2011112808 ps
T106 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2062524229 Aug 14 04:38:03 PM PDT 24 Aug 14 04:38:05 PM PDT 24 2178308431 ps
T107 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2517045063 Aug 14 04:38:30 PM PDT 24 Aug 14 04:38:32 PM PDT 24 2034132557 ps
T108 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2472819555 Aug 14 04:37:51 PM PDT 24 Aug 14 04:38:19 PM PDT 24 42526603272 ps
T109 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3021439778 Aug 14 04:37:48 PM PDT 24 Aug 14 04:37:50 PM PDT 24 2128151770 ps
T110 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2471168073 Aug 14 04:38:10 PM PDT 24 Aug 14 04:38:16 PM PDT 24 4017908079 ps
T111 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.761748544 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:56 PM PDT 24 2044608804 ps
T112 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1456671801 Aug 14 04:38:21 PM PDT 24 Aug 14 04:38:27 PM PDT 24 2013181893 ps
T54 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2280430058 Aug 14 04:37:53 PM PDT 24 Aug 14 04:39:27 PM PDT 24 42467286572 ps
T113 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1103752078 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:37 PM PDT 24 14365996583 ps
T114 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1203615197 Aug 14 04:38:24 PM PDT 24 Aug 14 04:39:52 PM PDT 24 42454602290 ps
T115 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.4230157215 Aug 14 04:38:13 PM PDT 24 Aug 14 04:38:15 PM PDT 24 2093442898 ps
T116 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.4227057093 Aug 14 04:38:12 PM PDT 24 Aug 14 04:38:14 PM PDT 24 2077938643 ps
T117 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2887292938 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:52 PM PDT 24 2041483666 ps
T118 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1220894380 Aug 14 04:38:33 PM PDT 24 Aug 14 04:38:39 PM PDT 24 2014151805 ps
T119 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2286488299 Aug 14 04:38:06 PM PDT 24 Aug 14 04:38:23 PM PDT 24 22387537752 ps
T120 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1527281062 Aug 14 04:38:07 PM PDT 24 Aug 14 04:38:13 PM PDT 24 2054964623 ps
T121 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4049563251 Aug 14 04:38:20 PM PDT 24 Aug 14 04:38:26 PM PDT 24 2048851723 ps
T122 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.846158201 Aug 14 04:37:57 PM PDT 24 Aug 14 04:38:03 PM PDT 24 2082324776 ps
T123 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4129391860 Aug 14 04:38:02 PM PDT 24 Aug 14 04:38:57 PM PDT 24 75333790327 ps
T124 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4085221229 Aug 14 04:38:12 PM PDT 24 Aug 14 04:38:17 PM PDT 24 2095238042 ps
T125 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2494561927 Aug 14 04:38:27 PM PDT 24 Aug 14 04:38:33 PM PDT 24 2010840635 ps
T126 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2819845176 Aug 14 04:38:27 PM PDT 24 Aug 14 04:38:30 PM PDT 24 2025374452 ps
T127 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3845389914 Aug 14 04:37:48 PM PDT 24 Aug 14 04:37:54 PM PDT 24 2027028678 ps
T128 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1081875711 Aug 14 04:38:23 PM PDT 24 Aug 14 04:38:24 PM PDT 24 2121713515 ps
T129 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.781814269 Aug 14 04:38:03 PM PDT 24 Aug 14 04:38:08 PM PDT 24 4129972524 ps
T130 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1348955165 Aug 14 04:37:56 PM PDT 24 Aug 14 04:37:58 PM PDT 24 2090540010 ps
T131 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2987511322 Aug 14 04:38:06 PM PDT 24 Aug 14 04:38:10 PM PDT 24 5280858046 ps
T132 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4102134055 Aug 14 04:38:28 PM PDT 24 Aug 14 04:38:34 PM PDT 24 2065234126 ps
T133 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2337851617 Aug 14 04:38:08 PM PDT 24 Aug 14 04:38:21 PM PDT 24 5000844931 ps
T134 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2484725147 Aug 14 04:38:07 PM PDT 24 Aug 14 04:38:11 PM PDT 24 2371672508 ps
T135 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1695786024 Aug 14 04:38:11 PM PDT 24 Aug 14 04:38:14 PM PDT 24 2227767638 ps
T136 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2403966179 Aug 14 04:38:09 PM PDT 24 Aug 14 04:38:30 PM PDT 24 8208619870 ps
T137 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3484124063 Aug 14 04:37:49 PM PDT 24 Aug 14 04:38:18 PM PDT 24 22291644006 ps
T138 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1093567161 Aug 14 04:38:22 PM PDT 24 Aug 14 04:39:16 PM PDT 24 42417319610 ps
T139 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3982259340 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:54 PM PDT 24 2165646585 ps
T140 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3691550669 Aug 14 04:38:01 PM PDT 24 Aug 14 04:38:29 PM PDT 24 22320172801 ps
T141 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3079585819 Aug 14 04:38:11 PM PDT 24 Aug 14 04:38:12 PM PDT 24 2127980026 ps
T142 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.756489595 Aug 14 04:38:23 PM PDT 24 Aug 14 04:38:27 PM PDT 24 2023913464 ps
T143 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1130925247 Aug 14 04:38:22 PM PDT 24 Aug 14 04:38:26 PM PDT 24 2110697673 ps
T144 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3235714433 Aug 14 04:38:24 PM PDT 24 Aug 14 04:38:42 PM PDT 24 10395484698 ps
T145 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2493894817 Aug 14 04:37:48 PM PDT 24 Aug 14 04:38:00 PM PDT 24 3239172739 ps
T146 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1113360741 Aug 14 04:37:57 PM PDT 24 Aug 14 04:37:59 PM PDT 24 2636581156 ps
T147 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3647593415 Aug 14 04:38:00 PM PDT 24 Aug 14 04:38:29 PM PDT 24 42532492293 ps
T148 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1189161236 Aug 14 04:38:05 PM PDT 24 Aug 14 04:38:11 PM PDT 24 2042965209 ps
T149 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2528906666 Aug 14 04:38:14 PM PDT 24 Aug 14 04:38:38 PM PDT 24 22369047190 ps
T150 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2368716010 Aug 14 04:37:52 PM PDT 24 Aug 14 04:38:09 PM PDT 24 2065832598 ps
T151 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1081227121 Aug 14 04:38:17 PM PDT 24 Aug 14 04:38:21 PM PDT 24 2016661329 ps
T152 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.104408491 Aug 14 04:37:51 PM PDT 24 Aug 14 04:38:03 PM PDT 24 2050471218 ps
T153 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1393646119 Aug 14 04:38:14 PM PDT 24 Aug 14 04:38:19 PM PDT 24 2012056613 ps
T154 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3365382966 Aug 14 04:38:05 PM PDT 24 Aug 14 04:38:08 PM PDT 24 2148160071 ps
T155 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2216021509 Aug 14 04:37:52 PM PDT 24 Aug 14 04:37:54 PM PDT 24 2287503087 ps
T156 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3997856041 Aug 14 04:38:18 PM PDT 24 Aug 14 04:38:25 PM PDT 24 2062303845 ps
T157 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3901918388 Aug 14 04:38:07 PM PDT 24 Aug 14 04:38:13 PM PDT 24 2011033594 ps
T158 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3121744731 Aug 14 04:38:03 PM PDT 24 Aug 14 04:38:05 PM PDT 24 2106091632 ps
T159 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3829627665 Aug 14 04:38:23 PM PDT 24 Aug 14 04:38:26 PM PDT 24 2021280068 ps
T160 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1755270204 Aug 14 04:37:55 PM PDT 24 Aug 14 04:38:01 PM PDT 24 2029914660 ps
T161 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.597476210 Aug 14 04:38:26 PM PDT 24 Aug 14 04:38:30 PM PDT 24 2072286568 ps
T162 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.569187024 Aug 14 04:38:14 PM PDT 24 Aug 14 04:38:16 PM PDT 24 2032257624 ps
T163 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.4033667420 Aug 14 04:38:12 PM PDT 24 Aug 14 04:38:18 PM PDT 24 2010255323 ps
T164 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3534591335 Aug 14 04:37:50 PM PDT 24 Aug 14 04:37:52 PM PDT 24 2034949781 ps
T165 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3932507842 Aug 14 04:37:51 PM PDT 24 Aug 14 04:37:52 PM PDT 24 2107625505 ps

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3873084869
Short name T5
Test name
Test status
Simulation time 42482035437 ps
CPU time 114.95 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:40:06 PM PDT 24
Peak memory 201464 kb
Host smart-37f6fc54-54cb-4608-a7ae-d7b8c02cbbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873084869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.3873084869
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2392766099
Short name T27
Test name
Test status
Simulation time 5408115434 ps
CPU time 2.2 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 201480 kb
Host smart-dc237d9a-2d40-49f8-8841-7e051ab27b26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392766099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.2392766099
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1118335
Short name T7
Test name
Test status
Simulation time 2035523028 ps
CPU time 7.07 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:41 PM PDT 24
Peak memory 201232 kb
Host smart-a0c17c8c-7da2-4271-94fa-07a560226b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.1118335
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1382391994
Short name T35
Test name
Test status
Simulation time 66194226471 ps
CPU time 81.9 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:39:42 PM PDT 24
Peak memory 201228 kb
Host smart-f04ed8c1-0101-4cfe-a16d-29a93d0d0600
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382391994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.1382391994
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2037971933
Short name T26
Test name
Test status
Simulation time 2013180256 ps
CPU time 5.32 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:31 PM PDT 24
Peak memory 200652 kb
Host smart-0df00805-13dd-476d-bb31-68f3ef4cfb21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037971933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.2037971933
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1927417958
Short name T16
Test name
Test status
Simulation time 2044340274 ps
CPU time 7.45 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:58 PM PDT 24
Peak memory 201244 kb
Host smart-98434354-df3c-46d1-afc9-259705ac3801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927417958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1927417958
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.246471710
Short name T25
Test name
Test status
Simulation time 3168746714 ps
CPU time 13.93 seconds
Started Aug 14 04:37:56 PM PDT 24
Finished Aug 14 04:38:10 PM PDT 24
Peak memory 200956 kb
Host smart-f8bb57f7-3661-4e16-925b-2cd0fa2826e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246471710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_aliasing.246471710
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1045495387
Short name T60
Test name
Test status
Simulation time 2034273344 ps
CPU time 1.95 seconds
Started Aug 14 04:37:46 PM PDT 24
Finished Aug 14 04:37:48 PM PDT 24
Peak memory 200652 kb
Host smart-8c759705-9e5d-47c6-bd15-77daacbaefab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045495387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.1045495387
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1068731782
Short name T4
Test name
Test status
Simulation time 22247864171 ps
CPU time 56.01 seconds
Started Aug 14 04:37:53 PM PDT 24
Finished Aug 14 04:38:49 PM PDT 24
Peak memory 201348 kb
Host smart-90ba1401-fdf9-4607-8199-40641a5df53e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068731782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.1068731782
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1146765276
Short name T46
Test name
Test status
Simulation time 22174000557 ps
CPU time 57.53 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:38:48 PM PDT 24
Peak memory 201304 kb
Host smart-a19b39a8-378d-420a-8b7f-463c6e833dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146765276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.1146765276
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.406650376
Short name T45
Test name
Test status
Simulation time 42499674648 ps
CPU time 103.47 seconds
Started Aug 14 04:38:11 PM PDT 24
Finished Aug 14 04:39:55 PM PDT 24
Peak memory 201336 kb
Host smart-1be4b114-c1dc-4f96-85bc-483e9eae84b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406650376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_tl_intg_err.406650376
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4129391860
Short name T123
Test name
Test status
Simulation time 75333790327 ps
CPU time 54.77 seconds
Started Aug 14 04:38:02 PM PDT 24
Finished Aug 14 04:38:57 PM PDT 24
Peak memory 201148 kb
Host smart-ad4d3b33-9f9f-4856-a87e-52e17bb48854
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129391860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.4129391860
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3831916058
Short name T33
Test name
Test status
Simulation time 6072025005 ps
CPU time 2.63 seconds
Started Aug 14 04:37:46 PM PDT 24
Finished Aug 14 04:37:49 PM PDT 24
Peak memory 200944 kb
Host smart-12eb74c4-be45-4332-b2de-b6f3fa3628ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831916058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3831916058
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1130925247
Short name T143
Test name
Test status
Simulation time 2110697673 ps
CPU time 3.66 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:26 PM PDT 24
Peak memory 201088 kb
Host smart-ee763202-fb4b-4fb6-90d6-0ddf5b006ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130925247 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1130925247
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1618222162
Short name T24
Test name
Test status
Simulation time 2071992490 ps
CPU time 2.03 seconds
Started Aug 14 04:37:53 PM PDT 24
Finished Aug 14 04:37:55 PM PDT 24
Peak memory 200788 kb
Host smart-1fba4c07-7d09-4410-87cd-e2d3cbaae1f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618222162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1618222162
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3534591335
Short name T164
Test name
Test status
Simulation time 2034949781 ps
CPU time 1.98 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:52 PM PDT 24
Peak memory 200740 kb
Host smart-c0b54956-20ca-4886-9893-c3034fd25513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534591335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.3534591335
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3369300985
Short name T82
Test name
Test status
Simulation time 4704155919 ps
CPU time 4.12 seconds
Started Aug 14 04:38:08 PM PDT 24
Finished Aug 14 04:38:12 PM PDT 24
Peak memory 201304 kb
Host smart-247c192f-4c6d-4a6b-b545-1123d7f46b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369300985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.3369300985
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2435266370
Short name T20
Test name
Test status
Simulation time 2307974920 ps
CPU time 5.42 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 209696 kb
Host smart-ad658856-c711-4442-9b84-0366d40c6f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435266370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.2435266370
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3647593415
Short name T147
Test name
Test status
Simulation time 42532492293 ps
CPU time 28.92 seconds
Started Aug 14 04:38:00 PM PDT 24
Finished Aug 14 04:38:29 PM PDT 24
Peak memory 201272 kb
Host smart-63ce408b-74cb-4bec-a8b2-15ed0bec06fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647593415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.3647593415
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2493894817
Short name T145
Test name
Test status
Simulation time 3239172739 ps
CPU time 11.41 seconds
Started Aug 14 04:37:48 PM PDT 24
Finished Aug 14 04:38:00 PM PDT 24
Peak memory 201128 kb
Host smart-cc412ebd-0cb5-4a5a-b676-f69734380d7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493894817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.2493894817
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1103752078
Short name T113
Test name
Test status
Simulation time 14365996583 ps
CPU time 17.51 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:37 PM PDT 24
Peak memory 201228 kb
Host smart-433e7686-9982-4a98-bdda-fd703bba666e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103752078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.1103752078
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4166271933
Short name T40
Test name
Test status
Simulation time 6100413993 ps
CPU time 4.96 seconds
Started Aug 14 04:38:06 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 201028 kb
Host smart-5a601a65-481c-4c5e-adf7-0aad8e7e3f7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166271933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.4166271933
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.597476210
Short name T161
Test name
Test status
Simulation time 2072286568 ps
CPU time 3.46 seconds
Started Aug 14 04:38:26 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 201088 kb
Host smart-c878b731-b1d0-4537-8ef6-22d27397d57d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597476210 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.597476210
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3845389914
Short name T127
Test name
Test status
Simulation time 2027028678 ps
CPU time 5.81 seconds
Started Aug 14 04:37:48 PM PDT 24
Finished Aug 14 04:37:54 PM PDT 24
Peak memory 200796 kb
Host smart-c565a9f4-de98-48aa-8bb2-2913b8d3fc74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845389914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3845389914
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.661986026
Short name T81
Test name
Test status
Simulation time 2091078769 ps
CPU time 1.45 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:37:53 PM PDT 24
Peak memory 200736 kb
Host smart-230928db-e41f-4fc9-9884-999c53a00cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661986026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.661986026
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1253079130
Short name T83
Test name
Test status
Simulation time 9883534219 ps
CPU time 8.65 seconds
Started Aug 14 04:38:04 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 201284 kb
Host smart-90208b9c-1ad5-47b4-a011-7dba140065dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253079130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.1253079130
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3240264899
Short name T18
Test name
Test status
Simulation time 2200433615 ps
CPU time 4.67 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 201244 kb
Host smart-47c145dd-fe91-4e59-8b71-f654bc362c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240264899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.3240264899
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.95672906
Short name T49
Test name
Test status
Simulation time 22229730447 ps
CPU time 26.45 seconds
Started Aug 14 04:37:47 PM PDT 24
Finished Aug 14 04:38:14 PM PDT 24
Peak memory 201220 kb
Host smart-6f17baba-b167-4cc6-a210-395770b798d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95672906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_tl_intg_err.95672906
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3021439778
Short name T109
Test name
Test status
Simulation time 2128151770 ps
CPU time 1.82 seconds
Started Aug 14 04:37:48 PM PDT 24
Finished Aug 14 04:37:50 PM PDT 24
Peak memory 200972 kb
Host smart-72d59830-546a-4f81-a20a-7070defc4049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021439778 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3021439778
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2062524229
Short name T106
Test name
Test status
Simulation time 2178308431 ps
CPU time 1.17 seconds
Started Aug 14 04:38:03 PM PDT 24
Finished Aug 14 04:38:05 PM PDT 24
Peak memory 200932 kb
Host smart-f682a63d-3b6c-4831-950d-6fc9f0d0ca20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062524229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.2062524229
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2906393517
Short name T73
Test name
Test status
Simulation time 2037213769 ps
CPU time 2.31 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:38:12 PM PDT 24
Peak memory 200736 kb
Host smart-42e76abf-0f0c-44c2-892e-42d2ba53bfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906393517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.2906393517
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1451528308
Short name T93
Test name
Test status
Simulation time 5862920530 ps
CPU time 2.44 seconds
Started Aug 14 04:37:51 PM PDT 24
Finished Aug 14 04:37:54 PM PDT 24
Peak memory 201148 kb
Host smart-a32cb65e-e1be-4950-8a47-7e454c9eb4b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451528308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1451528308
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.776523930
Short name T47
Test name
Test status
Simulation time 2047511984 ps
CPU time 7.62 seconds
Started Aug 14 04:38:02 PM PDT 24
Finished Aug 14 04:38:09 PM PDT 24
Peak memory 201080 kb
Host smart-a16bcd48-8498-4890-8b8e-c2d4a8a78cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776523930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.776523930
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3691550669
Short name T140
Test name
Test status
Simulation time 22320172801 ps
CPU time 28.83 seconds
Started Aug 14 04:38:01 PM PDT 24
Finished Aug 14 04:38:29 PM PDT 24
Peak memory 201208 kb
Host smart-8ed00682-e716-4daf-88c1-a70aba18a558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691550669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3691550669
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.846158201
Short name T122
Test name
Test status
Simulation time 2082324776 ps
CPU time 5.79 seconds
Started Aug 14 04:37:57 PM PDT 24
Finished Aug 14 04:38:03 PM PDT 24
Peak memory 201300 kb
Host smart-ae5dfd42-a9e7-441f-a3d2-31a7a5f0f209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846158201 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.846158201
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.362689867
Short name T70
Test name
Test status
Simulation time 2071768377 ps
CPU time 2.32 seconds
Started Aug 14 04:38:32 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 200944 kb
Host smart-0dcb5f79-e483-4459-a3af-1e472c9fac99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362689867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_r
w.362689867
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2215827454
Short name T15
Test name
Test status
Simulation time 5182562111 ps
CPU time 4.07 seconds
Started Aug 14 04:38:03 PM PDT 24
Finished Aug 14 04:38:08 PM PDT 24
Peak memory 201260 kb
Host smart-d4ba348b-7f40-43c1-92cd-4ff1ef0ad5d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215827454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.2215827454
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4110045330
Short name T84
Test name
Test status
Simulation time 2137081403 ps
CPU time 2.46 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 201032 kb
Host smart-c690e0c8-1a60-4807-ad4e-9c7f6e4dd08d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110045330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.4110045330
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1384764624
Short name T91
Test name
Test status
Simulation time 43876373767 ps
CPU time 13.2 seconds
Started Aug 14 04:37:53 PM PDT 24
Finished Aug 14 04:38:07 PM PDT 24
Peak memory 201280 kb
Host smart-f647ed39-a0aa-4171-9cff-ca2df99a1db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384764624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.1384764624
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4085221229
Short name T124
Test name
Test status
Simulation time 2095238042 ps
CPU time 4.98 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 201000 kb
Host smart-70df6dcd-7036-4284-98e3-1aa1a19651c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085221229 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4085221229
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2368716010
Short name T150
Test name
Test status
Simulation time 2065832598 ps
CPU time 6.4 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:38:09 PM PDT 24
Peak memory 200848 kb
Host smart-c467bc15-be45-4fa6-8822-487e61721266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368716010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.2368716010
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3953408100
Short name T74
Test name
Test status
Simulation time 2023368804 ps
CPU time 2.92 seconds
Started Aug 14 04:37:57 PM PDT 24
Finished Aug 14 04:38:00 PM PDT 24
Peak memory 200828 kb
Host smart-b0e4922d-abea-46ee-8157-e707daad4f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953408100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3953408100
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.104408491
Short name T152
Test name
Test status
Simulation time 2050471218 ps
CPU time 6.56 seconds
Started Aug 14 04:37:51 PM PDT 24
Finished Aug 14 04:38:03 PM PDT 24
Peak memory 201112 kb
Host smart-aba675d9-2357-46cc-895b-1486ba8c6205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104408491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error
s.104408491
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2472819555
Short name T108
Test name
Test status
Simulation time 42526603272 ps
CPU time 28.24 seconds
Started Aug 14 04:37:51 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 201224 kb
Host smart-30ead18c-df7a-4bae-9053-4bb3c021880b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472819555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.2472819555
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.73718777
Short name T85
Test name
Test status
Simulation time 2042683278 ps
CPU time 5.73 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:37:57 PM PDT 24
Peak memory 200996 kb
Host smart-d7626b74-d6ec-4343-b3ba-894486f4871f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73718777 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.73718777
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2560663917
Short name T96
Test name
Test status
Simulation time 2046860805 ps
CPU time 1.96 seconds
Started Aug 14 04:38:02 PM PDT 24
Finished Aug 14 04:38:04 PM PDT 24
Peak memory 200868 kb
Host smart-94c63188-0fb2-4bdb-89f3-c1e8137103a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560663917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2560663917
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2153326166
Short name T90
Test name
Test status
Simulation time 2040954685 ps
CPU time 1.85 seconds
Started Aug 14 04:38:08 PM PDT 24
Finished Aug 14 04:38:10 PM PDT 24
Peak memory 200652 kb
Host smart-eb3d9b02-0d06-43f3-b670-c6092b6dfd42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153326166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.2153326166
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.192823528
Short name T75
Test name
Test status
Simulation time 9606183954 ps
CPU time 23.82 seconds
Started Aug 14 04:37:55 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 201184 kb
Host smart-b9062408-e46f-45ac-bbe1-3d03aa79718a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192823528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.sysrst_ctrl_same_csr_outstanding.192823528
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2484725147
Short name T134
Test name
Test status
Simulation time 2371672508 ps
CPU time 3.46 seconds
Started Aug 14 04:38:07 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 201240 kb
Host smart-43957f7a-7da9-4d39-96a3-413475e10214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484725147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.2484725147
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3484124063
Short name T137
Test name
Test status
Simulation time 22291644006 ps
CPU time 29.58 seconds
Started Aug 14 04:37:49 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 201236 kb
Host smart-02b0e687-bd31-4c5d-bbdb-6695d39c64be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484124063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.3484124063
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3967717058
Short name T22
Test name
Test status
Simulation time 2132196720 ps
CPU time 3.84 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:26 PM PDT 24
Peak memory 200936 kb
Host smart-67ee7991-d1d3-4f7d-ba6a-9a150f03de0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967717058 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3967717058
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1152130658
Short name T43
Test name
Test status
Simulation time 2056323249 ps
CPU time 3.28 seconds
Started Aug 14 04:38:32 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 200912 kb
Host smart-0e96fae9-2096-4300-afc6-8ac41bb067ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152130658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.1152130658
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3932507842
Short name T165
Test name
Test status
Simulation time 2107625505 ps
CPU time 1 seconds
Started Aug 14 04:37:51 PM PDT 24
Finished Aug 14 04:37:52 PM PDT 24
Peak memory 200752 kb
Host smart-38699b75-0fc0-453e-abc4-2bd23b4fe478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932507842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3932507842
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1021231978
Short name T64
Test name
Test status
Simulation time 4607209419 ps
CPU time 13.24 seconds
Started Aug 14 04:38:05 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 200920 kb
Host smart-74ef603f-2402-4966-892a-57c174d613f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021231978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.1021231978
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1113360741
Short name T146
Test name
Test status
Simulation time 2636581156 ps
CPU time 2.24 seconds
Started Aug 14 04:37:57 PM PDT 24
Finished Aug 14 04:37:59 PM PDT 24
Peak memory 201148 kb
Host smart-665921dd-505f-4ffb-866f-0409eb20ca41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113360741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.1113360741
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1751837790
Short name T12
Test name
Test status
Simulation time 42436509891 ps
CPU time 114.92 seconds
Started Aug 14 04:38:01 PM PDT 24
Finished Aug 14 04:39:56 PM PDT 24
Peak memory 201312 kb
Host smart-76d80214-4cc4-43e6-8060-30a3f837d8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751837790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1751837790
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4102134055
Short name T132
Test name
Test status
Simulation time 2065234126 ps
CPU time 6.11 seconds
Started Aug 14 04:38:28 PM PDT 24
Finished Aug 14 04:38:34 PM PDT 24
Peak memory 216504 kb
Host smart-c8e15e44-6bba-43ef-a570-23dfb874b899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102134055 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4102134055
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.4189122165
Short name T31
Test name
Test status
Simulation time 2050406766 ps
CPU time 1.97 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 200896 kb
Host smart-75e323cd-7150-4102-b9c6-62921f0f3684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189122165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.4189122165
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3901918388
Short name T157
Test name
Test status
Simulation time 2011033594 ps
CPU time 5.79 seconds
Started Aug 14 04:38:07 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 201000 kb
Host smart-f961655a-a2af-4fc8-bd01-f287df79cbdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901918388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.3901918388
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3235714433
Short name T144
Test name
Test status
Simulation time 10395484698 ps
CPU time 17.72 seconds
Started Aug 14 04:38:24 PM PDT 24
Finished Aug 14 04:38:42 PM PDT 24
Peak memory 201208 kb
Host smart-d06ac72a-64e4-4b2e-9aea-ce1bf149623c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235714433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.3235714433
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2280430058
Short name T54
Test name
Test status
Simulation time 42467286572 ps
CPU time 93.93 seconds
Started Aug 14 04:37:53 PM PDT 24
Finished Aug 14 04:39:27 PM PDT 24
Peak memory 201248 kb
Host smart-34a76d84-ab4a-477b-aa58-463fe4d7dfaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280430058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.2280430058
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3545126717
Short name T77
Test name
Test status
Simulation time 2072791962 ps
CPU time 3.51 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:53 PM PDT 24
Peak memory 209364 kb
Host smart-dcb51413-3661-4337-a84c-5a6b438f2226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545126717 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3545126717
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3840982125
Short name T103
Test name
Test status
Simulation time 2063486148 ps
CPU time 3.77 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:54 PM PDT 24
Peak memory 200896 kb
Host smart-530bbf66-d557-4604-94b8-5c041d3af56f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840982125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3840982125
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3499914810
Short name T105
Test name
Test status
Simulation time 2011112808 ps
CPU time 5.72 seconds
Started Aug 14 04:37:55 PM PDT 24
Finished Aug 14 04:38:00 PM PDT 24
Peak memory 200696 kb
Host smart-2be5ea1d-f1e5-4a4c-9b52-3b7a6cc87c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499914810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.3499914810
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3969358219
Short name T44
Test name
Test status
Simulation time 4430703408 ps
CPU time 5.97 seconds
Started Aug 14 04:38:28 PM PDT 24
Finished Aug 14 04:38:34 PM PDT 24
Peak memory 200988 kb
Host smart-c34404d1-4583-4209-a835-73b2af714815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969358219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.3969358219
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3365382966
Short name T154
Test name
Test status
Simulation time 2148160071 ps
CPU time 2.4 seconds
Started Aug 14 04:38:05 PM PDT 24
Finished Aug 14 04:38:08 PM PDT 24
Peak memory 200992 kb
Host smart-70707585-3174-48f9-a84c-901c8790aeba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365382966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.3365382966
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1093567161
Short name T138
Test name
Test status
Simulation time 42417319610 ps
CPU time 54.02 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:39:16 PM PDT 24
Peak memory 201240 kb
Host smart-dbe91a1d-3404-4a83-a8d8-8f262905fdf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093567161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.1093567161
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2706189912
Short name T2
Test name
Test status
Simulation time 2143170905 ps
CPU time 1.49 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:37:54 PM PDT 24
Peak memory 200996 kb
Host smart-cac84326-6558-4418-8f82-16e8e26cea74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706189912 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2706189912
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2414762215
Short name T30
Test name
Test status
Simulation time 2038860207 ps
CPU time 5.98 seconds
Started Aug 14 04:38:03 PM PDT 24
Finished Aug 14 04:38:09 PM PDT 24
Peak memory 200816 kb
Host smart-b30b2c71-7703-47e9-acc6-b85d94043d85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414762215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.2414762215
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3829627665
Short name T159
Test name
Test status
Simulation time 2021280068 ps
CPU time 2.95 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:26 PM PDT 24
Peak memory 200684 kb
Host smart-e45dd832-21ba-4ab0-93bf-bc7cdb921191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829627665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3829627665
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.766087033
Short name T14
Test name
Test status
Simulation time 5017163338 ps
CPU time 6.06 seconds
Started Aug 14 04:37:48 PM PDT 24
Finished Aug 14 04:37:55 PM PDT 24
Peak memory 201220 kb
Host smart-9494048a-bd71-42a4-b0d3-a6161e067329
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766087033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.766087033
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1189161236
Short name T148
Test name
Test status
Simulation time 2042965209 ps
CPU time 6.54 seconds
Started Aug 14 04:38:05 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 201244 kb
Host smart-69beb99c-6956-47c8-b0ce-15256865a332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189161236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1189161236
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3971632166
Short name T52
Test name
Test status
Simulation time 42902387950 ps
CPU time 28.03 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 201284 kb
Host smart-46878012-2259-4ce2-bfb4-2fccc2d520b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971632166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3971632166
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2210784698
Short name T17
Test name
Test status
Simulation time 2040876734 ps
CPU time 6.32 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 201132 kb
Host smart-e66cd31f-6cd8-4735-afd8-232012a89a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210784698 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2210784698
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3024220999
Short name T101
Test name
Test status
Simulation time 2028537313 ps
CPU time 6.15 seconds
Started Aug 14 04:37:59 PM PDT 24
Finished Aug 14 04:38:05 PM PDT 24
Peak memory 200772 kb
Host smart-aa50f36b-1307-4fe8-bfdf-e6569ff1e2d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024220999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3024220999
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2930158049
Short name T94
Test name
Test status
Simulation time 2068503827 ps
CPU time 1.32 seconds
Started Aug 14 04:37:49 PM PDT 24
Finished Aug 14 04:37:51 PM PDT 24
Peak memory 200696 kb
Host smart-e7f28ac3-dca4-4bf5-8638-08887bd4d695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930158049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2930158049
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2293753652
Short name T11
Test name
Test status
Simulation time 8828237413 ps
CPU time 3.33 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 201296 kb
Host smart-d06f02df-332b-4f46-ba25-be54c67f0e59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293753652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2293753652
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3982259340
Short name T139
Test name
Test status
Simulation time 2165646585 ps
CPU time 3.53 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:54 PM PDT 24
Peak memory 201312 kb
Host smart-ffce5f33-f319-47a2-99cf-9c526e458f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982259340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.3982259340
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.761748544
Short name T111
Test name
Test status
Simulation time 2044608804 ps
CPU time 5.76 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:56 PM PDT 24
Peak memory 200944 kb
Host smart-92be2ac5-fb0b-4e5e-896a-e8d51121d16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761748544 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.761748544
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4049563251
Short name T121
Test name
Test status
Simulation time 2048851723 ps
CPU time 5.93 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:26 PM PDT 24
Peak memory 200768 kb
Host smart-e19577d7-b868-45d9-85f8-79fe475798fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049563251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.4049563251
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4136096359
Short name T87
Test name
Test status
Simulation time 2014013845 ps
CPU time 5.54 seconds
Started Aug 14 04:38:05 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 200764 kb
Host smart-5bfba8b6-3a42-47d3-a040-dc58b24bcbde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136096359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.4136096359
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2403966179
Short name T136
Test name
Test status
Simulation time 8208619870 ps
CPU time 21.24 seconds
Started Aug 14 04:38:09 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 201276 kb
Host smart-08caed97-886b-4290-a9c6-38c7f9a36859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403966179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2403966179
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2982084637
Short name T51
Test name
Test status
Simulation time 2076892895 ps
CPU time 4.6 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 201208 kb
Host smart-3c3c58ef-abbd-472b-a82d-340d0fad0240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982084637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.2982084637
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.264489802
Short name T41
Test name
Test status
Simulation time 2537816164 ps
CPU time 3.53 seconds
Started Aug 14 04:38:02 PM PDT 24
Finished Aug 14 04:38:06 PM PDT 24
Peak memory 201184 kb
Host smart-be6dba32-0636-4dae-b3c1-88287574d41c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264489802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_aliasing.264489802
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2423538995
Short name T13
Test name
Test status
Simulation time 22188232689 ps
CPU time 7.55 seconds
Started Aug 14 04:37:54 PM PDT 24
Finished Aug 14 04:38:01 PM PDT 24
Peak memory 201112 kb
Host smart-fe3402ae-74d6-4b1c-a158-e22bbbe4d035
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423538995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.2423538995
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2471168073
Short name T110
Test name
Test status
Simulation time 4017908079 ps
CPU time 5.77 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:38:16 PM PDT 24
Peak memory 200944 kb
Host smart-cea45c13-3db1-4869-8b0a-aaa4097424c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471168073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.2471168073
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3519084093
Short name T21
Test name
Test status
Simulation time 2046607808 ps
CPU time 6 seconds
Started Aug 14 04:38:00 PM PDT 24
Finished Aug 14 04:38:06 PM PDT 24
Peak memory 201024 kb
Host smart-fa3a719c-78f4-4826-8d3a-7d5bf61005d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519084093 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3519084093
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3249470025
Short name T71
Test name
Test status
Simulation time 2034895909 ps
CPU time 5.37 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 200928 kb
Host smart-017c6f72-9144-453f-aab6-44a0477f5501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249470025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3249470025
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3063149297
Short name T8
Test name
Test status
Simulation time 2017944147 ps
CPU time 3.92 seconds
Started Aug 14 04:38:07 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 200856 kb
Host smart-a3c28198-8a3b-49a3-8dbb-98038e28dcf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063149297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.3063149297
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.119443066
Short name T34
Test name
Test status
Simulation time 10696539747 ps
CPU time 48.44 seconds
Started Aug 14 04:38:02 PM PDT 24
Finished Aug 14 04:38:51 PM PDT 24
Peak memory 201364 kb
Host smart-a3e8688d-5cc6-4417-aab1-463978fff681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119443066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
sysrst_ctrl_same_csr_outstanding.119443066
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2126398336
Short name T68
Test name
Test status
Simulation time 2072075333 ps
CPU time 6.58 seconds
Started Aug 14 04:37:59 PM PDT 24
Finished Aug 14 04:38:05 PM PDT 24
Peak memory 201160 kb
Host smart-f22fa5f9-7afa-4987-a9c1-bdc817c0e45a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126398336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2126398336
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1070213047
Short name T53
Test name
Test status
Simulation time 42389216537 ps
CPU time 112.89 seconds
Started Aug 14 04:37:47 PM PDT 24
Finished Aug 14 04:39:40 PM PDT 24
Peak memory 201224 kb
Host smart-7a695b2d-9feb-43d2-982e-64680942e6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070213047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1070213047
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1081875711
Short name T128
Test name
Test status
Simulation time 2121713515 ps
CPU time 0.88 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 200784 kb
Host smart-111ac04e-9549-48ec-8783-faaad52b3a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081875711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.1081875711
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3010094384
Short name T55
Test name
Test status
Simulation time 2013602679 ps
CPU time 5.72 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:28 PM PDT 24
Peak memory 200740 kb
Host smart-2fa63031-1382-4c51-9a4b-f0d0e42278b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010094384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.3010094384
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1013924888
Short name T97
Test name
Test status
Simulation time 2025375646 ps
CPU time 2.96 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 200672 kb
Host smart-de665939-4a7b-4c94-a350-5ea4283d013a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013924888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.1013924888
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2517045063
Short name T107
Test name
Test status
Simulation time 2034132557 ps
CPU time 1.97 seconds
Started Aug 14 04:38:30 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 200776 kb
Host smart-6c62dc20-5f47-49cf-87b7-8900fecb0e95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517045063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.2517045063
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1548184925
Short name T6
Test name
Test status
Simulation time 2021135922 ps
CPU time 3.27 seconds
Started Aug 14 04:38:09 PM PDT 24
Finished Aug 14 04:38:12 PM PDT 24
Peak memory 200864 kb
Host smart-047dec4f-e993-45a1-ad65-980c7b87f33d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548184925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1548184925
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.4227057093
Short name T116
Test name
Test status
Simulation time 2077938643 ps
CPU time 1.12 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:14 PM PDT 24
Peak memory 200696 kb
Host smart-2603e3ec-49e2-481d-829f-c763b0c96833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227057093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.4227057093
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2819845176
Short name T126
Test name
Test status
Simulation time 2025374452 ps
CPU time 2.27 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 200668 kb
Host smart-1fa0e440-9ce8-4df7-b9ce-9c38e7d70570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819845176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.2819845176
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3783892123
Short name T58
Test name
Test status
Simulation time 2032015924 ps
CPU time 1.86 seconds
Started Aug 14 04:38:37 PM PDT 24
Finished Aug 14 04:38:39 PM PDT 24
Peak memory 200604 kb
Host smart-23d2cce9-26d9-40a5-a40d-be87869765b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783892123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.3783892123
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.756489595
Short name T142
Test name
Test status
Simulation time 2023913464 ps
CPU time 3.24 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 200656 kb
Host smart-b3c6d070-3a60-4c45-a33e-176b07ddf78e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756489595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.756489595
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.460424391
Short name T89
Test name
Test status
Simulation time 2028023837 ps
CPU time 3.19 seconds
Started Aug 14 04:38:24 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 200748 kb
Host smart-622c6820-ec06-4a65-8621-d31f02484f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460424391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_tes
t.460424391
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.741933548
Short name T29
Test name
Test status
Simulation time 2901914226 ps
CPU time 9.8 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:38:01 PM PDT 24
Peak memory 201232 kb
Host smart-9514d22c-1ab8-4893-b9b3-fc2bd9d50949
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741933548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.741933548
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2335571067
Short name T36
Test name
Test status
Simulation time 24139467557 ps
CPU time 63.74 seconds
Started Aug 14 04:37:46 PM PDT 24
Finished Aug 14 04:38:50 PM PDT 24
Peak memory 201268 kb
Host smart-848ca832-c190-4b25-8a44-851128d73b39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335571067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.2335571067
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3492058201
Short name T32
Test name
Test status
Simulation time 6066852931 ps
CPU time 2.73 seconds
Started Aug 14 04:38:23 PM PDT 24
Finished Aug 14 04:38:26 PM PDT 24
Peak memory 200876 kb
Host smart-f81b4662-94c0-487b-9dfd-5e87b6b9c044
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492058201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.3492058201
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2216021509
Short name T155
Test name
Test status
Simulation time 2287503087 ps
CPU time 1.84 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:37:54 PM PDT 24
Peak memory 201368 kb
Host smart-b5ac86fa-8ed8-4f53-a99e-6cfedd586e89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216021509 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2216021509
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1755270204
Short name T160
Test name
Test status
Simulation time 2029914660 ps
CPU time 6.27 seconds
Started Aug 14 04:37:55 PM PDT 24
Finished Aug 14 04:38:01 PM PDT 24
Peak memory 200864 kb
Host smart-04d53f26-0565-4012-ac51-515ec8679785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755270204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1755270204
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3262176087
Short name T57
Test name
Test status
Simulation time 2012582095 ps
CPU time 5.52 seconds
Started Aug 14 04:38:13 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 200672 kb
Host smart-3c5349a3-528a-48c0-b959-741b4b9128eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262176087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.3262176087
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.923751428
Short name T3
Test name
Test status
Simulation time 5520991181 ps
CPU time 8.39 seconds
Started Aug 14 04:38:00 PM PDT 24
Finished Aug 14 04:38:09 PM PDT 24
Peak memory 201184 kb
Host smart-64b5ba98-de96-4998-9ef8-b51aff59231f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923751428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
sysrst_ctrl_same_csr_outstanding.923751428
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.4007871247
Short name T50
Test name
Test status
Simulation time 2044793021 ps
CPU time 7.54 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:38:00 PM PDT 24
Peak memory 201440 kb
Host smart-724e13ca-73c9-47d4-a62f-8b40ba8a2ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007871247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.4007871247
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1203615197
Short name T114
Test name
Test status
Simulation time 42454602290 ps
CPU time 87.71 seconds
Started Aug 14 04:38:24 PM PDT 24
Finished Aug 14 04:39:52 PM PDT 24
Peak memory 201212 kb
Host smart-2a3a9e75-db47-4bbc-b14c-f9599321a9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203615197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.1203615197
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2887292938
Short name T117
Test name
Test status
Simulation time 2041483666 ps
CPU time 1.58 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:52 PM PDT 24
Peak memory 200620 kb
Host smart-ce59e485-296f-4a5f-b459-04df03654e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887292938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.2887292938
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1350656723
Short name T28
Test name
Test status
Simulation time 2039232101 ps
CPU time 1.92 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:22 PM PDT 24
Peak memory 200856 kb
Host smart-c477840e-1696-4c7d-a85e-5e189e5838fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350656723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.1350656723
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2494561927
Short name T125
Test name
Test status
Simulation time 2010840635 ps
CPU time 5.75 seconds
Started Aug 14 04:38:27 PM PDT 24
Finished Aug 14 04:38:33 PM PDT 24
Peak memory 200864 kb
Host smart-598c8adf-b578-43c7-af16-f968297b62de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494561927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2494561927
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3511466925
Short name T65
Test name
Test status
Simulation time 2023319604 ps
CPU time 2.99 seconds
Started Aug 14 04:37:52 PM PDT 24
Finished Aug 14 04:37:55 PM PDT 24
Peak memory 200704 kb
Host smart-51fab3eb-8cf3-439e-86d7-46adf5dba7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511466925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.3511466925
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.4291550748
Short name T61
Test name
Test status
Simulation time 2059580313 ps
CPU time 1.75 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 200748 kb
Host smart-c116e4c6-3176-467d-8369-ac56ac35a334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291550748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.4291550748
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.539831480
Short name T38
Test name
Test status
Simulation time 2027115643 ps
CPU time 3.02 seconds
Started Aug 14 04:38:07 PM PDT 24
Finished Aug 14 04:38:10 PM PDT 24
Peak memory 200728 kb
Host smart-d1a212f3-fe66-406b-a119-332d4610f85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539831480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.539831480
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.470713682
Short name T76
Test name
Test status
Simulation time 2013928408 ps
CPU time 5.9 seconds
Started Aug 14 04:38:30 PM PDT 24
Finished Aug 14 04:38:36 PM PDT 24
Peak memory 200756 kb
Host smart-fa05d71c-17b3-4f12-a1f9-4207e985bb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470713682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_tes
t.470713682
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.965287564
Short name T9
Test name
Test status
Simulation time 2015641610 ps
CPU time 5.63 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:38 PM PDT 24
Peak memory 200760 kb
Host smart-786e6621-eff6-4dc6-bec4-2ad6e267d683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965287564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.965287564
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3031292498
Short name T69
Test name
Test status
Simulation time 2037862124 ps
CPU time 1.97 seconds
Started Aug 14 04:38:25 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 200864 kb
Host smart-4d20b021-2f5a-4107-99db-2562dbea88ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031292498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.3031292498
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.829448070
Short name T23
Test name
Test status
Simulation time 2860422412 ps
CPU time 2.96 seconds
Started Aug 14 04:38:20 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 201292 kb
Host smart-223e9ee2-e4f5-4024-86b4-a5b6a20b008c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829448070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_aliasing.829448070
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1069137930
Short name T37
Test name
Test status
Simulation time 4057080788 ps
CPU time 3.58 seconds
Started Aug 14 04:38:28 PM PDT 24
Finished Aug 14 04:38:32 PM PDT 24
Peak memory 200992 kb
Host smart-9422604a-810a-4eaf-823f-cbf9d1d40f47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069137930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.1069137930
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4253859584
Short name T95
Test name
Test status
Simulation time 2096530443 ps
CPU time 2.17 seconds
Started Aug 14 04:37:48 PM PDT 24
Finished Aug 14 04:37:51 PM PDT 24
Peak memory 200960 kb
Host smart-c4d59cd8-839b-4f56-8279-8d26e26be2ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253859584 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4253859584
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1730984277
Short name T42
Test name
Test status
Simulation time 2063809874 ps
CPU time 3.38 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 200876 kb
Host smart-553c3512-8f9c-4ea4-8905-eae68778dcb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730984277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.1730984277
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4001904286
Short name T59
Test name
Test status
Simulation time 2024817150 ps
CPU time 1.92 seconds
Started Aug 14 04:38:09 PM PDT 24
Finished Aug 14 04:38:11 PM PDT 24
Peak memory 200736 kb
Host smart-c2889616-c961-405d-9383-7c4b68425eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001904286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.4001904286
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2323935987
Short name T1
Test name
Test status
Simulation time 7148882601 ps
CPU time 16.71 seconds
Started Aug 14 04:37:51 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 201320 kb
Host smart-b4367dbf-2e77-4ca0-b753-a1d313c72987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323935987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2323935987
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3671936539
Short name T104
Test name
Test status
Simulation time 3634878729 ps
CPU time 2.34 seconds
Started Aug 14 04:38:00 PM PDT 24
Finished Aug 14 04:38:03 PM PDT 24
Peak memory 201256 kb
Host smart-00fb7dc9-5e4f-441b-834c-e8f5bd55b303
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671936539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.3671936539
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1220894380
Short name T118
Test name
Test status
Simulation time 2014151805 ps
CPU time 5.43 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:39 PM PDT 24
Peak memory 200700 kb
Host smart-640d9d90-335b-44d6-be2f-a1132654cc5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220894380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1220894380
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.569187024
Short name T162
Test name
Test status
Simulation time 2032257624 ps
CPU time 1.86 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:16 PM PDT 24
Peak memory 200732 kb
Host smart-fb964d29-33b0-4ee0-8b73-ba7c2010514b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569187024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_tes
t.569187024
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.887143299
Short name T72
Test name
Test status
Simulation time 2019783579 ps
CPU time 3.25 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:20 PM PDT 24
Peak memory 200688 kb
Host smart-d991ada4-ece4-484c-a57a-48ac286c1559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887143299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_tes
t.887143299
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.824565060
Short name T10
Test name
Test status
Simulation time 2013136776 ps
CPU time 5.71 seconds
Started Aug 14 04:38:30 PM PDT 24
Finished Aug 14 04:38:36 PM PDT 24
Peak memory 200684 kb
Host smart-9fad4032-94e9-488f-8e9f-62853dddab17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824565060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.824565060
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2037915468
Short name T79
Test name
Test status
Simulation time 2031035557 ps
CPU time 1.94 seconds
Started Aug 14 04:38:22 PM PDT 24
Finished Aug 14 04:38:24 PM PDT 24
Peak memory 200668 kb
Host smart-d847f4f3-32d4-49be-a5ad-6fa5567a83d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037915468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2037915468
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1393646119
Short name T153
Test name
Test status
Simulation time 2012056613 ps
CPU time 5.36 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:19 PM PDT 24
Peak memory 200860 kb
Host smart-a90a08af-66c8-47eb-b236-d7d877cafe89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393646119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1393646119
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3318542946
Short name T39
Test name
Test status
Simulation time 2011860509 ps
CPU time 5.64 seconds
Started Aug 14 04:38:24 PM PDT 24
Finished Aug 14 04:38:30 PM PDT 24
Peak memory 200732 kb
Host smart-3dc7bd2a-5567-4798-9055-0104b2d99ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318542946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.3318542946
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3340411516
Short name T56
Test name
Test status
Simulation time 2031348205 ps
CPU time 2.56 seconds
Started Aug 14 04:38:33 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 200648 kb
Host smart-45ff2ce3-3956-4316-85fc-9ee0b4804e25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340411516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3340411516
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1456671801
Short name T112
Test name
Test status
Simulation time 2013181893 ps
CPU time 5.73 seconds
Started Aug 14 04:38:21 PM PDT 24
Finished Aug 14 04:38:27 PM PDT 24
Peak memory 200692 kb
Host smart-2b600f10-5dff-451e-97a9-aac36d18c790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456671801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1456671801
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1081227121
Short name T151
Test name
Test status
Simulation time 2016661329 ps
CPU time 3.3 seconds
Started Aug 14 04:38:17 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 200616 kb
Host smart-9c50dd0b-178b-40ae-9603-8a994e49c242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081227121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1081227121
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3121744731
Short name T158
Test name
Test status
Simulation time 2106091632 ps
CPU time 1.91 seconds
Started Aug 14 04:38:03 PM PDT 24
Finished Aug 14 04:38:05 PM PDT 24
Peak memory 200932 kb
Host smart-27863f5e-124f-4e6f-963e-6eae81e920f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121744731 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3121744731
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3997856041
Short name T156
Test name
Test status
Simulation time 2062303845 ps
CPU time 2.19 seconds
Started Aug 14 04:38:18 PM PDT 24
Finished Aug 14 04:38:25 PM PDT 24
Peak memory 200888 kb
Host smart-a98a9ab1-4004-422f-b2a7-6631bbdf136d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997856041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3997856041
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1891674375
Short name T100
Test name
Test status
Simulation time 2018225049 ps
CPU time 2.92 seconds
Started Aug 14 04:37:49 PM PDT 24
Finished Aug 14 04:37:52 PM PDT 24
Peak memory 200700 kb
Host smart-afa8e5e6-4c0e-4c9a-9f08-128f6b2ebc68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891674375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1891674375
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2773416034
Short name T99
Test name
Test status
Simulation time 5265364776 ps
CPU time 2.79 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 201288 kb
Host smart-0e186422-9f85-4ffd-b44f-e9a9e449a178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773416034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.2773416034
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.731558568
Short name T66
Test name
Test status
Simulation time 2126053043 ps
CPU time 7.91 seconds
Started Aug 14 04:37:49 PM PDT 24
Finished Aug 14 04:37:57 PM PDT 24
Peak memory 201104 kb
Host smart-264696eb-1323-4bc7-b5cf-14c6d22745a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731558568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors
.731558568
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2528906666
Short name T149
Test name
Test status
Simulation time 22369047190 ps
CPU time 23.94 seconds
Started Aug 14 04:38:14 PM PDT 24
Finished Aug 14 04:38:38 PM PDT 24
Peak memory 201312 kb
Host smart-057a3eeb-58ef-4295-a4ce-eaf2449779e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528906666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.2528906666
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2555403755
Short name T19
Test name
Test status
Simulation time 2040040873 ps
CPU time 6.1 seconds
Started Aug 14 04:37:47 PM PDT 24
Finished Aug 14 04:37:53 PM PDT 24
Peak memory 200912 kb
Host smart-de93dbc9-8aab-423e-98f4-a1e90312815a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555403755 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2555403755
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1527281062
Short name T120
Test name
Test status
Simulation time 2054964623 ps
CPU time 5.64 seconds
Started Aug 14 04:38:07 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 200940 kb
Host smart-3664ef0a-fcbf-4328-82ee-f490f2fe1d72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527281062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.1527281062
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2585256211
Short name T62
Test name
Test status
Simulation time 2021179364 ps
CPU time 3.17 seconds
Started Aug 14 04:38:02 PM PDT 24
Finished Aug 14 04:38:05 PM PDT 24
Peak memory 200700 kb
Host smart-c4dfcfc0-841b-4156-967f-dc5fec767304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585256211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.2585256211
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.781814269
Short name T129
Test name
Test status
Simulation time 4129972524 ps
CPU time 4.49 seconds
Started Aug 14 04:38:03 PM PDT 24
Finished Aug 14 04:38:08 PM PDT 24
Peak memory 201064 kb
Host smart-f766d410-1942-42fb-a3a6-9fe462584d8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781814269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_same_csr_outstanding.781814269
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.803419536
Short name T88
Test name
Test status
Simulation time 2097199175 ps
CPU time 2.73 seconds
Started Aug 14 04:37:50 PM PDT 24
Finished Aug 14 04:37:53 PM PDT 24
Peak memory 201252 kb
Host smart-13a7c47d-28a0-477a-8a7a-75a167b5fc11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803419536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors
.803419536
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2494595294
Short name T102
Test name
Test status
Simulation time 22728534628 ps
CPU time 8.18 seconds
Started Aug 14 04:38:00 PM PDT 24
Finished Aug 14 04:38:08 PM PDT 24
Peak memory 201264 kb
Host smart-21095bc6-dd40-4933-8205-d0531f6a26fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494595294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.2494595294
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1622023010
Short name T86
Test name
Test status
Simulation time 2137004883 ps
CPU time 2.7 seconds
Started Aug 14 04:38:10 PM PDT 24
Finished Aug 14 04:38:13 PM PDT 24
Peak memory 201060 kb
Host smart-8c29ca56-0cc1-4100-9cd7-929d6104d0a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622023010 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1622023010
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3362577401
Short name T78
Test name
Test status
Simulation time 2027226440 ps
CPU time 6.16 seconds
Started Aug 14 04:38:16 PM PDT 24
Finished Aug 14 04:38:22 PM PDT 24
Peak memory 200972 kb
Host smart-d875c654-2aa7-4c9d-905b-1cacd7f281c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362577401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.3362577401
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3256680184
Short name T63
Test name
Test status
Simulation time 2010575437 ps
CPU time 6.19 seconds
Started Aug 14 04:37:59 PM PDT 24
Finished Aug 14 04:38:06 PM PDT 24
Peak memory 200684 kb
Host smart-ad8a3fbc-2143-4b68-8653-73739ed2b431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256680184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.3256680184
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2337851617
Short name T133
Test name
Test status
Simulation time 5000844931 ps
CPU time 12.4 seconds
Started Aug 14 04:38:08 PM PDT 24
Finished Aug 14 04:38:21 PM PDT 24
Peak memory 201248 kb
Host smart-e5bebe75-1e14-49a5-b7cf-4ca493f29cb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337851617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2337851617
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2286488299
Short name T119
Test name
Test status
Simulation time 22387537752 ps
CPU time 16.54 seconds
Started Aug 14 04:38:06 PM PDT 24
Finished Aug 14 04:38:23 PM PDT 24
Peak memory 201296 kb
Host smart-6fc2185f-fdd7-482c-960e-a0ca86fc3102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286488299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.2286488299
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.81195627
Short name T80
Test name
Test status
Simulation time 2224832765 ps
CPU time 2.01 seconds
Started Aug 14 04:38:34 PM PDT 24
Finished Aug 14 04:38:36 PM PDT 24
Peak memory 201324 kb
Host smart-f9fcb5f2-bb31-4364-8f6a-8d2d188d0895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81195627 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.81195627
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1348955165
Short name T130
Test name
Test status
Simulation time 2090540010 ps
CPU time 1.74 seconds
Started Aug 14 04:37:56 PM PDT 24
Finished Aug 14 04:37:58 PM PDT 24
Peak memory 200900 kb
Host smart-cf71cbb3-1e72-46b1-a850-2ebf030bd61e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348955165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.1348955165
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.4033667420
Short name T163
Test name
Test status
Simulation time 2010255323 ps
CPU time 5.78 seconds
Started Aug 14 04:38:12 PM PDT 24
Finished Aug 14 04:38:18 PM PDT 24
Peak memory 200688 kb
Host smart-53dde632-01c7-442f-8616-2316bdeccb01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033667420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.4033667420
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1106545932
Short name T67
Test name
Test status
Simulation time 8550535119 ps
CPU time 22.09 seconds
Started Aug 14 04:38:39 PM PDT 24
Finished Aug 14 04:39:02 PM PDT 24
Peak memory 201240 kb
Host smart-d1e336b5-1460-42d7-a148-b63aa144ec64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106545932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.1106545932
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1840190228
Short name T48
Test name
Test status
Simulation time 2032010537 ps
CPU time 6.67 seconds
Started Aug 14 04:38:08 PM PDT 24
Finished Aug 14 04:38:14 PM PDT 24
Peak memory 201164 kb
Host smart-fdbb37cd-68df-4f72-ad17-16130c214223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840190228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.1840190228
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3048835810
Short name T92
Test name
Test status
Simulation time 42523929844 ps
CPU time 28.92 seconds
Started Aug 14 04:38:11 PM PDT 24
Finished Aug 14 04:38:40 PM PDT 24
Peak memory 201264 kb
Host smart-4962e53b-30b9-4d8e-a82f-62c34a8e72d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048835810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3048835810
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1292811234
Short name T98
Test name
Test status
Simulation time 2065345499 ps
CPU time 6.04 seconds
Started Aug 14 04:38:11 PM PDT 24
Finished Aug 14 04:38:17 PM PDT 24
Peak memory 200960 kb
Host smart-4139eda3-ce60-4cf7-91c8-7f0ce39f126f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292811234 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1292811234
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.4230157215
Short name T115
Test name
Test status
Simulation time 2093442898 ps
CPU time 1.82 seconds
Started Aug 14 04:38:13 PM PDT 24
Finished Aug 14 04:38:15 PM PDT 24
Peak memory 200960 kb
Host smart-19dc8eff-fe87-451f-b4d8-925fca445bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230157215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.4230157215
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3079585819
Short name T141
Test name
Test status
Simulation time 2127980026 ps
CPU time 1.02 seconds
Started Aug 14 04:38:11 PM PDT 24
Finished Aug 14 04:38:12 PM PDT 24
Peak memory 200868 kb
Host smart-be4c4162-04af-4e43-b7e2-7b8a05eac11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079585819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3079585819
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2987511322
Short name T131
Test name
Test status
Simulation time 5280858046 ps
CPU time 4.42 seconds
Started Aug 14 04:38:06 PM PDT 24
Finished Aug 14 04:38:10 PM PDT 24
Peak memory 201136 kb
Host smart-143e126e-2046-41ca-9bab-ece271d519c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987511322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.2987511322
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1695786024
Short name T135
Test name
Test status
Simulation time 2227767638 ps
CPU time 3.11 seconds
Started Aug 14 04:38:11 PM PDT 24
Finished Aug 14 04:38:14 PM PDT 24
Peak memory 201200 kb
Host smart-60d6355e-8796-4712-80bc-97159f7f89b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695786024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.1695786024
Directory /workspace/9.sysrst_ctrl_tl_errors/latest
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