| | | | | | | | | | | |
|
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg |
0 |
2 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_auto_block_debounce_ctl_cg |
0 |
5 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_detect_det_cg |
0 |
3 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_precondition_det_cg |
0 |
3 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg |
0 |
28 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg |
0 |
16 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
sysrst_ctrl_env_pkg::sysrst_ctrl_combo_detect_action_obj::sysrst_ctrl_combo_detect_action_cg |
0 |
28 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
sysrst_ctrl_env_pkg::sysrst_ctrl_combo_intr_status_obj::sysrst_ctrl_combo_intr_status_cg |
0 |
404 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg |
0 |
82 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
sysrst_ctrl_env_pkg::sysrst_ctrl_debounce_timer_obj::debounce_timer_cg |
0 |
3 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg |
0 |
24 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg |
6 |
33 |
18.18 |
18.18 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::pending_req_on_rst_cg |
1 |
2 |
50.00 |
50.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg |
12 |
15 |
80.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg |
13 |
14 |
92.86 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
alert_esc_agent_pkg::alert_handshake_complete_cg |
3 |
3 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0} |
9 |
9 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0} |
9 |
9 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0} |
13 |
13 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg |
2 |
2 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg |
4 |
4 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} |
1 |
1 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} |
137 |
137 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|