Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.68	65.71	59.09	87.44	0.00	58.43	99.42

Total modules in report: 40

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sysrst_ctrl_detect	0.00	0.00	0.00		0.00	0.00
sysrst_ctrl_detect	0.00				0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )	0.00	0.00	0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )	0.00					0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )	0.00		0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )	0.00	0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )	0.00					0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )	0.00		0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )	0.00		0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )	0.00		0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )	0.00	0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )	0.00	0.00	0.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )	0.00	0.00	0.00
sysrst_ctrl_combo	0.00	0.00	0.00
sysrst_ctrl_ulp	0.00	0.00	0.00
sysrst_ctrl_intr	0.00	0.00	0.00			0.00
sysrst_ctrl_keyintr	0.00	0.00
prim_onehot_check	0.00			0.00
prim_intr_hw	0.00	0.00	0.00			0.00
sysrst_ctrl_comboact	0.00	0.00	0.00			0.00
sysrst_ctrl_pin	0.00	0.00	0.00			0.00
sysrst_ctrl_autoblock	0.00	0.00	0.00			0.00
sysrst_ctrl	31.55	0.00	0.00	94.65
tlul_assert	33.33	0.00				0.00	100.00
prim_reg_cdc_arb	62.37	93.00	82.56			73.91	0.00
prim_reg_cdc_arb	36.96					73.91	0.00
prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 )	75.56	86.00	65.12
prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )	100.00	100.00	100.00
prim_sync_reqack	87.50	100.00	50.00			100.00	100.00
tlul_rsp_intg_gen	91.67	83.33					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	66.67	66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
prim_subreg_arb	93.17	87.50	92.00			100.00
prim_subreg_arb	100.00					100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )	100.00	100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )	50.00	50.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )	80.00	100.00	60.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )	100.00	100.00	100.00
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )	100.00		100.00
prim_reg_cdc	95.74	100.00	82.95			100.00	100.00
prim_reg_cdc	100.00	100.00				100.00	100.00
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )	75.00		75.00
prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )	90.91		90.91
sysrst_ctrl_reg_top	98.31	99.22	94.04			100.00	100.00
tlul_adapter_reg	98.98	100.00	95.92			100.00	100.00
sysrst_ctrl_csr_assert_fpv	100.00						100.00
tlul_data_integ_dec	100.00	100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
prim_alert_sender	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_subreg	100.00	100.00				100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 )	100.00		100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
prim_pulse_sync	100.00	100.00	100.00			100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_secded_inv_64_57_dec	100.00			100.00
prim_generic_flop	100.00	100.00				100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb