---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	259234	0	0	165
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	259234	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.sysrst_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	68578499	10662	0	0
tb.dut.sysrst_ctrl_csr_assert.auto_block_debounce_ctl_rd_A	0	0	68578499	1236	0	0
tb.dut.sysrst_ctrl_csr_assert.auto_block_out_ctl_rd_A	0	0	68578499	1860	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_0_rd_A	0	0	68578499	1050	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_1_rd_A	0	0	68578499	1164	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_2_rd_A	0	0	68578499	1033	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_3_rd_A	0	0	68578499	1015	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_0_rd_A	0	0	68578499	1650	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_1_rd_A	0	0	68578499	1728	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_2_rd_A	0	0	68578499	1529	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_3_rd_A	0	0	68578499	1560	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_0_rd_A	0	0	68578499	1056	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_1_rd_A	0	0	68578499	1079	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_2_rd_A	0	0	68578499	977	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_3_rd_A	0	0	68578499	1011	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_0_rd_A	0	0	68578499	1897	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_1_rd_A	0	0	68578499	1927	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_2_rd_A	0	0	68578499	1668	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_3_rd_A	0	0	68578499	1609	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_0_rd_A	0	0	68578499	1892	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_1_rd_A	0	0	68578499	1640	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_2_rd_A	0	0	68578499	1717	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_3_rd_A	0	0	68578499	1996	0	0
tb.dut.sysrst_ctrl_csr_assert.ec_rst_ctl_rd_A	0	0	68578499	989	0	0
tb.dut.sysrst_ctrl_csr_assert.intr_enable_rd_A	0	0	68578499	1703	0	0
tb.dut.sysrst_ctrl_csr_assert.key_intr_ctl_rd_A	0	0	68578499	3120	0	0
tb.dut.sysrst_ctrl_csr_assert.key_intr_debounce_ctl_rd_A	0	0	68578499	1057	0	0
tb.dut.sysrst_ctrl_csr_assert.key_invert_ctl_rd_A	0	0	68578499	3023	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_allowed_ctl_rd_A	0	0	68578499	3875	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_out_ctl_rd_A	0	0	68578499	2414	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_out_value_rd_A	0	0	68578499	2490	0	0
tb.dut.sysrst_ctrl_csr_assert.regwen_rd_A	0	0	68578499	1452	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_ac_debounce_ctl_rd_A	0	0	68578499	1036	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_ctl_rd_A	0	0	68578499	996	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_lid_debounce_ctl_rd_A	0	0	68578499	1053	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_pwrb_debounce_ctl_rd_A	0	0	68578499	1051	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	68578499	12165673	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	68578499	68532680	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	68578499	68532680	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	68578499	231923	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	68578499	68532680	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	68578499	68532680	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	165	165	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	68578591	2988791	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	68578499	5735	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	68578591	10340314	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	68578591	57732	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	68578499	6102	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	68578591	12165673	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	68578591	231923	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	68578591	12165673	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	68578591	231923	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	68578591	231923	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	68578591	231923	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	68578499	3635	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	68578499	3383	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	165	165	0	0
tb.dut.u_reg.en2addrHit	0	0	68578499	98678	0	0
tb.dut.u_reg.reAfterRv	0	0	68578499	98678	0	0
tb.dut.u_reg.rePulse	0	0	68578499	62474	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A	0	0	68578499	705947	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	861	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	861	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	861	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	803	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	872	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A	0	0	68578499	676214	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	826	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	826	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	826	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	771	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	836	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	165	165	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A	0	0	68578499	713513	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A	0	0	68578499	847	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	847	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	847	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	793	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	857	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A	0	0	68578499	747525	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A	0	0	68578499	890	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	890	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	890	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	832	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	899	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A	0	0	68578499	750989	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A	0	0	68578499	896	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	896	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	896	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	836	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	907	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A	0	0	68578499	717912	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A	0	0	68578499	852	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	852	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	852	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	798	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	861	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A	0	0	68578499	752976	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A	0	0	68578499	877	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	877	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	877	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	815	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	886	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A	0	0	68578499	686658	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A	0	0	68578499	834	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	834	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	834	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	777	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	842	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A	0	0	68578499	744855	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A	0	0	68578499	878	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	878	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	878	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	821	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	887	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A	0	0	68578499	768930	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A	0	0	68578499	915	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	915	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	915	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	853	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	925	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A	0	0	68578499	745905	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A	0	0	68578499	908	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	908	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	908	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	849	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	918	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A	0	0	68578499	702164	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A	0	0	68578499	831	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	831	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	831	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	775	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	839	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A	0	0	68578499	745366	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A	0	0	68578499	879	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	879	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	879	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	821	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	889	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A	0	0	68578499	748861	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A	0	0	68578499	896	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	896	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	896	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	838	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	906	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A	0	0	68578499	719776	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A	0	0	68578499	884	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	884	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	884	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	825	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	893	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A	0	0	68578499	732172	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A	0	0	68578499	888	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	888	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	888	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	831	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	896	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A	0	0	68578499	721449	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A	0	0	68578499	845	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	845	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	845	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	786	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	855	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A	0	0	68578499	702426	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A	0	0	68578499	844	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	844	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	844	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	784	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	852	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A	0	0	68578499	747534	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A	0	0	68578499	870	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	870	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	870	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	811	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	881	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A	0	0	68578499	708928	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A	0	0	68578499	862	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	862	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	862	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	805	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	873	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A	0	0	68578499	714995	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A	0	0	68578499	863	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	863	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	863	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	806	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	872	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A	0	0	68578499	757379	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A	0	0	68578499	889	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	889	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	889	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	831	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	898	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A	0	0	68578499	732902	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	871	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	871	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	871	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	812	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	880	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A	0	0	68578499	724668	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	855	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	855	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	855	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	798	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	865	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.BusySrcReqChk_A	0	0	68578499	714669	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	857	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	857	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	857	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	800	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	866	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.BusySrcReqChk_A	0	0	68578499	700472	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	842	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	842	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	842	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	786	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	852	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.BusySrcReqChk_A	0	0	68578499	733328	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	889	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	889	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	889	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	830	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	900	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.BusySrcReqChk_A	0	0	68578499	747700	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	882	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	882	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	882	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	823	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	892	0	0
tb.dut.u_reg.u_pin_out_value_cdc.BusySrcReqChk_A	0	0	68578499	715747	0	0
tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_pin_out_value_cdc.SrcAckBusyChk_A	0	0	68578499	843	0	0
tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	843	0	0
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	843	0	0
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	783	0	0
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	853	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	165	165	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	165	165	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	165	165	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	165	165	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	165	165	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	165	165	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	165	165	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.BusySrcReqChk_A	0	0	68578499	724022	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	853	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	853	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	853	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	794	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	862	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.BusySrcReqChk_A	0	0	68578499	752676	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	886	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	886	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	886	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	829	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	896	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.BusySrcReqChk_A	0	0	68578499	722675	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	864	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	864	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	864	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	806	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	874	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.BusySrcReqChk_A	0	0	68578499	716746	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcAckBusyChk_A	0	0	68578499	859	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	68578499	859	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	259234	859	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	800	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	867	0	0
tb.dut.u_reg.u_wkup_status_cdc.BusySrcReqChk_A	0	0	68578499	549565	0	0
tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A	0	0	259234	60004	0	0
tb.dut.u_reg.u_wkup_status_cdc.SrcAckBusyChk_A	0	0	68578499	521	0	0
tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A	0	0	68578499	68532680	0	0
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	68578499	521	0	0
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	259234	94	0	0
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	259234	464	0	0
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	68578499	532	0	0
tb.dut.u_reg.wePulse	0	0	68578499	36204	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	259234	0	0	165

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	68578591	218870	218870	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	68578591	3802	3802	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	68578591	9672	9672	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	68578591	7179	7179	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	68578591	9164	9164	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	68578591	5687	5687	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	68578591	3982	3982	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	68578591	4750	4750	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	68578591	10738	10738	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	68578591	5920	5920	145

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	68578591	218870	218870	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	68578591	3802	3802	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	68578591	9672	9672	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	68578591	7179	7179	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	68578591	9164	9164	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	68578591	5687	5687	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	68578591	3982	3982	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	68578591	4750	4750	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	68578591	10738	10738	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	68578591	5920	5920	145