Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T15 T11 T28 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T15 T11 T28 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T15 T11 T28 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T15 T11 T28 
149        1/1                    cnt_en = 1'b1;
           Tests:       T15 T11 T28 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T15 T11 T28 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T15 T11 T28 
163        1/1                    state_d = IdleSt;
           Tests:       T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T15 T11 T28 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T11 T28 
167        1/1                    if (trigger_active) begin
           Tests:       T15 T11 T28 
168        1/1                      state_d = DetectSt;
           Tests:       T15 T11 T28 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T60 T91 T92 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T15 T11 T28 
182        1/1                  cnt_en = 1'b1;
           Tests:       T15 T11 T28 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T15 T11 T28 
186        1/1                    state_d = IdleSt;
           Tests:       T92 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T92 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T15 T11 T28 
191        1/1                      state_d = StableSt;
           Tests:       T15 T11 T28 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T15 T11 T28 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T15 T11 T28 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T15 T11 T28 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T15 T11 T28 
206        1/1                    state_d = IdleSt;
           Tests:       T15 T11 T28 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T15 T11 T28 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T11,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T15,T11,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T11,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T11,T28
1	0	Covered	T4,T5,T13
1	1	Covered	T15,T11,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T11,T28
0	1	Covered	T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T11,T28
0	1	Covered	T15,T28,T52
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T11,T28
1	-	Covered	T15,T28,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T11,T28
DetectSt	168	Covered	T15,T11,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T15,T11,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T11,T28
DebounceSt->IdleSt	163	Covered	T30,T60,T91
DetectSt->IdleSt	186	Covered	T92
DetectSt->StableSt	191	Covered	T15,T11,T28
IdleSt->DebounceSt	148	Covered	T15,T11,T28
StableSt->IdleSt	206	Covered	T15,T11,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T11,T28
0	1	Covered	T15,T11,T28
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T15,T11,T28
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T11,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T30
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T11,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T91,T92
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T11,T28
DetectSt	-	-	-	-	1	-	-	Covered	T92
DetectSt	-	-	-	-	0	1	-	Covered	T15,T11,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T11,T28
StableSt	-	-	-	-	-	-	0	Covered	T15,T11,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	168	0	0
CntIncr_A	6968781	113942	0	0
CntNoWrap_A	6968781	6510129	0	0
DetectStDropOut_A	6968781	1	0	0
DetectedOut_A	6968781	539	0	0
DetectedPulseOut_A	6968781	77	0	0
DisabledIdleSt_A	6968781	6392538	0	0
DisabledNoDetection_A	6968781	6394343	0	0
EnterDebounceSt_A	6968781	90	0	0
EnterDetectSt_A	6968781	78	0	0
EnterStableSt_A	6968781	77	0	0
PulseIsPulse_A	6968781	77	0	0
StayInStableSt	6968781	462	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	5336	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	76	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	168	0	0
T3	813	0	0	0
T11	0	2	0	0
T15	652	4	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T52	0	4	0	0
T55	0	4	0	0
T58	0	4	0	0
T59	0	4	0	0
T60	0	1	0	0
T61	0	4	0	0
T62	426	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	113942	0	0
T3	813	0	0	0
T11	0	21	0	0
T15	652	92	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	20	0	0
T30	0	30	0	0
T52	0	195	0	0
T55	0	49	0	0
T58	0	96	0	0
T59	0	101	0	0
T60	0	26	0	0
T61	0	113	0	0
T62	426	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510129	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	247	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1	0	0
T87	17941	0	0	0
T92	2861	1	0	0
T93	539	0	0	0
T128	559	0	0	0
T129	433	0	0	0
T130	618	0	0	0
T131	429	0	0	0
T132	494	0	0	0
T133	522	0	0	0
T134	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	539	0	0
T3	813	0	0	0
T11	0	6	0	0
T15	652	12	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	8	0	0
T52	0	10	0	0
T55	0	10	0	0
T58	0	16	0	0
T59	0	15	0	0
T61	0	10	0	0
T62	426	0	0	0
T135	0	6	0	0
T136	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	77	0	0
T3	813	0	0	0
T11	0	1	0	0
T15	652	2	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	426	0	0	0
T135	0	1	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6392538	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	66	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6394343	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	66	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	90	0	0
T3	813	0	0	0
T11	0	1	0	0
T15	652	2	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	426	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	78	0	0
T3	813	0	0	0
T11	0	1	0	0
T15	652	2	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	426	0	0	0
T135	0	1	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	77	0	0
T3	813	0	0	0
T11	0	1	0	0
T15	652	2	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	426	0	0	0
T135	0	1	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	77	0	0
T3	813	0	0	0
T11	0	1	0	0
T15	652	2	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	426	0	0	0
T135	0	1	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	462	0	0
T3	813	0	0	0
T11	0	5	0	0
T15	652	10	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	7	0	0
T52	0	8	0	0
T55	0	8	0	0
T58	0	14	0	0
T59	0	13	0	0
T61	0	8	0	0
T62	426	0	0	0
T135	0	5	0	0
T136	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5336	0	0
T1	522	0	0	0
T2	2225	10	0	0
T3	0	2	0	0
T4	496	8	0	0
T5	423	2	0	0
T13	499	6	0	0
T14	405	0	0	0
T15	652	3	0	0
T16	408	0	0	0
T17	524	5	0	0
T18	446	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T27	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	76	0	0
T3	813	0	0	0
T15	652	2	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T24	854	0	0	0
T27	503	0	0	0
T28	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	426	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T9 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T9 T25 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T9 T25 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T9 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T9 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T9 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T9 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T11 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T9 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T9 T67 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T9 T67 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T9 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T67 T90 T94 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T9 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T9 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T9 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T104 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T104 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T9 T36 
191        1/1                      state_d = StableSt;
           Tests:       T2 T9 T36 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T9 T36 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T9 T36 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T9 T36 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T9 T36 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T9 T36 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T9 T36 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T4,T5,T13
1	1	Covered	T2,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T36
0	1	Covered	T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T36
0	1	Unreachable
1	0	Covered	T2,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T11
DetectSt	168	Covered	T2,T9,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T36
DebounceSt->IdleSt	163	Covered	T11,T67,T30
DetectSt->IdleSt	186	Covered	T104
DetectSt->StableSt	191	Covered	T2,T9,T36
IdleSt->DebounceSt	148	Covered	T2,T9,T11
StableSt->IdleSt	206	Covered	T2,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T36
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T67,T90,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T104
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	102	0	0
CntIncr_A	6968781	98946	0	0
CntNoWrap_A	6968781	6510195	0	0
DetectStDropOut_A	6968781	1	0	0
DetectedOut_A	6968781	288689	0	0
DetectedPulseOut_A	6968781	38	0	0
DisabledIdleSt_A	6968781	5333271	0	0
DisabledNoDetection_A	6968781	5335100	0	0
EnterDebounceSt_A	6968781	63	0	0
EnterDetectSt_A	6968781	39	0	0
EnterStableSt_A	6968781	38	0	0
PulseIsPulse_A	6968781	38	0	0
StayInStableSt	6968781	288651	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	5336	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_sticky_sva.StableStDropOut_A	6968781	786714	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	102	0	0
T2	2225	6	0	0
T3	813	0	0	0
T9	0	4	0	0
T11	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	2	0	0
T36	0	4	0	0
T48	0	2	0	0
T62	426	0	0	0
T65	0	4	0	0
T67	0	2	0	0
T89	0	2	0	0
T90	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	98946	0	0
T2	2225	258	0	0
T3	813	0	0	0
T9	0	76	0	0
T11	0	71	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	83	0	0
T36	0	196	0	0
T48	0	33	0	0
T62	426	0	0	0
T65	0	112	0	0
T67	0	122	0	0
T89	0	68	0	0
T90	0	300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510195	0	0
T1	522	121	0	0
T2	2225	1818	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1	0	0
T102	785	0	0	0
T104	1634	1	0	0
T144	524	0	0	0
T145	506	0	0	0
T146	421	0	0	0
T147	594	0	0	0
T148	519	0	0	0
T149	402	0	0	0
T150	494	0	0	0
T151	1535	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	288689	0	0
T2	2225	908	0	0
T3	813	0	0	0
T9	0	273	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	974	0	0
T48	0	135	0	0
T62	426	0	0	0
T65	0	307	0	0
T89	0	261	0	0
T92	0	227	0	0
T103	0	376	0	0
T140	0	518	0	0
T141	0	576	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	2	0	0
T89	0	1	0	0
T92	0	1	0	0
T103	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5333271	0	0
T1	522	121	0	0
T2	2225	81	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5335100	0	0
T1	522	122	0	0
T2	2225	82	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	63	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	2	0	0
T67	0	2	0	0
T89	0	1	0	0
T90	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	39	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	2	0	0
T89	0	1	0	0
T92	0	1	0	0
T103	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	2	0	0
T89	0	1	0	0
T92	0	1	0	0
T103	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	2	0	0
T89	0	1	0	0
T92	0	1	0	0
T103	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	288651	0	0
T2	2225	905	0	0
T3	813	0	0	0
T9	0	271	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	972	0	0
T48	0	134	0	0
T62	426	0	0	0
T65	0	305	0	0
T89	0	260	0	0
T92	0	226	0	0
T103	0	375	0	0
T140	0	517	0	0
T141	0	575	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5336	0	0
T1	522	0	0	0
T2	2225	10	0	0
T3	0	2	0	0
T4	496	8	0	0
T5	423	2	0	0
T13	499	6	0	0
T14	405	0	0	0
T15	652	3	0	0
T16	408	0	0	0
T17	524	5	0	0
T18	446	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T27	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	786714	0	0
T2	2225	512	0	0
T3	813	0	0	0
T9	0	1179	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	168	0	0
T48	0	313	0	0
T62	426	0	0	0
T65	0	156	0	0
T89	0	53	0	0
T92	0	196	0	0
T103	0	154	0	0
T140	0	131	0	0
T141	0	80	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T9 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T9 T25 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T9 T25 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T9 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T9 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T9 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T9 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T11 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T9 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T9 T67 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T9 T67 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T67 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T9 T67 T65 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T67 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T67 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T67 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T67 T90 T103 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T67 T90 T103 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T36 T48 
191        1/1                      state_d = StableSt;
           Tests:       T2 T36 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T36 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T36 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T36 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T36 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T36 T48 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T36 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T67,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T4,T5,T13
1	1	Covered	T2,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T48
0	1	Covered	T67,T90,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T48
0	1	Unreachable
1	0	Covered	T2,T36,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T11
DetectSt	168	Covered	T2,T67,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T36,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T67,T36
DebounceSt->IdleSt	163	Covered	T9,T11,T67
DetectSt->IdleSt	186	Covered	T67,T90,T103
DetectSt->StableSt	191	Covered	T2,T36,T48
IdleSt->DebounceSt	148	Covered	T2,T9,T11
StableSt->IdleSt	206	Covered	T2,T36,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T67,T36
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T67,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T67,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T67,T90,T103
DetectSt	-	-	-	-	0	1	-	Covered	T2,T36,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T36,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T36,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	128	0	0
CntIncr_A	6968781	264196	0	0
CntNoWrap_A	6968781	6510169	0	0
DetectStDropOut_A	6968781	13	0	0
DetectedOut_A	6968781	57189	0	0
DetectedPulseOut_A	6968781	34	0	0
DisabledIdleSt_A	6968781	5333271	0	0
DisabledNoDetection_A	6968781	5335100	0	0
EnterDebounceSt_A	6968781	81	0	0
EnterDetectSt_A	6968781	47	0	0
EnterStableSt_A	6968781	34	0	0
PulseIsPulse_A	6968781	34	0	0
StayInStableSt	6968781	57155	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_sticky_sva.StableStDropOut_A	6968781	850435	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	128	0	0
T2	2225	6	0	0
T3	813	0	0	0
T9	0	8	0	0
T11	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	2	0	0
T36	0	4	0	0
T48	0	2	0	0
T62	426	0	0	0
T65	0	5	0	0
T67	0	3	0	0
T89	0	2	0	0
T90	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	264196	0	0
T2	2225	126	0	0
T3	813	0	0	0
T9	0	432	0	0
T11	0	71	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	82	0	0
T36	0	80	0	0
T48	0	77	0	0
T62	426	0	0	0
T65	0	80	0	0
T67	0	128	0	0
T89	0	52	0	0
T90	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510169	0	0
T1	522	121	0	0
T2	2225	1818	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	13	0	0
T36	1824	0	0	0
T46	1509	0	0	0
T49	649	0	0	0
T57	438	0	0	0
T67	1519	1	0	0
T71	2243	0	0	0
T79	502	0	0	0
T82	468	0	0	0
T90	0	2	0	0
T101	0	1	0	0
T103	0	2	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	422	0	0	0
T156	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	57189	0	0
T2	2225	419	0	0
T3	813	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	499	0	0
T48	0	338	0	0
T62	426	0	0	0
T89	0	109	0	0
T94	0	391	0	0
T101	0	1	0	0
T139	0	330	0	0
T141	0	302	0	0
T142	0	219	0	0
T143	0	914	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	34	0	0
T2	2225	3	0	0
T3	813	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T89	0	1	0	0
T94	0	1	0	0
T101	0	1	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5333271	0	0
T1	522	121	0	0
T2	2225	81	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5335100	0	0
T1	522	122	0	0
T2	2225	82	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	81	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	8	0	0
T11	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	5	0	0
T67	0	2	0	0
T89	0	1	0	0
T90	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	47	0	0
T2	2225	3	0	0
T3	813	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T67	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0
T94	0	1	0	0
T103	0	2	0	0
T139	0	1	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	34	0	0
T2	2225	3	0	0
T3	813	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T89	0	1	0	0
T94	0	1	0	0
T101	0	1	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	34	0	0
T2	2225	3	0	0
T3	813	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T89	0	1	0	0
T94	0	1	0	0
T101	0	1	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	57155	0	0
T2	2225	416	0	0
T3	813	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	497	0	0
T48	0	337	0	0
T62	426	0	0	0
T89	0	108	0	0
T94	0	390	0	0
T139	0	329	0	0
T141	0	301	0	0
T142	0	218	0	0
T143	0	912	0	0
T157	0	280	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	850435	0	0
T2	2225	1138	0	0
T3	813	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	733	0	0
T48	0	84	0	0
T62	426	0	0	0
T89	0	219	0	0
T94	0	169	0	0
T101	0	105	0	0
T139	0	158	0	0
T141	0	393	0	0
T142	0	470623	0	0
T143	0	126	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T5 T13 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T9 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T9 T25 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T9 T25 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T9 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T9 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T9 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T9 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T11 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T9 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T9 T67 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T9 T67 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T9 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T67 T65 T94 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T9 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T9 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T9 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T65 T95 T96 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T65 T95 T96 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T9 T36 
191        1/1                      state_d = StableSt;
           Tests:       T2 T9 T36 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T9 T36 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T9 T36 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T9 T36 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T9 T36 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T9 T36 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T9 T36 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T4,T5,T13
1	1	Covered	T2,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T36
0	1	Covered	T65,T95,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T36
0	1	Unreachable
1	0	Covered	T2,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T11
DetectSt	168	Covered	T2,T9,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T36
DebounceSt->IdleSt	163	Covered	T11,T67,T30
DetectSt->IdleSt	186	Covered	T65,T95,T96
DetectSt->StableSt	191	Covered	T2,T9,T36
IdleSt->DebounceSt	148	Covered	T2,T9,T11
StableSt->IdleSt	206	Covered	T2,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T36
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T67,T65,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T65,T95,T96
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	118	0	0
CntIncr_A	6968781	58044	0	0
CntNoWrap_A	6968781	6510179	0	0
DetectStDropOut_A	6968781	10	0	0
DetectedOut_A	6968781	426499	0	0
DetectedPulseOut_A	6968781	38	0	0
DisabledIdleSt_A	6968781	5333271	0	0
DisabledNoDetection_A	6968781	5335100	0	0
EnterDebounceSt_A	6968781	70	0	0
EnterDetectSt_A	6968781	48	0	0
EnterStableSt_A	6968781	38	0	0
PulseIsPulse_A	6968781	38	0	0
StayInStableSt	6968781	426461	0	0
gen_high_event_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_sticky_sva.StableStDropOut_A	6968781	457410	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	118	0	0
T2	2225	6	0	0
T3	813	0	0	0
T9	0	4	0	0
T11	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	2	0	0
T36	0	4	0	0
T48	0	2	0	0
T62	426	0	0	0
T65	0	7	0	0
T67	0	2	0	0
T89	0	2	0	0
T90	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	58044	0	0
T2	2225	255	0	0
T3	813	0	0	0
T9	0	176	0	0
T11	0	71	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	84	0	0
T36	0	184	0	0
T48	0	19	0	0
T62	426	0	0	0
T65	0	65	0	0
T67	0	166	0	0
T89	0	42	0	0
T90	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510179	0	0
T1	522	121	0	0
T2	2225	1818	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	10	0	0
T37	11947	0	0	0
T65	1269	2	0	0
T83	13194	0	0	0
T95	0	2	0	0
T96	0	5	0	0
T158	0	1	0	0
T159	785	0	0	0
T160	778	0	0	0
T161	424	0	0	0
T162	500	0	0	0
T163	411	0	0	0
T164	3661	0	0	0
T165	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	426499	0	0
T2	2225	1334	0	0
T3	813	0	0	0
T9	0	1151	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	1002	0	0
T48	0	92	0	0
T62	426	0	0	0
T89	0	204	0	0
T90	0	392	0	0
T103	0	493	0	0
T139	0	152	0	0
T140	0	259	0	0
T141	0	183	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T89	0	1	0	0
T90	0	1	0	0
T103	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5333271	0	0
T1	522	121	0	0
T2	2225	81	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5335100	0	0
T1	522	122	0	0
T2	2225	82	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	70	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	5	0	0
T67	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	48	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T65	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0
T103	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T89	0	1	0	0
T90	0	1	0	0
T103	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T2	2225	3	0	0
T3	813	0	0	0
T9	0	2	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	2	0	0
T48	0	1	0	0
T62	426	0	0	0
T89	0	1	0	0
T90	0	1	0	0
T103	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	426461	0	0
T2	2225	1331	0	0
T3	813	0	0	0
T9	0	1149	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	1000	0	0
T48	0	91	0	0
T62	426	0	0	0
T89	0	203	0	0
T90	0	391	0	0
T103	0	492	0	0
T139	0	151	0	0
T140	0	258	0	0
T141	0	182	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	457410	0	0
T2	2225	135	0	0
T3	813	0	0	0
T9	0	233	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	0	0	0
T18	446	0	0	0
T19	526	0	0	0
T20	424	0	0	0
T27	503	0	0	0
T36	0	161	0	0
T48	0	390	0	0
T62	426	0	0	0
T89	0	148	0	0
T90	0	308	0	0
T103	0	42	0	0
T139	0	373	0	0
T140	0	407	0	0
T141	0	539	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T46 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T46 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T46 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T46 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T46 T30 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T46 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T46 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T46 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T46 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T166 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T46 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T46 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T46 T30 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T46 T30 
191        1/1                      state_d = StableSt;
           Tests:       T11 T46 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T46 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T46 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T46 T30 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T46 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T46 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T46 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T46,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T46,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T46,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T46,T49
1	0	Covered	T4,T5,T1
1	1	Covered	T11,T46,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T46,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T46,T30
0	1	Covered	T46,T45,T167
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T46,T30
1	-	Covered	T46,T45,T167

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T46,T30
DetectSt	168	Covered	T11,T46,T30
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T46,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T46,T30
DebounceSt->IdleSt	163	Covered	T166
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T46,T30
IdleSt->DebounceSt	148	Covered	T11,T46,T30
StableSt->IdleSt	206	Covered	T11,T46,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T46,T30
0	1	Covered	T11,T46,T30
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T46,T30
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T46,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T46,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T166
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T46,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T46,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T46,T30
StableSt	-	-	-	-	-	-	0	Covered	T11,T46,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	47	0	0
CntIncr_A	6968781	18350	0	0
CntNoWrap_A	6968781	6510250	0	0
DetectStDropOut_A	6968781	0	0	0
DetectedOut_A	6968781	1247	0	0
DetectedPulseOut_A	6968781	23	0	0
DisabledIdleSt_A	6968781	6242639	0	0
DisabledNoDetection_A	6968781	6244437	0	0
EnterDebounceSt_A	6968781	24	0	0
EnterDetectSt_A	6968781	23	0	0
EnterStableSt_A	6968781	23	0	0
PulseIsPulse_A	6968781	23	0	0
StayInStableSt	6968781	1213	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	47	0	0
T11	7404	2	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	18350	0	0
T11	7404	19	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	26	0	0
T45	0	37	0	0
T46	0	46	0	0
T48	0	30	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T166	0	77	0	0
T167	0	83	0	0
T168	0	70	0	0
T169	0	50	0	0
T170	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510250	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1247	0	0
T11	7404	15	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	8	0	0
T45	0	78	0	0
T46	0	92	0	0
T48	0	72	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T167	0	42	0	0
T168	0	71	0	0
T169	0	44	0	0
T170	0	38	0	0
T171	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	23	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6242639	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6244437	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	24	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	23	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	23	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	23	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1213	0	0
T11	7404	14	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	7	0	0
T45	0	77	0	0
T46	0	91	0	0
T48	0	70	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T167	0	41	0	0
T168	0	69	0	0
T169	0	43	0	0
T170	0	36	0	0
T171	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	10	0	0
T36	1824	0	0	0
T45	0	1	0	0
T46	1509	1	0	0
T49	649	0	0	0
T58	648	0	0	0
T71	2243	0	0	0
T155	422	0	0	0
T156	524	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	504	0	0	0
T178	8425	0	0	0
T179	418	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T8 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T8 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T8 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T8 T11 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T8 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T8 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T8 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T8 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T172 T180 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T8 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T8 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T93 T181 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T93 T181 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T8 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T8 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T8 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T8 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T8 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T8 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T11 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T8 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T4,T5,T13
1	1	Covered	T3,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T93,T181
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T48,T168
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T11
1	-	Covered	T3,T48,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T11
DetectSt	168	Covered	T3,T8,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T11
DebounceSt->IdleSt	163	Covered	T172,T180
DetectSt->IdleSt	186	Covered	T93,T181
DetectSt->StableSt	191	Covered	T3,T8,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T11
StableSt->IdleSt	206	Covered	T3,T11,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T93,T181
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T30
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	70	0	0
CntIncr_A	6968781	20285	0	0
CntNoWrap_A	6968781	6510227	0	0
DetectStDropOut_A	6968781	2	0	0
DetectedOut_A	6968781	2385	0	0
DetectedPulseOut_A	6968781	32	0	0
DisabledIdleSt_A	6968781	6432455	0	0
DisabledNoDetection_A	6968781	6434255	0	0
EnterDebounceSt_A	6968781	37	0	0
EnterDetectSt_A	6968781	34	0	0
EnterStableSt_A	6968781	32	0	0
PulseIsPulse_A	6968781	32	0	0
StayInStableSt	6968781	2340	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	1486	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	70	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	2	0	0
T11	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T48	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	2	0	0
T166	0	4	0	0
T168	0	2	0	0
T169	0	4	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	20285	0	0
T3	813	42	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	94	0	0
T11	0	19	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T48	0	30	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	90	0	0
T166	0	154	0	0
T168	0	70	0	0
T169	0	100	0	0
T182	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510227	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2	0	0
T93	539	1	0	0
T129	433	0	0	0
T130	618	0	0	0
T131	429	0	0	0
T132	494	0	0	0
T133	522	0	0	0
T134	504	0	0	0
T181	0	1	0	0
T183	526	0	0	0
T184	5464	0	0	0
T185	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2385	0	0
T3	813	43	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	42	0	0
T11	0	14	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T48	0	163	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	92	0	0
T166	0	427	0	0
T168	0	8	0	0
T169	0	94	0	0
T182	0	98	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	32	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6432455	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6434255	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	37	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	34	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	32	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	32	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2340	0	0
T3	813	42	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	40	0	0
T11	0	13	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T48	0	162	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T159	0	91	0	0
T166	0	424	0	0
T168	0	7	0	0
T169	0	91	0	0
T182	0	96	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1486	0	0
T1	522	0	0	0
T2	2225	0	0	0
T3	0	1	0	0
T4	496	3	0	0
T5	423	2	0	0
T6	0	2	0	0
T13	499	4	0	0
T14	405	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	4	0	0
T18	446	0	0	0
T19	0	6	0	0
T20	0	2	0	0
T27	0	3	0	0
T62	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	17	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T101	0	1	0	0
T159	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T186	0	2	0	0
T187	0	1	0	0
T188	0	1	0	0