Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 4 0 4 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 1 0 1 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 4 0 4 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values_0 1886 1 T7 1 T8 1 T47 1



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1002 1 T7 1 T47 1 T70 1
auto[1] 884 1 T8 1 T42 1 T2 2



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 945 1 T7 1 T8 1 T2 1
auto[1] 941 1 T47 1 T42 1 T2 1



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values_0 auto[0] auto[0] 510 1 T7 1 T70 1 T71 1
all_values_0 auto[0] auto[1] 492 1 T47 1 T4 2 T44 1
all_values_0 auto[1] auto[0] 435 1 T8 1 T2 1 T3 1
all_values_0 auto[1] auto[1] 449 1 T42 1 T2 1 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%