Assertions
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Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.CntClr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.CntIncr_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.EnterDebounceSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.EnterDetectSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h.DetectedOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h.DetectedPulseOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h.EnterStableSt_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h.PulseIsPulse_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h.StayInStableSt 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l.gen_not_sticky_sva.StableStDropOut_A 002047956000
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A 002047956000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertKnown_A 0042142101742051797400
tb.dut.BatOEnIsOne_A 0042142101742051797400
tb.dut.BatOKnown_A 0042142101742051797400
tb.dut.ECRSTOEnIsOne_A 0042142101742051797400
tb.dut.ECRSTOKnown_A 0042142101742051797400
tb.dut.FlashWpOEnIsOne_A 0042142101742051797400
tb.dut.FlashWpOKnown_A 0042142101742051797400
tb.dut.FpvSecCmRegWeOnehotCheck_A 004214210178000
tb.dut.IntrEventOKnown_A 0042142101742051797400
tb.dut.Key0OEnIsOne_A 0042142101742051797400
tb.dut.Key0OKnown_A 0042142101742051797400
tb.dut.Key1OEnIsOne_A 0042142101742051797400
tb.dut.Key1OKnown_A 0042142101742051797400
tb.dut.Key2OEnIsOne_A 0042142101742051797400
tb.dut.Key2OKnown_A 0042142101742051797400
tb.dut.OTRstOKnown_A 0042142101742051797400
tb.dut.OTWkOKnown_A 0042142101742051797400
tb.dut.PwrbOEnIsOne_A 0042142101742051797400
tb.dut.PwrbOKnown_A 0042142101742051797400
tb.dut.TlOAReadyKnown_A 0042142101742051797400
tb.dut.TlODValidKnown_A 0042142101742051797400
tb.dut.Z3WakeupOEnIsOne_A 0042142101742051797400
tb.dut.Z3WwakupOKnown_A 0042142101742051797400
tb.dut.sysrst_ctrl_csr_assert.TlulOOBAddrErr_A 00461473945916600
tb.dut.sysrst_ctrl_csr_assert.auto_block_debounce_ctl_rd_A 00461473945119900
tb.dut.sysrst_ctrl_csr_assert.auto_block_out_ctl_rd_A 00461473945218700
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_0_rd_A 00461473945230400
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_1_rd_A 00461473945228300
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_2_rd_A 00461473945242400
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_3_rd_A 00461473945245600
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_0_rd_A 00461473945297300
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_1_rd_A 00461473945321600
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_2_rd_A 00461473945282900
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_3_rd_A 00461473945290200
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_0_rd_A 00461473945100000
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_1_rd_A 0046147394597800
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_2_rd_A 00461473945100200
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_3_rd_A 00461473945108100
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_0_rd_A 00461473945155700
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_1_rd_A 00461473945164200
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_2_rd_A 00461473945179000
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_3_rd_A 00461473945148500
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_0_rd_A 00461473945314000
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_1_rd_A 00461473945315500
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_2_rd_A 00461473945329300
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_3_rd_A 00461473945316000
tb.dut.sysrst_ctrl_csr_assert.ec_rst_ctl_rd_A 00461473945101900
tb.dut.sysrst_ctrl_csr_assert.intr_enable_rd_A 00461473945148700
tb.dut.sysrst_ctrl_csr_assert.key_intr_ctl_rd_A 00461473945345800
tb.dut.sysrst_ctrl_csr_assert.key_intr_debounce_ctl_rd_A 0046147394599400
tb.dut.sysrst_ctrl_csr_assert.key_invert_ctl_rd_A 00461473945369200
tb.dut.sysrst_ctrl_csr_assert.pin_allowed_ctl_rd_A 00461473945428500
tb.dut.sysrst_ctrl_csr_assert.pin_out_ctl_rd_A 00461473945298600
tb.dut.sysrst_ctrl_csr_assert.pin_out_value_rd_A 00461473945319900
tb.dut.sysrst_ctrl_csr_assert.regwen_rd_A 00461473945116300
tb.dut.sysrst_ctrl_csr_assert.ulp_ac_debounce_ctl_rd_A 00461473945100400
tb.dut.sysrst_ctrl_csr_assert.ulp_ctl_rd_A 00461473945103000
tb.dut.sysrst_ctrl_csr_assert.ulp_lid_debounce_ctl_rd_A 0046147394596400
tb.dut.sysrst_ctrl_csr_assert.ulp_pwrb_debounce_ctl_rd_A 00461473945113100
tb.dut.tlul_assert_device.aKnown_A 00461473945996328500
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0046147394546048253100
tb.dut.tlul_assert_device.aReadyKnown_A 0046147394546048253100
tb.dut.tlul_assert_device.dKnown_A 0046147394532523000
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0046147394546048253100
tb.dut.tlul_assert_device.dReadyKnown_A 0046147394546048253100
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 0076276200
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tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 0076276200
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tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 0076276200
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tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 0076276200
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tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 0076276200
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tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 0076276200
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 0076276200
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1058010
Category 01058010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1058010
Severity 01058010


Summary for Assertions
NUMBERPERCENT
Total Number1058100.00
Uncovered11911.25
Success93988.75
Failure00.00
Incomplete40.38
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%