Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 99.03 97.85 100.00 92.31 99.26 98.84 86.61


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.75 46.75 63.77 63.77 49.76 49.76 80.37 80.37 0.00 0.00 68.05 68.05 52.41 52.41 12.92 12.92 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2559007234
77.30 30.55 92.91 29.14 86.19 36.43 87.44 7.08 73.08 73.08 94.55 26.50 91.33 38.92 15.60 2.68 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.1221151344
80.38 3.08 94.50 1.59 88.85 2.65 95.43 7.99 73.08 0.00 96.03 1.48 92.39 1.06 22.41 6.81 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.842770191
82.34 1.96 95.02 0.52 89.79 0.94 96.12 0.68 73.08 0.00 96.33 0.30 92.49 0.10 33.59 11.18 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.899186097
84.03 1.69 95.92 0.90 90.80 1.01 96.35 0.23 79.49 6.41 97.03 0.70 94.61 2.12 34.05 0.47 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1427560171
85.59 1.55 96.56 0.64 90.85 0.05 96.35 0.00 89.10 9.62 97.59 0.56 94.61 0.00 34.05 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1307214762
86.88 1.30 96.58 0.02 91.68 0.83 97.03 0.68 89.10 0.00 97.63 0.04 94.61 0.00 41.56 7.51 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3503149454
87.98 1.10 96.61 0.04 92.62 0.94 97.26 0.23 89.10 0.00 97.92 0.30 94.61 0.00 47.73 6.17 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2371969372
89.03 1.05 96.89 0.28 93.43 0.81 97.26 0.00 89.10 0.00 97.92 0.00 94.80 0.19 53.78 6.05 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2143253305
89.85 0.82 96.89 0.00 93.43 0.00 97.26 0.00 89.10 0.00 97.92 0.00 94.80 0.00 59.55 5.76 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.903978723
90.44 0.59 96.93 0.04 93.45 0.03 97.26 0.00 89.10 0.00 97.96 0.04 94.80 0.00 63.56 4.02 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.51694209
91.01 0.57 98.15 1.22 94.49 1.04 97.49 0.23 89.10 0.00 98.33 0.37 95.95 1.16 63.56 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.456706244
91.44 0.43 98.22 0.07 94.61 0.13 97.95 0.46 89.10 0.00 98.41 0.07 96.24 0.29 65.54 1.98 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3621452415
91.85 0.42 98.26 0.04 94.69 0.08 97.95 0.00 89.10 0.00 98.41 0.00 96.24 0.00 68.34 2.79 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.1422526474
92.25 0.39 98.32 0.06 94.97 0.28 97.95 0.00 89.10 0.00 98.44 0.04 96.34 0.10 70.61 2.27 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3964804115
92.59 0.35 98.33 0.02 94.97 0.00 97.95 0.00 89.10 0.00 98.48 0.04 96.34 0.00 72.99 2.39 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.583564652
92.92 0.32 98.33 0.00 95.02 0.05 99.77 1.83 89.10 0.00 98.48 0.00 96.44 0.10 73.28 0.29 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3715719340
93.17 0.25 98.43 0.09 95.12 0.10 99.77 0.00 90.38 1.28 98.59 0.11 96.63 0.19 73.28 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4196742745
93.42 0.25 98.43 0.00 95.15 0.03 99.77 0.00 90.38 0.00 98.59 0.00 96.72 0.10 74.91 1.63 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.202928468
93.62 0.20 98.43 0.00 95.15 0.00 99.77 0.00 90.38 0.00 98.59 0.00 96.72 0.00 76.31 1.40 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1490768042
93.81 0.19 98.47 0.04 96.03 0.88 99.77 0.00 90.38 0.00 98.59 0.00 96.82 0.10 76.60 0.29 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3995127925
93.99 0.18 98.50 0.04 96.46 0.43 99.77 0.00 90.38 0.00 98.67 0.07 97.50 0.67 76.66 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.349574754
94.16 0.17 98.54 0.04 96.64 0.18 99.77 0.00 91.03 0.64 98.70 0.04 97.78 0.29 76.66 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1735238661
94.32 0.16 98.54 0.00 96.69 0.05 99.77 0.00 91.03 0.00 98.70 0.00 97.88 0.10 77.65 0.99 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.1527154259
94.48 0.16 98.56 0.02 96.71 0.03 99.77 0.00 91.03 0.00 98.70 0.00 97.88 0.00 78.70 1.05 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1135120743
94.63 0.16 98.62 0.06 96.84 0.13 99.77 0.00 91.67 0.64 98.78 0.07 98.07 0.19 78.70 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4035605069
94.77 0.14 98.63 0.02 96.84 0.00 99.77 0.00 91.67 0.00 98.78 0.00 98.07 0.00 79.63 0.93 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3706186195
94.90 0.13 98.67 0.04 96.86 0.03 99.77 0.00 92.31 0.64 98.81 0.04 98.17 0.10 79.69 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1074400184
95.01 0.12 98.67 0.00 96.86 0.00 99.77 0.00 92.31 0.00 98.81 0.00 98.17 0.00 80.50 0.81 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3667750333
95.13 0.12 98.67 0.00 96.86 0.00 99.77 0.00 92.31 0.00 98.81 0.00 98.17 0.00 81.32 0.81 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1222775905
95.23 0.09 98.73 0.06 96.99 0.13 99.77 0.00 92.31 0.00 98.89 0.07 98.17 0.00 81.72 0.41 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1502255052
95.30 0.08 98.73 0.00 97.02 0.03 99.77 0.00 92.31 0.00 98.89 0.00 98.27 0.10 82.13 0.41 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4011153431
95.38 0.07 98.73 0.00 97.19 0.18 99.77 0.00 92.31 0.00 98.89 0.00 98.55 0.29 82.19 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.585974051
95.43 0.05 98.78 0.06 97.27 0.08 100.00 0.23 92.31 0.00 98.89 0.00 98.55 0.00 82.19 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.225176810
95.48 0.05 98.78 0.00 97.27 0.00 100.00 0.00 92.31 0.00 98.89 0.00 98.55 0.00 82.54 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1044928680
95.53 0.05 98.78 0.00 97.27 0.00 100.00 0.00 92.31 0.00 98.89 0.00 98.55 0.00 82.89 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1618692249
95.58 0.05 98.80 0.02 97.27 0.00 100.00 0.00 92.31 0.00 98.93 0.04 98.55 0.00 83.18 0.29 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2344515100
95.62 0.04 98.80 0.00 97.27 0.00 100.00 0.00 92.31 0.00 98.93 0.00 98.55 0.00 83.47 0.29 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1831377135
95.66 0.04 98.80 0.00 97.27 0.00 100.00 0.00 92.31 0.00 98.93 0.00 98.55 0.00 83.76 0.29 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.310071825
95.70 0.04 98.82 0.02 97.37 0.10 100.00 0.00 92.31 0.00 99.00 0.07 98.65 0.10 83.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3285728783
95.74 0.03 98.82 0.00 97.40 0.03 100.00 0.00 92.31 0.00 99.00 0.00 98.75 0.10 83.88 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1784617522
95.77 0.03 98.82 0.00 97.40 0.00 100.00 0.00 92.31 0.00 99.00 0.00 98.75 0.00 84.11 0.23 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.892693910
95.80 0.03 98.82 0.00 97.40 0.00 100.00 0.00 92.31 0.00 99.00 0.00 98.75 0.00 84.34 0.23 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3555246331
95.84 0.03 98.82 0.00 97.40 0.00 100.00 0.00 92.31 0.00 99.00 0.00 98.75 0.00 84.58 0.23 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.320411179
95.87 0.03 98.84 0.02 97.47 0.08 100.00 0.00 92.31 0.00 99.04 0.04 98.84 0.10 84.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2857677027
95.90 0.03 98.84 0.00 97.70 0.23 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 84.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1699189278
95.93 0.02 98.84 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 84.75 0.17 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3890620846
95.95 0.02 98.84 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 84.92 0.17 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.320850822
95.98 0.02 98.84 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.10 0.17 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1474228812
95.99 0.02 98.86 0.02 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.22 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.493746009
96.01 0.02 98.86 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.33 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3285815172
96.03 0.02 98.86 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.45 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.73207015
96.04 0.02 98.86 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.56 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1920219921
96.06 0.02 98.86 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.68 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2934535082
96.08 0.02 98.86 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.80 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.1895912324
96.09 0.02 98.86 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.84 0.00 85.91 0.12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3428439877
96.11 0.02 98.88 0.02 97.70 0.00 100.00 0.00 92.31 0.00 99.07 0.04 98.84 0.00 85.97 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2534349858
96.13 0.02 98.91 0.04 97.70 0.00 100.00 0.00 92.31 0.00 99.15 0.07 98.84 0.00 85.97 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3003896791
96.14 0.01 98.91 0.00 97.72 0.03 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.03 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1141757929
96.15 0.01 98.95 0.04 97.75 0.03 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.03 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1908597495
96.16 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.09 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1975072022
96.16 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.15 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.963461190
96.17 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.20 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3255213688
96.18 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.26 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1966580016
96.19 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.32 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3232010227
96.20 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.38 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.421199457
96.21 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.44 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2813045940
96.21 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.50 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2729548379
96.22 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.55 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1591718770
96.23 0.01 98.95 0.00 97.75 0.00 100.00 0.00 92.31 0.00 99.15 0.00 98.84 0.00 86.61 0.06 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1785587529
96.24 0.01 98.97 0.02 97.75 0.00 100.00 0.00 92.31 0.00 99.18 0.04 98.84 0.00 86.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.4249522773
96.25 0.01 98.99 0.02 97.75 0.00 100.00 0.00 92.31 0.00 99.22 0.04 98.84 0.00 86.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3667593714
96.25 0.01 99.01 0.02 97.75 0.00 100.00 0.00 92.31 0.00 99.26 0.04 98.84 0.00 86.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.746182414
96.26 0.01 99.01 0.00 97.80 0.05 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 86.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1548605388
96.27 0.01 99.01 0.00 97.83 0.03 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 86.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2212878052
96.27 0.01 99.01 0.00 97.85 0.03 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 86.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3439333975
96.27 0.01 99.03 0.02 97.85 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 86.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3186193318

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.733398281
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2793352959
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3140075486
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3575849828
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1025560208
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2943100328
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1569140929
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3040150704
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1983032340
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3501269237
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1918648987
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2448840312
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.593643725
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1130856145
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3975339717
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4124000339
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2780861011
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3502547829
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1453726007
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2335164646
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3908446484
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.931686032
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.657063840
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3447555285
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4075041345
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3576826245
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1287354091
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.838156816
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3834151602
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.4255422931
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2267701390
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2236941909
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1353445871
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.357384905
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.526124430
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3829718482
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.98064534
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2930617610
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.756745539
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1794936173
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2119506561
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1196404308
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1950292391
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1972484326
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2840606243
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3278383016
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3876144916
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2442832538
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2603617739
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3930929015
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4041331824
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1076069097
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.760433618
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1939895810
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.958792403
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3061008681
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3799158249
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4191763343
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3459181740
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.885389992
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Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2599290825 Oct 14 10:12:11 PM UTC 24 Oct 14 10:12:17 PM UTC 24 2529161179 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1779527053 Oct 14 10:12:13 PM UTC 24 Oct 14 10:12:17 PM UTC 24 2237246557 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.842770191 Oct 14 10:12:08 PM UTC 24 Oct 14 10:12:20 PM UTC 24 2483158280 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.3940636241 Oct 14 10:12:08 PM UTC 24 Oct 14 10:12:20 PM UTC 24 2110371376 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1908597495 Oct 14 10:12:09 PM UTC 24 Oct 14 10:12:24 PM UTC 24 2420015680 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.4229139016 Oct 14 10:12:17 PM UTC 24 Oct 14 10:12:26 PM UTC 24 2614937178 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.963461190 Oct 14 10:12:18 PM UTC 24 Oct 14 10:12:28 PM UTC 24 3542762541 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1480757640 Oct 14 10:12:18 PM UTC 24 Oct 14 10:12:29 PM UTC 24 3372515229 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2559007234 Oct 14 10:12:23 PM UTC 24 Oct 14 10:12:30 PM UTC 24 7614784845 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1455557619 Oct 14 10:12:26 PM UTC 24 Oct 14 10:12:31 PM UTC 24 2487051433 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3429806117 Oct 14 10:12:20 PM UTC 24 Oct 14 10:12:33 PM UTC 24 3548057224 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1044928680 Oct 14 10:12:17 PM UTC 24 Oct 14 10:12:34 PM UTC 24 2510586543 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.4133586243 Oct 14 10:12:18 PM UTC 24 Oct 14 10:12:35 PM UTC 24 5716823503 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.225176810 Oct 14 10:12:26 PM UTC 24 Oct 14 10:12:35 PM UTC 24 2010153322 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2871473337 Oct 14 10:12:27 PM UTC 24 Oct 14 10:12:38 PM UTC 24 2539628446 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1061841862 Oct 14 10:12:26 PM UTC 24 Oct 14 10:12:38 PM UTC 24 2113147768 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2965485892 Oct 14 10:12:26 PM UTC 24 Oct 14 10:12:39 PM UTC 24 2425921811 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2034243506 Oct 14 10:12:29 PM UTC 24 Oct 14 10:12:39 PM UTC 24 2509759134 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.23765879 Oct 14 10:12:31 PM UTC 24 Oct 14 10:12:39 PM UTC 24 2618331841 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.1836947876 Oct 14 10:12:29 PM UTC 24 Oct 14 10:12:40 PM UTC 24 2206903471 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3403041096 Oct 14 10:12:39 PM UTC 24 Oct 14 10:12:43 PM UTC 24 2030406937 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.73207015 Oct 14 10:12:40 PM UTC 24 Oct 14 10:12:43 PM UTC 24 2534489485 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1003746872 Oct 14 10:12:33 PM UTC 24 Oct 14 10:12:43 PM UTC 24 3080376940 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.525084165 Oct 14 10:12:41 PM UTC 24 Oct 14 10:12:45 PM UTC 24 2101792868 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.1553636460 Oct 14 10:12:41 PM UTC 24 Oct 14 10:12:46 PM UTC 24 2527819226 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2371969372 Oct 14 10:12:36 PM UTC 24 Oct 14 10:12:47 PM UTC 24 11879315308 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.300392883 Oct 14 10:12:31 PM UTC 24 Oct 14 10:12:48 PM UTC 24 4638576602 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3027345306 Oct 14 10:12:40 PM UTC 24 Oct 14 10:12:50 PM UTC 24 2403611588 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.767225214 Oct 14 10:12:40 PM UTC 24 Oct 14 10:12:50 PM UTC 24 2111264891 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.456706244 Oct 14 10:12:45 PM UTC 24 Oct 14 10:12:50 PM UTC 24 3472868895 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3473154789 Oct 14 10:12:42 PM UTC 24 Oct 14 10:12:50 PM UTC 24 2617859632 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4265271657 Oct 14 10:12:40 PM UTC 24 Oct 14 10:12:53 PM UTC 24 2353551126 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2100551169 Oct 14 10:12:35 PM UTC 24 Oct 14 10:12:53 PM UTC 24 6560503057 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.892693910 Oct 14 10:12:31 PM UTC 24 Oct 14 10:12:53 PM UTC 24 3419365342 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1528112299 Oct 14 10:12:43 PM UTC 24 Oct 14 10:12:55 PM UTC 24 3524038824 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.440118512 Oct 14 10:12:52 PM UTC 24 Oct 14 10:12:57 PM UTC 24 2264755704 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.1221151344 Oct 14 10:12:21 PM UTC 24 Oct 14 10:12:57 PM UTC 24 36343184158 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2963063883 Oct 14 10:12:53 PM UTC 24 Oct 14 10:12:57 PM UTC 24 2239713994 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2192239587 Oct 14 10:12:51 PM UTC 24 Oct 14 10:12:58 PM UTC 24 2023003421 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.3729370460 Oct 14 10:12:50 PM UTC 24 Oct 14 10:12:58 PM UTC 24 11098488152 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2151420771 Oct 14 10:12:53 PM UTC 24 Oct 14 10:12:58 PM UTC 24 2534104741 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.146808423 Oct 14 10:12:54 PM UTC 24 Oct 14 10:12:59 PM UTC 24 2627532541 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.899186097 Oct 14 10:12:33 PM UTC 24 Oct 14 10:12:59 PM UTC 24 42730424706 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1830945974 Oct 14 10:12:51 PM UTC 24 Oct 14 10:12:59 PM UTC 24 2469922330 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2534349858 Oct 14 10:12:44 PM UTC 24 Oct 14 10:13:00 PM UTC 24 8434554874 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1427560171 Oct 14 10:12:32 PM UTC 24 Oct 14 10:13:01 PM UTC 24 2270225927271 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.145172493 Oct 14 10:12:42 PM UTC 24 Oct 14 10:13:02 PM UTC 24 3735233881 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.267962339 Oct 14 10:12:51 PM UTC 24 Oct 14 10:13:02 PM UTC 24 2111831888 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1857055160 Oct 14 10:12:51 PM UTC 24 Oct 14 10:13:02 PM UTC 24 2190330939 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2102582595 Oct 14 10:12:49 PM UTC 24 Oct 14 10:13:03 PM UTC 24 5505378063 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3868449746 Oct 14 10:12:59 PM UTC 24 Oct 14 10:13:03 PM UTC 24 2025743280 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3661949844 Oct 14 10:13:00 PM UTC 24 Oct 14 10:13:04 PM UTC 24 2307297525 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.4160343979 Oct 14 10:12:57 PM UTC 24 Oct 14 10:13:08 PM UTC 24 3148483639 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3176922494 Oct 14 10:13:03 PM UTC 24 Oct 14 10:13:08 PM UTC 24 10587709142 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.502239188 Oct 14 10:12:58 PM UTC 24 Oct 14 10:13:05 PM UTC 24 4762002061 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4247018035 Oct 14 10:13:00 PM UTC 24 Oct 14 10:13:05 PM UTC 24 2415986927 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1284530329 Oct 14 10:13:00 PM UTC 24 Oct 14 10:13:05 PM UTC 24 2114925000 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2183263139 Oct 14 10:12:58 PM UTC 24 Oct 14 10:13:05 PM UTC 24 6010816914 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.3011985396 Oct 14 10:13:02 PM UTC 24 Oct 14 10:13:07 PM UTC 24 2530818558 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.64989996 Oct 14 10:13:02 PM UTC 24 Oct 14 10:13:07 PM UTC 24 2616396644 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3759758627 Oct 14 10:12:48 PM UTC 24 Oct 14 10:13:07 PM UTC 24 25859383859 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.1177304343 Oct 14 10:13:02 PM UTC 24 Oct 14 10:13:08 PM UTC 24 2249772742 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1155553927 Oct 14 10:13:00 PM UTC 24 Oct 14 10:13:08 PM UTC 24 2473626807 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.165097832 Oct 14 10:13:03 PM UTC 24 Oct 14 10:13:09 PM UTC 24 2992674724 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.701072507 Oct 14 10:12:59 PM UTC 24 Oct 14 10:13:10 PM UTC 24 3747383246 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3964804115 Oct 14 10:12:25 PM UTC 24 Oct 14 10:13:11 PM UTC 24 10589891379 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.2808573590 Oct 14 10:13:06 PM UTC 24 Oct 14 10:13:11 PM UTC 24 2047877398 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.585974051 Oct 14 10:13:04 PM UTC 24 Oct 14 10:13:11 PM UTC 24 5879706814 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2728427613 Oct 14 10:12:56 PM UTC 24 Oct 14 10:13:12 PM UTC 24 3700614502 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1740352434 Oct 14 10:13:09 PM UTC 24 Oct 14 10:13:13 PM UTC 24 2647747898 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.186996053 Oct 14 10:13:08 PM UTC 24 Oct 14 10:13:13 PM UTC 24 2475688258 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1677299190 Oct 14 10:13:09 PM UTC 24 Oct 14 10:13:13 PM UTC 24 3571520052 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2663941043 Oct 14 10:13:09 PM UTC 24 Oct 14 10:13:15 PM UTC 24 2532888216 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.4268339581 Oct 14 10:13:06 PM UTC 24 Oct 14 10:13:16 PM UTC 24 2108750369 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.294499242 Oct 14 10:13:08 PM UTC 24 Oct 14 10:13:17 PM UTC 24 2073097861 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1230220830 Oct 14 10:13:13 PM UTC 24 Oct 14 10:13:17 PM UTC 24 2026255097 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3714459768 Oct 14 10:13:03 PM UTC 24 Oct 14 10:13:18 PM UTC 24 3450920961 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.256784051 Oct 14 10:13:14 PM UTC 24 Oct 14 10:13:19 PM UTC 24 2137294480 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3386299059 Oct 14 10:13:15 PM UTC 24 Oct 14 10:13:20 PM UTC 24 2524514148 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.1142300552 Oct 14 10:13:15 PM UTC 24 Oct 14 10:13:20 PM UTC 24 2088471957 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.538640725 Oct 14 10:13:16 PM UTC 24 Oct 14 10:13:21 PM UTC 24 2623005095 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.211013391 Oct 14 10:13:09 PM UTC 24 Oct 14 10:13:22 PM UTC 24 3349239432 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.537874191 Oct 14 10:13:05 PM UTC 24 Oct 14 10:13:22 PM UTC 24 3222420878 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2886207795 Oct 14 10:13:17 PM UTC 24 Oct 14 10:13:22 PM UTC 24 4833804446 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2395417641 Oct 14 10:13:15 PM UTC 24 Oct 14 10:13:23 PM UTC 24 2470926902 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2485198510 Oct 14 10:13:18 PM UTC 24 Oct 14 10:13:23 PM UTC 24 6678674414 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.3388453981 Oct 14 10:13:19 PM UTC 24 Oct 14 10:13:24 PM UTC 24 3201833411 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.710403998 Oct 14 10:13:11 PM UTC 24 Oct 14 10:13:25 PM UTC 24 3330233711 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1880613402 Oct 14 10:13:10 PM UTC 24 Oct 14 10:13:26 PM UTC 24 4393506733 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.226394582 Oct 14 10:13:12 PM UTC 24 Oct 14 10:13:26 PM UTC 24 3339173949 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1508447815 Oct 14 10:13:23 PM UTC 24 Oct 14 10:13:27 PM UTC 24 2140610828 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.80086012 Oct 14 10:13:23 PM UTC 24 Oct 14 10:13:27 PM UTC 24 2044961200 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.619435162 Oct 14 10:13:24 PM UTC 24 Oct 14 10:13:28 PM UTC 24 2507023964 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3770265788 Oct 14 10:13:26 PM UTC 24 Oct 14 10:13:30 PM UTC 24 3358233337 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.1684661590 Oct 14 10:13:24 PM UTC 24 Oct 14 10:13:32 PM UTC 24 2521413080 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2419296359 Oct 14 10:13:12 PM UTC 24 Oct 14 10:13:32 PM UTC 24 6952504148 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3734119544 Oct 14 10:13:05 PM UTC 24 Oct 14 10:13:32 PM UTC 24 7936465163 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2861760113 Oct 14 10:13:28 PM UTC 24 Oct 14 10:13:32 PM UTC 24 3014685830 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1026895306 Oct 14 10:13:18 PM UTC 24 Oct 14 10:13:34 PM UTC 24 3466807696 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2313153901 Oct 14 10:13:26 PM UTC 24 Oct 14 10:13:35 PM UTC 24 3447714720 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.431795807 Oct 14 10:13:24 PM UTC 24 Oct 14 10:13:36 PM UTC 24 2100605404 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.4227208249 Oct 14 10:13:33 PM UTC 24 Oct 14 10:13:38 PM UTC 24 2472663252 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.4010716946 Oct 14 10:13:33 PM UTC 24 Oct 14 10:13:38 PM UTC 24 2112520954 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.3074634551 Oct 14 10:13:32 PM UTC 24 Oct 14 10:13:38 PM UTC 24 2018957370 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2422915406 Oct 14 10:13:21 PM UTC 24 Oct 14 10:13:39 PM UTC 24 3370335164 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1411778181 Oct 14 10:13:25 PM UTC 24 Oct 14 10:13:39 PM UTC 24 2612626872 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.2895854329 Oct 14 10:13:33 PM UTC 24 Oct 14 10:13:41 PM UTC 24 2081051904 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1387597421 Oct 14 10:13:33 PM UTC 24 Oct 14 10:13:42 PM UTC 24 2514255124 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.479986225 Oct 14 10:13:39 PM UTC 24 Oct 14 10:13:42 PM UTC 24 10536371408 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3715719340 Oct 14 10:12:37 PM UTC 24 Oct 14 10:13:43 PM UTC 24 42019146720 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.4194876481 Oct 14 10:13:37 PM UTC 24 Oct 14 10:13:45 PM UTC 24 3719516671 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.1163849416 Oct 14 10:13:43 PM UTC 24 Oct 14 10:13:48 PM UTC 24 2460954714 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.1567497535 Oct 14 10:13:43 PM UTC 24 Oct 14 10:13:49 PM UTC 24 2121089531 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.2857630915 Oct 14 10:13:45 PM UTC 24 Oct 14 10:13:49 PM UTC 24 2092510207 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1958736733 Oct 14 10:13:35 PM UTC 24 Oct 14 10:13:50 PM UTC 24 2612539274 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3926960217 Oct 14 10:13:22 PM UTC 24 Oct 14 10:13:51 PM UTC 24 10867649407 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3998727803 Oct 14 10:13:29 PM UTC 24 Oct 14 10:13:53 PM UTC 24 4591689816 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.555386834 Oct 14 10:12:58 PM UTC 24 Oct 14 10:13:53 PM UTC 24 27336128039 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3620317640 Oct 14 10:13:42 PM UTC 24 Oct 14 10:13:54 PM UTC 24 2009844164 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1656134433 Oct 14 10:12:58 PM UTC 24 Oct 14 10:13:54 PM UTC 24 76365902210 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3036787657 Oct 14 10:12:59 PM UTC 24 Oct 14 10:13:55 PM UTC 24 42116472151 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1488379741 Oct 14 10:13:40 PM UTC 24 Oct 14 10:13:55 PM UTC 24 3044310021 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1943717976 Oct 14 10:13:27 PM UTC 24 Oct 14 10:13:56 PM UTC 24 706028187381 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4035605069 Oct 14 10:13:54 PM UTC 24 Oct 14 10:13:59 PM UTC 24 3040538288 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2773011024 Oct 14 10:13:49 PM UTC 24 Oct 14 10:14:03 PM UTC 24 2607409911 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.101541302 Oct 14 10:13:51 PM UTC 24 Oct 14 10:14:04 PM UTC 24 3839775221 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2781901683 Oct 14 10:13:11 PM UTC 24 Oct 14 10:14:05 PM UTC 24 70327683707 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1951062142 Oct 14 10:13:48 PM UTC 24 Oct 14 10:14:05 PM UTC 24 2512818558 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.758566148 Oct 14 10:14:02 PM UTC 24 Oct 14 10:14:06 PM UTC 24 2274819735 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1307214762 Oct 14 10:12:35 PM UTC 24 Oct 14 10:14:06 PM UTC 24 34416452853 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.4234081971 Oct 14 10:12:51 PM UTC 24 Oct 14 10:14:06 PM UTC 24 22013110455 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.1685714433 Oct 14 10:13:56 PM UTC 24 Oct 14 10:14:07 PM UTC 24 2011836829 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.612809645 Oct 14 10:14:00 PM UTC 24 Oct 14 10:14:07 PM UTC 24 2465287075 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3975293332 Oct 14 10:14:04 PM UTC 24 Oct 14 10:14:07 PM UTC 24 2528558860 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2256208980 Oct 14 10:13:52 PM UTC 24 Oct 14 10:14:08 PM UTC 24 5317901660 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2472740448 Oct 14 10:14:05 PM UTC 24 Oct 14 10:14:08 PM UTC 24 2626059046 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2980372157 Oct 14 10:14:06 PM UTC 24 Oct 14 10:14:09 PM UTC 24 5120879801 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.1054374292 Oct 14 10:13:57 PM UTC 24 Oct 14 10:14:10 PM UTC 24 2109141235 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.291159168 Oct 14 10:14:07 PM UTC 24 Oct 14 10:14:11 PM UTC 24 3752336416 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1262331704 Oct 14 10:13:41 PM UTC 24 Oct 14 10:14:15 PM UTC 24 6248381637 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3878166527 Oct 14 10:13:20 PM UTC 24 Oct 14 10:14:15 PM UTC 24 45330316372 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3768320014 Oct 14 10:14:11 PM UTC 24 Oct 14 10:14:16 PM UTC 24 2489749525 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.2052019562 Oct 14 10:13:05 PM UTC 24 Oct 14 10:14:16 PM UTC 24 42015388463 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3398962597 Oct 14 10:14:12 PM UTC 24 Oct 14 10:14:16 PM UTC 24 2530009940 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2633579754 Oct 14 10:14:10 PM UTC 24 Oct 14 10:14:17 PM UTC 24 2115498395 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.840450534 Oct 14 10:14:09 PM UTC 24 Oct 14 10:14:19 PM UTC 24 2010044285 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.678908285 Oct 14 10:14:08 PM UTC 24 Oct 14 10:14:19 PM UTC 24 14123372520 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.871354510 Oct 14 10:14:16 PM UTC 24 Oct 14 10:14:19 PM UTC 24 3305100543 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3384589407 Oct 14 10:14:11 PM UTC 24 Oct 14 10:14:19 PM UTC 24 2083702453 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.2182890490 Oct 14 10:15:32 PM UTC 24 Oct 14 10:15:41 PM UTC 24 2038883320 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3617539373 Oct 14 10:14:06 PM UTC 24 Oct 14 10:14:20 PM UTC 24 3464127059 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1735238661 Oct 14 10:14:17 PM UTC 24 Oct 14 10:14:22 PM UTC 24 3308766523 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.455231466 Oct 14 10:14:07 PM UTC 24 Oct 14 10:14:22 PM UTC 24 3395294485 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3867352654 Oct 14 10:14:16 PM UTC 24 Oct 14 10:14:23 PM UTC 24 4235042936 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1695036424 Oct 14 10:14:21 PM UTC 24 Oct 14 10:14:25 PM UTC 24 2135123221 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2958641282 Oct 14 10:14:21 PM UTC 24 Oct 14 10:14:25 PM UTC 24 2033942943 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3195215109 Oct 14 10:14:16 PM UTC 24 Oct 14 10:14:25 PM UTC 24 2614207807 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3667750333 Oct 14 10:14:23 PM UTC 24 Oct 14 10:14:27 PM UTC 24 2555904693 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.888225381 Oct 14 10:14:23 PM UTC 24 Oct 14 10:14:27 PM UTC 24 2106595485 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2707927882 Oct 14 10:13:55 PM UTC 24 Oct 14 10:14:28 PM UTC 24 5237775979 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2048367811 Oct 14 10:14:24 PM UTC 24 Oct 14 10:14:29 PM UTC 24 2632370482 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4191105688 Oct 14 10:14:26 PM UTC 24 Oct 14 10:14:30 PM UTC 24 11445438751 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.588461283 Oct 14 10:13:54 PM UTC 24 Oct 14 10:14:30 PM UTC 24 46061752710 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.4098434365 Oct 14 10:14:19 PM UTC 24 Oct 14 10:14:32 PM UTC 24 7900890897 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1011108771 Oct 14 10:14:26 PM UTC 24 Oct 14 10:14:33 PM UTC 24 3717227415 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.4068340851 Oct 14 10:14:32 PM UTC 24 Oct 14 10:14:35 PM UTC 24 2090422512 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2670620035 Oct 14 10:14:21 PM UTC 24 Oct 14 10:14:35 PM UTC 24 8285074770 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1601517641 Oct 14 10:14:21 PM UTC 24 Oct 14 10:14:35 PM UTC 24 2466943731 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3960184059 Oct 14 10:14:25 PM UTC 24 Oct 14 10:14:37 PM UTC 24 2791544605 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.2204644212 Oct 14 10:14:33 PM UTC 24 Oct 14 10:14:38 PM UTC 24 2132959008 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3003656575 Oct 14 10:14:30 PM UTC 24 Oct 14 10:14:39 PM UTC 24 14898351426 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1964223088 Oct 14 10:14:28 PM UTC 24 Oct 14 10:14:40 PM UTC 24 3238824005 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3555246331 Oct 14 10:14:36 PM UTC 24 Oct 14 10:14:40 PM UTC 24 2538621480 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.4070952162 Oct 14 10:14:36 PM UTC 24 Oct 14 10:14:42 PM UTC 24 2168347809 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1502255052 Oct 14 10:12:18 PM UTC 24 Oct 14 10:14:43 PM UTC 24 157444181574 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.639939172 Oct 14 10:14:38 PM UTC 24 Oct 14 10:14:44 PM UTC 24 3281958114 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1074400184 Oct 14 10:14:38 PM UTC 24 Oct 14 10:14:48 PM UTC 24 3111979543 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.942088187 Oct 14 10:14:39 PM UTC 24 Oct 14 10:14:48 PM UTC 24 7333967057 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.4090225910 Oct 14 10:14:34 PM UTC 24 Oct 14 10:14:48 PM UTC 24 2467247419 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2699704203 Oct 14 10:14:36 PM UTC 24 Oct 14 10:14:48 PM UTC 24 2611101005 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.2627749365 Oct 14 10:14:42 PM UTC 24 Oct 14 10:14:51 PM UTC 24 3145136127 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2922419809 Oct 14 10:12:25 PM UTC 24 Oct 14 10:14:52 PM UTC 24 42010792757 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4000293504 Oct 14 10:14:49 PM UTC 24 Oct 14 10:14:52 PM UTC 24 2062654620 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3911826762 Oct 14 10:14:18 PM UTC 24 Oct 14 10:14:54 PM UTC 24 26592738690 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.3107129776 Oct 14 10:14:49 PM UTC 24 Oct 14 10:14:56 PM UTC 24 2500384152 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1700080294 Oct 14 10:14:49 PM UTC 24 Oct 14 10:14:58 PM UTC 24 2015469297 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.2930025154 Oct 14 10:14:49 PM UTC 24 Oct 14 10:15:00 PM UTC 24 2108361890 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.2928373735 Oct 14 10:15:21 PM UTC 24 Oct 14 10:15:41 PM UTC 24 9256544476 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1876907246 Oct 14 10:14:52 PM UTC 24 Oct 14 10:15:00 PM UTC 24 2512015136 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2728782418 Oct 14 10:14:53 PM UTC 24 Oct 14 10:15:03 PM UTC 24 3484724827 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3146263943 Oct 14 10:14:52 PM UTC 24 Oct 14 10:15:04 PM UTC 24 2611590719 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3708602544 Oct 14 10:14:44 PM UTC 24 Oct 14 10:15:05 PM UTC 24 17405217402 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.4011879762 Oct 14 10:15:05 PM UTC 24 Oct 14 10:15:09 PM UTC 24 2135951961 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2737357271 Oct 14 10:15:04 PM UTC 24 Oct 14 10:15:10 PM UTC 24 2015877751 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2266778258 Oct 14 10:15:02 PM UTC 24 Oct 14 10:15:12 PM UTC 24 9252540673 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.3182175842 Oct 14 10:14:59 PM UTC 24 Oct 14 10:15:12 PM UTC 24 2964533326 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.384635802 Oct 14 10:14:53 PM UTC 24 Oct 14 10:15:12 PM UTC 24 3619083580 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1376012482 Oct 14 10:15:08 PM UTC 24 Oct 14 10:15:13 PM UTC 24 2087058620 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2164932780 Oct 14 10:15:09 PM UTC 24 Oct 14 10:15:13 PM UTC 24 2534507411 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.696436852 Oct 14 10:15:13 PM UTC 24 Oct 14 10:15:18 PM UTC 24 3504116619 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.777685090 Oct 14 10:15:13 PM UTC 24 Oct 14 10:15:18 PM UTC 24 7609256408 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1477874099 Oct 14 10:15:11 PM UTC 24 Oct 14 10:15:20 PM UTC 24 2612074470 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.967449814 Oct 14 10:15:06 PM UTC 24 Oct 14 10:15:20 PM UTC 24 2458541142 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.716508759 Oct 14 10:15:14 PM UTC 24 Oct 14 10:15:21 PM UTC 24 5633815638 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.665419685 Oct 14 10:15:21 PM UTC 24 Oct 14 10:15:26 PM UTC 24 2032648550 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3186193318 Oct 14 10:14:08 PM UTC 24 Oct 14 10:15:30 PM UTC 24 26078108463 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1357456288 Oct 14 10:15:22 PM UTC 24 Oct 14 10:15:31 PM UTC 24 2107922255 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1418934590 Oct 14 10:15:13 PM UTC 24 Oct 14 10:15:31 PM UTC 24 3819093478 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.1597682945 Oct 14 10:13:28 PM UTC 24 Oct 14 10:15:32 PM UTC 24 131848419235 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.760574115 Oct 14 10:15:19 PM UTC 24 Oct 14 10:15:33 PM UTC 24 5051960711 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3314583474 Oct 14 10:15:26 PM UTC 24 Oct 14 10:15:34 PM UTC 24 2467643308 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1474228812 Oct 14 10:13:55 PM UTC 24 Oct 14 10:15:34 PM UTC 24 780661190323 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1492544296 Oct 14 10:13:55 PM UTC 24 Oct 14 10:15:36 PM UTC 24 33185163241 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1702642677 Oct 14 10:15:01 PM UTC 24 Oct 14 10:15:38 PM UTC 24 8989537926 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.989430554 Oct 14 10:15:33 PM UTC 24 Oct 14 10:15:39 PM UTC 24 2617328346 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2191287703 Oct 14 10:15:35 PM UTC 24 Oct 14 10:15:40 PM UTC 24 6283464860 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.4202382670 Oct 14 10:15:34 PM UTC 24 Oct 14 10:15:41 PM UTC 24 3832398486 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.524236616 Oct 14 10:15:41 PM UTC 24 Oct 14 10:15:44 PM UTC 24 2120720391 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.1971336315 Oct 14 10:15:42 PM UTC 24 Oct 14 10:15:46 PM UTC 24 2123997679 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.564422896 Oct 14 10:15:43 PM UTC 24 Oct 14 10:15:46 PM UTC 24 2490105745 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2634227136 Oct 14 10:15:32 PM UTC 24 Oct 14 10:15:48 PM UTC 24 2509939173 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.3178378905 Oct 14 10:15:40 PM UTC 24 Oct 14 10:15:51 PM UTC 24 6316137190 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3974749466 Oct 14 10:15:37 PM UTC 24 Oct 14 10:15:52 PM UTC 24 2737270131 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1490359927 Oct 14 10:15:45 PM UTC 24 Oct 14 10:15:52 PM UTC 24 2223830053 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1207757688 Oct 14 10:15:48 PM UTC 24 Oct 14 10:15:54 PM UTC 24 2628648093 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3458667251 Oct 14 10:15:47 PM UTC 24 Oct 14 10:15:56 PM UTC 24 2517780119 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.359033653 Oct 14 10:15:54 PM UTC 24 Oct 14 10:15:57 PM UTC 24 2764940876 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.983147315 Oct 14 10:15:33 PM UTC 24 Oct 14 10:15:57 PM UTC 24 4094539207 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.67429620 Oct 14 10:15:53 PM UTC 24 Oct 14 10:15:58 PM UTC 24 6399470241 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1725014060 Oct 14 10:15:40 PM UTC 24 Oct 14 10:15:58 PM UTC 24 13726049218 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1135120743 Oct 14 10:12:21 PM UTC 24 Oct 14 10:16:00 PM UTC 24 72215975064 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1583810146 Oct 14 10:15:49 PM UTC 24 Oct 14 10:16:02 PM UTC 24 2743198395 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.356606440 Oct 14 10:16:01 PM UTC 24 Oct 14 10:16:04 PM UTC 24 2203617914 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1741816215 Oct 14 10:16:00 PM UTC 24 Oct 14 10:16:05 PM UTC 24 2491995944 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3342738214 Oct 14 10:16:04 PM UTC 24 Oct 14 10:16:09 PM UTC 24 2626915522 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.2336662251 Oct 14 10:15:59 PM UTC 24 Oct 14 10:16:11 PM UTC 24 2014949645 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3943558008 Oct 14 10:15:59 PM UTC 24 Oct 14 10:16:11 PM UTC 24 2114007079 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.2665138560 Oct 14 10:16:03 PM UTC 24 Oct 14 10:16:13 PM UTC 24 2514335414 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3887854194 Oct 14 10:14:43 PM UTC 24 Oct 14 10:16:13 PM UTC 24 24332721083 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.609282520 Oct 14 10:15:14 PM UTC 24 Oct 14 10:16:16 PM UTC 24 134956240855 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.493746009 Oct 14 10:12:44 PM UTC 24 Oct 14 10:16:18 PM UTC 24 110062868256 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4206961939 Oct 14 10:16:10 PM UTC 24 Oct 14 10:16:20 PM UTC 24 3246208072 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2381242687 Oct 14 10:16:14 PM UTC 24 Oct 14 10:16:22 PM UTC 24 4848415715 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2320890680 Oct 14 10:16:21 PM UTC 24 Oct 14 10:16:25 PM UTC 24 2027114200 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.2741287577 Oct 14 10:16:22 PM UTC 24 Oct 14 10:16:26 PM UTC 24 2130109687 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3785270730 Oct 14 10:13:40 PM UTC 24 Oct 14 10:16:28 PM UTC 24 38509602782 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2143253305 Oct 14 10:14:27 PM UTC 24 Oct 14 10:16:31 PM UTC 24 119380468685 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3078493231 Oct 14 10:16:26 PM UTC 24 Oct 14 10:16:31 PM UTC 24 2464447123 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.4169884573 Oct 14 10:16:27 PM UTC 24 Oct 14 10:16:33 PM UTC 24 2237242320 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.67869402 Oct 14 10:16:28 PM UTC 24 Oct 14 10:16:33 PM UTC 24 2538044924 ps
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