Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.60	98.92	96.07	100.00	96.15	98.26	99.63	94.17

Total tests in report: 908

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
61.43	61.43	72.32	72.32	67.03	67.03	57.06	57.06	96.15	96.15	76.19	76.19	54.78	54.78	6.49	6.49	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2764422014
71.30	9.87	85.98	13.65	78.43	11.39	63.67	6.61	96.15	0.00	87.54	11.35	72.10	17.32	15.27	8.78	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.248008918
78.44	7.14	87.09	1.12	81.07	2.65	92.94	29.27	96.15	0.00	87.71	0.17	75.56	3.46	28.57	13.30	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2750492636
85.06	6.62	96.17	9.08	88.15	7.08	96.36	3.42	96.15	0.00	95.09	7.38	92.70	17.13	30.81	2.24	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1702405865
88.58	3.52	97.09	0.91	91.70	3.55	97.27	0.91	96.15	0.00	96.21	1.11	94.85	2.15	46.78	15.98	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4062470689
91.27	2.69	97.14	0.05	91.75	0.05	97.27	0.00	96.15	0.00	96.28	0.07	95.04	0.19	65.27	18.48	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.633443422
92.26	0.99	97.26	0.12	92.25	0.50	97.27	0.00	96.15	0.00	96.28	0.00	95.13	0.09	71.48	6.22	/workspace/coverage/default/3.sysrst_ctrl_stress_all.4073719220
93.12	0.86	97.75	0.49	93.13	0.88	97.72	0.46	96.15	0.00	96.80	0.52	96.72	1.59	73.56	2.07	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2705851628
93.73	0.61	97.80	0.05	93.99	0.86	98.18	0.46	96.15	0.00	96.83	0.03	97.00	0.28	76.17	2.62	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2235234590
94.20	0.47	97.82	0.02	94.16	0.17	98.18	0.00	96.15	0.00	96.83	0.00	97.00	0.00	79.28	3.11	/workspace/coverage/default/49.sysrst_ctrl_stress_all.462027706
94.48	0.27	98.00	0.19	94.42	0.26	98.41	0.23	96.15	0.00	97.15	0.31	97.38	0.37	79.83	0.55	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1876629099
94.73	0.26	98.00	0.00	94.42	0.00	98.41	0.00	96.15	0.00	97.15	0.00	97.38	0.00	81.62	1.80	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3279501086
94.99	0.25	98.02	0.02	94.64	0.21	98.63	0.23	96.15	0.00	97.22	0.07	97.38	0.00	82.88	1.25	/workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2659891254
95.22	0.23	98.24	0.22	94.76	0.12	99.32	0.68	96.15	0.00	97.29	0.07	97.57	0.19	83.21	0.33	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1777606187
95.42	0.20	98.29	0.05	94.80	0.05	99.32	0.00	96.15	0.00	97.35	0.07	97.66	0.09	84.35	1.15	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3209361719
95.60	0.18	98.29	0.00	94.80	0.00	99.32	0.00	96.15	0.00	97.35	0.00	97.66	0.00	85.61	1.25	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.3486428804
95.77	0.17	98.29	0.00	94.80	0.00	99.32	0.00	96.15	0.00	97.35	0.00	97.66	0.00	86.80	1.20	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3744659495
95.91	0.14	98.36	0.07	95.09	0.29	99.32	0.00	96.15	0.00	97.42	0.07	98.22	0.56	86.80	0.00	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.698917669
96.04	0.13	98.36	0.00	95.11	0.02	99.32	0.00	96.15	0.00	97.42	0.00	98.31	0.09	87.57	0.76	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.429104601
96.15	0.12	98.36	0.00	95.16	0.05	99.32	0.00	96.15	0.00	97.42	0.00	98.31	0.00	88.33	0.76	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1444669327
96.25	0.10	98.46	0.10	95.28	0.12	99.32	0.00	96.15	0.00	97.53	0.10	98.69	0.37	88.33	0.00	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.1314614350
96.35	0.10	98.46	0.00	95.30	0.02	99.77	0.46	96.15	0.00	97.53	0.00	98.78	0.09	88.44	0.11	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.4166349460
96.43	0.09	98.46	0.00	95.30	0.00	99.77	0.00	96.15	0.00	97.53	0.00	98.78	0.00	89.04	0.60	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.778736185
96.51	0.08	98.46	0.00	95.30	0.00	99.77	0.00	96.15	0.00	97.53	0.00	98.78	0.00	89.59	0.55	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1991905768
96.59	0.08	98.46	0.00	95.30	0.00	99.77	0.00	96.15	0.00	97.56	0.03	98.78	0.00	90.08	0.49	/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2560989542
96.66	0.07	98.46	0.00	95.33	0.02	99.77	0.00	96.15	0.00	97.56	0.00	98.88	0.09	90.46	0.38	/workspace/coverage/default/41.sysrst_ctrl_combo_detect.2591645508
96.72	0.07	98.49	0.03	95.35	0.02	99.77	0.00	96.15	0.00	97.60	0.03	98.97	0.09	90.73	0.27	/workspace/coverage/default/42.sysrst_ctrl_stress_all.2794774781
96.78	0.05	98.56	0.07	95.40	0.05	99.77	0.00	96.15	0.00	97.67	0.07	99.16	0.19	90.73	0.00	/workspace/coverage/default/39.sysrst_ctrl_edge_detect.1061623278
96.82	0.05	98.56	0.00	95.40	0.00	99.77	0.00	96.15	0.00	97.67	0.00	99.16	0.00	91.06	0.33	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3806579074
96.87	0.05	98.56	0.00	95.66	0.26	99.77	0.00	96.15	0.00	97.67	0.00	99.16	0.00	91.11	0.05	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1420303822
96.91	0.04	98.63	0.07	95.73	0.07	99.77	0.00	96.15	0.00	97.77	0.10	99.16	0.00	91.17	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4248727474
96.95	0.04	98.66	0.03	95.76	0.02	99.77	0.00	96.15	0.00	97.81	0.03	99.25	0.09	91.28	0.11	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2510748992
96.99	0.04	98.66	0.00	95.80	0.05	100.00	0.23	96.15	0.00	97.81	0.00	99.25	0.00	91.28	0.00	/workspace/coverage/default/10.sysrst_ctrl_alert_test.2116463394
97.03	0.04	98.66	0.00	95.80	0.00	100.00	0.00	96.15	0.00	97.81	0.00	99.25	0.00	91.55	0.27	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3185663138
97.07	0.03	98.71	0.05	95.83	0.02	100.00	0.00	96.15	0.00	97.88	0.07	99.34	0.09	91.55	0.00	/workspace/coverage/default/12.sysrst_ctrl_edge_detect.2794648200
97.10	0.03	98.71	0.00	95.85	0.02	100.00	0.00	96.15	0.00	97.88	0.00	99.44	0.09	91.66	0.11	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1145141851
97.13	0.03	98.71	0.00	95.85	0.00	100.00	0.00	96.15	0.00	97.88	0.00	99.44	0.00	91.88	0.22	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2721053962
97.16	0.03	98.71	0.00	95.85	0.00	100.00	0.00	96.15	0.00	97.88	0.00	99.44	0.00	92.09	0.22	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.430671253
97.19	0.03	98.71	0.00	95.88	0.02	100.00	0.00	96.15	0.00	97.88	0.00	99.44	0.00	92.26	0.16	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.919812195
97.21	0.03	98.75	0.03	95.90	0.02	100.00	0.00	96.15	0.00	97.91	0.03	99.53	0.09	92.26	0.00	/workspace/coverage/default/25.sysrst_ctrl_stress_all.2073075600
97.24	0.02	98.75	0.00	95.90	0.00	100.00	0.00	96.15	0.00	97.91	0.00	99.53	0.00	92.42	0.16	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1417887294
97.26	0.02	98.75	0.00	95.90	0.00	100.00	0.00	96.15	0.00	97.91	0.00	99.53	0.00	92.58	0.16	/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1989064450
97.28	0.02	98.75	0.00	95.90	0.00	100.00	0.00	96.15	0.00	97.91	0.00	99.53	0.00	92.75	0.16	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2340905402
97.31	0.02	98.80	0.05	95.90	0.00	100.00	0.00	96.15	0.00	98.02	0.10	99.53	0.00	92.75	0.00	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1027465436
97.33	0.02	98.81	0.02	95.92	0.02	100.00	0.00	96.15	0.00	98.05	0.03	99.53	0.00	92.80	0.05	/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3327600723
97.34	0.02	98.81	0.00	95.92	0.00	100.00	0.00	96.15	0.00	98.05	0.00	99.53	0.00	92.91	0.11	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2229725476
97.36	0.02	98.81	0.00	95.92	0.00	100.00	0.00	96.15	0.00	98.05	0.00	99.53	0.00	93.02	0.11	/workspace/coverage/default/4.sysrst_ctrl_combo_detect.2574515965
97.37	0.02	98.81	0.00	95.92	0.00	100.00	0.00	96.15	0.00	98.05	0.00	99.53	0.00	93.13	0.11	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2262897905
97.39	0.02	98.81	0.00	95.92	0.00	100.00	0.00	96.15	0.00	98.05	0.00	99.53	0.00	93.24	0.11	/workspace/coverage/default/7.sysrst_ctrl_stress_all.1981444984
97.40	0.01	98.85	0.03	95.92	0.00	100.00	0.00	96.15	0.00	98.12	0.07	99.53	0.00	93.24	0.00	/workspace/coverage/default/2.sysrst_ctrl_edge_detect.1235366295
97.42	0.01	98.88	0.03	95.92	0.00	100.00	0.00	96.15	0.00	98.19	0.07	99.53	0.00	93.24	0.00	/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2152359049
97.43	0.01	98.88	0.00	95.92	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.09	93.24	0.00	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.69575598
97.44	0.01	98.88	0.00	96.00	0.07	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.24	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.846375658
97.45	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.29	0.05	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3682523822
97.46	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.35	0.05	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.606720672
97.46	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.40	0.05	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2141123809
97.47	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.46	0.05	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.262166222
97.48	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.51	0.05	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.198810610
97.49	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.57	0.05	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1787881023
97.50	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.62	0.05	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1999052790
97.50	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.68	0.05	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3113180644
97.51	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.73	0.05	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2652452553
97.52	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.78	0.05	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1423961360
97.53	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.84	0.05	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.34018698
97.53	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.89	0.05	/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1002708967
97.54	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	93.95	0.05	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4089358840
97.55	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	94.00	0.05	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4233273591
97.56	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	94.06	0.05	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1692071702
97.57	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	94.11	0.05	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1151185927
97.57	0.01	98.88	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.63	0.00	94.17	0.05	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3401728361
97.58	0.01	98.90	0.02	96.00	0.00	100.00	0.00	96.15	0.00	98.22	0.03	99.63	0.00	94.17	0.00	/workspace/coverage/default/20.sysrst_ctrl_stress_all.2585758035
97.59	0.01	98.92	0.02	96.00	0.00	100.00	0.00	96.15	0.00	98.26	0.03	99.63	0.00	94.17	0.00	/workspace/coverage/default/26.sysrst_ctrl_edge_detect.272111727
97.59	0.01	98.92	0.00	96.04	0.05	100.00	0.00	96.15	0.00	98.26	0.00	99.63	0.00	94.17	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.185203053

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3322394607
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.961220067
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2565810981
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.72774822
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1140118270
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.498934310
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.83981070
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1013033732
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2576675925
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.879582662
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2026568941
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.270289595
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1122843211
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.293290392
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1746241027
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1058174568
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1243640227
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2664006586
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2447005335
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2088611024
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3057602890
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.239034329
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1896491712
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.361866300
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1157143394
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2714326100
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1646415335
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2483532953
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1410400086
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3199909582
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.52956108
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2316225234
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3091498846
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/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3147493147
/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3589546575
/workspace/coverage/default/38.sysrst_ctrl_smoke.3271628479
/workspace/coverage/default/38.sysrst_ctrl_stress_all.1556526792
/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4001471955
/workspace/coverage/default/39.sysrst_ctrl_alert_test.2864213279
/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2526112181
/workspace/coverage/default/39.sysrst_ctrl_combo_detect.2511573207
/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2262537775
/workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3320970684
/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.292533520
/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2139778558
/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2659769326
/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1588770739
/workspace/coverage/default/39.sysrst_ctrl_smoke.142297397
/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1660428987
/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3378629429
/workspace/coverage/default/4.sysrst_ctrl_alert_test.3255695635
/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1599564159
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2387622353
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2818685378
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.641795864
/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1552248934
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3965183992
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1401174716
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.546918139
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3274579778
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1232592940
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3879506349
/workspace/coverage/default/4.sysrst_ctrl_smoke.516050512
/workspace/coverage/default/4.sysrst_ctrl_stress_all.4114878316
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2351992344
/workspace/coverage/default/40.sysrst_ctrl_alert_test.1510324569
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2533000219
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.3838190455
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2223368452
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.3550931776
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2154694087
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1962478357
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3965007075
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2499809525
/workspace/coverage/default/40.sysrst_ctrl_smoke.1289709579
/workspace/coverage/default/40.sysrst_ctrl_stress_all.2052678521
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2271728817
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.790408896
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3129125833
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.4274623034
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1977809674
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.1177199459
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.286618378
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1556174144
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2548784916
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2884921952
/workspace/coverage/default/41.sysrst_ctrl_smoke.1645955370
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2574375999
/workspace/coverage/default/42.sysrst_ctrl_alert_test.903573847
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1789356531
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4126752162
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.1693053761
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3875082642
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2630571799
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.284715003
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.281593595
/workspace/coverage/default/42.sysrst_ctrl_smoke.1847525199
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3816982925
/workspace/coverage/default/43.sysrst_ctrl_alert_test.3387574406
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1136161421
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.769608981
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2330300103
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2969508185
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2314027261
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1526956965
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1839773679
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1461333905
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3392479545
/workspace/coverage/default/43.sysrst_ctrl_smoke.1014631482
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3583750776
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4169236262
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.101061200
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3151633668
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2567704248
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1666626829
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1839247747
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1172958353
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1398225822
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3938549089
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1426114924
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2357337114
/workspace/coverage/default/44.sysrst_ctrl_smoke.3081103358
/workspace/coverage/default/44.sysrst_ctrl_stress_all.310105109
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1168106867
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.22291412
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3784122879
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.593528399
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1143161789
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.4213411277
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2075229673
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1386740296
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2491773627
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1307178198
/workspace/coverage/default/45.sysrst_ctrl_smoke.1603824698
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2251323053
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4092844052
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1750694457
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1982826357
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.961358707
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1808007335
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3101482592
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.116550898
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.537621862
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3693254054
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1388210242
/workspace/coverage/default/46.sysrst_ctrl_smoke.3749905358
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3603962292
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2144436632
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3906294863
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2988981010
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2731456331
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3413254985
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1538074297
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3676884693
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.58745761
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.216011798
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2556014472
/workspace/coverage/default/47.sysrst_ctrl_smoke.1420556055
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2669874357
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.656068243
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1675294208
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3930598170
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1257511738
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.4123487817
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2065006236
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1392968505
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1091260062
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3104317972
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2355068414
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2946793704
/workspace/coverage/default/48.sysrst_ctrl_smoke.1032142304
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2893129678
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.664508578
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2070891708
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1225599532
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.572157665
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.4058390513
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.4230919483
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3053028211
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.681697236
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1866522519
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.4123131275
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3177922431
/workspace/coverage/default/49.sysrst_ctrl_smoke.2633889851
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2997783522
/workspace/coverage/default/5.sysrst_ctrl_alert_test.791903313
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1349348177
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.635243638
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3083570826
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2742951611
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.4125604214
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3137293222
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2083278570
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3042128849
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2912737528
/workspace/coverage/default/5.sysrst_ctrl_smoke.1555921148
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3820904523
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2115535249
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3547121855
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1130455766
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.764350932
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2152325594
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3485221358
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1084060290
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.697086869
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2800846610
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2382338096
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1818473334
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1605948990
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.166861645
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.233036378
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1503261547
/workspace/coverage/default/6.sysrst_ctrl_smoke.3659288080
/workspace/coverage/default/6.sysrst_ctrl_stress_all.206874523
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3506656260
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1134263412
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1855945438
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3923297052
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.946430592
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1183241573
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2019541675
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.591460990
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3259008086
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3156002745
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.75911521
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.904118105
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3411226896
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.4283974257
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4136809709
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1893644800
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1351732930
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.914085633
/workspace/coverage/default/7.sysrst_ctrl_smoke.3779604124
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4147554611
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3796756898
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2622592238
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.619384788
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2928438003
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.648411206
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.625494803
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3400641429
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2922965274
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.387531868
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.4293088288
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.4198257754
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1842237205
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.4278480870
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1534114338
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1110991693
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2609743825
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2338537954
/workspace/coverage/default/8.sysrst_ctrl_smoke.2008273178
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3899339922
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1601844555
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.788795610
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2253270054
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3324353522
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1714017696
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.4042184778
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2093497311
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4082720653
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1647453122
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1459333624
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3075626054
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2008495822
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1583513894
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1469696280
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1662756681
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1248613278
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2294075599
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2761685945
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.16413468
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1105478086
/workspace/coverage/default/9.sysrst_ctrl_smoke.3929830508
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2169780685
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3714596035
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.519618590
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2285210318
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.4264413627
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2621789653
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2397751796
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2720038751
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1829767610
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2855140560
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4212909489
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.936082770

Total test records in report: 908

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2764422014	May 29 12:30:51 AM PDT 23	May 29 12:30:58 AM PDT 23	2044237962 ps
T5	/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2054781203	May 29 12:31:21 AM PDT 23	May 29 12:31:25 AM PDT 23	2019576117 ps
T6	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1157143394	May 29 12:30:43 AM PDT 23	May 29 12:30:49 AM PDT 23	2049756033 ps
T2	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2979049256	May 29 12:30:45 AM PDT 23	May 29 12:31:03 AM PDT 23	7672991556 ps
T24	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3756274586	May 29 12:30:37 AM PDT 23	May 29 12:30:45 AM PDT 23	2042014727 ps
T25	/workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2198978478	May 29 12:31:31 AM PDT 23	May 29 12:31:33 AM PDT 23	2033317724 ps
T3	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1876629099	May 29 12:30:32 AM PDT 23	May 29 12:30:40 AM PDT 23	7727651709 ps
T26	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3486624983	May 29 12:30:47 AM PDT 23	May 29 12:30:51 AM PDT 23	2027012185 ps
T7	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2725104978	May 29 12:30:49 AM PDT 23	May 29 12:31:45 AM PDT 23	42325207264 ps
T27	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2235234590	May 29 12:30:38 AM PDT 23	May 29 12:30:46 AM PDT 23	2067836522 ps
T8	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.255414364	May 29 12:30:47 AM PDT 23	May 29 12:32:38 AM PDT 23	42311890299 ps
T9	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2194348471	May 29 12:30:35 AM PDT 23	May 29 12:30:37 AM PDT 23	2095181224 ps
T10	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2750492636	May 29 12:30:41 AM PDT 23	May 29 12:31:19 AM PDT 23	22233525640 ps
T4	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3754375639	May 29 12:29:24 AM PDT 23	May 29 12:29:26 AM PDT 23	2225317706 ps
T288	/workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2659891254	May 29 12:31:21 AM PDT 23	May 29 12:31:24 AM PDT 23	2023854278 ps
T11	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.749240991	May 29 12:29:24 AM PDT 23	May 29 12:29:29 AM PDT 23	6075285164 ps
T12	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2480321775	May 29 12:30:49 AM PDT 23	May 29 12:30:52 AM PDT 23	2057757638 ps
T13	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328454336	May 29 12:30:38 AM PDT 23	May 29 12:30:41 AM PDT 23	2052075855 ps
T43	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3013870860	May 29 12:30:51 AM PDT 23	May 29 12:31:22 AM PDT 23	22255640030 ps
T307	/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.394648928	May 29 12:31:31 AM PDT 23	May 29 12:31:33 AM PDT 23	2032719366 ps
T35	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1434260111	May 29 12:30:49 AM PDT 23	May 29 12:30:51 AM PDT 23	2195649163 ps
T281	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2713065498	May 29 12:30:49 AM PDT 23	May 29 12:30:54 AM PDT 23	2054171856 ps
T317	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2565810981	May 29 12:29:55 AM PDT 23	May 29 12:30:00 AM PDT 23	6077250271 ps
T296	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.4006969154	May 29 12:30:42 AM PDT 23	May 29 12:30:44 AM PDT 23	2029631292 ps
T286	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1417887294	May 29 12:30:37 AM PDT 23	May 29 12:32:30 AM PDT 23	42309444847 ps
T367	/workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3595000388	May 29 12:30:48 AM PDT 23	May 29 12:30:54 AM PDT 23	2010787050 ps
T387	/workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1258419915	May 29 12:31:21 AM PDT 23	May 29 12:31:27 AM PDT 23	2013615960 ps
T70	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1155009439	May 29 12:30:47 AM PDT 23	May 29 12:30:53 AM PDT 23	2048283611 ps
T308	/workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1752710907	May 29 12:31:49 AM PDT 23	May 29 12:31:51 AM PDT 23	2044880672 ps
T309	/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3830376224	May 29 12:31:53 AM PDT 23	May 29 12:31:55 AM PDT 23	2109939783 ps
T310	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3596640811	May 29 12:29:43 AM PDT 23	May 29 12:29:47 AM PDT 23	2049616926 ps
T311	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.17325624	May 29 12:30:47 AM PDT 23	May 29 12:30:50 AM PDT 23	2034531421 ps
T36	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1592226142	May 29 12:30:33 AM PDT 23	May 29 12:30:45 AM PDT 23	7829359100 ps
T282	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1420303822	May 29 12:30:48 AM PDT 23	May 29 12:30:54 AM PDT 23	2083439594 ps
T297	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2954458779	May 29 12:29:35 AM PDT 23	May 29 12:29:36 AM PDT 23	2073904620 ps
T298	/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3869310464	May 29 12:30:42 AM PDT 23	May 29 12:30:45 AM PDT 23	2034688185 ps
T291	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.682183513	May 29 12:30:38 AM PDT 23	May 29 12:30:45 AM PDT 23	4030567794 ps
T299	/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1905877516	May 29 12:31:34 AM PDT 23	May 29 12:31:36 AM PDT 23	2046938639 ps
T37	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3653110241	May 29 12:30:34 AM PDT 23	May 29 12:30:40 AM PDT 23	2058156172 ps
T388	/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2362940252	May 29 12:31:03 AM PDT 23	May 29 12:31:09 AM PDT 23	2012581072 ps
T38	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3700990222	May 29 12:30:45 AM PDT 23	May 29 12:30:51 AM PDT 23	2048711839 ps
T39	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.879582662	May 29 12:29:18 AM PDT 23	May 29 12:29:24 AM PDT 23	2520368221 ps
T283	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.839571889	May 29 12:30:47 AM PDT 23	May 29 12:30:52 AM PDT 23	2131669383 ps
T389	/workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2435821114	May 29 12:31:26 AM PDT 23	May 29 12:31:32 AM PDT 23	2009603757 ps
T40	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3903095591	May 29 12:30:47 AM PDT 23	May 29 12:30:57 AM PDT 23	9680237415 ps
T285	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3835104251	May 29 12:30:41 AM PDT 23	May 29 12:30:48 AM PDT 23	2021254640 ps
T41	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2747865469	May 29 12:29:32 AM PDT 23	May 29 12:29:40 AM PDT 23	7086473983 ps
T390	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.694954533	May 29 12:30:42 AM PDT 23	May 29 12:30:48 AM PDT 23	2008891813 ps
T284	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1243640227	May 29 12:29:19 AM PDT 23	May 29 12:29:24 AM PDT 23	2475896770 ps
T303	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2026568941	May 29 12:29:32 AM PDT 23	May 29 12:30:05 AM PDT 23	53423686336 ps
T391	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.4191973542	May 29 12:30:46 AM PDT 23	May 29 12:30:49 AM PDT 23	2115448267 ps
T42	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2847226729	May 29 12:30:49 AM PDT 23	May 29 12:30:54 AM PDT 23	4564099881 ps
T300	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1687812635	May 29 12:29:19 AM PDT 23	May 29 12:29:22 AM PDT 23	2186251490 ps
T392	/workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.607385462	May 29 12:31:39 AM PDT 23	May 29 12:31:41 AM PDT 23	2033504351 ps
T366	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1444669327	May 29 12:30:40 AM PDT 23	May 29 12:30:50 AM PDT 23	22318289962 ps
T393	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3643193284	May 29 12:30:48 AM PDT 23	May 29 12:30:54 AM PDT 23	2011031314 ps
T394	/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3204055773	May 29 12:31:05 AM PDT 23	May 29 12:31:11 AM PDT 23	2013792217 ps
T304	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.401566950	May 29 12:29:43 AM PDT 23	May 29 12:30:29 AM PDT 23	9590013975 ps
T395	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2474699110	May 29 12:30:45 AM PDT 23	May 29 12:31:08 AM PDT 23	8824903624 ps
T396	/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2015548040	May 29 12:31:21 AM PDT 23	May 29 12:31:27 AM PDT 23	2010934495 ps
T305	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1508652902	May 29 12:30:34 AM PDT 23	May 29 12:30:36 AM PDT 23	2104905502 ps
T292	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1041530864	May 29 12:29:44 AM PDT 23	May 29 12:29:49 AM PDT 23	2596527022 ps
T397	/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2410004016	May 29 12:31:38 AM PDT 23	May 29 12:31:40 AM PDT 23	2031156601 ps
T386	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.72774822	May 29 12:29:45 AM PDT 23	May 29 12:29:48 AM PDT 23	2069564035 ps
T398	/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.347966679	May 29 12:30:41 AM PDT 23	May 29 12:30:43 AM PDT 23	2046791334 ps
T399	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1241612700	May 29 12:30:38 AM PDT 23	May 29 12:30:44 AM PDT 23	2014526129 ps
T295	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.293290392	May 29 12:29:32 AM PDT 23	May 29 12:29:34 AM PDT 23	2117442430 ps
T400	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3473774900	May 29 12:30:40 AM PDT 23	May 29 12:30:42 AM PDT 23	2109110463 ps
T401	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1122843211	May 29 12:29:32 AM PDT 23	May 29 12:29:34 AM PDT 23	2085355463 ps
T402	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3199909582	May 29 12:30:36 AM PDT 23	May 29 12:30:39 AM PDT 23	2187582925 ps
T293	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1810446868	May 29 12:29:31 AM PDT 23	May 29 12:30:26 AM PDT 23	22213592139 ps
T301	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3074073466	May 29 12:30:38 AM PDT 23	May 29 12:31:34 AM PDT 23	22157896209 ps
T302	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1410400086	May 29 12:30:39 AM PDT 23	May 29 12:31:02 AM PDT 23	42895425904 ps
T403	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.961220067	May 29 12:29:27 AM PDT 23	May 29 12:30:38 AM PDT 23	65612047605 ps
T404	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1761949965	May 29 12:30:29 AM PDT 23	May 29 12:30:32 AM PDT 23	2017246782 ps
T405	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.86087240	May 29 12:30:51 AM PDT 23	May 29 12:30:53 AM PDT 23	2119323524 ps
T294	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3857734060	May 29 12:30:47 AM PDT 23	May 29 12:30:49 AM PDT 23	2100021429 ps
T406	/workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3132390200	May 29 12:31:31 AM PDT 23	May 29 12:31:37 AM PDT 23	2016125839 ps
T306	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.69575598	May 29 12:30:38 AM PDT 23	May 29 12:30:44 AM PDT 23	2054860735 ps
T407	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3369607218	May 29 12:30:30 AM PDT 23	May 29 12:32:17 AM PDT 23	42406743353 ps
T408	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3973883958	May 29 12:30:47 AM PDT 23	May 29 12:30:50 AM PDT 23	2158224994 ps
T409	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1282236524	May 29 12:30:28 AM PDT 23	May 29 12:30:30 AM PDT 23	2028933805 ps
T410	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2370894957	May 29 12:30:52 AM PDT 23	May 29 12:31:04 AM PDT 23	22673608893 ps
T411	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3357141205	May 29 12:30:32 AM PDT 23	May 29 12:30:36 AM PDT 23	5265486196 ps
T312	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.391644016	May 29 12:30:36 AM PDT 23	May 29 12:30:39 AM PDT 23	2488882400 ps
T412	/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1543766512	May 29 12:30:42 AM PDT 23	May 29 12:30:48 AM PDT 23	2010880543 ps
T413	/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3789051024	May 29 12:30:49 AM PDT 23	May 29 12:30:52 AM PDT 23	2018013725 ps
T414	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.846375658	May 29 12:30:43 AM PDT 23	May 29 12:30:46 AM PDT 23	2429615979 ps
T313	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.652414693	May 29 12:30:32 AM PDT 23	May 29 12:30:34 AM PDT 23	2053642598 ps
T415	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.344895046	May 29 12:30:34 AM PDT 23	May 29 12:30:36 AM PDT 23	2150280480 ps
T416	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.239034329	May 29 12:30:37 AM PDT 23	May 29 12:30:42 AM PDT 23	9525079730 ps
T417	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1393567080	May 29 12:30:39 AM PDT 23	May 29 12:30:41 AM PDT 23	2052413003 ps
T314	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4078085084	May 29 12:30:33 AM PDT 23	May 29 12:30:35 AM PDT 23	2067550605 ps
T418	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2447005335	May 29 12:30:47 AM PDT 23	May 29 12:30:49 AM PDT 23	2213955363 ps
T419	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1492629050	May 29 12:30:48 AM PDT 23	May 29 12:30:55 AM PDT 23	2096819701 ps
T420	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1768616698	May 29 12:29:32 AM PDT 23	May 29 12:29:36 AM PDT 23	2138345173 ps
T421	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1956185955	May 29 12:30:47 AM PDT 23	May 29 12:31:04 AM PDT 23	22409802899 ps
T422	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1058174568	May 29 12:29:32 AM PDT 23	May 29 12:29:55 AM PDT 23	9548486890 ps
T423	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.43548372	May 29 12:30:54 AM PDT 23	May 29 12:31:21 AM PDT 23	7258973415 ps
T424	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2664006586	May 29 12:29:19 AM PDT 23	May 29 12:31:12 AM PDT 23	42302381833 ps
T287	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.984789217	May 29 12:30:32 AM PDT 23	May 29 12:30:36 AM PDT 23	2183216975 ps
T425	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.244864699	May 29 12:30:39 AM PDT 23	May 29 12:30:42 AM PDT 23	2129485467 ps
T426	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3490353792	May 29 12:29:44 AM PDT 23	May 29 12:30:13 AM PDT 23	33791250776 ps
T427	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.956199612	May 29 12:30:35 AM PDT 23	May 29 12:30:59 AM PDT 23	9228614360 ps
T428	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3057602890	May 29 12:30:39 AM PDT 23	May 29 12:30:40 AM PDT 23	2074147066 ps
T429	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2459677242	May 29 12:30:40 AM PDT 23	May 29 12:30:43 AM PDT 23	2206498633 ps
T430	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2576675925	May 29 12:29:14 AM PDT 23	May 29 12:31:00 AM PDT 23	42366499173 ps
T431	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2316225234	May 29 12:30:39 AM PDT 23	May 29 12:30:52 AM PDT 23	9614747502 ps
T44	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1777606187	May 29 02:37:28 AM PDT 23	May 29 02:37:31 AM PDT 23	2525522336 ps
T45	/workspace/coverage/default/15.sysrst_ctrl_alert_test.169959392	May 29 02:37:37 AM PDT 23	May 29 02:37:39 AM PDT 23	2051455144 ps
T46	/workspace/coverage/default/23.sysrst_ctrl_smoke.983696727	May 29 02:38:47 AM PDT 23	May 29 02:38:49 AM PDT 23	2130112352 ps
T71	/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.4274848505	May 29 02:37:32 AM PDT 23	May 29 02:37:39 AM PDT 23	2413176063 ps
T14	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.1663654051	May 29 02:38:43 AM PDT 23	May 29 02:38:52 AM PDT 23	3286066244 ps
T15	/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2070891708	May 29 02:40:10 AM PDT 23	May 29 02:40:52 AM PDT 23	813723076549 ps
T16	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.248008918	May 29 02:36:59 AM PDT 23	May 29 02:43:03 AM PDT 23	150675713638 ps
T28	/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.4257434783	May 29 02:39:03 AM PDT 23	May 29 02:39:06 AM PDT 23	3883100087 ps
T29	/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1839773679	May 29 02:39:40 AM PDT 23	May 29 02:39:45 AM PDT 23	2427529294 ps
T30	/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.790408896	May 29 02:39:21 AM PDT 23	May 29 02:39:23 AM PDT 23	3366633831 ps
T31	/workspace/coverage/default/30.sysrst_ctrl_alert_test.2635037740	May 29 02:39:09 AM PDT 23	May 29 02:39:14 AM PDT 23	2013541106 ps
T32	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3414040916	May 29 02:39:28 AM PDT 23	May 29 02:39:34 AM PDT 23	2201393291 ps
T33	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.624402356	May 29 02:38:59 AM PDT 23	May 29 02:39:29 AM PDT 23	27586306896 ps
T34	/workspace/coverage/default/29.sysrst_ctrl_alert_test.3371138575	May 29 02:39:03 AM PDT 23	May 29 02:39:05 AM PDT 23	2113649255 ps
T62	/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3697377586	May 29 02:38:32 AM PDT 23	May 29 02:38:36 AM PDT 23	2244810853 ps
T63	/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3876854398	May 29 02:37:26 AM PDT 23	May 29 02:37:31 AM PDT 23	2615106624 ps
T72	/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2073557728	May 29 02:38:42 AM PDT 23	May 29 02:38:47 AM PDT 23	2412301292 ps
T17	/workspace/coverage/default/2.sysrst_ctrl_combo_detect.3773698589	May 29 02:37:01 AM PDT 23	May 29 02:37:56 AM PDT 23	103105697547 ps
T18	/workspace/coverage/default/20.sysrst_ctrl_stress_all.2585758035	May 29 02:38:22 AM PDT 23	May 29 02:38:51 AM PDT 23	11502573006 ps
T19	/workspace/coverage/default/3.sysrst_ctrl_stress_all.4073719220	May 29 02:37:02 AM PDT 23	May 29 02:48:29 AM PDT 23	256470292470 ps
T432	/workspace/coverage/default/41.sysrst_ctrl_alert_test.3129125833	May 29 02:39:38 AM PDT 23	May 29 02:39:46 AM PDT 23	2016063368 ps
T128	/workspace/coverage/default/32.sysrst_ctrl_smoke.1149713287	May 29 02:39:01 AM PDT 23	May 29 02:39:03 AM PDT 23	2130276237 ps
T318	/workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2645849132	May 29 02:38:41 AM PDT 23	May 29 02:38:44 AM PDT 23	2527293126 ps
T20	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1145141851	May 29 02:40:14 AM PDT 23	May 29 02:42:11 AM PDT 23	44873564919 ps
T21	/workspace/coverage/default/0.sysrst_ctrl_stress_all.501635863	May 29 02:36:15 AM PDT 23	May 29 02:36:31 AM PDT 23	12407218052 ps
T22	/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2560989542	May 29 02:39:59 AM PDT 23	May 29 02:41:43 AM PDT 23	80503093034 ps
T97	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3042128849	May 29 02:36:59 AM PDT 23	May 29 02:37:01 AM PDT 23	2180298700 ps
T98	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.4245979377	May 29 02:36:57 AM PDT 23	May 29 02:37:52 AM PDT 23	22011522455 ps
T99	/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.4253919484	May 29 02:38:43 AM PDT 23	May 29 02:38:50 AM PDT 23	2513568696 ps
T100	/workspace/coverage/default/37.sysrst_ctrl_smoke.433843116	May 29 02:39:28 AM PDT 23	May 29 02:39:30 AM PDT 23	2124385260 ps
T126	/workspace/coverage/default/27.sysrst_ctrl_alert_test.3383753394	May 29 02:39:23 AM PDT 23	May 29 02:39:26 AM PDT 23	2017925998 ps
T23	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.477629103	May 29 02:38:29 AM PDT 23	May 29 02:38:36 AM PDT 23	3303334446 ps
T52	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.3486428804	May 29 02:37:39 AM PDT 23	May 29 02:38:06 AM PDT 23	37909330059 ps
T127	/workspace/coverage/default/24.sysrst_ctrl_smoke.1789979992	May 29 02:38:33 AM PDT 23	May 29 02:38:40 AM PDT 23	2112537423 ps
T53	/workspace/coverage/default/20.sysrst_ctrl_combo_detect.1927362542	May 29 02:38:22 AM PDT 23	May 29 02:39:59 AM PDT 23	191260260886 ps
T203	/workspace/coverage/default/2.sysrst_ctrl_alert_test.295052252	May 29 02:36:59 AM PDT 23	May 29 02:37:01 AM PDT 23	2040163016 ps
T50	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2705851628	May 29 02:37:37 AM PDT 23	May 29 02:38:31 AM PDT 23	39896572822 ps
T51	/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3778582627	May 29 02:39:13 AM PDT 23	May 29 02:39:17 AM PDT 23	11920872305 ps
T135	/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2567704248	May 29 02:39:52 AM PDT 23	May 29 02:39:56 AM PDT 23	3372420287 ps
T55	/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2314027261	May 29 02:39:46 AM PDT 23	May 29 02:39:49 AM PDT 23	2970532216 ps
T433	/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1808007335	May 29 02:39:45 AM PDT 23	May 29 02:39:47 AM PDT 23	3483918419 ps
T434	/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2756926333	May 29 02:39:14 AM PDT 23	May 29 02:39:17 AM PDT 23	4075426385 ps
T49	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2330300103	May 29 02:39:48 AM PDT 23	May 29 02:40:43 AM PDT 23	34042976783 ps
T92	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2387622353	May 29 02:37:02 AM PDT 23	May 29 02:37:04 AM PDT 23	2277443604 ps
T435	/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1749168167	May 29 02:37:37 AM PDT 23	May 29 02:37:39 AM PDT 23	2276561075 ps
T319	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3440911256	May 29 02:38:33 AM PDT 23	May 29 02:38:35 AM PDT 23	2541108412 ps
T93	/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.4042184778	May 29 02:40:13 AM PDT 23	May 29 02:40:30 AM PDT 23	25350205275 ps
T54	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.75911521	May 29 02:37:13 AM PDT 23	May 29 02:39:45 AM PDT 23	105251304675 ps
T94	/workspace/coverage/default/14.sysrst_ctrl_stress_all.1653689017	May 29 02:37:36 AM PDT 23	May 29 02:41:20 AM PDT 23	93413162805 ps
T320	/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1588770739	May 29 02:39:16 AM PDT 23	May 29 02:39:18 AM PDT 23	2529530329 ps
T436	/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.269014745	May 29 02:38:19 AM PDT 23	May 29 02:38:21 AM PDT 23	2154397555 ps
T58	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.375369358	May 29 02:37:02 AM PDT 23	May 29 02:37:04 AM PDT 23	3903359821 ps
T221	/workspace/coverage/default/1.sysrst_ctrl_smoke.3123579564	May 29 02:36:58 AM PDT 23	May 29 02:37:02 AM PDT 23	2119225229 ps
T89	/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.593528399	May 29 02:40:00 AM PDT 23	May 29 02:40:04 AM PDT 23	3506170781 ps
T222	/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3660154506	May 29 02:37:46 AM PDT 23	May 29 02:37:50 AM PDT 23	4269639418 ps
T79	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2887575220	May 29 02:36:54 AM PDT 23	May 29 02:36:59 AM PDT 23	3079590193 ps
T47	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1702405865	May 29 02:35:59 AM PDT 23	May 29 02:36:11 AM PDT 23	35998465339 ps
T113	/workspace/coverage/default/9.sysrst_ctrl_smoke.3929830508	May 29 02:37:11 AM PDT 23	May 29 02:37:12 AM PDT 23	2223600712 ps
T60	/workspace/coverage/default/18.sysrst_ctrl_combo_detect.2218384603	May 29 02:38:18 AM PDT 23	May 29 02:41:36 AM PDT 23	150857398909 ps
T114	/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.322081641	May 29 02:39:00 AM PDT 23	May 29 02:39:03 AM PDT 23	2524900955 ps
T437	/workspace/coverage/default/10.sysrst_ctrl_alert_test.2116463394	May 29 02:37:25 AM PDT 23	May 29 02:37:27 AM PDT 23	2023581298 ps
T438	/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1351732930	May 29 02:37:06 AM PDT 23	May 29 02:37:13 AM PDT 23	2089310761 ps
T48	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.784708463	May 29 02:39:04 AM PDT 23	May 29 02:39:31 AM PDT 23	59049835318 ps
T124	/workspace/coverage/default/38.sysrst_ctrl_stress_all.1556526792	May 29 02:39:26 AM PDT 23	May 29 02:39:58 AM PDT 23	11438441511 ps
T439	/workspace/coverage/default/46.sysrst_ctrl_smoke.3749905358	May 29 02:40:07 AM PDT 23	May 29 02:40:13 AM PDT 23	2112364508 ps
T56	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4062470689	May 29 02:38:48 AM PDT 23	May 29 02:39:47 AM PDT 23	51015127535 ps
T217	/workspace/coverage/default/10.sysrst_ctrl_smoke.77104644	May 29 02:37:04 AM PDT 23	May 29 02:37:06 AM PDT 23	2157183981 ps
T75	/workspace/coverage/default/10.sysrst_ctrl_combo_detect.3987952982	May 29 02:37:28 AM PDT 23	May 29 02:37:57 AM PDT 23	88099091535 ps
T218	/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1332294138	May 29 02:39:10 AM PDT 23	May 29 02:39:11 AM PDT 23	3751206797 ps
T61	/workspace/coverage/default/37.sysrst_ctrl_edge_detect.797293893	May 29 02:39:28 AM PDT 23	May 29 02:39:30 AM PDT 23	2587809030 ps
T219	/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.4162046289	May 29 02:35:59 AM PDT 23	May 29 02:36:05 AM PDT 23	14998411759 ps
T220	/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3460968988	May 29 02:35:58 AM PDT 23	May 29 02:36:06 AM PDT 23	2611998399 ps
T64	/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3055702651	May 29 02:39:00 AM PDT 23	May 29 02:39:03 AM PDT 23	7367883813 ps
T57	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.979653430	May 29 02:37:33 AM PDT 23	May 29 02:38:14 AM PDT 23	17118711224 ps
T157	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3151612895	May 29 02:37:37 AM PDT 23	May 29 02:37:46 AM PDT 23	3406618895 ps
T158	/workspace/coverage/default/21.sysrst_ctrl_smoke.967303315	May 29 02:38:43 AM PDT 23	May 29 02:38:44 AM PDT 23	2209541108 ps
T159	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.76909863	May 29 02:39:26 AM PDT 23	May 29 02:39:34 AM PDT 23	2611250376 ps
T160	/workspace/coverage/default/22.sysrst_ctrl_smoke.1204847505	May 29 02:38:37 AM PDT 23	May 29 02:38:41 AM PDT 23	2115193426 ps
T161	/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4136809709	May 29 02:37:01 AM PDT 23	May 29 02:37:04 AM PDT 23	2622111350 ps
T76	/workspace/coverage/default/21.sysrst_ctrl_stress_all.380750545	May 29 02:38:39 AM PDT 23	May 29 02:46:28 AM PDT 23	187128814701 ps
T255	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3485221358	May 29 02:40:10 AM PDT 23	May 29 02:40:52 AM PDT 23	59941282275 ps
T384	/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2503622129	May 29 02:37:25 AM PDT 23	May 29 02:37:33 AM PDT 23	2512587191 ps
T440	/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1675294208	May 29 02:39:59 AM PDT 23	May 29 02:40:05 AM PDT 23	7529125499 ps
T101	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1265441332	May 29 02:38:25 AM PDT 23	May 29 02:39:44 AM PDT 23	56109332913 ps
T59	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.698917669	May 29 02:37:28 AM PDT 23	May 29 02:37:33 AM PDT 23	3614876033 ps
T65	/workspace/coverage/default/42.sysrst_ctrl_stress_all.2794774781	May 29 02:39:52 AM PDT 23	May 29 02:40:01 AM PDT 23	13534208664 ps
T136	/workspace/coverage/default/30.sysrst_ctrl_smoke.3225934427	May 29 02:39:08 AM PDT 23	May 29 02:39:09 AM PDT 23	2145828331 ps
T95	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2229725476	May 29 02:38:25 AM PDT 23	May 29 02:38:28 AM PDT 23	2830238164 ps
T96	/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.963594728	May 29 02:36:56 AM PDT 23	May 29 02:36:58 AM PDT 23	3534097614 ps
T125	/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1257511738	May 29 02:40:11 AM PDT 23	May 29 02:40:14 AM PDT 23	3839664275 ps
T102	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3547121855	May 29 02:40:11 AM PDT 23	May 29 02:41:01 AM PDT 23	68927779687 ps
T174	/workspace/coverage/default/33.sysrst_ctrl_edge_detect.1875799143	May 29 02:39:02 AM PDT 23	May 29 02:39:07 AM PDT 23	3062012883 ps
T175	/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4126752162	May 29 02:39:36 AM PDT 23	May 29 02:39:44 AM PDT 23	3554032684 ps
T176	/workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1177900655	May 29 02:38:43 AM PDT 23	May 29 02:38:46 AM PDT 23	3798920014 ps
T441	/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1171986475	May 29 02:36:06 AM PDT 23	May 29 02:36:09 AM PDT 23	2197923178 ps
T383	/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2774528375	May 29 02:37:35 AM PDT 23	May 29 02:37:42 AM PDT 23	2512494131 ps
T442	/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3012776877	May 29 02:38:25 AM PDT 23	May 29 02:38:27 AM PDT 23	2439985797 ps
T443	/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2065006236	May 29 02:40:09 AM PDT 23	May 29 02:40:22 AM PDT 23	4090270665 ps
T444	/workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.829508043	May 29 02:38:59 AM PDT 23	May 29 02:39:07 AM PDT 23	2608647027 ps
T162	/workspace/coverage/default/17.sysrst_ctrl_stress_all.4023868389	May 29 02:37:33 AM PDT 23	May 29 02:38:19 AM PDT 23	18885094867 ps
T385	/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3392479545	May 29 02:39:41 AM PDT 23	May 29 02:39:47 AM PDT 23	2518276689 ps
T84	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.118888935	May 29 02:37:33 AM PDT 23	May 29 02:37:36 AM PDT 23	4056603562 ps
T245	/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1503261547	May 29 02:37:12 AM PDT 23	May 29 02:37:14 AM PDT 23	2571698853 ps
T246	/workspace/coverage/default/49.sysrst_ctrl_stress_all.462027706	May 29 02:40:13 AM PDT 23	May 29 02:47:07 AM PDT 23	175237177781 ps
T247	/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.332737215	May 29 02:38:25 AM PDT 23	May 29 02:38:32 AM PDT 23	2614810041 ps
T248	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.2026040051	May 29 02:38:20 AM PDT 23	May 29 02:40:04 AM PDT 23	168736982338 ps
T249	/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1552248934	May 29 02:36:53 AM PDT 23	May 29 02:36:55 AM PDT 23	2968790990 ps
T250	/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1401174716	May 29 02:36:59 AM PDT 23	May 29 02:37:07 AM PDT 23	2614104129 ps
T251	/workspace/coverage/default/48.sysrst_ctrl_smoke.1032142304	May 29 02:39:52 AM PDT 23	May 29 02:39:54 AM PDT 23	2179755921 ps
T252	/workspace/coverage/default/49.sysrst_ctrl_alert_test.1225599532	May 29 02:40:11 AM PDT 23	May 29 02:40:15 AM PDT 23	2015614373 ps
T253	/workspace/coverage/default/49.sysrst_ctrl_smoke.2633889851	May 29 02:40:12 AM PDT 23	May 29 02:40:18 AM PDT 23	2111218321 ps
T445	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1091260062	May 29 02:40:11 AM PDT 23	May 29 02:40:15 AM PDT 23	2618889490 ps
T446	/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3274579778	May 29 02:36:54 AM PDT 23	May 29 02:36:56 AM PDT 23	2130797875 ps
T90	/workspace/coverage/default/47.sysrst_ctrl_stress_all.2669874357	May 29 02:40:00 AM PDT 23	May 29 02:40:38 AM PDT 23	59995746998 ps
T447	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3454149355	May 29 02:38:47 AM PDT 23	May 29 02:38:50 AM PDT 23	3896227424 ps
T256	/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2928438003	May 29 02:40:11 AM PDT 23	May 29 02:41:32 AM PDT 23	35391883984 ps
T448	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3871435487	May 29 02:39:03 AM PDT 23	May 29 02:39:06 AM PDT 23	2420922558 ps
T449	/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1061779851	May 29 02:37:32 AM PDT 23	May 29 02:37:34 AM PDT 23	2096420328 ps
T450	/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.257633568	May 29 02:39:26 AM PDT 23	May 29 02:39:29 AM PDT 23	3650616561 ps
T163	/workspace/coverage/default/35.sysrst_ctrl_edge_detect.3385046176	May 29 02:39:25 AM PDT 23	May 29 02:39:36 AM PDT 23	3702320321 ps
T66	/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1586085221	May 29 02:38:17 AM PDT 23	May 29 02:41:42 AM PDT 23	3047931900481 ps
T91	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2008495822	May 29 02:37:12 AM PDT 23	May 29 02:37:16 AM PDT 23	3207550392 ps
T78	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.185203053	May 29 02:36:58 AM PDT 23	May 29 02:38:42 AM PDT 23	40121853603 ps
T451	/workspace/coverage/default/33.sysrst_ctrl_stress_all.2428458471	May 29 02:38:55 AM PDT 23	May 29 02:39:05 AM PDT 23	14495569461 ps
T452	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3756412778	May 29 02:37:39 AM PDT 23	May 29 02:37:48 AM PDT 23	3618470624 ps
T453	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2732459821	May 29 02:37:35 AM PDT 23	May 29 02:37:42 AM PDT 23	2410824101 ps
T77	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.128077821	May 29 02:37:37 AM PDT 23	May 29 02:38:58 AM PDT 23	126592894328 ps
T115	/workspace/coverage/default/19.sysrst_ctrl_smoke.1981036851	May 29 02:38:20 AM PDT 23	May 29 02:38:22 AM PDT 23	2158917928 ps
T116	/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.864789358	May 29 02:38:17 AM PDT 23	May 29 02:38:25 AM PDT 23	2609502094 ps
T103	/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1469696280	May 29 02:37:11 AM PDT 23	May 29 02:37:50 AM PDT 23	24583422937 ps
T117	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4233273591	May 29 02:40:16 AM PDT 23	May 29 02:40:53 AM PDT 23	52997427361 ps
T67	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.146668428	May 29 02:39:28 AM PDT 23	May 29 02:42:10 AM PDT 23	64462073197 ps
T118	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1092564923	May 29 02:39:07 AM PDT 23	May 29 02:39:09 AM PDT 23	2636809565 ps
T119	/workspace/coverage/default/6.sysrst_ctrl_stress_all.206874523	May 29 02:36:53 AM PDT 23	May 29 02:36:57 AM PDT 23	13500908608 ps
T120	/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2630571799	May 29 02:39:41 AM PDT 23	May 29 02:39:45 AM PDT 23	2425860206 ps
T454	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2286413435	May 29 02:38:17 AM PDT 23	May 29 02:38:19 AM PDT 23	2528567815 ps
T259	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.936082770	May 29 02:40:12 AM PDT 23	May 29 02:41:36 AM PDT 23	67805621127 ps
T382	/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2997783522	May 29 02:40:10 AM PDT 23	May 29 02:41:08 AM PDT 23	880581867184 ps
T455	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.4208699016	May 29 02:38:18 AM PDT 23	May 29 02:38:27 AM PDT 23	3033021736 ps
T456	/workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.278680372	May 29 02:38:44 AM PDT 23	May 29 02:38:53 AM PDT 23	3191173120 ps
T260	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2093497311	May 29 02:40:15 AM PDT 23	May 29 02:42:15 AM PDT 23	50954687826 ps
T457	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.345669149	May 29 02:38:18 AM PDT 23	May 29 02:38:23 AM PDT 23	2517245409 ps