Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.33 99.18 96.99 100.00 100.00 98.67 99.71 93.78


Total tests in report: 919
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
42.39 42.39 66.34 66.34 46.39 46.39 54.91 54.91 4.49 4.49 69.21 69.21 54.05 54.05 1.36 1.36 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2704060435
68.98 26.59 89.79 23.46 77.22 30.84 60.39 5.48 73.08 68.59 90.76 21.55 87.09 33.04 4.53 3.16 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.3284265803
77.12 8.14 94.16 4.37 86.02 8.80 90.53 30.14 73.08 0.00 94.42 3.66 88.92 1.83 12.70 8.18 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2169574353
81.55 4.43 96.62 2.46 89.43 3.41 91.21 0.68 78.85 5.77 96.64 2.22 95.28 6.36 22.79 10.09 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.240570850
84.36 2.81 97.05 0.43 90.32 0.88 92.01 0.80 78.85 0.00 96.64 0.00 95.47 0.19 40.19 17.39 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3699659642
86.95 2.59 97.14 0.09 90.47 0.15 92.01 0.00 79.49 0.64 96.71 0.07 95.66 0.19 57.14 16.96 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1964462790
88.27 1.32 97.72 0.58 90.72 0.25 92.01 0.00 87.18 7.69 97.19 0.48 95.76 0.10 57.31 0.16 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.1652396181
89.25 0.98 97.74 0.02 90.93 0.20 92.69 0.68 87.18 0.00 97.23 0.04 95.76 0.00 63.25 5.94 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2527373867
90.13 0.87 97.80 0.06 91.03 0.10 92.69 0.00 87.82 0.64 97.34 0.11 96.05 0.29 68.16 4.91 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.4198068302
90.94 0.82 97.97 0.17 91.94 0.91 93.84 1.14 87.82 0.00 97.34 0.00 96.05 0.00 71.65 3.49 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.4158748925
91.68 0.74 98.04 0.07 92.37 0.43 96.80 2.97 87.82 0.00 97.49 0.15 96.15 0.10 73.12 1.47 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2693341825
92.27 0.59 98.12 0.07 92.62 0.25 97.26 0.46 89.10 1.28 97.67 0.18 96.72 0.58 74.43 1.31 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.239090861
92.81 0.53 98.19 0.07 92.69 0.08 97.26 0.00 90.38 1.28 97.74 0.07 96.92 0.19 76.44 2.02 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.606151105
93.27 0.46 98.28 0.09 93.02 0.33 97.26 0.00 90.38 0.00 97.74 0.00 97.01 0.10 79.17 2.73 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2386114106
93.62 0.35 98.38 0.09 93.17 0.15 97.26 0.00 92.31 1.92 97.86 0.11 97.21 0.19 79.17 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.2221896232
93.97 0.35 98.38 0.00 93.20 0.03 99.32 2.05 92.31 0.00 97.86 0.00 97.30 0.10 79.44 0.27 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1126318832
94.31 0.34 98.43 0.06 94.16 0.96 99.32 0.00 92.31 0.00 97.93 0.07 97.98 0.67 80.04 0.60 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1975577777
94.62 0.31 98.51 0.07 94.39 0.23 99.32 0.00 93.59 1.28 98.00 0.07 98.46 0.48 80.04 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.3330602536
94.92 0.30 98.54 0.04 94.54 0.15 99.32 0.00 94.23 0.64 98.04 0.04 98.55 0.10 81.19 1.15 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2185848038
95.20 0.28 98.58 0.04 94.62 0.08 99.32 0.00 94.23 0.00 98.08 0.04 98.65 0.10 82.93 1.74 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3008461222
95.44 0.24 98.58 0.00 94.67 0.05 99.32 0.00 95.51 1.28 98.08 0.00 98.75 0.10 83.15 0.22 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.800920655
95.67 0.23 98.68 0.09 94.67 0.00 99.32 0.00 95.51 0.00 98.08 0.00 98.75 0.00 84.68 1.53 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.681035254
95.89 0.22 98.71 0.04 94.74 0.08 99.32 0.00 96.79 1.28 98.15 0.07 98.75 0.00 84.73 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.948688866
96.09 0.21 98.77 0.06 95.10 0.35 99.54 0.23 97.44 0.64 98.23 0.07 98.84 0.10 84.73 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.700012435
96.25 0.15 98.77 0.00 96.06 0.96 99.54 0.00 97.44 0.00 98.23 0.00 98.84 0.00 84.84 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.775258367
96.40 0.15 98.82 0.06 96.08 0.03 99.54 0.00 97.44 0.00 98.23 0.00 98.84 0.00 85.82 0.98 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4213410601
96.54 0.14 98.82 0.00 96.16 0.08 99.54 0.00 97.44 0.00 98.23 0.00 98.84 0.00 86.75 0.93 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.4207751869
96.68 0.14 98.88 0.06 96.18 0.03 99.54 0.00 98.08 0.64 98.30 0.07 98.94 0.10 86.80 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.751099421
96.80 0.13 98.92 0.04 96.26 0.08 99.54 0.00 98.72 0.64 98.34 0.04 99.04 0.10 86.80 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2770100148
96.93 0.12 98.92 0.00 96.26 0.00 99.54 0.00 98.72 0.00 98.34 0.00 99.04 0.00 87.68 0.87 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.2031623479
97.05 0.12 98.94 0.02 96.31 0.05 99.54 0.00 99.36 0.64 98.37 0.04 99.13 0.10 87.68 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.2890658889
97.17 0.12 98.96 0.02 96.31 0.00 99.54 0.00 99.36 0.00 98.37 0.00 99.13 0.00 88.50 0.82 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.4139842874
97.27 0.10 98.97 0.02 96.31 0.00 99.54 0.00 100.00 0.64 98.41 0.04 99.13 0.00 88.50 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.2629042347
97.36 0.09 98.99 0.02 96.41 0.10 99.77 0.23 100.00 0.00 98.45 0.04 99.13 0.00 88.77 0.27 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.93382107
97.43 0.07 98.99 0.00 96.44 0.03 99.77 0.00 100.00 0.00 98.45 0.00 99.13 0.00 89.20 0.44 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2633721264
97.49 0.06 98.99 0.00 96.44 0.00 99.77 0.00 100.00 0.00 98.45 0.00 99.13 0.00 89.64 0.44 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2828458533
97.55 0.06 99.01 0.02 96.46 0.03 99.77 0.00 100.00 0.00 98.45 0.00 99.13 0.00 90.02 0.38 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1796463440
97.60 0.05 99.07 0.06 96.54 0.08 100.00 0.23 100.00 0.00 98.45 0.00 99.13 0.00 90.02 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2137073025
97.65 0.05 99.10 0.04 96.69 0.15 100.00 0.00 100.00 0.00 98.52 0.07 99.23 0.10 90.02 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1394229024
97.70 0.05 99.12 0.02 96.69 0.00 100.00 0.00 100.00 0.00 98.56 0.04 99.23 0.00 90.29 0.27 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1654046093
97.75 0.05 99.12 0.00 96.69 0.00 100.00 0.00 100.00 0.00 98.56 0.00 99.23 0.00 90.62 0.33 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3181496944
97.79 0.04 99.16 0.04 96.71 0.03 100.00 0.00 100.00 0.00 98.63 0.07 99.33 0.10 90.68 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1944847450
97.82 0.03 99.16 0.00 96.74 0.03 100.00 0.00 100.00 0.00 98.63 0.00 99.33 0.00 90.89 0.22 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3670694020
97.85 0.03 99.18 0.02 96.76 0.03 100.00 0.00 100.00 0.00 98.67 0.04 99.42 0.10 90.95 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3612463776
97.89 0.03 99.18 0.00 96.84 0.08 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.10 91.00 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2403155902
97.92 0.03 99.18 0.00 96.84 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 91.22 0.22 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.2503577946
97.95 0.03 99.18 0.00 96.84 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 91.44 0.22 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2707715321
97.98 0.03 99.18 0.00 96.84 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 91.66 0.22 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.602749498
98.00 0.02 99.18 0.00 96.84 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 91.82 0.16 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.733328271
98.03 0.02 99.18 0.00 96.84 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 91.98 0.16 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3305109608
98.05 0.02 99.18 0.00 96.84 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 92.15 0.16 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.797333609
98.07 0.02 99.18 0.00 96.84 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 92.31 0.16 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.812490484
98.09 0.02 99.18 0.00 96.87 0.03 100.00 0.00 100.00 0.00 98.67 0.00 99.52 0.00 92.42 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.2616864731
98.11 0.02 99.18 0.00 96.89 0.03 100.00 0.00 100.00 0.00 98.67 0.00 99.61 0.10 92.42 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3137151281
98.13 0.02 99.18 0.00 96.92 0.03 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.10 92.42 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.264116098
98.14 0.02 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 92.53 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1175169097
98.16 0.02 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 92.64 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1558551204
98.17 0.02 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 92.75 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2657949315
98.19 0.02 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 92.86 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1863892970
98.21 0.02 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 92.97 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.427179634
98.22 0.02 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.08 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3690742458
98.24 0.02 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.18 0.11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1936961067
98.24 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.24 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1573086269
98.25 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.29 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.1258074251
98.26 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.35 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2974392462
98.27 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.40 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.904906819
98.28 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.46 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.563978863
98.28 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.51 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1469764401
98.29 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.57 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1574445950
98.30 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.62 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.250160691
98.31 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.68 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1356656267
98.31 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.73 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3385500421
98.32 0.01 99.18 0.00 96.92 0.00 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.78 0.05 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1903604343
98.33 0.01 99.18 0.00 96.97 0.05 100.00 0.00 100.00 0.00 98.67 0.00 99.71 0.00 93.78 0.00 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.765638070

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4123088781
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1121364119
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1139401827
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3152207448
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.830091598
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.720398685
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.689520360
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.450938997
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3526708768
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1253571873
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1890623791
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.162139694
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.160305510
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/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2534673429
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.148034507
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1766471768
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2393031786
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1119563628
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2620297909
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3010012028
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.249115518
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1892736564
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3991176906
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2380482967
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.978067839
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2614965513
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.829657751
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.48313100



Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2704060435 Feb 08 10:03:51 AM UTC 25 Feb 08 10:03:56 AM UTC 25 2545984863 ps
T2 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1251689532 Feb 08 10:03:51 AM UTC 25 Feb 08 10:03:57 AM UTC 25 2429943431 ps
T4 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2693341825 Feb 08 10:03:52 AM UTC 25 Feb 08 10:03:57 AM UTC 25 3332894727 ps
T12 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2073077456 Feb 08 10:03:53 AM UTC 25 Feb 08 10:03:57 AM UTC 25 3733275986 ps
T13 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.88756479 Feb 08 10:03:52 AM UTC 25 Feb 08 10:03:59 AM UTC 25 2619429737 ps
T14 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.4207751869 Feb 08 10:03:51 AM UTC 25 Feb 08 10:03:59 AM UTC 25 2062170735 ps
T15 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.1332766611 Feb 08 10:03:51 AM UTC 25 Feb 08 10:04:00 AM UTC 25 2114447241 ps
T16 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.521601682 Feb 08 10:03:52 AM UTC 25 Feb 08 10:04:01 AM UTC 25 5192844740 ps
T17 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1194253681 Feb 08 10:03:58 AM UTC 25 Feb 08 10:04:03 AM UTC 25 2134517704 ps
T3 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2600256782 Feb 08 10:03:55 AM UTC 25 Feb 08 10:04:04 AM UTC 25 2404869757 ps
T22 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.1258074251 Feb 08 10:03:51 AM UTC 25 Feb 08 10:04:05 AM UTC 25 2457481696 ps
T31 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3485297655 Feb 08 10:04:00 AM UTC 25 Feb 08 10:04:06 AM UTC 25 2244886877 ps
T74 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2137073025 Feb 08 10:03:58 AM UTC 25 Feb 08 10:04:06 AM UTC 25 2013384693 ps
T23 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1746646007 Feb 08 10:04:00 AM UTC 25 Feb 08 10:04:07 AM UTC 25 2490686228 ps
T7 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2785729346 Feb 08 10:04:01 AM UTC 25 Feb 08 10:04:07 AM UTC 25 2534022399 ps
T25 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2169574353 Feb 08 10:03:52 AM UTC 25 Feb 08 10:04:10 AM UTC 25 2513368402 ps
T81 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.3683336824 Feb 08 10:04:02 AM UTC 25 Feb 08 10:04:11 AM UTC 25 2025749365 ps
T5 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.884572565 Feb 08 10:04:07 AM UTC 25 Feb 08 10:04:13 AM UTC 25 3446240732 ps
T26 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.93382107 Feb 08 10:04:04 AM UTC 25 Feb 08 10:04:16 AM UTC 25 2508350430 ps
T27 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.733328271 Feb 08 10:04:07 AM UTC 25 Feb 08 10:04:19 AM UTC 25 3228276057 ps
T6 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3725275141 Feb 08 10:03:55 AM UTC 25 Feb 08 10:04:20 AM UTC 25 37895246315 ps
T65 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3117432393 Feb 08 10:04:04 AM UTC 25 Feb 08 10:04:21 AM UTC 25 2614801966 ps
T8 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3201499473 Feb 08 10:04:08 AM UTC 25 Feb 08 10:04:25 AM UTC 25 3137648407 ps
T66 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3644963231 Feb 08 10:04:21 AM UTC 25 Feb 08 10:04:26 AM UTC 25 2031932795 ps
T67 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.4049046532 Feb 08 10:04:22 AM UTC 25 Feb 08 10:04:28 AM UTC 25 2123424820 ps
T68 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1889578550 Feb 08 10:04:06 AM UTC 25 Feb 08 10:04:32 AM UTC 25 4094633236 ps
T29 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.214085048 Feb 08 10:04:27 AM UTC 25 Feb 08 10:04:32 AM UTC 25 2284652853 ps
T57 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1094862110 Feb 08 10:04:27 AM UTC 25 Feb 08 10:04:33 AM UTC 25 2214372394 ps
T69 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.4178969434 Feb 08 10:04:34 AM UTC 25 Feb 08 10:04:37 AM UTC 25 3077423715 ps
T82 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2757364252 Feb 08 10:04:34 AM UTC 25 Feb 08 10:04:40 AM UTC 25 2640447957 ps
T220 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.2007382248 Feb 08 10:04:28 AM UTC 25 Feb 08 10:04:41 AM UTC 25 2058499407 ps
T24 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3044083808 Feb 08 10:04:25 AM UTC 25 Feb 08 10:04:42 AM UTC 25 2453250728 ps
T9 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2746200269 Feb 08 10:04:38 AM UTC 25 Feb 08 10:04:44 AM UTC 25 5195448408 ps
T28 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2551132927 Feb 08 10:04:17 AM UTC 25 Feb 08 10:04:46 AM UTC 25 13309435440 ps
T83 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.1747084306 Feb 08 10:04:33 AM UTC 25 Feb 08 10:04:47 AM UTC 25 2511755858 ps
T10 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.1404920248 Feb 08 10:04:42 AM UTC 25 Feb 08 10:04:52 AM UTC 25 2789368605 ps
T101 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2047161810 Feb 08 10:04:48 AM UTC 25 Feb 08 10:04:52 AM UTC 25 2047109569 ps
T11 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3322307893 Feb 08 10:04:11 AM UTC 25 Feb 08 10:04:56 AM UTC 25 150090025068 ps
T51 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.2616864731 Feb 08 10:04:47 AM UTC 25 Feb 08 10:04:56 AM UTC 25 7979638153 ps
T58 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3473825244 Feb 08 10:04:35 AM UTC 25 Feb 08 10:04:56 AM UTC 25 3461722517 ps
T93 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.254135538 Feb 08 10:04:53 AM UTC 25 Feb 08 10:04:58 AM UTC 25 2127530236 ps
T94 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.640603777 Feb 08 10:04:19 AM UTC 25 Feb 08 10:04:58 AM UTC 25 42217731350 ps
T95 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.1138418049 Feb 08 10:04:57 AM UTC 25 Feb 08 10:05:03 AM UTC 25 2242518114 ps
T84 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1773919646 Feb 08 10:04:57 AM UTC 25 Feb 08 10:05:03 AM UTC 25 2536257387 ps
T59 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2471347680 Feb 08 10:04:57 AM UTC 25 Feb 08 10:05:04 AM UTC 25 2547659542 ps
T60 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3781881439 Feb 08 10:05:03 AM UTC 25 Feb 08 10:05:07 AM UTC 25 3871293878 ps
T75 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3004509989 Feb 08 10:04:53 AM UTC 25 Feb 08 10:05:09 AM UTC 25 2459942874 ps
T132 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.173759483 Feb 08 10:04:55 AM UTC 25 Feb 08 10:05:09 AM UTC 25 2433882823 ps
T45 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2770100148 Feb 08 10:05:07 AM UTC 25 Feb 08 10:05:11 AM UTC 25 3693054618 ps
T282 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.881592638 Feb 08 10:05:12 AM UTC 25 Feb 08 10:05:16 AM UTC 25 2080940749 ps
T85 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1720818392 Feb 08 10:04:59 AM UTC 25 Feb 08 10:05:16 AM UTC 25 2609651506 ps
T98 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1126318832 Feb 08 10:03:58 AM UTC 25 Feb 08 10:05:17 AM UTC 25 22010495347 ps
T283 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1965138751 Feb 08 10:05:12 AM UTC 25 Feb 08 10:05:17 AM UTC 25 2125978774 ps
T284 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.349453619 Feb 08 10:04:59 AM UTC 25 Feb 08 10:05:17 AM UTC 25 3777497186 ps
T285 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2277164549 Feb 08 10:05:19 AM UTC 25 Feb 08 10:05:24 AM UTC 25 2736949847 ps
T87 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2894833465 Feb 08 10:05:17 AM UTC 25 Feb 08 10:05:24 AM UTC 25 2525329952 ps
T286 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4243572487 Feb 08 10:05:17 AM UTC 25 Feb 08 10:05:25 AM UTC 25 2161098063 ps
T86 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2115716452 Feb 08 10:05:19 AM UTC 25 Feb 08 10:05:26 AM UTC 25 2524755321 ps
T71 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3591593627 Feb 08 10:05:25 AM UTC 25 Feb 08 10:05:30 AM UTC 25 4049887865 ps
T477 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.2888235244 Feb 08 10:05:17 AM UTC 25 Feb 08 10:05:30 AM UTC 25 2162847274 ps
T478 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.72493382 Feb 08 10:05:19 AM UTC 25 Feb 08 10:05:30 AM UTC 25 2613205295 ps
T61 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.884645167 Feb 08 10:05:19 AM UTC 25 Feb 08 10:05:32 AM UTC 25 3150812163 ps
T49 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1103099880 Feb 08 10:05:26 AM UTC 25 Feb 08 10:05:32 AM UTC 25 3319619952 ps
T76 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.4253045439 Feb 08 10:05:17 AM UTC 25 Feb 08 10:05:33 AM UTC 25 2443401672 ps
T21 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.3284265803 Feb 08 10:04:12 AM UTC 25 Feb 08 10:05:33 AM UTC 25 39282173385 ps
T77 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3491608673 Feb 08 10:05:33 AM UTC 25 Feb 08 10:05:37 AM UTC 25 2622403959 ps
T157 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2794802972 Feb 08 10:05:34 AM UTC 25 Feb 08 10:05:38 AM UTC 25 2137613963 ps
T158 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.1686114155 Feb 08 10:05:32 AM UTC 25 Feb 08 10:05:40 AM UTC 25 2021452618 ps
T32 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.4158748925 Feb 08 10:04:14 AM UTC 25 Feb 08 10:05:42 AM UTC 25 100550621067 ps
T72 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.2812614593 Feb 08 10:05:10 AM UTC 25 Feb 08 10:05:42 AM UTC 25 8732361590 ps
T159 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2561298049 Feb 08 10:05:38 AM UTC 25 Feb 08 10:05:43 AM UTC 25 2538303907 ps
T160 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2728880660 Feb 08 10:05:39 AM UTC 25 Feb 08 10:05:45 AM UTC 25 2623227276 ps
T161 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1460450821 Feb 08 10:05:33 AM UTC 25 Feb 08 10:05:45 AM UTC 25 2114389441 ps
T248 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3923952611 Feb 08 10:05:39 AM UTC 25 Feb 08 10:05:46 AM UTC 25 4170023423 ps
T30 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1905304967 Feb 08 10:04:43 AM UTC 25 Feb 08 10:05:47 AM UTC 25 44417148309 ps
T39 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.700012435 Feb 08 10:05:41 AM UTC 25 Feb 08 10:05:50 AM UTC 25 5642822907 ps
T167 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.872878066 Feb 08 10:05:47 AM UTC 25 Feb 08 10:05:52 AM UTC 25 2045247216 ps
T53 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.7707735 Feb 08 10:05:43 AM UTC 25 Feb 08 10:05:53 AM UTC 25 4030912535 ps
T78 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.855892837 Feb 08 10:05:51 AM UTC 25 Feb 08 10:05:56 AM UTC 25 2497710524 ps
T40 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3699659642 Feb 08 10:03:55 AM UTC 25 Feb 08 10:05:58 AM UTC 25 147054128236 ps
T168 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.1958919982 Feb 08 10:05:47 AM UTC 25 Feb 08 10:05:59 AM UTC 25 2108648098 ps
T62 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2792859780 Feb 08 10:05:41 AM UTC 25 Feb 08 10:06:00 AM UTC 25 3538521471 ps
T169 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.4245523757 Feb 08 10:05:54 AM UTC 25 Feb 08 10:06:02 AM UTC 25 2200351025 ps
T170 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.530701657 Feb 08 10:05:55 AM UTC 25 Feb 08 10:06:03 AM UTC 25 2518541165 ps
T99 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2975539995 Feb 08 10:04:47 AM UTC 25 Feb 08 10:06:05 AM UTC 25 22013203638 ps
T479 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3781209354 Feb 08 10:05:59 AM UTC 25 Feb 08 10:06:06 AM UTC 25 2623408812 ps
T70 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.728271915 Feb 08 10:06:01 AM UTC 25 Feb 08 10:06:06 AM UTC 25 4132369004 ps
T63 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2486377155 Feb 08 10:06:00 AM UTC 25 Feb 08 10:06:08 AM UTC 25 3826075573 ps
T145 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.107246871 Feb 08 10:05:57 AM UTC 25 Feb 08 10:06:10 AM UTC 25 2610283108 ps
T52 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2303706774 Feb 08 10:06:04 AM UTC 25 Feb 08 10:06:14 AM UTC 25 2476615295 ps
T146 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3975193265 Feb 08 10:06:06 AM UTC 25 Feb 08 10:06:20 AM UTC 25 2011783045 ps
T147 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3722897264 Feb 08 10:05:46 AM UTC 25 Feb 08 10:06:20 AM UTC 25 7300546239 ps
T148 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.199060412 Feb 08 10:06:08 AM UTC 25 Feb 08 10:06:22 AM UTC 25 2110217604 ps
T149 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2037266785 Feb 08 10:06:15 AM UTC 25 Feb 08 10:06:26 AM UTC 25 2094552793 ps
T150 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.2714051619 Feb 08 10:06:21 AM UTC 25 Feb 08 10:06:27 AM UTC 25 2538045358 ps
T79 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.449416124 Feb 08 10:06:11 AM UTC 25 Feb 08 10:06:29 AM UTC 25 2469864656 ps
T151 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3632467930 Feb 08 10:06:23 AM UTC 25 Feb 08 10:06:30 AM UTC 25 3551737870 ps
T480 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.933692812 Feb 08 10:06:21 AM UTC 25 Feb 08 10:06:34 AM UTC 25 2610533981 ps
T64 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.778679471 Feb 08 10:06:24 AM UTC 25 Feb 08 10:06:34 AM UTC 25 3563560754 ps
T48 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.267686389 Feb 08 10:06:30 AM UTC 25 Feb 08 10:06:36 AM UTC 25 2755240236 ps
T42 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2179412647 Feb 08 10:05:43 AM UTC 25 Feb 08 10:06:37 AM UTC 25 54828539922 ps
T56 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.1652396181 Feb 08 10:03:56 AM UTC 25 Feb 08 10:06:37 AM UTC 25 39985500732 ps
T152 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3837908386 Feb 08 10:05:10 AM UTC 25 Feb 08 10:06:38 AM UTC 25 22012426478 ps
T80 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.98105896 Feb 08 10:06:37 AM UTC 25 Feb 08 10:06:42 AM UTC 25 2486017619 ps
T153 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.2218408203 Feb 08 10:06:35 AM UTC 25 Feb 08 10:06:42 AM UTC 25 2017085320 ps
T154 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.116444968 Feb 08 10:06:36 AM UTC 25 Feb 08 10:06:44 AM UTC 25 2122431746 ps
T155 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.252921031 Feb 08 10:06:39 AM UTC 25 Feb 08 10:06:45 AM UTC 25 2631278857 ps
T73 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.444431553 Feb 08 10:06:27 AM UTC 25 Feb 08 10:06:46 AM UTC 25 743158578630 ps
T54 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.240570850 Feb 08 10:05:08 AM UTC 25 Feb 08 10:06:46 AM UTC 25 44809021341 ps
T41 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.916383983 Feb 08 10:04:41 AM UTC 25 Feb 08 10:06:50 AM UTC 25 165650103446 ps
T88 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3180684791 Feb 08 10:05:08 AM UTC 25 Feb 08 10:06:51 AM UTC 25 95569552670 ps
T226 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.3341442151 Feb 08 10:06:37 AM UTC 25 Feb 08 10:06:53 AM UTC 25 2226370900 ps
T131 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.800920655 Feb 08 10:05:45 AM UTC 25 Feb 08 10:06:54 AM UTC 25 19843995511 ps
T50 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.4160361011 Feb 08 10:06:47 AM UTC 25 Feb 08 10:06:55 AM UTC 25 4281112722 ps
T96 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2261889761 Feb 08 10:06:44 AM UTC 25 Feb 08 10:06:55 AM UTC 25 4874150178 ps
T227 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1644822976 Feb 08 10:06:38 AM UTC 25 Feb 08 10:06:55 AM UTC 25 2513285784 ps
T228 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1575631372 Feb 08 10:06:43 AM UTC 25 Feb 08 10:06:55 AM UTC 25 2774260421 ps
T133 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.925175164 Feb 08 10:06:43 AM UTC 25 Feb 08 10:06:56 AM UTC 25 3284519545 ps
T89 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2261499749 Feb 08 10:05:44 AM UTC 25 Feb 08 10:06:59 AM UTC 25 31587772496 ps
T481 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2534673429 Feb 08 10:06:55 AM UTC 25 Feb 08 10:07:01 AM UTC 25 2479158924 ps
T482 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.148034507 Feb 08 10:06:56 AM UTC 25 Feb 08 10:07:01 AM UTC 25 2158948828 ps
T156 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3755508054 Feb 08 10:06:57 AM UTC 25 Feb 08 10:07:02 AM UTC 25 3704127635 ps
T55 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1696365099 Feb 08 10:03:56 AM UTC 25 Feb 08 10:07:02 AM UTC 25 65124855501 ps
T483 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2393031786 Feb 08 10:06:55 AM UTC 25 Feb 08 10:07:03 AM UTC 25 2121301069 ps
T484 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.822832151 Feb 08 10:06:56 AM UTC 25 Feb 08 10:07:03 AM UTC 25 2625250061 ps
T485 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2441868319 Feb 08 10:06:54 AM UTC 25 Feb 08 10:07:04 AM UTC 25 2011109747 ps
T368 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1758892522 Feb 08 10:06:56 AM UTC 25 Feb 08 10:07:05 AM UTC 25 3129364547 ps
T217 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.4109232442 Feb 08 10:06:06 AM UTC 25 Feb 08 10:07:08 AM UTC 25 15610920020 ps
T90 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.221609788 Feb 08 10:06:30 AM UTC 25 Feb 08 10:07:09 AM UTC 25 24091361910 ps
T46 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.166450791 Feb 08 10:07:03 AM UTC 25 Feb 08 10:07:09 AM UTC 25 5818492329 ps
T307 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1766471768 Feb 08 10:06:56 AM UTC 25 Feb 08 10:07:09 AM UTC 25 2508388296 ps
T308 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.4069213391 Feb 08 10:07:05 AM UTC 25 Feb 08 10:07:10 AM UTC 25 2132293575 ps
T309 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.596181375 Feb 08 10:07:04 AM UTC 25 Feb 08 10:07:12 AM UTC 25 2011241011 ps
T310 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.1822925926 Feb 08 10:07:06 AM UTC 25 Feb 08 10:07:14 AM UTC 25 2487183025 ps
T311 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1310590137 Feb 08 10:07:08 AM UTC 25 Feb 08 10:07:15 AM UTC 25 2166998585 ps
T312 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2476283010 Feb 08 10:07:10 AM UTC 25 Feb 08 10:07:16 AM UTC 25 2623585415 ps
T115 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2403155902 Feb 08 10:06:33 AM UTC 25 Feb 08 10:07:17 AM UTC 25 26386855464 ps
T97 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3157106163 Feb 08 10:07:13 AM UTC 25 Feb 08 10:07:18 AM UTC 25 3676662026 ps
T162 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2620297909 Feb 08 10:06:59 AM UTC 25 Feb 08 10:07:19 AM UTC 25 5908866057 ps
T173 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3776123180 Feb 08 10:07:10 AM UTC 25 Feb 08 10:07:20 AM UTC 25 2508790708 ps
T125 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2152178067 Feb 08 10:07:15 AM UTC 25 Feb 08 10:07:20 AM UTC 25 3240105686 ps
T174 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4213410601 Feb 08 10:05:31 AM UTC 25 Feb 08 10:07:21 AM UTC 25 227759195608 ps
T175 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2197714748 Feb 08 10:06:52 AM UTC 25 Feb 08 10:07:22 AM UTC 25 15136671384 ps
T176 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.770895636 Feb 08 10:07:20 AM UTC 25 Feb 08 10:07:24 AM UTC 25 2251126133 ps
T177 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.4073006704 Feb 08 10:07:20 AM UTC 25 Feb 08 10:07:25 AM UTC 25 2136519858 ps
T178 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1796463440 Feb 08 10:04:45 AM UTC 25 Feb 08 10:07:26 AM UTC 25 192839983652 ps
T179 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3553549383 Feb 08 10:07:20 AM UTC 25 Feb 08 10:07:26 AM UTC 25 2489519692 ps
T243 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2270205902 Feb 08 10:07:22 AM UTC 25 Feb 08 10:07:28 AM UTC 25 3449818757 ps
T244 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3721487616 Feb 08 10:07:22 AM UTC 25 Feb 08 10:07:28 AM UTC 25 4151052332 ps
T245 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.38330178 Feb 08 10:07:19 AM UTC 25 Feb 08 10:07:30 AM UTC 25 2013181298 ps
T486 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2752806671 Feb 08 10:08:25 AM UTC 25 Feb 08 10:08:36 AM UTC 25 2509293944 ps
T487 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.965934903 Feb 08 10:07:21 AM UTC 25 Feb 08 10:07:32 AM UTC 25 2620813944 ps
T47 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.490341130 Feb 08 10:07:27 AM UTC 25 Feb 08 10:07:34 AM UTC 25 3465733267 ps
T488 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1732587187 Feb 08 10:07:31 AM UTC 25 Feb 08 10:07:35 AM UTC 25 2073275120 ps
T489 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.381506504 Feb 08 10:07:10 AM UTC 25 Feb 08 10:07:35 AM UTC 25 5366385808 ps
T490 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2581906403 Feb 08 10:07:21 AM UTC 25 Feb 08 10:07:36 AM UTC 25 2511890386 ps
T491 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1534299530 Feb 08 10:07:31 AM UTC 25 Feb 08 10:07:36 AM UTC 25 2138181682 ps
T492 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.774873141 Feb 08 10:07:32 AM UTC 25 Feb 08 10:07:36 AM UTC 25 2191333623 ps
T493 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.4177704222 Feb 08 10:07:32 AM UTC 25 Feb 08 10:07:38 AM UTC 25 2476208091 ps
T121 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3173948645 Feb 08 10:03:57 AM UTC 25 Feb 08 10:07:39 AM UTC 25 117049581077 ps
T251 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.530123257 Feb 08 10:06:03 AM UTC 25 Feb 08 10:07:39 AM UTC 25 64539939986 ps
T252 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.2196774979 Feb 08 10:07:32 AM UTC 25 Feb 08 10:07:40 AM UTC 25 2519086507 ps
T253 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3183694524 Feb 08 10:07:36 AM UTC 25 Feb 08 10:07:40 AM UTC 25 3188591154 ps
T254 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3332238234 Feb 08 10:07:37 AM UTC 25 Feb 08 10:07:43 AM UTC 25 2953961911 ps
T255 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.2981397679 Feb 08 10:07:42 AM UTC 25 Feb 08 10:07:45 AM UTC 25 2573127617 ps
T256 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2086958578 Feb 08 10:08:23 AM UTC 25 Feb 08 10:08:36 AM UTC 25 2481650177 ps
T257 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1988418124 Feb 08 10:07:41 AM UTC 25 Feb 08 10:07:46 AM UTC 25 2021820380 ps
T100 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.948688866 Feb 08 10:06:06 AM UTC 25 Feb 08 10:07:46 AM UTC 25 38154679838 ps
T258 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3541072485 Feb 08 10:07:36 AM UTC 25 Feb 08 10:07:48 AM UTC 25 2613084907 ps
T494 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1939524043 Feb 08 10:07:44 AM UTC 25 Feb 08 10:07:49 AM UTC 25 2082545168 ps
T356 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3359749638 Feb 08 10:05:31 AM UTC 25 Feb 08 10:07:49 AM UTC 25 42015092792 ps
T163 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3312726471 Feb 08 10:07:37 AM UTC 25 Feb 08 10:07:49 AM UTC 25 4740119358 ps
T43 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.2732387895 Feb 08 10:05:04 AM UTC 25 Feb 08 10:07:50 AM UTC 25 59372623240 ps
T495 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.1241048897 Feb 08 10:07:41 AM UTC 25 Feb 08 10:07:50 AM UTC 25 2113877311 ps
T496 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3391005226 Feb 08 10:07:46 AM UTC 25 Feb 08 10:07:52 AM UTC 25 2618469453 ps
T358 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1417976486 Feb 08 10:07:47 AM UTC 25 Feb 08 10:07:52 AM UTC 25 2955645175 ps
T497 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2132646031 Feb 08 10:07:36 AM UTC 25 Feb 08 10:07:53 AM UTC 25 3277529740 ps
T91 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2910494394 Feb 08 10:06:47 AM UTC 25 Feb 08 10:07:56 AM UTC 25 92664328361 ps
T498 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.759379704 Feb 08 10:07:52 AM UTC 25 Feb 08 10:07:57 AM UTC 25 2042242562 ps
T164 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1160692505 Feb 08 10:07:49 AM UTC 25 Feb 08 10:07:57 AM UTC 25 3590843924 ps
T499 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3693273917 Feb 08 10:08:26 AM UTC 25 Feb 08 10:08:35 AM UTC 25 2618228662 ps
T370 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2111928750 Feb 08 10:07:53 AM UTC 25 Feb 08 10:07:59 AM UTC 25 2497818307 ps
T126 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1119563628 Feb 08 10:07:04 AM UTC 25 Feb 08 10:07:59 AM UTC 25 13625962434 ps
T313 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1725049963 Feb 08 10:07:47 AM UTC 25 Feb 08 10:08:00 AM UTC 25 3272279297 ps
T314 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.963160191 Feb 08 10:07:44 AM UTC 25 Feb 08 10:08:00 AM UTC 25 2509707331 ps
T315 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4090359294 Feb 08 10:07:56 AM UTC 25 Feb 08 10:08:01 AM UTC 25 2186180889 ps
T316 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.2368565440 Feb 08 10:07:52 AM UTC 25 Feb 08 10:08:03 AM UTC 25 2108878786 ps
T317 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.2141213011 Feb 08 10:07:57 AM UTC 25 Feb 08 10:08:06 AM UTC 25 2524710577 ps
T318 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.4222990453 Feb 08 10:06:28 AM UTC 25 Feb 08 10:08:06 AM UTC 25 112979823932 ps
T319 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.639866917 Feb 08 10:08:00 AM UTC 25 Feb 08 10:08:08 AM UTC 25 4429179393 ps
T218 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.3580054168 Feb 08 10:07:50 AM UTC 25 Feb 08 10:08:08 AM UTC 25 2443108272 ps
T320 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2226444330 Feb 08 10:08:31 AM UTC 25 Feb 08 10:08:42 AM UTC 25 2016660780 ps
T500 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3668942708 Feb 08 10:08:00 AM UTC 25 Feb 08 10:08:09 AM UTC 25 3478665940 ps
T501 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1887250138 Feb 08 10:07:59 AM UTC 25 Feb 08 10:08:11 AM UTC 25 2613288730 ps
T502 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2650669750 Feb 08 10:08:07 AM UTC 25 Feb 08 10:08:12 AM UTC 25 2032957868 ps
T129 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2883741994 Feb 08 10:07:17 AM UTC 25 Feb 08 10:08:13 AM UTC 25 36185842359 ps
T503 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.4063485680 Feb 08 10:08:08 AM UTC 25 Feb 08 10:08:13 AM UTC 25 2144647192 ps
T504 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3060970532 Feb 08 10:07:51 AM UTC 25 Feb 08 10:08:14 AM UTC 25 8843346352 ps
T165 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.290269412 Feb 08 10:08:00 AM UTC 25 Feb 08 10:08:14 AM UTC 25 5811168204 ps
T505 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2661287253 Feb 08 10:08:13 AM UTC 25 Feb 08 10:08:17 AM UTC 25 2660101586 ps
T371 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1298707480 Feb 08 10:08:09 AM UTC 25 Feb 08 10:08:17 AM UTC 25 2471749530 ps
T506 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.1913594800 Feb 08 10:08:11 AM UTC 25 Feb 08 10:08:18 AM UTC 25 2528872219 ps
T221 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2667389324 Feb 08 10:08:02 AM UTC 25 Feb 08 10:08:19 AM UTC 25 2728971777 ps
T374 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1952236384 Feb 08 10:08:14 AM UTC 25 Feb 08 10:08:19 AM UTC 25 4953073255 ps
T246 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.1083415271 Feb 08 10:07:40 AM UTC 25 Feb 08 10:08:23 AM UTC 25 14469678820 ps
T92 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3305109608 Feb 08 10:07:16 AM UTC 25 Feb 08 10:08:23 AM UTC 25 86534399527 ps
T507 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.4203984214 Feb 08 10:08:20 AM UTC 25 Feb 08 10:08:25 AM UTC 25 2136128289 ps
T194 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.2025696647 Feb 08 10:08:15 AM UTC 25 Feb 08 10:08:26 AM UTC 25 2452543769 ps
T508 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3767656526 Feb 08 10:08:10 AM UTC 25 Feb 08 10:08:27 AM UTC 25 2200831084 ps
T123 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2238104403 Feb 08 10:07:29 AM UTC 25 Feb 08 10:08:27 AM UTC 25 15998313063 ps
T509 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3292803692 Feb 08 10:08:23 AM UTC 25 Feb 08 10:08:29 AM UTC 25 2186255014 ps
T510 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2839725652 Feb 08 10:08:14 AM UTC 25 Feb 08 10:08:29 AM UTC 25 3154120394 ps
T474 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2828458533 Feb 08 10:07:18 AM UTC 25 Feb 08 10:08:30 AM UTC 25 21351596414 ps
T359 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2116488758 Feb 08 10:08:14 AM UTC 25 Feb 08 10:08:30 AM UTC 25 3688640487 ps
T511 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1107578484 Feb 08 10:08:19 AM UTC 25 Feb 08 10:08:30 AM UTC 25 2015003601 ps
T373 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.575310399 Feb 08 10:08:35 AM UTC 25 Feb 08 10:08:38 AM UTC 25 2589346862 ps
T360 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.2385950462 Feb 08 10:08:19 AM UTC 25 Feb 08 10:08:33 AM UTC 25 12649017075 ps
T512 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1106722092 Feb 08 10:08:27 AM UTC 25 Feb 08 10:08:33 AM UTC 25 2831715265 ps
T232 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2944947686 Feb 08 10:05:30 AM UTC 25 Feb 08 10:08:33 AM UTC 25 51776645390 ps
T372 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.449115982 Feb 08 10:08:33 AM UTC 25 Feb 08 10:08:38 AM UTC 25 2487511165 ps
T192 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.2890658889 Feb 08 10:08:30 AM UTC 25 Feb 08 10:08:42 AM UTC 25 5614599394 ps
T210 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.56316058 Feb 08 10:08:37 AM UTC 25 Feb 08 10:08:42 AM UTC 25 2636415195 ps
T211 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2057498252 Feb 08 10:08:37 AM UTC 25 Feb 08 10:08:42 AM UTC 25 3428524120 ps
T124 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3157007830 Feb 08 10:07:03 AM UTC 25 Feb 08 10:08:46 AM UTC 25 88279836928 ps
T212 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.4000120088 Feb 08 10:08:33 AM UTC 25 Feb 08 10:08:47 AM UTC 25 2109780520 ps
T44 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2336060071 Feb 08 10:08:18 AM UTC 25 Feb 08 10:08:48 AM UTC 25 32642687982 ps
T213 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1112240164 Feb 08 10:08:33 AM UTC 25 Feb 08 10:08:48 AM UTC 25 2105622822 ps
T214 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1303299981 Feb 08 10:08:37 AM UTC 25 Feb 08 10:08:49 AM UTC 25 3625786326 ps
T215 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.2629042347 Feb 08 10:08:43 AM UTC 25 Feb 08 10:08:52 AM UTC 25 4509132813 ps
T216 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3283008248 Feb 08 10:08:47 AM UTC 25 Feb 08 10:08:53 AM UTC 25 2035899284 ps
T513 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.3136125130 Feb 08 10:08:48 AM UTC 25 Feb 08 10:08:54 AM UTC 25 2483479766 ps
T514 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.877774680 Feb 08 10:08:47 AM UTC 25 Feb 08 10:08:55 AM UTC 25 2118913601 ps
T515 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1172805058 Feb 08 10:08:49 AM UTC 25 Feb 08 10:08:55 AM UTC 25 2274101590 ps
T516 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1864272625 Feb 08 10:08:27 AM UTC 25 Feb 08 10:08:56 AM UTC 25 4830489758 ps
T357 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1964462790 Feb 08 10:07:51 AM UTC 25 Feb 08 10:08:57 AM UTC 25 67314780550 ps
T383 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3492578111 Feb 08 10:08:49 AM UTC 25 Feb 08 10:08:58 AM UTC 25 2520554982 ps
T384 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2645701024 Feb 08 10:08:55 AM UTC 25 Feb 08 10:09:00 AM UTC 25 3242618870 ps
T193 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1843622759 Feb 08 10:06:51 AM UTC 25 Feb 08 10:09:01 AM UTC 25 40611053464 ps
T377 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3321111432 Feb 08 10:08:56 AM UTC 25 Feb 08 10:09:02 AM UTC 25 8102096813 ps
T385 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.4163503481 Feb 08 10:08:54 AM UTC 25 Feb 08 10:09:03 AM UTC 25 2612016014 ps
T287 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.3181597114 Feb 08 10:08:57 AM UTC 25 Feb 08 10:09:04 AM UTC 25 3039367183 ps
T386 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2912134193 Feb 08 10:09:01 AM UTC 25 Feb 08 10:09:07 AM UTC 25 2024980881 ps
T387 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3096549467 Feb 08 10:09:03 AM UTC 25 Feb 08 10:09:08 AM UTC 25 2117977149 ps
T361 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2386114106 Feb 08 10:07:37 AM UTC 25 Feb 08 10:09:11 AM UTC 25 167470045139 ps
T517 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.1927271963 Feb 08 10:09:08 AM UTC 25 Feb 08 10:09:12 AM UTC 25 2618436813 ps
T518 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3398974503 Feb 08 10:09:04 AM UTC 25 Feb 08 10:09:13 AM UTC 25 2202420014 ps
T519 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1668650806 Feb 08 10:08:54 AM UTC 25 Feb 08 10:09:13 AM UTC 25 3036846136 ps
T520 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.332416782 Feb 08 10:09:03 AM UTC 25 Feb 08 10:09:15 AM UTC 25 2463790625 ps
T521 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.4054568171 Feb 08 10:09:12 AM UTC 25 Feb 08 10:09:20 AM UTC 25 3599488963 ps
T522 /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.710130496 Feb 08 10:09:13 AM UTC 25 Feb 08 10:09:20 AM UTC 25 8514763457 ps
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