|
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4123088781 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1121364119 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1139401827 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3152207448 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.830091598 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.720398685 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.689520360 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.450938997 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3526708768 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1253571873 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1890623791 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.162139694 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.160305510 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3937575698 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.696259766 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2867245528 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.747365449 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3215877956 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2054390471 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.433250084 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1096241070 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1289726199 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1889258843 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3357230858 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1328709420 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2397958631 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.245517586 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3735075634 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1020631166 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1949517827 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.793727168 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2389659870 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1698233267 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3560568841 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1736802828 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.391028283 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2488059143 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2823049285 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.652662013 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2645993988 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1703222282 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3835642062 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3797872901 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2983516624 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.468977328 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.205705951 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2607595421 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1790433789 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1248014138 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3403319947 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328486483 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1510223317 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3662718672 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3457966260 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1871587390 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2547129671 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.806369596 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3792228863 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1035116021 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3672845249 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3051860025 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.559283376 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3458150625 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2876019993 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1959412431 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.742343330 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2514291698 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3845877068 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.462046266 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1367309972 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.556892947 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.4183987094 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.839733690 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2881950953 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1748854391 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.523979826 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098418553 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1261050613 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3609740614 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1986068011 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2663892190 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2103302152 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3416709626 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4141793862 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4234621891 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.560264378 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2914328702 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.360373605 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3538921661 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1001404393 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3191529838 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4115606518 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3062086392 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1515931126 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4187118917 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3044311819 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.4109893056 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3049595927 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2727040529 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2582644298 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1670754735 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1399631652 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.158759113 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.822684595 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2815712621 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1352980172 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1779195321 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1799131764 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2900891743 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1171476214 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3382812050 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1597588153 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1947479455 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2305914319 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1371064544 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2619863097 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.317714917 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2611452403 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3750286033 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.818974883 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1624701067 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3525070832 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3032628769 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1225725386 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1716444690 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.283030298 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2307440927 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3693646328 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2219023902 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2251686199 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.793284184 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3814064120 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3318659068 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.807389308 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3483935108 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2114517610 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3428675547 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3294070613 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.633521484 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4156843007 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3862615783 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1042193673 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3670315799 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.494234677 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2464084629 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.764376503 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3388329143 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3534191080 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2973782509 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3395936362 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2775993132 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.269003184 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1775551304 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3630742420 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3142073330 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3314990629 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.537546690 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3725275141 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1251689532 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.521601682 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2600256782 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.88756479 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.1332766611 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3173948645 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1696365099 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2073077456 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3644963231 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3661562224 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3485297655 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2785729346 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3322307893 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1889578550 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3201499473 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3117432393 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1746646007 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.3683336824 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.640603777 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1194253681 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2551132927 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.884572565 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.38330178 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1140928418 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.381506504 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2152178067 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2476283010 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.1822925926 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1310590137 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3776123180 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.4069213391 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2883741994 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3157106163 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1732587187 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2270205902 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3976745428 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1166095728 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3721487616 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.490341130 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.965934903 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3553549383 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.770895636 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2581906403 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.4073006704 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2238104403 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1988418124 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3183694524 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3156760497 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2132646031 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3332238234 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3541072485 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.4177704222 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.774873141 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.2196774979 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1534299530 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.1083415271 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2533086922 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3312726471 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.759379704 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1417976486 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2401398826 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1867529180 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1725049963 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.3580054168 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3391005226 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.2981397679 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1939524043 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.963160191 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.1241048897 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3060970532 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1160692505 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2650669750 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3668942708 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.345661609 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1101561055 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.639866917 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2667389324 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1887250138 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2111928750 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4090359294 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.2141213011 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.2368565440 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.290269412 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1107578484 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2116488758 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.3675064538 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2336060071 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2839725652 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.2025696647 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2661287253 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1298707480 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3767656526 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.1913594800 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.4063485680 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.2385950462 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1952236384 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2226444330 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1106722092 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2863610799 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2500440447 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1864272625 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3693273917 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2086958578 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3292803692 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2752806671 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.4203984214 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2815861723 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3283008248 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2057498252 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2439084649 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1303299981 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.56316058 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.449115982 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1112240164 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.575310399 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.4000120088 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1937886027 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.117024808 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2912134193 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2645701024 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.1103966322 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1668650806 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.3181597114 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.4163503481 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.3136125130 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1172805058 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3492578111 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.877774680 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2743520730 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3321111432 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2720698241 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.4054568171 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2549136417 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.66087397 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3544027090 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2551480683 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.332416782 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3398974503 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.1927271963 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3096549467 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2295637282 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.710130496 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2047161810 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3473825244 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.916383983 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1094862110 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.214085048 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1905304967 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.4178969434 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.1404920248 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2757364252 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3044083808 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.2007382248 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.1747084306 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2975539995 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.4049046532 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2746200269 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.4190433750 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2059427727 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2959649306 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.3900051661 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.579021357 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.1061312965 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.1812546434 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.4076279924 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.3120843443 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2230488820 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1488284828 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.36737296 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1092258034 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1978846015 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3390703204 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1658091942 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2771429969 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.579161467 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.196367583 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1724855628 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.924687832 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2367656960 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2612313933 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1566484161 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3619098464 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.4211500534 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1913717634 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1126459145 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.233951565 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3898216125 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1220154891 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.577975504 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3080122626 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.751610260 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.3610302612 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2618540099 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2413190772 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.3702120152 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.4192676160 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.533213704 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.422460844 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.600890602 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.3772798052 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.448853713 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.1212528661 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.446249850 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.1752560615 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3411307747 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1994672103 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3822179602 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.285400960 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1725379792 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1242478689 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.879268137 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.48228088 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.489828578 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.2668431925 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3237641569 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.476523137 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.704654272 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.4216589438 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2029281016 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1651060357 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3162261919 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3605437917 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.2495919529 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.320294091 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3815549915 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.401134980 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4133768487 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1166872180 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3748408368 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4064830166 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3539676231 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2453065608 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2360403587 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.402715522 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4168390404 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1982040996 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1693176164 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1899017962 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4033607239 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.20998901 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3940834165 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2266524303 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.399610489 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1647037214 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2124718456 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1998775318 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2149022556 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2116946852 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.2389393336 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1090702465 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.345904183 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.506863268 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.364966847 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.920606441 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.2398735125 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2835689755 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3051551281 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.11601288 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.457942829 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2888824102 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2600825762 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3386563513 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.810859486 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.1526359951 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3152076410 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.585172047 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.361547423 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3720636564 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1945416413 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2006057288 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3564088267 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1537769987 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.874853700 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1503719203 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1499996445 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1566268532 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.261267574 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.2146648725 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3238455264 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2614625051 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.911191085 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3358897539 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1358658473 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.881592638 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3781881439 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.2732387895 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.173759483 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2471347680 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3180684791 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.349453619 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1720818392 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3004509989 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.1138418049 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1773919646 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3837908386 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.254135538 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.2812614593 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3928001080 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.887546292 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.2774668247 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.4155929538 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1158480118 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.2943140654 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3475862989 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1166547564 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.613964180 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.697460875 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.495733538 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1731640921 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1521918057 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.531026256 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3669551316 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2282987385 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1283851699 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.202265181 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.783755480 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2902208333 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3386663835 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1502299807 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1879462164 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.607069501 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.204748412 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2369061665 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3503185190 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.220435998 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.2457983488 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.44251706 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.3226049816 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.579224180 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1713469382 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.97943629 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3472404751 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2602561532 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2036055191 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2140799564 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3328585123 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.4135713105 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2660272643 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.163872211 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.1033120751 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1522486849 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1685871034 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1200701670 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.2942641832 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1920201161 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.2404514861 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.248529203 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.725160209 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.850087366 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3410997253 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2147302025 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2821443045 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1515795761 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.591895351 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1346181519 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2561158658 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.4294197035 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3208632711 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.868750970 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.844637016 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3308044449 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.1630706215 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3462164367 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1305383036 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1339908537 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.629858128 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1226592694 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.630024031 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.4044537976 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3894784702 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2111182076 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3192143002 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.568868015 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.264835964 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.4283195214 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.4234799282 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.813546451 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2622494011 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.149079156 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2990027439 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3887101619 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.2682265784 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2901788275 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3692627171 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.673937490 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1646412412 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3260968360 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.674546117 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.629242584 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1932246121 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.3761767308 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3048470299 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2726367570 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.737363326 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.1150225298 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4264533188 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3088765035 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.793697435 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2411326836 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1265143502 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.372801668 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.365879344 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1603400618 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2757431536 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.884745956 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4257279206 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3746294507 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2324696026 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.435356167 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3883899691 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.773132793 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.3708001819 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1777417000 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3514454396 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3192673108 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1817754325 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.1106495323 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.1101138658 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.4166463798 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3373876246 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2366705896 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1664062870 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2278263916 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.4193235345 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3992299416 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.286388898 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3581930171 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3541391496 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.3438236517 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.251071730 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2844955033 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.3340142604 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1229529253 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2268953705 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.1686114155 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.884645167 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3708650072 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4243572487 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2894833465 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2277164549 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1103099880 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.72493382 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.4253045439 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.2888235244 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2115716452 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3359749638 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1965138751 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2944947686 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3591593627 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2897550048 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3190321470 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3611722033 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4048022059 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1081228422 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2490057231 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3284964121 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2031057218 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.736036829 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.3824040697 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2164122870 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3454383236 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.820134571 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.619030264 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1250986 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2551141865 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.3914311365 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3516104544 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1419436703 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.3475788601 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.3069145764 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3494390751 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3092020102 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1497688627 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3236292540 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1821456471 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3974014080 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.537970931 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1578366585 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1824315366 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2057332375 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1003465603 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1289145451 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.1143138029 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2598499106 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3644048641 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.97700810 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3673768102 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.435343914 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1648953917 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1366705731 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3792501214 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.886790721 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3419681649 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.692676442 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3799626356 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.1875559509 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.80824953 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1814197100 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.587844755 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4005074822 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3271449763 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.843576764 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1445137796 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.1722729801 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.86456662 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.228213993 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2834904296 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3023320456 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.1001007873 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.1199143875 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2901504593 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.3358223398 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4012902746 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.836969184 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3247755709 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1099999905 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2970722514 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3857311921 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.447020963 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2853847285 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.316374635 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2756973413 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.3306371506 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4033308032 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.388200823 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3677402385 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3024131115 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.668186974 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1739091644 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2358122183 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.648341723 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1671649957 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1052624772 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.749998224 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1460671110 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.3090695404 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.1553525846 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1980825660 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3680619428 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.299492960 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2783907772 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.581427157 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3235710964 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2166045690 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1458051177 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3764857959 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.631658526 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.701284035 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.3241546255 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3893234032 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1837036370 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1471176821 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3392498913 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1660995163 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2288773621 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3945910844 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4015976664 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3158227971 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.1648898031 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2489892767 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3688293263 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4041210833 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3388559013 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2414549229 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.428501936 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.874713478 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4013996363 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2366305628 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2069835774 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2602481591 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3845079203 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1783938885 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3284974041 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.990473578 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3525906550 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.1573744763 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.2407694440 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2691193915 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2640798648 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.33715971 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2277527385 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.872878066 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2792859780 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2179412647 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2261499749 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3923952611 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.7707735 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2728880660 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3491608673 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2794802972 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2561298049 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1460450821 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3722897264 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1992069803 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3815606940 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2602061061 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3588530917 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2740251937 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.219388431 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2041518442 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3975193265 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2486377155 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.530123257 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3781209354 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2303706774 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.107246871 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.855892837 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.4245523757 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.530701657 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.1958919982 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.4109232442 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.728271915 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1142055358 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2816374092 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.699429591 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2888057335 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.614130733 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1715304222 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3055934058 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1535235405 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2983444448 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.2218408203 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.778679471 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.4222990453 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.221609788 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3632467930 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.267686389 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.933692812 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.449416124 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2037266785 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.2714051619 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.199060412 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.444431553 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3277494576 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1518430709 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3687466809 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3568156759 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1204496928 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2136463937 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1863744077 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1199821914 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3395989364 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3503387715 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2441868319 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.925175164 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2910494394 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1575631372 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.4160361011 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.252921031 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.98105896 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.3341442151 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1644822976 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.116444968 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2197714748 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1843622759 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2261889761 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3976058015 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3513489044 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3689215284 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1388692577 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1140644811 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2115860633 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.43747656 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.848084338 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.280847798 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.596181375 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3755508054 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.4005860126 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3157007830 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1758892522 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.166450791 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.822832151 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2534673429 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.148034507 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1766471768 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2393031786 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1119563628 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2620297909 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3010012028 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.249115518 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1892736564 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3991176906 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2380482967 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.978067839 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2614965513 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.829657751 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.48313100 |