Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 95.43 98.12 90.45 100.00 88.64 97.21 98.14
dut 95.43 98.12 90.45 100.00 88.64 97.21 98.14
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_intr_hw 100.00 100.00 100.00
u_prim_sync_reqack 100.00 100.00 100.00 100.00
ack_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
req_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg 97.64 99.33 91.49 100.00 98.25 99.15
subtree...
u_sysrst_ctrl_autoblock 96.61 96.00 90.91 100.00 96.15 100.00
u_sysrst_ctrl_detect 95.63 95.65 87.50 100.00 95.00 100.00
u_sysrst_ctrl_combo 96.77 97.32 90.00 100.00 96.55 100.00
gen_combo_trigger[0].u_combo_act 97.62 100.00 92.86 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 95.68 95.65 87.50 100.00 95.24 100.00
gen_combo_trigger[1].u_combo_act 97.62 100.00 92.86 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 95.68 95.65 87.50 100.00 95.24 100.00
gen_combo_trigger[2].u_combo_act 97.62 100.00 92.86 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 95.68 95.65 87.50 100.00 95.24 100.00
gen_combo_trigger[3].u_combo_act 97.62 100.00 92.86 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 95.68 95.65 87.50 100.00 95.24 100.00
u_sysrst_ctrl_keyintr 87.95 91.38 81.50 83.33 90.00 93.55
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 87.93 91.30 81.25 83.33 90.00 93.75
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 87.84 91.30 81.25 83.33 90.00 93.33
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 87.93 91.30 81.25 83.33 90.00 93.75
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 87.84 91.30 81.25 83.33 90.00 93.33
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 87.93 91.30 81.25 83.33 90.00 93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 87.84 91.30 81.25 83.33 90.00 93.33
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 87.93 91.30 81.25 83.33 90.00 93.75
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 87.84 91.30 81.25 83.33 90.00 93.33
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 87.93 91.30 81.25 83.33 90.00 93.75
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 87.84 91.30 81.25 83.33 90.00 93.33
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 87.93 91.30 81.25 83.33 90.00 93.75
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 87.84 91.30 81.25 83.33 90.00 93.33
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 87.93 91.30 81.25 83.33 90.00 93.75
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 87.84 91.30 81.25 83.33 90.00 93.33
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_cfg_ac_present_i_pin 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_ulp 93.87 94.20 89.74 94.44 93.10 97.87
u_sysrst_ctrl_detect_ac_present 96.42 95.35 92.31 100.00 94.44 100.00
u_sysrst_ctrl_detect_lid_open 96.59 95.65 92.31 100.00 95.00 100.00
u_sysrst_ctrl_detect_pwrb 88.60 91.30 84.62 83.33 90.00 93.75
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%