| | | | | | | |
tb |
86.44 |
93.70 |
91.26 |
100.00 |
51.28 |
93.56 |
88.86 |
dut |
86.44 |
93.70 |
91.26 |
100.00 |
51.28 |
93.56 |
88.86 |
gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
sysrst_ctrl_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_prim_flop_2sync_input |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_prim_sync_reqack |
87.50 |
100.00 |
50.00 |
|
|
100.00 |
100.00 |
gen_nrz_hs_protocol.ack_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_nrz_hs_protocol.req_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_reg |
98.62 |
99.17 |
95.24 |
100.00 |
|
98.71 |
100.00 |
subtree... |
|
|
|
|
|
|
|
u_sysrst_ctrl_autoblock |
97.32 |
96.00 |
94.44 |
|
100.00 |
96.15 |
100.00 |
u_sysrst_ctrl_detect |
96.23 |
95.65 |
90.48 |
|
100.00 |
95.00 |
100.00 |
u_sysrst_ctrl_combo |
64.71 |
67.63 |
73.40 |
|
50.00 |
68.00 |
64.52 |
gen_combo_trigger[0].u_combo_act |
99.19 |
100.00 |
97.56 |
|
|
100.00 |
|
gen_combo_trigger[0].u_sysrst_ctrl_detect |
96.27 |
95.65 |
90.48 |
|
100.00 |
95.24 |
100.00 |
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre |
19.90 |
18.60 |
21.05 |
|
0.00 |
28.57 |
31.25 |
gen_combo_trigger[1].u_combo_act |
99.19 |
100.00 |
97.56 |
|
|
100.00 |
|
gen_combo_trigger[1].u_sysrst_ctrl_detect |
96.27 |
95.65 |
90.48 |
|
100.00 |
95.24 |
100.00 |
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre |
19.90 |
18.60 |
21.05 |
|
0.00 |
28.57 |
31.25 |
gen_combo_trigger[2].u_combo_act |
99.19 |
100.00 |
97.56 |
|
|
100.00 |
|
gen_combo_trigger[2].u_sysrst_ctrl_detect |
96.27 |
95.65 |
90.48 |
|
100.00 |
95.24 |
100.00 |
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre |
19.90 |
18.60 |
21.05 |
|
0.00 |
28.57 |
31.25 |
gen_combo_trigger[3].u_combo_act |
99.19 |
100.00 |
97.56 |
|
|
100.00 |
|
gen_combo_trigger[3].u_sysrst_ctrl_detect |
96.27 |
95.65 |
90.48 |
|
100.00 |
95.24 |
100.00 |
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre |
19.90 |
18.60 |
21.05 |
|
0.00 |
28.57 |
31.25 |
u_sysrst_ctrl_keyintr |
62.09 |
73.38 |
65.32 |
|
38.10 |
68.21 |
65.44 |
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l |
76.13 |
86.96 |
76.19 |
|
50.00 |
80.00 |
87.50 |
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h |
31.04 |
45.65 |
42.86 |
|
0.00 |
40.00 |
26.67 |
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l |
80.90 |
89.13 |
76.19 |
|
66.67 |
85.00 |
87.50 |
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h |
31.04 |
45.65 |
42.86 |
|
0.00 |
40.00 |
26.67 |
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l |
31.00 |
45.65 |
38.10 |
|
0.00 |
40.00 |
31.25 |
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h |
65.55 |
76.09 |
66.67 |
|
50.00 |
75.00 |
60.00 |
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l |
31.95 |
45.65 |
42.86 |
|
0.00 |
40.00 |
31.25 |
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h |
75.96 |
86.96 |
76.19 |
|
50.00 |
80.00 |
86.67 |
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l |
76.13 |
86.96 |
76.19 |
|
50.00 |
80.00 |
87.50 |
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h |
65.55 |
76.09 |
66.67 |
|
50.00 |
75.00 |
60.00 |
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l |
76.13 |
86.96 |
76.19 |
|
50.00 |
80.00 |
87.50 |
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h |
65.55 |
76.09 |
66.67 |
|
50.00 |
75.00 |
60.00 |
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l |
76.13 |
86.96 |
76.19 |
|
50.00 |
80.00 |
87.50 |
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h |
83.97 |
89.13 |
85.71 |
|
66.67 |
85.00 |
93.33 |
u_sysrst_ctrl_pin |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_ac_present_i_pin |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sysrst_ctrl_ulp |
97.71 |
97.10 |
94.92 |
|
100.00 |
96.55 |
100.00 |
u_sysrst_ctrl_detect_ac_present |
96.63 |
95.35 |
93.33 |
|
100.00 |
94.44 |
100.00 |
u_sysrst_ctrl_detect_lid_open |
97.02 |
95.65 |
94.44 |
|
100.00 |
95.00 |
100.00 |
u_sysrst_ctrl_detect_pwrb |
98.89 |
100.00 |
94.44 |
|
100.00 |
100.00 |
100.00 |