Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 99.09 99.18 96.99 100.00 100.00 98.67 99.71
dut 99.09 99.18 96.99 100.00 100.00 98.67 99.71
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg 99.07 99.38 97.02 100.00 98.94 100.00
subtree...
u_sysrst_ctrl_autoblock 99.44 100.00 97.22 100.00 100.00 100.00
u_sysrst_ctrl_detect 99.05 100.00 95.24 100.00 100.00 100.00
u_sysrst_ctrl_combo 99.01 100.00 97.07 100.00 98.00 100.00
gen_combo_trigger[0].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 99.05 100.00 95.24 100.00 100.00 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
gen_combo_trigger[1].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
gen_combo_trigger[2].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 99.05 100.00 95.24 100.00 100.00 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
gen_combo_trigger[3].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 99.05 100.00 95.24 100.00 100.00 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
u_sysrst_ctrl_intr 96.25 100.00 85.00 100.00 100.00
u_match_sync 87.50 100.00 50.00 100.00 100.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_intr_o 100.00 100.00 100.00 100.00 100.00
u_sysrst_ctrl_keyintr 97.78 96.91 96.94 100.00 96.43 98.62
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 99.05 100.00 95.24 100.00 100.00 100.00
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 98.13 95.65 100.00 100.00 95.00 100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 98.13 95.65 100.00 100.00 95.00 100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 95.84 95.65 95.24 100.00 95.00 93.33
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 95.93 95.65 95.24 100.00 95.00 93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 98.13 95.65 100.00 100.00 95.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 98.13 95.65 100.00 100.00 95.00 100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 98.13 95.65 100.00 100.00 95.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 99.05 100.00 95.24 100.00 100.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 99.05 100.00 95.24 100.00 100.00 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 95.93 95.65 95.24 100.00 95.00 93.75
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 99.05 100.00 95.24 100.00 100.00 100.00
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_cfg_ac_present_i_pin 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_ulp 98.98 100.00 94.92 100.00 100.00 100.00
u_sysrst_ctrl_detect_ac_present 98.67 100.00 93.33 100.00 100.00 100.00
u_sysrst_ctrl_detect_lid_open 98.89 100.00 94.44 100.00 100.00 100.00
u_sysrst_ctrl_detect_pwrb 98.89 100.00 94.44 100.00 100.00 100.00
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