Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 99.58 90.77 100.00 100.00 96.05 100.00


Total modules in report: 38
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_reg_cdc_arb 88.13 100.00 68.75 95.65
prim_reg_cdc_arb 82.20 68.75 95.65
prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 ) 100.00 100.00
prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=15,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 ) 100.00 100.00
prim_pulse_sync 91.67 100.00 66.67 100.00 100.00
sysrst_ctrl_detect 92.62 95.69 83.47 100.00 83.95 100.00
sysrst_ctrl_detect 100.00 100.00 100.00
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 ) 88.25 95.56 80.95
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 ) 95.83 95.83
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 ) 86.96 86.96
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 ) 82.35 82.35
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 ) 85.71 85.71
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 ) 82.35 82.35
prim_sync_reqack 95.24 100.00 85.71 100.00
prim_subreg_arb 96.30 88.89 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 + DW=16,SwAccess=0 + DW=32,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1 ) 66.67 66.67
prim_subreg_arb ( parameter DW=1,SwAccess=3 ) 100.00 100.00
prim_subreg_arb ( parameter DW=16,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0 ) 100.00 100.00
prim_onehot_check 96.65 100.00 89.94 100.00
prim_reg_cdc 96.67 100.00 86.67 100.00 100.00
sysrst_ctrl_comboact 97.62 100.00 92.86 100.00
sysrst_ctrl_csr_assert_fpv 100.00 100.00
tlul_data_integ_dec 100.00 100.00
sysrst_ctrl_combo 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
sysrst_ctrl_ulp 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_rsp_intg_gen 100.00 100.00 100.00
sysrst_ctrl_keyintr 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0 + DW=1,SwAccess=0,RESVAL + DW=1,SwAccess=5,RESVAL=1 + DW=1,SwAccess=1,RESVAL=0 ) 100.00 100.00
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL ) 100.00 100.00
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0 ) 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00
sysrst_ctrl_reg_top 100.00 100.00 100.00 100.00 100.00
tlul_adapter_reg 100.00 100.00 100.00 100.00 100.00
sysrst_ctrl 100.00 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
sysrst_ctrl_pin 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
sysrst_ctrl_autoblock 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_flop
prim_flop_2sync
tb
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