Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
1669 2726 61.23 1669 2726 61.23 1


Total groups in report: 22
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
sysrst_ctrl_env_pkg::sysrst_ctrl_combo_intr_status_obj::sysrst_ctrl_combo_intr_status_cg 155 404 38.37 38.37 1 100 1 1 64 64
sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg 19 33 57.58 57.58 1 100 1 1 64 64
sysrst_ctrl_env_pkg::sysrst_ctrl_combo_detect_action_obj::sysrst_ctrl_combo_detect_action_cg 201 270 74.44 35.28 1 100 1 1 64 64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 12 15 80.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 13 14 92.86 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0} 9 9 100.00 1 100 1 0 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0} 9 9 100.00 1 100 1 0 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0} 13 13 100.00 1 100 1 0 64 64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg 2 2 100.00 100.00 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_auto_block_debounce_ctl_cg 5 5 100.00 100.00 1 100 1 1 64 64
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_detect_det_cg 3 3 100.00 100.00 1 100 1 1 64 64
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg 28 28 100.00 100.00 1 100 1 1 64 64
tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg 16 16 100.00 100.00 1 100 1 1 64 64
sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg 24 24 100.00 95.83 1 100 1 1 64 64
sysrst_ctrl_env_pkg::sysrst_ctrl_debounce_timer_obj::debounce_timer_cg 3 3 100.00 100.00 1 100 1 1 64 64
sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg 92 92 100.00 80.00 1 100 1 1 64 64
sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg 24 24 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%