Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1232

1

T20

11

T32

10

T42

2

auto[1]

1758

1

T20

2

T32

13

T42

13

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2531

1

T20

13

T32

20

T42

15

auto[1]

459

1

T32

3

T92

3

T40

4

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2833

1

T20

12

T32

20

T42

15

auto[1]

157

1

T20

1

T32

3

T39

10

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2841

1

T20

13

T32

23

T42

15

auto[1]

149

1

T40

2

T39

10

T41

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2846

1

T20

13

T32

23

T42

13

auto[1]

144

1

T42

2

T43

6

T44

7

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1954

1

T20

13

T32

23

T42

15

auto[1]

1036

1

T92

10

T40

20

T43

29

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1271

1

T20

2

T32

11

T42

2

auto[1]

1719

1

T20

11

T32

12

T42

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1229

1

T20

1

T32

9

T42

15

auto[1]

1761

1

T20

12

T32

14

T92

12

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1238

1

T20

2

T32

8

T42

3

auto[1]

1752

1

T20

11

T32

15

T42

12

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1220

1

T20

3

T32

9

T42

1

auto[1]

1770

1

T20

10

T32

14

T42

14

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

46

1

T39

1

T95

1

T236

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T329

1

T330

2

T254

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T32

1

T41

1

T235

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T44

1

T251

1

T225

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T32

2

T41

1

T235

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T40

1

T104

1

T329

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T39

2

T234

1

T236

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T40

2

T251

1

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T43

1

T236

1

T252

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T44

1

T251

1

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T40

1

T235

1

T251

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T40

1

T43

1

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T32

1

T129

1

T222

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T44

1

T113

1

T331

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T42

2

T235

1

T234

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T40

2

T251

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T92

1

T95

2

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T40

1

T104

1

T111

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T20

1

T39

1

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T251

1

T330

1

T113

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T39

1

T235

1

T236

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T43

1

T251

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T32

1

T39

1

T235

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T40

1

T44

2

T104

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T39

1

T234

2

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T44

1

T111

2

T255

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T32

1

T92

1

T41

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T41

3

T232

1

T329

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

64

1

T20

1

T32

1

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T40

1

T44

2

T255

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

68

1

T32

1

T236

1

T233

15

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

63

1

T44

1

T111

1

T129

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T42

1

T44

1

T236

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T251

1

T329

1

T330

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T234

1

T237

1

T261

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T251

1

T329

1

T253

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T32

1

T42

1

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T44

1

T251

2

T113

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T42

1

T234

1

T236

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T111

1

T330

1

T332

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T20

1

T92

1

T235

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T43

1

T104

1

T111

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T32

2

T235

1

T236

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T40

1

T44

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T235

1

T133

1

T237

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T40

1

T104

1

T251

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

73

1

T32

1

T42

10

T39

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

40

1

T111

2

T224

7

T254

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T32

1

T232

1

T133

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T40

2

T104

1

T111

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

28

1

T20

1

T236

1

T252

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T43

1

T104

1

T111

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T41

1

T234

1

T236

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T92

3

T40

2

T43

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T32

1

T234

1

T236

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

48

1

T104

2

T251

1

T225

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T32

1

T235

1

T223

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T254

1

T113

1

T333

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T32

1

T235

1

T112

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

57

1

T92

4

T40

1

T232

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

99

1

T20

9

T32

1

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

55

1

T223

9

T111

1

T334

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

237

1

T32

3

T40

2

T43

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T43

2

T251

1

T330

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T263

1

T335

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T253

1

T255

1

T256

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T251

1

T336

1

T337

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T104

1

T329

1

T253

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T44

2

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T43

1

T254

1

T338

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T104

2

T339

1

T331

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T340

1

T336

2

T337

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T92

2

T43

1

T41

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T43

2

T104

1

T330

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T104

1

T240

1

T341

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T232

2

T342

1

T331

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T104

1

T332

1

T343

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T43

1

T340

1

T336

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T251

1

T330

1

T262

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T329

1

T113

1

T344

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T43

1

T44

1

T329

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T43

1

T263

2

T337

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T40

1

T43

1

T44

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T44

1

T329

1

T330

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T263

1

T339

1

T345

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T254

1

T339

1

T264

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T43

2

T104

1

T224

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T262

1

T346

3

T263

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T40

1

T225

1

T330

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T329

1

T330

1

T263

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T43

1

T251

1

T331

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T44

1

T225

2

T340

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T104

1

T339

1

T347

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T92

1

T263

1

T348

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T40

1

T44

2

T349

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

105

1

T40

1

T43

11

T104

1

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T39

2

T95

1

T236

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T329

1

T330

2

T254

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T32

1

T41

1

T235

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T44

1

T251

1

T225

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T32

2

T39

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T40

1

T104

1

T251

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T39

2

T234

1

T236

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T40

2

T104

1

T251

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T43

1

T236

1

T252

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T44

3

T251

1

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T32

1

T40

1

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T40

1

T43

2

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T32

1

T129

1

T135

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T44

1

T104

2

T113

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T42

2

T39

1

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T40

2

T251

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T32

1

T92

1

T95

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T92

2

T40

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T20

1

T39

1

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T43

2

T104

1

T251

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T39

1

T235

1

T236

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T43

1

T104

1

T251

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T32

1

T39

3

T235

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

42

1

T40

1

T44

2

T104

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T39

1

T234

2

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T44

1

T104

1

T111

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

56

1

T32

1

T92

1

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T43

1

T41

3

T232

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

71

1

T20

1

T32

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T40

1

T44

2

T251

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

60

1

T32

1

T236

1

T233

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

72

1

T44

1

T111

1

T129

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T42

1

T39

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T43

1

T44

1

T251

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T234

1

T237

1

T261

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T43

1

T251

1

T329

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T32

1

T42

1

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T40

1

T43

1

T44

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T42

1

T234

1

T236

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T44

1

T111

1

T329

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T20

1

T92

1

T235

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T43

1

T104

1

T111

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T32

2

T235

1

T236

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34

1

T40

1

T44

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T235

1

T236

1

T133

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T40

1

T43

2

T104

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

74

1

T32

1

T42

10

T39

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

48

1

T111

2

T224

7

T254

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T32

1

T232

1

T133

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T40

3

T104

1

T111

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T236

1

T252

2

T135

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T43

1

T104

1

T111

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T41

1

T234

1

T236

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T92

3

T40

2

T43

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T32

1

T235

1

T234

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

56

1

T44

1

T104

2

T251

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T32

1

T39

1

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T104

1

T254

1

T113

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

78

1

T32

1

T235

1

T112

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

64

1

T92

5

T40

1

T232

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

99

1

T20

9

T32

1

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

61

1

T40

1

T44

2

T223

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

151

1

T40

2

T43

3

T235

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

106

1

T40

1

T43

13

T104

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T350

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T351

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T329

1

T254

1

T255

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T39

2

T95

1

T236

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T329

1

T330

2

T254

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T32

1

T41

1

T235

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T44

1

T251

1

T225

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T32

2

T39

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T40

1

T104

1

T251

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T39

2

T234

1

T236

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T40

2

T104

1

T251

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T43

1

T236

1

T252

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T44

3

T251

1

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T32

1

T40

1

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T40

1

T43

2

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T32

1

T129

1

T135

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T44

1

T104

2

T113

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T42

2

T39

1

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T40

2

T251

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T32

1

T92

1

T95

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T92

2

T40

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T20

1

T39

1

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T43

2

T104

1

T251

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T39

1

T235

1

T236

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T43

1

T104

1

T251

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T32

1

T39

3

T235

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T40

1

T44

2

T104

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T39

1

T234

2

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T44

1

T104

1

T111

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T32

1

T92

1

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T43

1

T41

3

T232

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

74

1

T20

1

T32

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T40

1

T44

2

T251

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

70

1

T32

1

T236

1

T233

15

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

72

1

T44

1

T111

1

T129

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T42

1

T39

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T43

1

T44

1

T251

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T234

1

T237

1

T261

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T43

1

T251

1

T329

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T32

1

T42

1

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T40

1

T43

1

T44

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T42

1

T234

1

T236

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T44

1

T111

1

T329

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T20

1

T92

1

T235

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T43

1

T104

1

T111

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

58

1

T32

2

T235

1

T236

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34

1

T40

1

T44

1

T104

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T235

1

T236

1

T133

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T40

1

T43

2

T104

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

71

1

T32

1

T42

10

T39

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

48

1

T111

2

T224

7

T254

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T32

1

T232

1

T133

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T40

3

T104

1

T111

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T20

1

T236

1

T252

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T43

1

T104

1

T111

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T234

1

T236

1

T133

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T92

3

T40

2

T43

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T32

1

T235

1

T234

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

56

1

T44

1

T104

2

T251

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T32

1

T39

1

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T104

1

T254

1

T113

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

76

1

T32

1

T235

1

T112

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

64

1

T92

5

T40

1

T232

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

92

1

T20

9

T32

1

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

61

1

T40

1

T44

2

T223

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

153

1

T32

3

T43

3

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

107

1

T40

1

T43

13

T104

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T41

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T352

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T351

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T329

1

T263

1

T353

1

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded