Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1376

1

T6

8

T11

4

T32

6

auto[1]

1810

1

T6

20

T11

28

T32

8

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2734

1

T6

20

T11

32

T32

11

auto[1]

452

1

T6

8

T32

3

T40

5

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3016

1

T6

20

T11

32

T32

14

auto[1]

170

1

T6

8

T40

3

T41

4

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3013

1

T6

28

T11

21

T32

10

auto[1]

173

1

T11

11

T32

4

T30

1

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3033

1

T6

28

T11

32

T32

14

auto[1]

153

1

T42

3

T43

4

T44

4

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2187

1

T6

28

T11

23

T32

14

auto[1]

999

1

T11

9

T30

9

T40

14

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1364

1

T6

9

T11

32

T32

8

auto[1]

1822

1

T6

19

T32

6

T40

16

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1320

1

T6

9

T11

32

T32

6

auto[1]

1866

1

T6

19

T32

8

T30

10

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1455

1

T6

9

T11

3

T32

6

auto[1]

1731

1

T6

19

T11

29

T32

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1362

1

T6

11

T11

5

T32

7

auto[1]

1824

1

T6

17

T11

27

T32

7

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

73

1

T32

1

T40

1

T174

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T42

3

T185

1

T136

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T6

1

T30

1

T40

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T42

1

T136

1

T140

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T11

1

T32

1

T88

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T42

1

T140

2

T407

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T11

2

T174

1

T251

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T41

1

T92

1

T361

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T11

1

T121

1

T251

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T43

1

T361

1

T185

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T6

1

T11

4

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T41

1

T185

2

T407

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T11

2

T40

1

T88

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T43

2

T185

1

T136

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T11

13

T30

1

T40

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32

1

T11

9

T40

4

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T40

1

T174

1

T121

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T41

1

T136

2

T140

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T174

2

T178

1

T121

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T41

1

T185

1

T136

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T6

1

T174

1

T121

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T361

2

T136

2

T274

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T6

1

T174

2

T178

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T42

1

T185

1

T140

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T32

1

T88

1

T174

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T43

1

T136

3

T407

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T318

1

T352

1

T139

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T41

1

T43

1

T136

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T32

1

T40

1

T88

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T42

4

T41

1

T124

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

79

1

T6

2

T30

1

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

53

1

T30

9

T42

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T6

1

T32

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T41

1

T43

1

T185

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T6

1

T40

1

T251

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T274

3

T333

1

T408

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T40

1

T251

1

T124

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T43

1

T140

1

T409

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

75

1

T40

1

T178

2

T121

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T40

2

T185

1

T140

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T88

2

T174

2

T121

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T42

1

T41

2

T136

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T174

2

T121

1

T328

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T185

1

T410

1

T140

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T178

1

T121

1

T251

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

29

1

T42

1

T185

1

T411

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39

1

T6

1

T251

1

T137

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T43

1

T361

1

T140

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

64

1

T32

1

T88

2

T174

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T42

1

T41

1

T43

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T6

1

T174

1

T251

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T92

1

T136

3

T140

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T88

1

T174

2

T178

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T407

1

T301

1

T367

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

111

1

T40

3

T42

1

T121

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

62

1

T40

3

T43

1

T92

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T6

1

T88

1

T251

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T42

1

T41

2

T361

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

75

1

T178

2

T318

1

T362

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

51

1

T41

1

T92

2

T361

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

67

1

T6

1

T88

14

T178

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T41

1

T43

1

T124

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

251

1

T6

8

T32

4

T42

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T185

1

T140

2

T407

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T334

1

T412

1

T108

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T361

1

T331

1

T333

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T410

1

T413

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T41

1

T297

1

T334

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T361

1

T333

1

T414

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T297

1

T332

1

T415

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T361

2

T334

1

T414

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T185

1

T301

1

T334

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T136

1

T410

1

T331

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T43

1

T297

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T361

1

T185

1

T410

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T301

1

T416

1

T417

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T334

1

T414

2

T418

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T361

1

T416

1

T419

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T410

1

T420

1

T409

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T43

1

T361

1

T410

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T361

1

T185

1

T297

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T361

1

T410

1

T332

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T361

1

T274

2

T333

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T40

3

T361

1

T410

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T42

1

T41

1

T410

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T410

1

T412

1

T414

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T41

1

T301

1

T367

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T185

1

T333

1

T421

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T422

1

T418

2

T423

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T42

1

T333

1

T334

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T274

1

T334

1

T412

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T40

2

T41

1

T361

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T43

1

T410

1

T424

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T42

1

T43

1

T92

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T124

4

T333

1

T334

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

98

1

T43

3

T361

4

T185

2

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T32

1

T40

1

T174

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T42

3

T185

1

T136

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T6

1

T30

1

T40

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T42

1

T361

1

T136

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T6

1

T11

1

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T42

1

T410

1

T140

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T11

2

T32

1

T174

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T41

2

T92

1

T361

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T11

1

T121

1

T251

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T43

1

T361

2

T185

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T6

2

T11

4

T32

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T41

1

T185

2

T407

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T11

2

T40

1

T88

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T43

2

T361

2

T185

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T11

13

T30

1

T40

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

39

1

T11

9

T40

4

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T40

1

T174

1

T121

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T41

1

T136

3

T410

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T32

1

T174

2

T178

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T41

1

T43

1

T185

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T6

1

T174

1

T121

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T361

3

T185

1

T136

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T6

1

T174

2

T178

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T42

1

T185

1

T140

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T32

1

T88

1

T174

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T43

1

T136

3

T407

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T318

1

T352

1

T139

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T41

1

T43

1

T361

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T6

1

T32

1

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T42

4

T41

1

T124

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

78

1

T6

2

T30

1

T178

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

62

1

T30

9

T42

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

64

1

T6

1

T32

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T41

1

T43

1

T361

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T6

1

T40

1

T251

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T361

1

T410

1

T274

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T40

1

T251

1

T124

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T43

1

T361

1

T140

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T40

1

T178

2

T121

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T40

5

T361

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

66

1

T6

1

T88

2

T174

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T42

2

T41

3

T136

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T6

1

T174

2

T121

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T185

1

T410

2

T140

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T178

1

T121

1

T251

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T42

1

T41

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T6

1

T251

1

T137

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T43

1

T361

1

T185

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T32

1

T88

1

T174

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T42

1

T41

1

T43

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T6

2

T174

1

T251

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T42

1

T92

1

T136

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

69

1

T6

1

T88

1

T174

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T407

1

T274

1

T301

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

111

1

T40

3

T42

1

T121

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

74

1

T40

5

T41

1

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T6

1

T88

1

T251

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T42

1

T41

2

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

80

1

T6

1

T178

2

T318

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T42

1

T41

1

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T6

1

T88

9

T178

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T41

1

T43

1

T124

11

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

168

1

T32

4

T42

3

T178

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

95

1

T43

3

T361

2

T185

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T419

1

T425

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T361

2

T274

2

T414

7

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T32

1

T40

1

T174

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T42

3

T185

1

T136

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T6

1

T30

1

T40

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T42

1

T361

1

T136

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T6

1

T11

1

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T42

1

T410

1

T140

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T11

2

T32

1

T174

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T41

2

T92

1

T361

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T11

1

T121

1

T251

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T43

1

T361

2

T185

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T6

2

T11

4

T32

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T41

1

T185

2

T407

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T11

2

T40

1

T88

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T43

2

T361

2

T185

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

66

1

T11

2

T30

1

T40

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

39

1

T11

9

T40

4

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T40

1

T174

1

T121

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T41

1

T136

3

T410

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T32

1

T174

2

T178

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T41

1

T43

1

T185

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T6

1

T174

1

T121

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T361

3

T185

1

T136

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T6

1

T174

2

T178

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T42

1

T185

1

T140

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T32

1

T88

1

T174

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T43

1

T136

3

T407

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T318

1

T352

1

T139

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T41

1

T43

1

T361

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T6

1

T32

1

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T42

4

T41

1

T124

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

80

1

T6

2

T40

1

T178

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

62

1

T30

9

T42

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

65

1

T6

1

T32

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T41

1

T43

1

T361

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

66

1

T6

1

T40

1

T251

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T361

1

T410

1

T274

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T40

1

T251

1

T124

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T43

1

T361

1

T140

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

77

1

T40

1

T178

2

T121

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T40

5

T361

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T6

1

T88

2

T174

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T42

2

T41

3

T136

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T6

1

T174

2

T121

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T185

1

T410

2

T140

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T178

1

T121

1

T251

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T42

1

T41

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T6

1

T251

1

T137

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T43

1

T361

1

T185

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

69

1

T32

1

T88

2

T174

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T42

1

T41

1

T43

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T6

2

T174

1

T251

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T42

1

T92

1

T136

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

70

1

T6

1

T88

1

T174

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T407

1

T274

1

T301

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

110

1

T40

3

T42

1

T121

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

74

1

T40

5

T41

1

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T6

1

T88

1

T251

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T42

1

T41

2

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

80

1

T6

1

T178

2

T318

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T42

1

T41

1

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

68

1

T6

1

T88

14

T178

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T41

1

T43

1

T124

11

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

154

1

T6

8

T42

3

T41

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

93

1

T43

3

T361

4

T185

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T413

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T185

2

T410

2

T274

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded